Re: [Qemu-devel] [Patch 1/2][PXA27x] initial keypad support
andrzej zaborowski wrote: Hi, On 12/12/2007, Armin <[EMAIL PROTECTED]> wrote: Here is an attempt to add PXA27x keypad support. It currently only supports the matrix type interface. It still needs direct and mulitswitch support added. Just wanted to get something out there for folks to pound on. Comment and feedback welcome. Here are some comments: * Several bits in KPC and KPREC should be reset on read. The IRQ should be reset when it becomes masked in KPC, and potentially asserted when it becomes unmasked. Done, I think I got the reset on read . The MI and DI interrupt bits are set after a scan has completed and then the IRQ is asserted. I think I got it. * It's wasteful to go through all keys in the 8x8 matrix on every event. It can be avoided easily by mapping qemu keycode to matrix position, rather than position to keycode, for example the PalmT|E matrix keypad does that. Yeah, that was a bit overkill ; ) * Please convert the indentation in the file to use spaces, before considering for inclusion. sure thing * The bit definitions and pxa2xx_keypad_s struct are local to the keypad module so they shouldn't be in the header file exposed to the whole world. Ok. * Please set a copyright owner. Ok. Regarding mainstone keypad patch: * Probably not worth to stick the keymap in a file of its own since it is not shared between different machines - it's an integral part of mainstone. Done Thanks for the feedback. New patches to follow. -Armin
[Qemu-devel] [Patch 1/2v2][PXA27x] initial keypad support
Hello,
Here is a new series of keypad support patches for the PXA27x.
I believe I have addressed all the concerns from my first set of patch.
Feedback and comment welcome.
-Armin
Index: qemu/hw/pxa.h
===
--- qemu.orig/hw/pxa.h
+++ qemu/hw/pxa.h
@@ -13,6 +13,7 @@
# define PXA2XX_PIC_SSP3 0
# define PXA2XX_PIC_USBH2 2
# define PXA2XX_PIC_USBH1 3
+# define PXA2XX_PIC_KEYPAD 4
# define PXA2XX_PIC_PWRI2C 6
# define PXA25X_PIC_HWUART 7
# define PXA27X_PIC_OST_4_11 7
@@ -120,6 +121,17 @@ i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2
struct pxa2xx_i2s_s;
struct pxa2xx_fir_s;
+/* pxa2xx_kpad.c */
+struct keymap {
+int column;
+int row;
+};
+struct pxa2xx_keypad_s;
+struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base,
+qemu_irq irq);
+void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map,
+int size);
+
struct pxa2xx_state_s {
CPUState *env;
qemu_irq *pic;
@@ -133,6 +145,7 @@ struct pxa2xx_state_s {
struct pxa2xx_pcmcia_s *pcmcia[2];
struct pxa2xx_i2s_s *i2s;
struct pxa2xx_fir_s *fir;
+struct pxa2xx_keypad_s *kp;
/* Power management */
target_phys_addr_t pm_base;
Index: qemu/hw/pxa2xx.c
===
--- qemu.orig/hw/pxa2xx.c
+++ qemu/hw/pxa2xx.c
@@ -2156,6 +2156,7 @@ struct pxa2xx_state_s *pxa270_init(unsig
/* GPIO1 resets the processor */
/* The handler can be overridden by board-specific code */
pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
+ s->kp = pxa27x_keypad_init(0x4150, s->pic[PXA2XX_PIC_KEYPAD]);
return s;
}
Index: qemu/hw/pxa2xx_keypad.c
===
--- /dev/null
+++ qemu/hw/pxa2xx_keypad.c
@@ -0,0 +1,344 @@
+/*
+ * Intel PXA27X Keypad Controller emulation.
+ *
+ * Copyright (c) 2007 MontaVista Software, Inc
+ * Written by Armin Kuster <[EMAIL PROTECTED]>
+ * or <[EMAIL PROTECTED]>
+ *
+ * This code is licensed under the GPLv2.
+ */
+
+#include "hw.h"
+#include "pxa.h"
+#include "console.h"
+
+/*
+ * Keypad
+ */
+#define KPC 0x00/* Keypad Interface Control register */
+#define KPDK0x08/* Keypad Interface Direct Key register */
+#define KPREC 0x10/* Keypad Interface Rotary Encoder register */
+#define KPMK0x18/* Keypad Interface Matrix Key register */
+#define KPAS0x20/* Keypad Interface Automatic Scan register */
+#define KPASMKP00x28/* Keypad Interface Automatic Scan Multiple
+Key Presser register 0 */
+#define KPASMKP10x30/* Keypad Interface Automatic Scan Multiple
+Key Presser register 1 */
+#define KPASMKP20x38/* Keypad Interface Automatic Scan Multiple
+Key Presser register 2 */
+#define KPASMKP30x40/* Keypad Interface Automatic Scan Multiple
+Key Presser register 3 */
+#define KPKDI 0x48/* Keypad Interface Key Debounce Interval
+register */
+
+/* Keypad defines */
+#define KPC_AS (0x1 << 30) /* Automatic Scan bit */
+#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
+#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
+#define KPC_IMKP(0x1 << 21) /* Ignore Multiple Key Press */
+#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
+#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
+#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
+#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
+#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
+#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
+#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
+#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
+#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
+#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
+#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */
+#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
+#define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */
+#define KPC_REE1(0x1 << 3) /* Rotary Encoder1 Enable */
+#define KPC_REE0(0x1 << 2) /* Rotary Encoder0 Enable */
+#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
+#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
+
+#define KPDK_DKP(0x1 << 31)
+#define KPDK_DK7(0x1 << 7)
+#define KPDK_DK6(0x1 << 6)
+#define KPDK_DK5(0x1 << 5)
+#define KPDK_DK4(0x1 << 4)
+#defi
[Qemu-devel] [Patch 2/2v2][PXA27x] Mainstone keypad support
Here is the Mainstone keypad martix
-Armin
Index: qemu/hw/mainstone.c
===
--- qemu.orig/hw/mainstone.c
+++ qemu/hw/mainstone.c
@@ -18,6 +18,45 @@
#include "sysemu.h"
#include "flash.h"
+static struct keymap map[0xE0] = {
+[0 ... 0xDf] = { -1, -1 },
+[0x1e] = {0,0}, /* a */
+[0x30] = {0,1}, /* b */
+[0x2e] = {0,2}, /* c */
+[0x20] = {0,3}, /* d */
+[0x12] = {0,4}, /* e */
+[0x21] = {0,5}, /* f */
+[0x22] = {1,0}, /* g */
+[0x23] = {1,1}, /* h */
+[0x17] = {1,2}, /* i */
+[0x24] = {1,3}, /* j */
+[0x25] = {1,4}, /* k */
+[0x26] = {1,5}, /* l */
+[0x32] = {2,0}, /* m */
+[0x31] = {2,1}, /* n */
+[0x18] = {2,2}, /* o */
+[0x19] = {2,3}, /* p */
+[0x10] = {2,4}, /* q */
+[0x13] = {2,5}, /* r */
+[0x1f] = {3,0}, /* s */
+[0x14] = {3,1}, /* t */
+[0x16] = {3,2}, /* u */
+[0x2f] = {3,3}, /* v */
+[0x11] = {3,4}, /* w */
+[0x2d] = {3,5}, /* x */
+[0x15] = {4,2}, /* y */
+[0x2c] = {4,3}, /* z */
+[0xc7] = {5,0}, /* Home */
+[0x2a] = {5,1}, /* shift */
+[0x39] = {5,2}, /* space */
+[0x39] = {5,3}, /* space */
+[0x1c] = {5,5}, /* enter */
+[0xc8] = {6,0}, /* up */
+[0xd0] = {6,1}, /* down */
+[0xcb] = {6,2}, /* left */
+[0xcd] = {6,3}, /* right */
+};
+
enum mainstone_model_e { mainstone };
static void mainstone_common_init(int ram_size, int vga_ram_size,
@@ -30,6 +69,7 @@ static void mainstone_common_init(int ra
struct pxa2xx_state_s *cpu;
qemu_irq *mst_irq;
int index;
+int a;
if (!cpu_model)
cpu_model = "pxa270-c5";
@@ -79,6 +119,10 @@ static void mainstone_common_init(int ra
mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);
+/* setup keypad */
+printf("map addr %p\n",&map);
+ pxa27x_register_keypad(cpu->kp, map, 0xe0);
+
/* MMC/SD host */
pxa2xx_mmci_handlers(cpu->mmc, NULL, mst_irq[MMC_IRQ]);
Index: qemu/hw/mainstone.h
===
--- qemu.orig/hw/mainstone.h
+++ qemu/hw/mainstone.h
@@ -34,5 +34,4 @@
extern qemu_irq
*mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq);
-
#endif /* __MAINSTONE_H__ */
[Qemu-devel] test
Sorry for the noise. I sent out new patches last night and have not seen it on the list. - Armin
[Qemu-devel] [Patch 1/2] switch support - resend
Hello,
I have wanted a scheme to change switch settings at boot time so I
change the behavior of the Linux kernel and here is one solution I put
together.
This may be one way to simulate switch or jumper settings one may change
on a board before booting.
It uses a simple text file for input. The file name is pointed to by
-config on the command line.
example:
config file:
[switches]
7:on
[jumpers]
Note: both [switches] and [jumpers] are required at the moment
to use:
qemu-system-arm -M mainstone -kernel /tftpboot/mainstone -pflash
~/mst_flashl1 -config ~/config.txt
this will enable the processor flash bank on the Mainstone and if I
change 7:on to 7:off , I get the main mother board flash.
feedback and comment are always welcome.
-Armin
Index: qemu/vl.c
===
--- qemu.orig/vl.c
+++ qemu/vl.c
@@ -232,6 +232,8 @@ const char *prom_envs[MAX_PROM_ENVS];
#endif
int nb_drives_opt;
char drives_opt[MAX_DRIVES][1024];
+int configed = 0;
+const char *qemu_config;
static CPUState *cur_cpu;
static CPUState *next_cpu;
@@ -1547,6 +1549,118 @@ static void quit_timers(void)
alarm_timer->stop(alarm_timer);
alarm_timer = NULL;
}
+/**/
+/* config file */
+#define CONFIG_MAXLEN 256
+
+int switch_get_value(SwitchInterfaceType interface, int number)
+{
+int index;
+
+struct spdt_switch *sw = config_table[interface].sw;
+
+for (index = 0; index < config_table[interface].nb_switches; index++){
+if(sw[index].num == number)
+return sw[index].value;
+}
+return -1;
+}
+
+static ssize_t config_rdline(FILE *fd, char *buf, size_t bufsz)
+{
+int i, ch;
+for(i = 0; i < bufsz && (ch=fgetc(fd)) != '\n' ; i++) {
+if (ch == EOF) {
+*buf = '\0';
+return -1;
+}
+if(ch == '[') {
+return -2;
+}
+*buf++ = ch;
+}
+*buf = '\0';
+return i;
+}
+
+static int config_read_switches(FILE *fd, int index)
+{
+int cnt = 0;
+int size = 0;
+char *tmp;
+int sw_size = sizeof(struct spdt_switch);
+struct spdt_switch *sw;
+
+sw = (struct spdt_switch*) malloc(sw_size);
+if(!sw) {
+printf("config_read_switches - Malloc error!!");
+return -ENOMEM;
+}
+
+config_table[index].sw = sw;
+while(size != -1) {
+char buf[CONFIG_MAXLEN];
+
+size = config_rdline(fd, buf, CONFIG_MAXLEN);
+if(size <= 0) {
+break;
+}
+
+tmp = strchr(buf, ':');
+sw[cnt].value = (strcmp(++tmp,"off")) ? 1 : 0 ;
+sw[cnt].num = atoi(buf);
+sw_size += sizeof(struct spdt_switch);
+sw = (struct spdt_switch *) realloc(config_table[index].sw, sw_size );
+if(!sw)
+return -1;
+cnt++;
+};
+return cnt;
+}
+
+static int config_file_read(char const *file)
+{
+FILE *fd;
+int index;
+
+struct {
+char *key;
+SwitchInterfaceType interface;
+} switch_keywords[]= {
+{"switches", CFG_SPDT_SWITCH},
+{"jumpers", CFG_JUMPERS_SWITCH}
+};
+
+fd = fopen(file,"r");
+if(fd < 0) {
+printf("Open error\n");
+return -1;
+}
+
+for(index = 0; index < (sizeof(switch_keywords)/sizeof(switch_keywords[0]));
+index++){
+
+int ret;
+char buf[CONFIG_MAXLEN];
+ret = config_rdline(fd, buf, CONFIG_MAXLEN);
+if(ret == -1) {
+return -1;
+}
+if(ret == -2) {
+ret = config_rdline(fd, buf, CONFIG_MAXLEN);
+if(ret == -1) {
+return -1;
+}
+}
+if(strstr(buf, switch_keywords[index].key) != NULL) {
+int cnt;
+cnt = config_read_switches(fd,switch_keywords[index].interface);
+config_table[index].nb_switches = cnt;
+}
+}
+fclose(fd);
+return 1;
+}
/***/
/* character device */
@@ -7562,6 +7676,7 @@ static void help(int exitcode)
#endif
"-clock force the use of the given methods for timer alarm.\n"
"To see what timers are available use -clock help\n"
+ "-config fileconfig file for kernel startup like switches and jumpers\n"
"\n"
"During emulation, the following keys are useful:\n"
"ctrl-alt-f toggle full screen\n"
@@ -7664,6 +7779,7 @@ enum {
QEMU_OPTION_old_param,
QEMU_OPTION_clock,
QEMU_OPTION_startdate,
+QEMU_OPTION_config,
};
typedef struct QEMUOption {
@@ -7772,6 +7888,7 @@ const QEMUOption qemu_options[] = {
#endif
{ "clock",
[Qemu-devel] [Patch 2/2] switch support, Mainstone - resend
Here is the use of the switches patch on a Mainstone.
-Armin
Index: qemu/hw/mainstone.c
===
--- qemu.orig/hw/mainstone.c
+++ qemu/hw/mainstone.c
@@ -51,32 +51,28 @@ static void mainstone_common_init(int ra
/* There are two 32MiB flash devices on the board */
index = drive_get_index(IF_PFLASH, 0, 0);
if (index == -1) {
-fprintf(stderr, "Two flash images must be given with the "
+fprintf(stderr, "One flash image must be given with the "
"'pflash' parameter\n");
exit(1);
}
-if (!pflash_cfi01_register(MST_FLASH_0,
- mainstone_ram + PXA2XX_INTERNAL_SIZE,
- drives_table[index].bdrv,
- 256 * 1024, 128, 4, 0, 0, 0, 0)) {
-fprintf(stderr, "qemu: Error registering flash memory.\n");
-exit(1);
-}
-index = drive_get_index(IF_PFLASH, 0, 1);
-if (index == -1) {
-fprintf(stderr, "Two flash images must be given with the "
-"'pflash' parameter\n");
-exit(1);
-}
-if (!pflash_cfi01_register(MST_FLASH_1,
- mainstone_ram + PXA2XX_INTERNAL_SIZE,
- drives_table[index].bdrv,
- 256 * 1024, 128, 4, 0, 0, 0, 0)) {
-fprintf(stderr, "qemu: Error registering flash memory.\n");
-exit(1);
+if(switch_get_value(CFG_SPDT_SWITCH, 7)) {
+if (!pflash_cfi01_register(MST_FLASH_0,
+mainstone_ram + PXA2XX_INTERNAL_SIZE,
+drives_table[index].bdrv,
+256 * 1024, 128, 4, 0, 0, 0, 0)) {
+fprintf(stderr, "qemu: Error registering flash memory.\n");
+exit(1);
+}
+}else{
+if (!pflash_cfi01_register(MST_FLASH_1,
+mainstone_ram + PXA2XX_INTERNAL_SIZE,
+drives_table[index].bdrv,
+256 * 1024, 128, 4, 0, 0, 0, 0)) {
+fprintf(stderr, "qemu: Error registering flash memory.\n");
+exit(1);
+}
}
-
mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);
/* MMC/SD host */
[Qemu-devel] [Patch 1/2] switch support
Hello,
I have wanted a scheme to change switch settings at boot time so I
change the behavior of the Linux kernel and here is one solution I put
together.
This may be one way to simulate switch or jumper settings one may change
on a board before booting.
It uses a simple text file for input. The file name is pointed to by
-config on the command line.
example:
config file:
[switches]
7:on
[jumpers]
Note: both [switches] and [jumpers] are required at the moment
to use:
qemu-system-arm -M mainstone -kernel /tftpboot/mainstone -pflash
~/mst_flashl1 -config ~/config.txt
this will enable the processor flash bank on the Mainstone and if I
change 7:on to 7:off , I get the main mother board flash.
feedback and comment are always welcome.
-Armin
Index: qemu/vl.c
===
--- qemu.orig/vl.c
+++ qemu/vl.c
@@ -232,6 +232,8 @@ const char *prom_envs[MAX_PROM_ENVS];
#endif
int nb_drives_opt;
char drives_opt[MAX_DRIVES][1024];
+int configed = 0;
+const char *qemu_config;
static CPUState *cur_cpu;
static CPUState *next_cpu;
@@ -1547,6 +1549,118 @@ static void quit_timers(void)
alarm_timer->stop(alarm_timer);
alarm_timer = NULL;
}
+/**/
+/* config file */
+#define CONFIG_MAXLEN 256
+
+int switch_get_value(SwitchInterfaceType interface, int number)
+{
+int index;
+
+struct spdt_switch *sw = config_table[interface].sw;
+
+for (index = 0; index < config_table[interface].nb_switches; index++){
+if(sw[index].num == number)
+return sw[index].value;
+}
+return -1;
+}
+
+static ssize_t config_rdline(FILE *fd, char *buf, size_t bufsz)
+{
+int i, ch;
+for(i = 0; i < bufsz && (ch=fgetc(fd)) != '\n' ; i++) {
+if (ch == EOF) {
+*buf = '\0';
+return -1;
+}
+if(ch == '[') {
+return -2;
+}
+*buf++ = ch;
+}
+*buf = '\0';
+return i;
+}
+
+static int config_read_switches(FILE *fd, int index)
+{
+int cnt = 0;
+int size = 0;
+char *tmp;
+int sw_size = sizeof(struct spdt_switch);
+struct spdt_switch *sw;
+
+sw = (struct spdt_switch*) malloc(sw_size);
+if(!sw) {
+printf("config_read_switches - Malloc error!!");
+return -ENOMEM;
+}
+
+config_table[index].sw = sw;
+while(size != -1) {
+char buf[CONFIG_MAXLEN];
+
+size = config_rdline(fd, buf, CONFIG_MAXLEN);
+if(size <= 0) {
+break;
+}
+
+tmp = strchr(buf, ':');
+sw[cnt].value = (strcmp(++tmp,"off")) ? 1 : 0 ;
+sw[cnt].num = atoi(buf);
+sw_size += sizeof(struct spdt_switch);
+sw = (struct spdt_switch *) realloc(config_table[index].sw, sw_size );
+if(!sw)
+return -1;
+cnt++;
+};
+return cnt;
+}
+
+static int config_file_read(char const *file)
+{
+FILE *fd;
+int index;
+
+struct {
+char *key;
+SwitchInterfaceType interface;
+} switch_keywords[]= {
+{"switches", CFG_SPDT_SWITCH},
+{"jumpers", CFG_JUMPERS_SWITCH}
+};
+
+fd = fopen(file,"r");
+if(fd < 0) {
+printf("Open error\n");
+return -1;
+}
+
+for(index = 0; index < (sizeof(switch_keywords)/sizeof(switch_keywords[0]));
+index++){
+
+int ret;
+char buf[CONFIG_MAXLEN];
+ret = config_rdline(fd, buf, CONFIG_MAXLEN);
+if(ret == -1) {
+return -1;
+}
+if(ret == -2) {
+ret = config_rdline(fd, buf, CONFIG_MAXLEN);
+if(ret == -1) {
+return -1;
+}
+}
+if(strstr(buf, switch_keywords[index].key) != NULL) {
+int cnt;
+cnt = config_read_switches(fd,switch_keywords[index].interface);
+config_table[index].nb_switches = cnt;
+}
+}
+fclose(fd);
+return 1;
+}
/***/
/* character device */
@@ -7562,6 +7676,7 @@ static void help(int exitcode)
#endif
"-clock force the use of the given methods for timer alarm.\n"
"To see what timers are available use -clock help\n"
+ "-config fileconfig file for kernel startup like switches and jumpers\n"
"\n"
"During emulation, the following keys are useful:\n"
"ctrl-alt-f toggle full screen\n"
@@ -7664,6 +7779,7 @@ enum {
QEMU_OPTION_old_param,
QEMU_OPTION_clock,
QEMU_OPTION_startdate,
+QEMU_OPTION_config,
};
typedef struct QEMUOption {
@@ -7772,6 +7888,7 @@ const QEMUOption qemu_options[] = {
#endif
{ "clock",
[Qemu-devel] [Patch 2/2] switch support, Mainstone
Here is the use of the switches patch on a Mainstone.
-Armin
Index: qemu/hw/mainstone.c
===
--- qemu.orig/hw/mainstone.c
+++ qemu/hw/mainstone.c
@@ -51,32 +51,28 @@ static void mainstone_common_init(int ra
/* There are two 32MiB flash devices on the board */
index = drive_get_index(IF_PFLASH, 0, 0);
if (index == -1) {
-fprintf(stderr, "Two flash images must be given with the "
+fprintf(stderr, "One flash image must be given with the "
"'pflash' parameter\n");
exit(1);
}
-if (!pflash_cfi01_register(MST_FLASH_0,
- mainstone_ram + PXA2XX_INTERNAL_SIZE,
- drives_table[index].bdrv,
- 256 * 1024, 128, 4, 0, 0, 0, 0)) {
-fprintf(stderr, "qemu: Error registering flash memory.\n");
-exit(1);
-}
-index = drive_get_index(IF_PFLASH, 0, 1);
-if (index == -1) {
-fprintf(stderr, "Two flash images must be given with the "
-"'pflash' parameter\n");
-exit(1);
-}
-if (!pflash_cfi01_register(MST_FLASH_1,
- mainstone_ram + PXA2XX_INTERNAL_SIZE,
- drives_table[index].bdrv,
- 256 * 1024, 128, 4, 0, 0, 0, 0)) {
-fprintf(stderr, "qemu: Error registering flash memory.\n");
-exit(1);
+if(switch_get_value(CFG_SPDT_SWITCH, 7)) {
+if (!pflash_cfi01_register(MST_FLASH_0,
+mainstone_ram + PXA2XX_INTERNAL_SIZE,
+drives_table[index].bdrv,
+256 * 1024, 128, 4, 0, 0, 0, 0)) {
+fprintf(stderr, "qemu: Error registering flash memory.\n");
+exit(1);
+}
+}else{
+if (!pflash_cfi01_register(MST_FLASH_1,
+mainstone_ram + PXA2XX_INTERNAL_SIZE,
+drives_table[index].bdrv,
+256 * 1024, 128, 4, 0, 0, 0, 0)) {
+fprintf(stderr, "qemu: Error registering flash memory.\n");
+exit(1);
+}
}
-
mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);
/* MMC/SD host */
Re: [Qemu-devel] [Patch 1/2v2][PXA27x] initial keypad support
andrzej zaborowski wrote: On 13/12/2007, Armin <[EMAIL PROTECTED]> wrote: Hello, Here is a new series of keypad support patches for the PXA27x. I believe I have addressed all the concerns from my first set of patch. Thanks! I just changed the use of cpu_abort to an exit() because cpu_single_env will typically be NULL at the time of initialisation. Please test. Cheers Andrzej, It works fine. Thanks. -Armin
[Qemu-devel] [Patch 1/2] switch support v2
Hello,
Here is a set of patches against the latest cvs and fixed a bad patch also.
I have wanted a scheme to change switch settings at boot time so I
change the behavior of the Linux kernel and here is one solution I put
together.
This may be one way to simulate switch or jumper settings one may change
on a board before booting.
It uses a simple text file for input. The file name is pointed to by
-config on the command line.
example:
config file:
[switches]
7:on
[jumpers]
Note: both [switches] and [jumpers] are required at the moment
to use:
qemu-system-arm -M mainstone -kernel /tftpboot/mainstone -pflash
~/mst_flashl1 -config ~/config.txt
this will enable the processor flash bank on the Mainstone and if I
change 7:on to 7:off , I get the main mother board flash.
feedback and comment are always welcome.
-Armin
Index: qemu_dev/vl.c
===
--- qemu_dev.orig/vl.c
+++ qemu_dev/vl.c
@@ -232,6 +232,8 @@ const char *prom_envs[MAX_PROM_ENVS];
#endif
int nb_drives_opt;
char drives_opt[MAX_DRIVES][1024];
+int configed = 0;
+const char *qemu_config;
static CPUState *cur_cpu;
static CPUState *next_cpu;
@@ -1557,6 +1559,118 @@ static void quit_timers(void)
alarm_timer->stop(alarm_timer);
alarm_timer = NULL;
}
+/**/
+/* config file */
+#define CONFIG_MAXLEN 256
+
+int switch_get_value(SwitchInterfaceType interface, int number)
+{
+int index;
+
+struct spdt_switch *sw = config_table[interface].sw;
+
+for (index = 0; index < config_table[interface].nb_switches; index++){
+if(sw[index].num == number)
+return sw[index].value;
+}
+return -1;
+}
+
+static ssize_t config_rdline(FILE *fd, char *buf, size_t bufsz)
+{
+int i, ch;
+for(i = 0; i < bufsz && (ch=fgetc(fd)) != '\n' ; i++) {
+if (ch == EOF) {
+*buf = '\0';
+return -1;
+}
+if(ch == '[') {
+return -2;
+}
+*buf++ = ch;
+}
+*buf = '\0';
+return i;
+}
+
+static int config_read_switches(FILE *fd, int index)
+{
+int cnt = 0;
+int size = 0;
+char *tmp;
+int sw_size = sizeof(struct spdt_switch);
+struct spdt_switch *sw;
+
+sw = (struct spdt_switch*) malloc(sw_size);
+if(!sw) {
+printf("config_read_switches - Malloc error!!");
+return -ENOMEM;
+}
+
+config_table[index].sw = sw;
+while(size != -1) {
+char buf[CONFIG_MAXLEN];
+
+size = config_rdline(fd, buf, CONFIG_MAXLEN);
+if(size <= 0) {
+break;
+}
+
+tmp = strchr(buf, ':');
+sw[cnt].value = (strcmp(++tmp,"off")) ? 1 : 0 ;
+sw[cnt].num = atoi(buf);
+sw_size += sizeof(struct spdt_switch);
+sw = (struct spdt_switch *) realloc(config_table[index].sw, sw_size );
+if(!sw)
+return -1;
+cnt++;
+};
+return cnt;
+}
+
+static int config_file_read(char const *file)
+{
+FILE *fd;
+int index;
+
+struct {
+char *key;
+SwitchInterfaceType interface;
+} switch_keywords[]= {
+{"switches", CFG_SPDT_SWITCH},
+{"jumpers", CFG_JUMPERS_SWITCH}
+};
+
+fd = fopen(file,"r");
+if(fd < 0) {
+printf("Open error\n");
+return -1;
+}
+
+for(index = 0; index < (sizeof(switch_keywords)/sizeof(switch_keywords[0]));
+index++){
+
+int ret;
+char buf[CONFIG_MAXLEN];
+ret = config_rdline(fd, buf, CONFIG_MAXLEN);
+if(ret == -1) {
+return -1;
+}
+if(ret == -2) {
+ret = config_rdline(fd, buf, CONFIG_MAXLEN);
+if(ret == -1) {
+return -1;
+}
+}
+if(strstr(buf, switch_keywords[index].key) != NULL) {
+int cnt;
+cnt = config_read_switches(fd,switch_keywords[index].interface);
+config_table[index].nb_switches = cnt;
+}
+}
+fclose(fd);
+return 1;
+}
/***/
/* character device */
@@ -7590,6 +7704,7 @@ static void help(int exitcode)
#endif
"-clock force the use of the given methods for timer alarm.\n"
"To see what timers are available use -clock help\n"
+ "-config fileconfig file for kernel startup like switches and jumpers\n"
"\n"
"During emulation, the following keys are useful:\n"
"ctrl-alt-f toggle full screen\n"
@@ -7692,6 +7807,7 @@ enum {
QEMU_OPTION_old_param,
QEMU_OPTION_clock,
QEMU_OPTION_startdate,
+QEMU_OPTION_config,
};
typedef struct QEMUOpt
[Qemu-devel] [Patch 2/2] switch support, Mainstone v2
Mainstone patch against latest cvs.
-Armin
Index: qemu_dev/hw/mainstone.c
===
--- qemu_dev.orig/hw/mainstone.c
+++ qemu_dev/hw/mainstone.c
@@ -87,33 +87,31 @@ static void mainstone_common_init(int ra
/* Setup initial (reset) machine state */
cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
-/* There are two 32MiB flash devices on the board */
+/* There are two 32MiB flash devices on the board
+ * switch #7 governs which bank to use
+ */
index = drive_get_index(IF_PFLASH, 0, 0);
if (index == -1) {
-fprintf(stderr, "Two flash images must be given with the "
+fprintf(stderr, "One flash image must be given with the "
"'pflash' parameter\n");
exit(1);
}
-if (!pflash_cfi01_register(MST_FLASH_0,
- mainstone_ram + PXA2XX_INTERNAL_SIZE,
- drives_table[index].bdrv,
- 256 * 1024, 128, 4, 0, 0, 0, 0)) {
-fprintf(stderr, "qemu: Error registering flash memory.\n");
-exit(1);
-}
-
-index = drive_get_index(IF_PFLASH, 0, 1);
-if (index == -1) {
-fprintf(stderr, "Two flash images must be given with the "
-"'pflash' parameter\n");
-exit(1);
-}
-if (!pflash_cfi01_register(MST_FLASH_1,
- mainstone_ram + PXA2XX_INTERNAL_SIZE,
- drives_table[index].bdrv,
- 256 * 1024, 128, 4, 0, 0, 0, 0)) {
-fprintf(stderr, "qemu: Error registering flash memory.\n");
-exit(1);
+if(switch_get_value(CFG_SPDT_SWITCH, 7)) {
+if (!pflash_cfi01_register(MST_FLASH_0,
+mainstone_ram + PXA2XX_INTERNAL_SIZE,
+drives_table[index].bdrv,
+256 * 1024, 128, 4, 0, 0, 0, 0)) {
+fprintf(stderr, "qemu: Error registering flash memory.\n");
+exit(1);
+}
+} else {
+if (!pflash_cfi01_register(MST_FLASH_1,
+mainstone_ram + PXA2XX_INTERNAL_SIZE,
+drives_table[index].bdrv,
+256 * 1024, 128, 4, 0, 0, 0, 0)) {
+fprintf(stderr, "qemu: Error registering flash memory.\n");
+exit(1);
+}
}
mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);
Re: [Qemu-devel] [Patch 1/2] switch support v2
Johannes Schindelin wrote: Hi, On Sun, 16 Dec 2007, Armin wrote: This may be one way to simulate switch or jumper settings one may change on a board before booting. It uses a simple text file for input. The file name is pointed to by -config on the command line. example: config file: [switches] 7:on [jumpers] I find this format utterly ugly. I can only make it better then : ) You have sections like INI files, but then refuse to keep to that format. Besides, I fail to see why this has to be a config file? It can be named anything , I suppose "switch"would be better All other settings are command line switches and/or monitor settings, and there is no good reason why switches and jumpers should not be handled that way. Do you mean something like -sw or -jp? regards, -Armin
Re: [Qemu-devel] [Patch 1/2] switch support v2
Laurent Vivier wrote: Hi, if you just want to configure which bank to use with pflash, perhaps you can do something like: qemu -drive if=pflash,unit=0 to use the first bank, and qemu -drive if=pflash,unit=1 to use the second bank. Yes, that might work for the flash case but does not address other switches settings. In my case, the Mainstone has two rotary switches that define which frequency to boot up in. - Armin Laurent Le lundi 17 décembre 2007 à 07:29 -1000, Armin a écrit : Johannes Schindelin wrote: Hi, On Sun, 16 Dec 2007, Armin wrote: This may be one way to simulate switch or jumper settings one may change on a board before booting. It uses a simple text file for input. The file name is pointed to by -config on the command line. example: config file: [switches] 7:on [jumpers] I find this format utterly ugly. I can only make it better then : ) You have sections like INI files, but then refuse to keep to that format. Besides, I fail to see why this has to be a config file? It can be named anything , I suppose "switch"would be better All other settings are command line switches and/or monitor settings, and there is no good reason why switches and jumpers should not be handled that way. Do you mean something like -sw or -jp? regards, -Armin
Re: [Qemu-devel] [Patch 1/2] switch support v2
Laurent Vivier wrote: Le lundi 17 décembre 2007 à 09:40 -1000, Armin a écrit : Laurent Vivier wrote: Hi, if you just want to configure which bank to use with pflash, perhaps you can do something like: qemu -drive if=pflash,unit=0 to use the first bank, and qemu -drive if=pflash,unit=1 to use the second bank. Yes, that might work for the flash case but does not address other switches settings. In my case, the Mainstone has two rotary switches that define which frequency to boot up in. But I don't think qemu able to emulate frequency ? So it should be useless. I am sure that is true and my example might be very week in the above case. I think if a board we are trying to emulate has boot time configurations governed by jumpers or switches for enabling or disabling certain hardware devices , then having a runtime solution seems more appropriate. It seems silly to have to rebuild to qemu if one wants to switch device A to be uart #2 from an IrdA device when using "-switches 1=on" could do the same. regards, Armin
Re: [Qemu-devel] [Patch 1/2] switch support v2
Laurent Vivier wrote: Le mardi 18 décembre 2007 à 08:40 -1000, Armin a écrit : Laurent Vivier wrote: Le lundi 17 décembre 2007 à 09:40 -1000, Armin a écrit : Laurent Vivier wrote: Hi, if you just want to configure which bank to use with pflash, perhaps you can do something like: qemu -drive if=pflash,unit=0 to use the first bank, and qemu -drive if=pflash,unit=1 to use the second bank. Yes, that might work for the flash case but does not address other switches settings. In my case, the Mainstone has two rotary switches that define which frequency to boot up in. But I don't think qemu able to emulate frequency ? So it should be useless. I am sure that is true and my example might be very week in the above case. I think if a board we are trying to emulate has boot time configurations governed by jumpers or switches for enabling or disabling certain hardware devices , then having a runtime solution seems more appropriate. It seems silly to have to rebuild to qemu if one wants to switch device A to be uart #2 from an IrdA device when using "-switches 1=on" could do the same. Well, my opinion is not really important here, but I think "-switches 1=on" is too low level... using the "meaning" could be more user-friendly, something like "-deviceA uart2". Sure your opinion matters, I can get an idea stuck in my little brain and not see the trees in the forest. "-device", that got me thinking... Lets say I have a mips port that has one PCI slot on it. I could get a listing of PCI cards supported by this port and select one for use by that PCI slot. This could be extended for local bus (i.e switches & jumpers) , PCMCIA and SD slots. Regards, Armin
[Qemu-devel] Philips USB1400 chip
Hello, Is anyone working on a port for the Philips UCB1400 audio codec with touch screen and power management chip? or did I miss it in the sources? - Armin
[Qemu-devel] PXA27x AC97
Hello, Is anyone working on the PXA27x AC97 emulation? I don't want to dup effort. TIA Armin
Re: [Qemu-devel] PXA27x AC97
andrzej zaborowski wrote: Hi, On 11/01/2008, Armin <[EMAIL PROTECTED]> wrote: Is anyone working on the PXA27x AC97 emulation? I don't want to dup effort. Not that I know of, but Virtual Box has a PCI AC97 implementation (for PC emulator) and the hackndev qemu tree has dummy PXA27x AC97 registers (zero functionality) at http://git2.hackndev.com/gitweb?p=qemu.git;a=blob;h=817f022208fc0e7ba4a681917e3e6ef3d0c4fae6;hb=9950e2d157ca4bc73662df5069be3c51ef52a856;f=hw/palm.c Maybe it can be helpful. Yes, it does. I would like to create a pxa2xx_ac97.c so more boards can leverage the functionality. I do have the framework put together that I started early. I will see where it takes me. - Armin Regards
[Qemu-devel] PXA board support -MainstoneII
Hello, I am new to Qemu and just started to poke around. This morning I pulled my first copy from cvs and noticed many Arm PXA boards being supported. Is anyone working on adding the Intel MainstoneII ? kind regards, Armin
[Qemu-devel] [Patch] PXA27x Mainstone II board support
Hello,
The following patch adds basic PXA27x Mainstone II support.
Boots from initrd at the monument.
Comments and Feedback welcome.
Kind regards,
Armin
diff -ruN qemu_org/hw/boards.h qemu/hw/boards.h
--- qemu_org/hw/boards.h 2007-11-17 22:46:57.0 -1000
+++ qemu/hw/boards.h 2007-11-18 17:51:37.0 -1000
@@ -92,4 +92,7 @@
/* dummy_m68k.c */
extern QEMUMachine dummy_m68k_machine;
+/* Arm PXA27x - mainstone.c */
+extern QEMUMachine mainstone2_machine;
+
#endif
diff -ruN qemu_org/hw/mainstone.c qemu/hw/mainstone.c
--- qemu_org/hw/mainstone.c 1969-12-31 14:00:00.0 -1000
+++ qemu/hw/mainstone.c 2007-11-18 17:52:00.0 -1000
@@ -0,0 +1,67 @@
+/*
+ * PXA270-based Intel Mainstone platforms.
+ *
+ * Copyright (c) 2007 by Armin Kuster <[EMAIL PROTECTED]> or
+ *<[EMAIL PROTECTED]>
+ *
+ * Code based on spitz platform by Andrzej Zaborowski <[EMAIL PROTECTED]>
+ *
+ * This code is licensed under the GNU GPL v2.
+ */
+#include "hw.h"
+#include "pxa.h"
+#include "arm-misc.h"
+#include "sysemu.h"
+#include "qemu-timer.h"
+#include "net.h"
+#include "devices.h"
+#include "console.h"
+#include "boards.h"
+
+enum mainstone_model_e { mainstone };
+
+static void mainstone_common_init(int ram_size, int vga_ram_size,
+DisplayState *ds, const char *kernel_filename,
+const char *kernel_cmdline, const char *initrd_filename,
+const char *cpu_model, enum mainstone_model_e model, int arm_id)
+{
+uint32_t mainstone_ram = 0x0400;
+uint32_t mainstone_rom = 0x0080;
+struct pxa2xx_state_s *cpu;
+qemu_irq *mst_irq;
+
+if (!cpu_model)
+cpu_model = "pxa270-c5";
+
+/* Setup CPU & memory */
+if (ram_size < mainstone_ram + mainstone_rom + PXA2XX_INTERNAL_SIZE) {
+fprintf(stderr, "This platform requires %i bytes of memory\n",
+mainstone_ram + mainstone_rom + PXA2XX_INTERNAL_SIZE);
+exit(1);
+}
+cpu = pxa270_init(mainstone_ram, ds, cpu_model);
+
+cpu_register_physical_memory(0, mainstone_rom,
+qemu_ram_alloc(mainstone_rom) | IO_MEM_ROM);
+
+/* Setup initial (reset) machine state */
+cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
+
+arm_load_kernel(cpu->env, mainstone_ram, kernel_filename, kernel_cmdline,
+initrd_filename, arm_id, PXA2XX_SDRAM_BASE);
+}
+
+static void mainstone_init(int ram_size, int vga_ram_size,
+const char *boot_device, DisplayState *ds,
+const char *kernel_filename, const char *kernel_cmdline,
+const char *initrd_filename, const char *cpu_model)
+{
+mainstone_common_init(ram_size, vga_ram_size, ds, kernel_filename,
+kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
+}
+
+QEMUMachine mainstone2_machine = {
+"mainstone",
+"Mainstone II (PXA27x)",
+mainstone_init,
+};
diff -ruN qemu_org/Makefile.target qemu/Makefile.target
--- qemu_org/Makefile.target 2007-11-18 12:34:46.0 -1000
+++ qemu/Makefile.target 2007-11-18 17:53:12.0 -1000
@@ -499,6 +499,7 @@
VL_OBJS+= spitz.o ide.o serial.o nand.o ecc.o
VL_OBJS+= omap.o omap_lcdc.o omap1_clk.o omap_mmc.o omap_i2c.o
VL_OBJS+= palm.o tsc210x.o
+VL_OBJS+= mainstone.o
CPPFLAGS += -DHAS_AUDIO
endif
ifeq ($(TARGET_BASE_ARCH), sh4)
diff -ruN qemu_org/vl.c qemu/vl.c
--- qemu_org/vl.c 2007-11-18 15:05:22.0 -1000
+++ qemu/vl.c 2007-11-18 17:51:37.0 -1000
@@ -7451,6 +7451,7 @@
qemu_register_machine(&lm3s811evb_machine);
qemu_register_machine(&lm3s6965evb_machine);
qemu_register_machine(&connex_machine);
+qemu_register_machine(&mainstone2_machine);
#elif defined(TARGET_SH4)
qemu_register_machine(&shix_machine);
qemu_register_machine(&r2d_machine);
[Qemu-devel] Mainstone II
Hello, I have just added networking support for the Mainstone II. Since the source its not in cvs, do I resend a new Mainstone patch or just a diff from the one I sent out earlier? TIA, Armin
Re: [Qemu-devel] Mainstone II
andrzej zaborowski wrote: Andrzej, Hi, On 22/11/2007, Armin <[EMAIL PROTECTED]> wrote: Hello, I have just added networking support for the Mainstone II. Since the source its not in cvs, do I resend a new Mainstone patch or just a diff from the one I sent out earlier? I think a new patch will make it easier for people to try it out before it ends up in cvs. Ok, will send one out shortly. Are there more software-accessible peripherals on this board? Yes, PCMCIA MMC USB LCD Keypad Audio few switches Is there a public kernel tree that supports this board (or would the "mainstone" Intel HCDDBBVA0 support from mainline work)? Yes, latest mainline works. Can pflash_cfi01.c or pflash_cfi02.c be used to implement the cfi flash? I will need to look into it. Kind regards, Armin
[Qemu-devel] [Patch] [Take 2] Mainstone II support
Hello all,
Attached it a patch against the latest cvs base. This adds support for
the Mainstone II board. Included is support for the ethernet device (
SMC911x ) and ramdisk ( initrd ). Kernel sources used are from
Kernel.org mainline. More device support to follow.
Feedback and comment welcome.
Enjoy,
Armin
diff -ruN qemu/hw/boards.h qemu_new/hw/boards.h
--- qemu/hw/boards.h 2007-11-17 22:46:57.0 -1000
+++ qemu_new/hw/boards.h 2007-11-22 09:07:20.0 -1000
@@ -92,4 +92,7 @@
/* dummy_m68k.c */
extern QEMUMachine dummy_m68k_machine;
+/* Arm PXA27x - mainstone.c */
+extern QEMUMachine mainstone2_machine;
+
#endif
diff -ruN qemu/hw/mainstone.c qemu_new/hw/mainstone.c
--- qemu/hw/mainstone.c 1969-12-31 14:00:00.0 -1000
+++ qemu_new/hw/mainstone.c 2007-11-22 09:57:21.0 -1000
@@ -0,0 +1,311 @@
+/*
+ * PXA270-based Intel Mainstone platforms.
+ *
+ * Copyright (c) 2007 by Armin Kuster <[EMAIL PROTECTED]> or
+ *<[EMAIL PROTECTED]>
+ *
+ * Code based on spitz platform by Andrzej Zaborowski <[EMAIL PROTECTED]>
+ *
+ * This code is licensed under the GNU GPL v2.
+ */
+#include "hw.h"
+#include "pxa.h"
+#include "arm-misc.h"
+#include "sysemu.h"
+#include "qemu-timer.h"
+#include "net.h"
+#include "devices.h"
+#include "console.h"
+#include "boards.h"
+
+#define MST_ETH_PHYS 0x1300
+#define MST_FPGA_PHYS 0x0800
+
+/* Mainstone FPGA for extern irqs */
+#define FPGA_GPIO_PIN 0
+#define MST_NUM_IRQS 16
+#define MST_BASE MST_FPGA_PHYS
+#define MST_LEDDAT1 0x10
+#define MST_LEDDAT2 0x14
+#define MST_LEDCTRL 0x40
+#define MST_GPSWR 0x60
+#define MST_MSCWR1 0x80
+#define MST_MSCWR2 0x84
+#define MST_MSCWR3 0x88
+#define MST_MSCRD 0x90
+#define MST_INTMSKENA 0xc0
+#define MST_INTSETCLR 0xd0
+#define MST_PCMCIA0 0xe0
+#define MST_PCMCIA1 0xe4
+
+/* IRQ definitions */
+#define ETHERNET_IRQ 3
+
+typedef struct mst_irq_state{
+ target_phys_addr_t target_base;
+ qemu_irq *parent;
+ qemu_irq *pins;
+
+ uint32_t prev_level;
+ uint32_t leddat1;
+ uint32_t leddat2;
+ uint32_t ledctrl;
+ uint32_t gpswr;
+ uint32_t mscwr1;
+ uint32_t mscwr2;
+ uint32_t mscwr3;
+ uint32_t mscrd;
+ uint32_t intmskena;
+ uint32_t intsetclr;
+ uint32_t pcmcia0;
+ uint32_t pcmcia1;
+}mst_irq_state;
+
+static void
+mst_fpga_update_gpio(mst_irq_state *s)
+{
+ uint32_t level, diff;
+ int bit;
+ level = s->prev_level ^ s->intsetclr;
+
+ for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
+ bit = ffs(diff) - 1;
+ qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
+ }
+ s->prev_level = level;
+}
+
+static void
+mst_fpga_set_irq(void *opaque, int irq, int level)
+{
+ mst_irq_state *s = (mst_irq_state *)opaque;
+
+ if (level)
+ s->prev_level |= 1u << irq;
+ else
+ s->prev_level &= ~(1u << irq);
+
+ if(s->intmskena & (1u << irq)) {
+ s->intsetclr = 1u << irq;
+ qemu_set_irq(s->parent[0], level);
+ }
+}
+
+
+static uint32_t
+mst_fpga_readb(void *opaque, target_phys_addr_t addr)
+{
+ mst_irq_state *s = (mst_irq_state *) opaque;
+ addr -= s->target_base;
+
+ switch (addr) {
+ case MST_LEDDAT1:
+ return s->leddat1;
+ case MST_LEDDAT2:
+ return s->leddat2;
+ case MST_LEDCTRL:
+ return s->ledctrl;
+ case MST_GPSWR:
+ return s->gpswr;
+ case MST_MSCWR1:
+ return s->mscwr1;
+ case MST_MSCWR2:
+ return s->mscwr2;
+ case MST_MSCWR3:
+ return s->mscwr3;
+ case MST_MSCRD:
+ return s->mscrd;
+ case MST_INTMSKENA:
+ return s->intmskena;
+ case MST_INTSETCLR:
+ return s->intsetclr;
+ case MST_PCMCIA0:
+ return s->pcmcia0;
+ case MST_PCMCIA1:
+ return s->pcmcia1;
+ default:
+ printf("Mainstone - mst_fpga_readb: Bad register offset "
+ REG_FMT " \n", addr);
+ }
+ return 0;
+}
+
+static void
+mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
+{
+ mst_irq_state *s = (mst_irq_state *) opaque;
+ addr -= s->target_base;
+ value &= 0x;
+
+ switch (addr) {
+ case MST_LEDDAT1:
+ s->leddat1 = value;
+ break;
+ case MST_LEDDAT2:
+ s->leddat2 = value;
+ break;
+ case MST_LEDCTRL:
+ s->ledctrl = value;
+ break;
+ case MST_GPSWR:
+ s->gpswr = value;
+ break;
+ case MST_MSCWR1:
+ s->mscwr1 = value;
+ break;
+ case MST_MSCWR2:
+ s->mscwr2 = value;
+ break;
+ case MST_MSCWR3:
+ s->mscwr3 = value;
+ break;
+ case MST_MSCRD:
+ s->mscrd = value;
+ break;
+ case MST_INTMSKENA: /* Mask interupt */
+ s->intmskena = (value & 0xFEEFF);
+ mst_fpga_update_gpio(s);
+ break;
+ case MST_INTSETCLR: /* clear or set interrupt */
+ s->intsetclr = (value & 0xFEEFF);
+ break;
+ case MST_PCMCIA0:
+ s->pcmcia0 = value;
+ break;
+ case MST_PCMCIA1:
+ s->pcmcia1 = value;
+ break;
+ default:
+ printf("Mainstone - mst_fpga_writeb: Bad regis
[Qemu-devel] pflash_register question
Hello, I see there are two instances of pflash_register() , one for pflash_cfi01.c and the other in pflash_cfi02.c. In order to get the proper one, I assume we use link order? - Armin
[Qemu-devel] Mainstone re-org
I though of this after my last patch, so my apologizes for the extra work.
I pulled the FPGA code out since it will be used by many other devices
on the Mainstone. I do not want to bloat the main file.
I am working on flash support now.
feedback and comments welcome.
Kind regards,
- Armin
Index: qemu/hw/mainstone.c
===
--- qemu.orig/hw/mainstone.c
+++ qemu/hw/mainstone.c
@@ -14,245 +14,7 @@
#include "net.h"
#include "devices.h"
#include "boards.h"
-
-#define MST_ETH_PHYS 0x1300
-#define MST_FPGA_PHYS 0x0800
-
-/* Mainstone FPGA for extern irqs */
-#define FPGA_GPIO_PIN 0
-#define MST_NUM_IRQS 16
-#define MST_BASE MST_FPGA_PHYS
-#define MST_LEDDAT1 0x10
-#define MST_LEDDAT2 0x14
-#define MST_LEDCTRL 0x40
-#define MST_GPSWR 0x60
-#define MST_MSCWR1 0x80
-#define MST_MSCWR2 0x84
-#define MST_MSCWR3 0x88
-#define MST_MSCRD 0x90
-#define MST_INTMSKENA 0xc0
-#define MST_INTSETCLR 0xd0
-#define MST_PCMCIA0 0xe0
-#define MST_PCMCIA1 0xe4
-
-/* IRQ definitions */
-#define ETHERNET_IRQ 3
-
-typedef struct mst_irq_state {
-target_phys_addr_t target_base;
-qemu_irq *parent;
-qemu_irq *pins;
-
-uint32_t prev_level;
-uint32_t leddat1;
-uint32_t leddat2;
-uint32_t ledctrl;
-uint32_t gpswr;
-uint32_t mscwr1;
-uint32_t mscwr2;
-uint32_t mscwr3;
-uint32_t mscrd;
-uint32_t intmskena;
-uint32_t intsetclr;
-uint32_t pcmcia0;
-uint32_t pcmcia1;
-} mst_irq_state;
-
-static void
-mst_fpga_update_gpio(mst_irq_state *s)
-{
-uint32_t level, diff;
-int bit;
-level = s->prev_level ^ s->intsetclr;
-
-for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
-bit = ffs(diff) - 1;
-qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
-}
-s->prev_level = level;
-}
-
-static void
-mst_fpga_set_irq(void *opaque, int irq, int level)
-{
-mst_irq_state *s = (mst_irq_state *)opaque;
-
-if (level)
-s->prev_level |= 1u << irq;
-else
-s->prev_level &= ~(1u << irq);
-
-if(s->intmskena & (1u << irq)) {
-s->intsetclr = 1u << irq;
-qemu_set_irq(s->parent[0], level);
-}
-}
-
-static uint32_t
-mst_fpga_readb(void *opaque, target_phys_addr_t addr)
-{
-mst_irq_state *s = (mst_irq_state *) opaque;
-addr -= s->target_base;
-
-switch (addr) {
-case MST_LEDDAT1:
-return s->leddat1;
-case MST_LEDDAT2:
-return s->leddat2;
-case MST_LEDCTRL:
-return s->ledctrl;
-case MST_GPSWR:
-return s->gpswr;
-case MST_MSCWR1:
-return s->mscwr1;
-case MST_MSCWR2:
-return s->mscwr2;
-case MST_MSCWR3:
-return s->mscwr3;
-case MST_MSCRD:
-return s->mscrd;
-case MST_INTMSKENA:
-return s->intmskena;
-case MST_INTSETCLR:
-return s->intsetclr;
-case MST_PCMCIA0:
-return s->pcmcia0;
-case MST_PCMCIA1:
-return s->pcmcia1;
-default:
-printf("Mainstone - mst_fpga_readb: Bad register offset "
-REG_FMT " \n", addr);
-}
-return 0;
-}
-
-static void
-mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
-{
-mst_irq_state *s = (mst_irq_state *) opaque;
-addr -= s->target_base;
-value &= 0x;
-
-switch (addr) {
-case MST_LEDDAT1:
-s->leddat1 = value;
-break;
-case MST_LEDDAT2:
-s->leddat2 = value;
-break;
-case MST_LEDCTRL:
-s->ledctrl = value;
-break;
-case MST_GPSWR:
-s->gpswr = value;
-break;
-case MST_MSCWR1:
-s->mscwr1 = value;
-break;
-case MST_MSCWR2:
-s->mscwr2 = value;
-break;
-case MST_MSCWR3:
-s->mscwr3 = value;
-break;
-case MST_MSCRD:
-s->mscrd = value;
-break;
-case MST_INTMSKENA: /* Mask interupt */
-s->intmskena = (value & 0xFEEFF);
-mst_fpga_update_gpio(s);
-break;
-case MST_INTSETCLR: /* clear or set interrupt */
-s->intsetclr = (value & 0xFEEFF);
-break;
-case MST_PCMCIA0:
-s->pcmcia0 = value;
-break;
-case MST_PCMCIA1:
-s->pcmcia1 = value;
-break;
-default:
-printf("Mainstone - mst_fpga_writeb: Bad register offset "
-REG_FMT " \n", addr);
-}
-}
-
-CPUReadMemoryFunc *mst_fpga_readfn[] = {
-mst_fpga_readb,
-mst_fpga_readb,
-mst_fpga_readb,
-};
-CPUWriteMemoryFunc *mst_fpga_writefn[] = {
-mst_fpga_writeb,
-mst_fpga_writeb,
-mst_fpga_writeb,
-};
-
-static void
-mst_fpga_save(QEMUFile *f, void *opaque)
-{
-struct mst_irq_state *s = (mst_irq_state *) opaque;
-
-qemu
Re: [Qemu-devel] pflash_register question
andrzej zaborowski wrote: On 25/11/2007, Armin <[EMAIL PROTECTED]> wrote: I see there are two instances of pflash_register() , one for pflash_cfi01.c and the other in pflash_cfi02.c. In order to get the proper one, I assume we use link order? No, ofcourse we will need to rename one of them. To be honest, I missed the fact that the functions collide when I merged pflash_cfi01.c. Regards Many thanks
[Qemu-devel] pflash usage question
Hello all, I have two questions regarding how to use pflash. 1) I have two 64MiB flash devices, so do I use one "-pflash" on the command line that has an image that is the total size of both flashes or use two "-pflash" on the command line. 2) The parameters for the pflash register are a bit confusing. The block size for my device is 64 but that does not work, I currently have tested it with 128. Also, the sector value, I could not find that reference in the datasheet for my flash. How should I use it? I used 128 * 1024 and that worked too. With the values I mentions above, I can mount the flash and us it as a root file system. I do get messages when I erase but I know that is not supported at the moment. If someone can set me straight on #1 and #2 then I will have be submitting flash support for the Mainstone shortly. TIA, Armin
[Qemu-devel] [Patch][update] Mainstone re-org plus flash
Hello,
This includes the previous Mainstone re-org patch I sent earlier plus
flash support.
This adds two 32MiB flash devices. Mounts from mtdblock2 on flash device
0 fine at boot.
TIA
Armin
Index: qemu/hw/mainstone.c
===
--- qemu.orig/hw/mainstone.c
+++ qemu/hw/mainstone.c
@@ -14,245 +14,9 @@
#include "net.h"
#include "devices.h"
#include "boards.h"
-
-#define MST_ETH_PHYS 0x1300
-#define MST_FPGA_PHYS 0x0800
-
-/* Mainstone FPGA for extern irqs */
-#define FPGA_GPIO_PIN 0
-#define MST_NUM_IRQS 16
-#define MST_BASE MST_FPGA_PHYS
-#define MST_LEDDAT1 0x10
-#define MST_LEDDAT2 0x14
-#define MST_LEDCTRL 0x40
-#define MST_GPSWR 0x60
-#define MST_MSCWR1 0x80
-#define MST_MSCWR2 0x84
-#define MST_MSCWR3 0x88
-#define MST_MSCRD 0x90
-#define MST_INTMSKENA 0xc0
-#define MST_INTSETCLR 0xd0
-#define MST_PCMCIA0 0xe0
-#define MST_PCMCIA1 0xe4
-
-/* IRQ definitions */
-#define ETHERNET_IRQ 3
-
-typedef struct mst_irq_state {
-target_phys_addr_t target_base;
-qemu_irq *parent;
-qemu_irq *pins;
-
-uint32_t prev_level;
-uint32_t leddat1;
-uint32_t leddat2;
-uint32_t ledctrl;
-uint32_t gpswr;
-uint32_t mscwr1;
-uint32_t mscwr2;
-uint32_t mscwr3;
-uint32_t mscrd;
-uint32_t intmskena;
-uint32_t intsetclr;
-uint32_t pcmcia0;
-uint32_t pcmcia1;
-} mst_irq_state;
-
-static void
-mst_fpga_update_gpio(mst_irq_state *s)
-{
-uint32_t level, diff;
-int bit;
-level = s->prev_level ^ s->intsetclr;
-
-for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
-bit = ffs(diff) - 1;
-qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
-}
-s->prev_level = level;
-}
-
-static void
-mst_fpga_set_irq(void *opaque, int irq, int level)
-{
-mst_irq_state *s = (mst_irq_state *)opaque;
-
-if (level)
-s->prev_level |= 1u << irq;
-else
-s->prev_level &= ~(1u << irq);
-
-if(s->intmskena & (1u << irq)) {
-s->intsetclr = 1u << irq;
-qemu_set_irq(s->parent[0], level);
-}
-}
-
-static uint32_t
-mst_fpga_readb(void *opaque, target_phys_addr_t addr)
-{
-mst_irq_state *s = (mst_irq_state *) opaque;
-addr -= s->target_base;
-
-switch (addr) {
-case MST_LEDDAT1:
-return s->leddat1;
-case MST_LEDDAT2:
-return s->leddat2;
-case MST_LEDCTRL:
-return s->ledctrl;
-case MST_GPSWR:
-return s->gpswr;
-case MST_MSCWR1:
-return s->mscwr1;
-case MST_MSCWR2:
-return s->mscwr2;
-case MST_MSCWR3:
-return s->mscwr3;
-case MST_MSCRD:
-return s->mscrd;
-case MST_INTMSKENA:
-return s->intmskena;
-case MST_INTSETCLR:
-return s->intsetclr;
-case MST_PCMCIA0:
-return s->pcmcia0;
-case MST_PCMCIA1:
-return s->pcmcia1;
-default:
-printf("Mainstone - mst_fpga_readb: Bad register offset "
-REG_FMT " \n", addr);
-}
-return 0;
-}
-
-static void
-mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
-{
-mst_irq_state *s = (mst_irq_state *) opaque;
-addr -= s->target_base;
-value &= 0x;
-
-switch (addr) {
-case MST_LEDDAT1:
-s->leddat1 = value;
-break;
-case MST_LEDDAT2:
-s->leddat2 = value;
-break;
-case MST_LEDCTRL:
-s->ledctrl = value;
-break;
-case MST_GPSWR:
-s->gpswr = value;
-break;
-case MST_MSCWR1:
-s->mscwr1 = value;
-break;
-case MST_MSCWR2:
-s->mscwr2 = value;
-break;
-case MST_MSCWR3:
-s->mscwr3 = value;
-break;
-case MST_MSCRD:
-s->mscrd = value;
-break;
-case MST_INTMSKENA: /* Mask interupt */
-s->intmskena = (value & 0xFEEFF);
-mst_fpga_update_gpio(s);
-break;
-case MST_INTSETCLR: /* clear or set interrupt */
-s->intsetclr = (value & 0xFEEFF);
-break;
-case MST_PCMCIA0:
-s->pcmcia0 = value;
-break;
-case MST_PCMCIA1:
-s->pcmcia1 = value;
-break;
-default:
-printf("Mainstone - mst_fpga_writeb: Bad register offset "
-REG_FMT " \n", addr);
-}
-}
-
-CPUReadMemoryFunc *mst_fpga_readfn[] = {
-mst_fpga_readb,
-mst_fpga_readb,
-mst_fpga_readb,
-};
-CPUWriteMemoryFunc *mst_fpga_writefn[] = {
-mst_fpga_writeb,
-mst_fpga_writeb,
-mst_fpga_writeb,
-};
-
-static void
-mst_fpga_save(QEMUFile *f, void *opaque)
-{
-struct mst_irq_state *s = (mst_irq_state *) opaque;
-
-qemu_put_be32s(f, &s->prev_level);
-qemu_put_be32s(f, &s->leddat1);
-qemu_put_be32s(f
Re: [Qemu-devel] [Patch][update] Mainstone re-org plus flash
Thiemo, Thiemo Seufer wrote: Armin wrote: Hello, This includes the previous Mainstone re-org patch I sent earlier plus flash support. This adds two 32MiB flash devices. Mounts from mtdblock2 on flash device 0 fine at boot. I did some guesswork on the flash initialization to make it build with Laurent's -disk patch. Please check if it is still correct. works fine. Many thanks -Armin
[Qemu-devel] [Patch][Pxa2xx] Mainstone mmc support
Hello, Please consider this patch for inclusion. This adds MMC and the rest of the FPGA irq definitions for the Mainstone II Kind regards, Armin Index: qemu/hw/mainstone.c === --- qemu.orig/hw/mainstone.c +++ qemu/hw/mainstone.c @@ -76,6 +76,10 @@ static void mainstone_common_init(int ra } mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0); + +/* MMC/SD host */ +pxa2xx_mmci_handlers(cpu->mmc, mst_irq[MMC_IRQ], mst_irq[MMC_IRQ]); + smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]); arm_load_kernel(cpu->env, mainstone_ram, kernel_filename, kernel_cmdline, Index: qemu/hw/mainstone.h === --- qemu.orig/hw/mainstone.h +++ qemu/hw/mainstone.h @@ -17,7 +17,20 @@ #define MST_FLASH_1 0x0400 /* IRQ definitions */ -#define ETHERNET_IRQ 3 +#define MMC_IRQ 0 +#define USIM_IRQ 1 +#define USBC_IRQ 2 +#define ETHERNET_IRQ 3 +#define AC97_IRQ 4 +#define PEN_IRQ 5 +#define MSINS_IRQ 6 +#define EXBRD_IRQ 7 +#define S0_CD_IRQ 9 +#define S0_STSCHG_IRQ 10 +#define S0_IRQ11 +#define S1_CD_IRQ 13 +#define S1_STSCHG_IRQ 14 +#define S1_IRQ15 extern qemu_irq *mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq);
Re: [Qemu-devel] [Patch][Pxa2xx] Mainstone mmc support
Andrzej, andrzej zaborowski wrote: On 08/12/2007, Armin <[EMAIL PROTECTED]> wrote: Hello, Please consider this patch for inclusion. This adds MMC and the rest of the FPGA irq definitions for the Mainstone II Why are both the write-protect and card-detect signals being connected to one input? If one of the inputs doesn't exist then just pass NULL for the parameter, The write protect does not exist so I will change it to a "NULL" thanks, - Armin
Re: [Qemu-devel] [Patch][update] Mainstone re-org plus flash
andrzej zaborowski wrote: On 10/12/2007, andrzej zaborowski <[EMAIL PROTECTED]> wrote: On 02/12/2007, Armin <[EMAIL PROTECTED]> wrote: Thiemo, Thiemo Seufer wrote: Armin wrote: Hello, This includes the previous Mainstone re-org patch I sent earlier plus flash support. This adds two 32MiB flash devices. Mounts from mtdblock2 on flash device 0 fine at boot. I did some guesswork on the flash initialization to make it build with Laurent's -disk patch. Please check if it is still correct. works fine. Note that both chips get mapped at the same offset in phys_ram_base, I'm quite sure this is a bug and not intentional? It may corrupt data if the OS reads from both chips. I wanted to convert mainstone.c to use qemu_ram_alloc like other pxa boards but I want to make sure this is not intentional. The value of mainstone_rom indicates this too. Sorry, mainstone_rom is not related to this issue, but that means that the ram_size check allows too low values and qemu may crash. It also means that the two flash chips *and* the ROM all overlap. I think gumstix.c registers the flash correctly, you may wnat to look in it. Regards will do. I seem to remember that the two mappings are mutually exclusive and possible controlled by an external switch.. I will need to double check that. sorry for the trouble. -Armin
[Qemu-devel] [Patch 1/2][PXA27x] initial keypad support
Hello,
Please consider this for inclusion
Here is an attempt to add PXA27x keypad support. It currently only
supports the matrix type interface. It still needs direct and
mulitswitch support added.
Just wanted to get something out there for folks to pound on.
Comment and feedback welcome.
-Armin
Index: qemu/hw/pxa.h
===
--- qemu.orig/hw/pxa.h
+++ qemu/hw/pxa.h
@@ -13,6 +13,7 @@
# define PXA2XX_PIC_SSP3 0
# define PXA2XX_PIC_USBH2 2
# define PXA2XX_PIC_USBH1 3
+# define PXA2XX_PIC_KEYPAD 4
# define PXA2XX_PIC_PWRI2C 6
# define PXA25X_PIC_HWUART 7
# define PXA27X_PIC_OST_4_11 7
@@ -61,6 +62,52 @@
# define PXA2XX_INTERNAL_BASE 0x5c00
# define PXA2XX_INTERNAL_SIZE 0x4
+/* Keypad defines */
+#define KPC_AS (0x1 << 30) /* Automatic Scan bit */
+#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
+#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
+#define KPC_IMKP(0x1 << 21) /* Ignore Multiple Key Press */
+#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
+#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
+#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
+#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
+#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
+#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
+#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
+#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
+#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
+#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
+#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */
+#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
+#define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */
+#define KPC_REE1(0x1 << 3) /* Rotary Encoder1 Enable */
+#define KPC_REE0(0x1 << 2) /* Rotary Encoder0 Enable */
+#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
+#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
+
+#define KPDK_DKP(0x1 << 31)
+#define KPDK_DK7(0x1 << 7)
+#define KPDK_DK6(0x1 << 6)
+#define KPDK_DK5(0x1 << 5)
+#define KPDK_DK4(0x1 << 4)
+#define KPDK_DK3(0x1 << 3)
+#define KPDK_DK2(0x1 << 2)
+#define KPDK_DK1(0x1 << 1)
+#define KPDK_DK0(0x1 << 0)
+
+#define KPREC_OF1 (0x1 << 31)
+#define kPREC_UF1 (0x1 << 30)
+#define KPREC_OF0 (0x1 << 15)
+#define KPREC_UF0 (0x1 << 14)
+
+#define KPMK_MKP(0x1 << 31)
+#define KPAS_SO (0x1 << 31)
+#define KPASMKPx_SO (0x1 << 31)
+
+
+#define KPASMKPx_MKC(row, col) (1 << (row + 16 * (col % 2)))
+
+
/* pxa2xx_pic.c */
qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
@@ -120,6 +167,13 @@ i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2
struct pxa2xx_i2s_s;
struct pxa2xx_fir_s;
+/* pxa2xx_kpad.c */
+struct pxa2xx_keypad_s;
+struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base,
+qemu_irq irq);
+void pxa27_register_keyboard(struct pxa2xx_keypad_s *kp, int **keymap, int
+size);
+
struct pxa2xx_state_s {
CPUState *env;
qemu_irq *pic;
@@ -133,6 +187,7 @@ struct pxa2xx_state_s {
struct pxa2xx_pcmcia_s *pcmcia[2];
struct pxa2xx_i2s_s *i2s;
struct pxa2xx_fir_s *fir;
+struct pxa2xx_keypad_s *kp;
/* Power management */
target_phys_addr_t pm_base;
@@ -200,6 +255,25 @@ struct pxa2xx_i2s_s {
uint32_t fifo[16];
};
+#define PXAKBD_MAXROW 8
+#define PXAKBD_MAXCOL 8
+
+struct pxa2xx_keypad_s{
+target_phys_addr_t base;
+qemu_irq irq;
+ int keymap[PXAKBD_MAXCOL][PXAKBD_MAXROW];
+uint32_tkpc;
+uint32_tkpdk;
+uint32_tkprec;
+uint32_tkpmk;
+uint32_tkpas;
+uint32_tkpasmkp0;
+uint32_tkpasmkp1;
+uint32_tkpasmkp2;
+uint32_tkpasmkp3;
+uint32_tkpkdi;
+};
+
# define PA_FMT "0x%08lx"
# define REG_FMT "0x" TARGET_FMT_plx
Index: qemu/hw/pxa2xx.c
===
--- qemu.orig/hw/pxa2xx.c
+++ qemu/hw/pxa2xx.c
@@ -2156,6 +2156,7 @@ struct pxa2xx_state_s *pxa270_init(unsig
/* GPIO1 resets the processor */
/* The handler can be overridden by board-specific code */
pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
+ s->kp = pxa27x_keypad_init(0x4150, s->pic[PXA2XX_PIC_KEYPAD]);
return s;
}
Index: qemu/hw/pxa2xx_keypad.c
===
--- /dev/null
+++ qemu/hw/pxa2xx_keypad
[Qemu-devel] [Patch 2/2][PXA27x] Mainstone keypad support
This is the mainstone II keypad support for alpha numeric keypad.
excludes the multiswitch and rotatory switch support
Needs "[Patch 1/2][PXA27x] initial keypad support" patch in order to work
- Armin
Index: qemu/hw/mainstone.c
===
--- qemu.orig/hw/mainstone.c
+++ qemu/hw/mainstone.c
@@ -78,6 +78,7 @@ static void mainstone_common_init(int ra
}
mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);
+ mst_keyboard_register(cpu->kp);
/* MMC/SD host */
pxa2xx_mmci_handlers(cpu->mmc, NULL, mst_irq[MMC_IRQ]);
Index: qemu/hw/mst_kpad.c
===
--- /dev/null
+++ qemu/hw/mst_kpad.c
@@ -0,0 +1,30 @@
+/*
+ * PXA270-based Intel Mainstone Keypad support.
+ *
+ * Copyright (c) 2007 by Armin Kuster <[EMAIL PROTECTED]> or
+ *<[EMAIL PROTECTED]>
+ *
+ * This code is licensed under the GNU GPL v2.
+ */
+
+
+#include "hw.h"
+#include "pxa.h"
+
+/* main keypad layout */
+int mst_keymap[PXAKBD_MAXROW][PXAKBD_MAXCOL] = {
+ { 0x1e, 0x30, 0x2e, 0x20, 0x12, 0x21, -1, -1},
+ { 0x22, 0x23, 0x17, 0x24, 0x25, 0x26, -1, -1},
+ { 0x32, 0x31, 0x18, 0x19, 0x10, 0x13, -1, -1},
+ { 0x1f, 0x14, 0x16, 0x2f, 0x11, 0x2d, -1, -1},
+ { -1, -1, 0x15, 0x2c, -1, -1, -1, -1},
+ { 0xc7, 0x2a, 0x39, 0x39, -1, 0x1c, -1, -1},
+ { 0xc8, 0xd0, 0xcb, 0xcd, -1, -1, -1, -1},
+ { -1, -1, -1, -1, -1, -1, -1, -1}
+};
+
+void mst_keyboard_register(struct pxa2xx_keypad_s *kp)
+{
+ pxa27_register_keyboard(kp, mst_keymap, sizeof(mst_keymap));
+
+}
Index: qemu/hw/mainstone.h
===
--- qemu.orig/hw/mainstone.h
+++ qemu/hw/mainstone.h
@@ -34,5 +34,5 @@
extern qemu_irq
*mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq);
-
+extern void mst_keyboard_register(struct pxa2xx_keypad_s *kp);
#endif /* __MAINSTONE_H__ */
Index: qemu/Makefile.target
===
--- qemu.orig/Makefile.target
+++ qemu/Makefile.target
@@ -499,7 +499,7 @@ VL_OBJS+= pflash_cfi01.o gumstix.o
VL_OBJS+= spitz.o ide.o serial.o nand.o ecc.o
VL_OBJS+= omap.o omap_lcdc.o omap1_clk.o omap_mmc.o omap_i2c.o
VL_OBJS+= palm.o tsc210x.o
-VL_OBJS+= mst_fpga.o mainstone.o
+VL_OBJS+= mst_fpga.o mainstone.o mst_kpad.o
CPPFLAGS += -DHAS_AUDIO
endif
ifeq ($(TARGET_BASE_ARCH), sh4)
[Bug 1875080] [NEW] USB host device data transfer with control endpoint
Public bug reported: QEMU emulator version 4.2.0 Host -> Arch Linux kernel version: 5.4.34-1-lts Guest -> Various Linux Distros I sent a control message with data through endpoint zero. On the other side message is received with all fields correct except data buffer. I've tested the data field inside guest with usbmon and data field was correct but after packet leaved qemu, data filed is lost. ** Affects: qemu Importance: Undecided Status: New ** Summary changed: - USB host device data transfer of control endpoint + USB host device data transfer with control endpoint -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1875080 Title: USB host device data transfer with control endpoint Status in QEMU: New Bug description: QEMU emulator version 4.2.0 Host -> Arch Linux kernel version: 5.4.34-1-lts Guest -> Various Linux Distros I sent a control message with data through endpoint zero. On the other side message is received with all fields correct except data buffer. I've tested the data field inside guest with usbmon and data field was correct but after packet leaved qemu, data filed is lost. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1875080/+subscriptions
[Qemu-devel] [Bug 1010484] Re: slirp to accept non-local dns server
** Patch added: "removes checking for if dns server isn't in local subnet." https://bugs.launchpad.net/bugs/1010484/+attachment/3180767/+files/sliprp_dns_address.diff -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1010484 Title: slirp to accept non-local dns server Status in QEMU: New Bug description: current version of slirp doesn't allow feeded dns address to be outside of given network. in many scenarios you need to provide dns server that isn't local. this simple patch removes checking for if dns server isn't in local subnet. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1010484/+subscriptions
[Qemu-devel] [Bug 1010484] [NEW] slirp to accept non-local dns server
Public bug reported: current version of slirp doesn't allow feeded dns address to be outside of given network. in many scenarios you need to provide dns server that isn't local. this simple patch removes checking for if dns server isn't in local subnet. ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1010484 Title: slirp to accept non-local dns server Status in QEMU: New Bug description: current version of slirp doesn't allow feeded dns address to be outside of given network. in many scenarios you need to provide dns server that isn't local. this simple patch removes checking for if dns server isn't in local subnet. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1010484/+subscriptions
[Qemu-devel] Problems with bridge Networking
Well Maybe I know for some of you its a very commented and boring subject, :( But Im very desesperate. I use ubuntu 9.04 and i emulate a winxp I have the next problem I configure the tun/tap and all great any error, I have an IP from my dhcp, I can see my virtual machine (winxp) from my other computers, but In my virtual machine I cant connect to internet, I mean, when I start my browser it doenst resolve anything, I cant see google or any another web page Really its very weird. I hope some of you can help me, and thanks so much. I follow the next steps apt-get install qemu bla bla bla (all package :p) *apt-get install bridge-utils uml-utilities* *modprobe tun modprobe bridge modprobe kqemu * *# ifconfig eth1 down* *# brctl addbr br0* *# ifconfig eth1 0.0.0.0 promisc up* *# ifconfig br0 192.168.0.2 netmask 255.255.255.0 broadcast 192.168.0.255 up * *# brctl stp br0 off* *# brctl setfd br0 1* *# brctl sethello br0 1* *# brctl addif br0 eth1* *# route add default gw 192.168.0.1 dev br0 * vim /etc/qemu-ifup *#!/bin/sh* *ifconfig $1 0.0.0.0 promisc up* *brctl addif br0 $1* *chmod +x /etc/qemu-ifup Starting qemu **qemu -localtime -m 256 -boot c -hda winxp.img -net tap -net nic,model=rtl8139* Im doing something wrong? thanks for read, and I hope somebody help me, Im very desesperate thanks so much regards
[Qemu-devel] guest-exec of qemu-guest-agent fails on Windows guest
Hi everyone,
We are trying to use guest-exec[0] command of qemu-guest-agent. However,
discovered that whatever command we try to run, it ends up with the
following error on the host side:
> error: Guest agent is not responding: Guest agent not available for now
An example of what we run on the host side:
> virsh qemu-agent-command --domain armin_1 '{ "execute": "guest-exec",
"arguments": { "path": "C:/Windows/System32/ipconfig.exe",
"capture-output": false } }'
Because Windows was complaining about `gspawn-win64-helper-console.exe`
whenever we ran a command on host, we tried to run it directly from cli and
it failed on the following assertion:
> g_assert (argc >= ARG_COUNT); // [1]
This picture[2] might be a bit more useful as it includes the output of
`qemu-ga` in verbose mode.
Any idea how we can solve it and/or what we are doing wrong?
Thanks in advance.
[0]
https://github.com/qemu/qemu/blob/fbddc2e5608eb655493253d080598375db61a748/qga/qapi-schema.json#L1024
[1]
https://github.com/GNOME/glib/blob/8edcf67b0221efa3c2ada67c44eff29939b1704d/glib/gspawn-win32-helper.c#L208
[2] https://ibin.co/3GTVo4WXfR7a.png
---
Armin ranjbar
Re: [Qemu-devel] guest-exec of qemu-guest-agent fails on Windows guest
We have tried qemu-ga from Fedora [1] which didn't have guest-exec and guest-exec-status (qemu-ga -b ? didn't list them and running guest-exec returned command not found) and also build msi from HEAD ourselves. gspawn-exec files are there, when we try to run guest-exec command qemu-ga windows application (which is running on foreground for testing) fails at gspawn-win32-helper.c [2] assertion, what happens on windows is that the "gspawn-win32-helper application stopped working" dialog appears. [1] https://fedoraproject.org/wiki/Windows_Virtio_Drivers [2] https://github.com/GNOME/glib/blob/8edcf67b0221efa3c2ada67c44eff29939b1704d/glib/gspawn-win32-helper.c#L208 --- Armin ranjbar On Fri, Mar 24, 2017 at 7:33 PM, Michael Roth wrote: > What steps did you use to install qga? Did you use the .msi > installer? If not you'll need to make those glib helper executables > available to the agent by placing them in the install directory or > somewhere in its executable paths. The MSI installer should handle > all this for you. > >
