download.qemu.org file list
Hi, I am not sure if this is the right list to send this to, but the https://download.qemu.org/ download server is showing no files available for listing. Is this unintentional? Or should I be querying the Gitlab tags from now on for version info? Thanks, --Rahul
Re: [PATCH 22/22] accel/tcg: also suppress asynchronous IRQs for cpu_io_recompile
Hi Alex,
January 9, 2025 at 6:06 PM, "Alex Bennée" wrote:
> While it would be technically correct to allow an IRQ to happen (as
> the offending instruction never really completed) it messes up
> instrumentation. We already take care to only use memory
> instrumentation on the block, we should also suppress IRQs.
>
> Signed-off-by: Alex Bennée
> Cc: Richard Henderson
> Cc: Julian Ganz
> ---
> accel/tcg/translate-all.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index 453eb20ec9..d56ca13cdd 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -633,9 +633,10 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
> * Exit the loop and potentially generate a new TB executing the
> * just the I/O insns. We also limit instrumentation to memory
> * operations only (which execute after completion) so we don't
> - * double instrument the instruction.
> + * double instrument the instruction. Also don't let an IRQ sneak
> + * in before we execute it.
> */
> - cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | n;
> + cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_NOIRQ | n;
>
> if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
> vaddr pc = cpu->cc->get_pc(cpu);
> --
> 2.39.5
Reviewed-by: Julian Ganz
[PATCH v2 03/13] hw/char/imx_serial: Update all state before restarting ageing timer
Fixes characters to be "echoed" after each keystroke rather than after every
other since imx_serial_rx_fifo_ageing_timer_restart() would see ~UTS1_RXEMPTY
only after every other keystroke.
Signed-off-by: Bernhard Beschow
---
hw/char/imx_serial.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index f805da23ff..be06f39a4d 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -381,14 +381,14 @@ static void imx_put_data(void *opaque, uint32_t value)
if (fifo32_num_used(&s->rx_fifo) >= rxtl) {
s->usr1 |= USR1_RRDY;
}
-
-imx_serial_rx_fifo_ageing_timer_restart(s);
-
s->usr2 |= USR2_RDR;
s->uts1 &= ~UTS1_RXEMPTY;
if (value & URXD_BRK) {
s->usr2 |= USR2_BRCD;
}
+
+imx_serial_rx_fifo_ageing_timer_restart(s);
+
imx_update(s);
}
--
2.48.0
[PATCH v2 02/13] hw/char/imx_serial: Fix reset value of UFCR register
The value of the UCFR register is respected when echoing characters to the
terminal, but its reset value is reserved. Fix the reset value to the one
documented in the datasheet.
While at it move the related attribute out of the section of unimplemented
registers since its value is actually respected.
Signed-off-by: Bernhard Beschow
---
include/hw/char/imx_serial.h | 2 +-
hw/char/imx_serial.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index 65f0e97c76..90ba3ff18c 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -109,13 +109,13 @@ struct IMXSerialState {
uint32_t ucr1;
uint32_t ucr2;
uint32_t uts1;
+uint32_t ufcr;
/*
* The registers below are implemented just so that the
* guest OS sees what it has written
*/
uint32_t onems;
-uint32_t ufcr;
uint32_t ubmr;
uint32_t ubrc;
uint32_t ucr3;
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 12705a1337..f805da23ff 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -159,6 +159,7 @@ static void imx_serial_reset(IMXSerialState *s)
s->ucr3 = 0x700;
s->ubmr = 0;
s->ubrc = 4;
+s->ufcr = BIT(11) | BIT(0);
fifo32_reset(&s->rx_fifo);
timer_del(&s->ageing_timer);
--
2.48.0
[PATCH v2 05/13] hw/gpio/imx_gpio: Don't clear input GPIO values upon reset
Input GPIO values such as a present SD card may get notified before the GPIO controller itself gets reset. Claring the input values thus loses data. Assuming that input GPIO events are only fired when the state changes, the input values shouldn't be reset. Signed-off-by: Bernhard Beschow --- hw/gpio/imx_gpio.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c index 898f80f8c8..67c47a7280 100644 --- a/hw/gpio/imx_gpio.c +++ b/hw/gpio/imx_gpio.c @@ -302,7 +302,6 @@ static void imx_gpio_reset(DeviceState *dev) s->dr = 0; s->gdir = 0; -s->psr = 0; s->icr = 0; s->imr = 0; s->isr = 0; -- 2.48.0
[PATCH v2 11/13] hw/i2c/imx_i2c: Convert DPRINTF() to trace events
Also print the QOM canonical path when tracing which allows for distinguishing
the many instances a typical i.MX SoC has.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
---
hw/i2c/imx_i2c.c| 21 +
hw/i2c/trace-events | 5 +
2 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
index c565fd5b8a..d62213b9e0 100644
--- a/hw/i2c/imx_i2c.c
+++ b/hw/i2c/imx_i2c.c
@@ -25,18 +25,7 @@
#include "hw/i2c/i2c.h"
#include "qemu/log.h"
#include "qemu/module.h"
-
-#ifndef DEBUG_IMX_I2C
-#define DEBUG_IMX_I2C 0
-#endif
-
-#define DPRINTF(fmt, args...) \
-do { \
-if (DEBUG_IMX_I2C) { \
-fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_I2C, \
- __func__, ##args); \
-} \
-} while (0)
+#include "trace.h"
static const char *imx_i2c_get_regname(unsigned offset)
{
@@ -152,8 +141,8 @@ static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
break;
}
-DPRINTF("read %s [0x%" HWADDR_PRIx "] -> 0x%02x\n",
-imx_i2c_get_regname(offset), offset, value);
+trace_imx_i2c_read(DEVICE(s)->canonical_path, imx_i2c_get_regname(offset),
+ offset, value);
return (uint64_t)value;
}
@@ -163,8 +152,8 @@ static void imx_i2c_write(void *opaque, hwaddr offset,
{
IMXI2CState *s = IMX_I2C(opaque);
-DPRINTF("write %s [0x%" HWADDR_PRIx "] <- 0x%02x\n",
-imx_i2c_get_regname(offset), offset, (int)value);
+trace_imx_i2c_read(DEVICE(s)->canonical_path, imx_i2c_get_regname(offset),
+ offset, value);
value &= 0xff;
diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
index f708a7ace1..1ad0e95c0e 100644
--- a/hw/i2c/trace-events
+++ b/hw/i2c/trace-events
@@ -56,3 +56,8 @@ npcm7xx_smbus_recv_fifo(const char *id, uint8_t received,
uint8_t expected) "%s
pca954x_write_bytes(uint8_t value) "PCA954X write data: 0x%02x"
pca954x_read_data(uint8_t value) "PCA954X read data: 0x%02x"
+
+# imx_i2c.c
+
+imx_i2c_read(const char *id, const char *reg, uint64_t ofs, uint64_t value)
"%s:[%s (0x%" PRIx64 ")] -> 0x%02" PRIx64
+imx_i2c_write(const char *id, const char *reg, uint64_t ofs, uint64_t value)
"%s:[%s (0x%" PRIx64 ")] <- 0x%02" PRIx64
--
2.48.0
[PATCH v2 09/13] hw/timer/imx_gpt: Remove unused define
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
---
hw/timer/imx_gpt.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index 2663a9d9ef..11eca9fa4d 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -20,10 +20,6 @@
#include "qemu/log.h"
#include "trace.h"
-#ifndef DEBUG_IMX_GPT
-#define DEBUG_IMX_GPT 0
-#endif
-
static const char *imx_gpt_reg_name(uint32_t reg)
{
switch (reg) {
--
2.48.0
[PATCH v2 00/13] i.MX and SDHCI improvements
This series fixes some details in i.MX platform devices, improves SDHCI compatibility with U-Boot and modernizes some code. The first 5 patches are bugfixes 1/ resolving infinite loop in U-Boot esdhc driver, 2/ fixing a character echoing issue in imx-serial, 3/ fixing IRQ sharing issue in Designware PCIe emulation, and 4/ fixing GPIO level preservation across resets in imx-gpio. Patches 6 and 7 modernize SD card emulation by turning presence and write-protect GPIOs into qdev GPIOs and then further allowing the GPIOs to be inverted, just like device tree allows. The rest of the series is cosmetics including turning DPRINTF() into trace events which eases debugging. v2: * Drop redundant implementation of TYPE_OR_IRQ (David, Zoltan) * Use absolute QOM paths when tracing in imx_gpio and imx_i2c (Phil) * Trace hexadecimal values in imx_serial (Phil) * Do NOT move inversion of presence and write-protect GPIOs since that changes the internal logic of the device Bernhard Beschow (13): hw/sd/sdhci: Set SDHC_NIS_DMA bit when appropriate hw/char/imx_serial: Fix reset value of UFCR register hw/char/imx_serial: Update all state before restarting ageing timer hw/pci-host/designware: Expose MSI IRQ hw/gpio/imx_gpio: Don't clear input GPIO values upon reset hw/sd/sd: Remove legacy sd_set_cb() in favor of GPIOs hw/sd/sd: Allow for inverting polarities of presence and write-protect GPIOs hw/char/imx_serial: Turn some DPRINTF() statements into trace events hw/timer/imx_gpt: Remove unused define tests/qtest/libqos: Reuse TYPE_IMX_I2C define hw/i2c/imx_i2c: Convert DPRINTF() to trace events hw/misc/imx6_src: Convert DPRINTF() to trace events hw/gpio/imx_gpio: Turn DPRINTF() into trace events include/hw/arm/fsl-imx6.h | 4 +- include/hw/arm/fsl-imx7.h | 4 +- include/hw/char/imx_serial.h | 2 +- include/hw/pci-host/designware.h | 1 + include/hw/sd/sdcard_legacy.h | 1 - hw/arm/fsl-imx6.c | 13 - hw/arm/fsl-imx7.c | 13 - hw/char/imx_serial.c | 65 ++ hw/gpio/imx_gpio.c | 19 +++ hw/i2c/imx_i2c.c | 21 ++- hw/misc/imx6_src.c | 23 ++-- hw/pci-host/designware.c | 7 +-- hw/sd/sd.c | 39 ++--- hw/sd/sdhci.c | 11 +++- hw/timer/imx_gpt.c | 4 -- tests/qtest/libqos/arm-imx25-pdk-machine.c | 5 +- tests/qtest/libqos/i2c-imx.c | 4 +- hw/arm/Kconfig | 2 + hw/char/trace-events | 5 ++ hw/gpio/trace-events | 5 ++ hw/i2c/trace-events| 5 ++ hw/misc/trace-events | 6 ++ 22 files changed, 151 insertions(+), 108 deletions(-) -- 2.48.0
[PATCH v2 13/13] hw/gpio/imx_gpio: Turn DPRINTF() into trace events
While at it add a trace event for input GPIO events.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
---
hw/gpio/imx_gpio.c | 18 +++---
hw/gpio/trace-events | 5 +
2 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c
index 67c47a7280..25546221e0 100644
--- a/hw/gpio/imx_gpio.c
+++ b/hw/gpio/imx_gpio.c
@@ -24,6 +24,7 @@
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "trace.h"
#ifndef DEBUG_IMX_GPIO
#define DEBUG_IMX_GPIO 0
@@ -34,14 +35,6 @@ typedef enum IMXGPIOLevel {
IMX_GPIO_LEVEL_HIGH = 1,
} IMXGPIOLevel;
-#define DPRINTF(fmt, args...) \
-do { \
-if (DEBUG_IMX_GPIO) { \
-fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPIO, \
- __func__, ##args); \
-} \
-} while (0)
-
static const char *imx_gpio_reg_name(uint32_t reg)
{
switch (reg) {
@@ -111,6 +104,8 @@ static void imx_gpio_set(void *opaque, int line, int level)
IMXGPIOState *s = IMX_GPIO(opaque);
IMXGPIOLevel imx_level = level ? IMX_GPIO_LEVEL_HIGH : IMX_GPIO_LEVEL_LOW;
+trace_imx_gpio_set(DEVICE(s)->canonical_path, line, imx_level);
+
imx_gpio_set_int_line(s, line, imx_level);
/* this is an input signal, so set PSR */
@@ -200,7 +195,8 @@ static uint64_t imx_gpio_read(void *opaque, hwaddr offset,
unsigned size)
break;
}
-DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value);
+trace_imx_gpio_read(DEVICE(s)->canonical_path, imx_gpio_reg_name(offset),
+reg_value);
return reg_value;
}
@@ -210,8 +206,8 @@ static void imx_gpio_write(void *opaque, hwaddr offset,
uint64_t value,
{
IMXGPIOState *s = IMX_GPIO(opaque);
-DPRINTF("(%s, value = 0x%" PRIx32 ")\n", imx_gpio_reg_name(offset),
-(uint32_t)value);
+trace_imx_gpio_write(DEVICE(s)->canonical_path, imx_gpio_reg_name(offset),
+ value);
switch (offset) {
case DR_ADDR:
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index b91cc7e9a4..cea896b28f 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -1,5 +1,10 @@
# See docs/devel/tracing.rst for syntax documentation.
+# imx_gpio.c
+imx_gpio_read(const char *id, const char *reg, uint32_t value) "%s:[%s] ->
0x%" PRIx32
+imx_gpio_write(const char *id, const char *reg, uint32_t value) "%s:[%s] <-
0x%" PRIx32
+imx_gpio_set(const char *id, int line, int level) "%s:[%d] <- %d"
+
# npcm7xx_gpio.c
npcm7xx_gpio_read(const char *id, uint64_t offset, uint64_t value) " %s
offset: 0x%04" PRIx64 " value 0x%08" PRIx64
npcm7xx_gpio_write(const char *id, uint64_t offset, uint64_t value) "%s
offset: 0x%04" PRIx64 " value 0x%08" PRIx64
--
2.48.0
[PATCH v2 08/13] hw/char/imx_serial: Turn some DPRINTF() statements into trace events
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
---
hw/char/imx_serial.c | 58 +---
hw/char/trace-events | 5
2 files changed, 44 insertions(+), 19 deletions(-)
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index be06f39a4d..38b4865157 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -27,6 +27,7 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/fifo32.h"
+#include "trace.h"
#ifndef DEBUG_IMX_UART
#define DEBUG_IMX_UART 0
@@ -185,10 +186,10 @@ static uint64_t imx_serial_read(void *opaque, hwaddr
offset,
unsigned size)
{
IMXSerialState *s = (IMXSerialState *)opaque;
+Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
uint32_t c, rx_used;
uint8_t rxtl = s->ufcr & TL_MASK;
-
-DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
+uint64_t value;
switch (offset >> 2) {
case 0x0: /* URXD */
@@ -209,49 +210,67 @@ static uint64_t imx_serial_read(void *opaque, hwaddr
offset,
imx_serial_rx_fifo_ageing_timer_restart(s);
qemu_chr_fe_accept_input(&s->chr);
}
-return c;
+value = c;
+break;
case 0x20: /* UCR1 */
-return s->ucr1;
+value = s->ucr1;
+break;
case 0x21: /* UCR2 */
-return s->ucr2;
+value = s->ucr2;
+break;
case 0x25: /* USR1 */
-return s->usr1;
+value = s->usr1;
+break;
case 0x26: /* USR2 */
-return s->usr2;
+value = s->usr2;
+break;
case 0x2A: /* BRM Modulator */
-return s->ubmr;
+value = s->ubmr;
+break;
case 0x2B: /* Baud Rate Count */
-return s->ubrc;
+value = s->ubrc;
+break;
case 0x2d: /* Test register */
-return s->uts1;
+value = s->uts1;
+break;
case 0x24: /* UFCR */
-return s->ufcr;
+value = s->ufcr;
+break;
case 0x2c:
-return s->onems;
+value = s->onems;
+break;
case 0x22: /* UCR3 */
-return s->ucr3;
+value = s->ucr3;
+break;
case 0x23: /* UCR4 */
-return s->ucr4;
+value = s->ucr4;
+break;
case 0x29: /* BRM Incremental */
-return 0x0; /* TODO */
+value = 0x0; /* TODO */
+break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
-return 0;
+value = 0;
+break;
}
+
+trace_imx_serial_read(chr ? chr->label : "NODEV", offset, value);
+
+return value;
}
static void imx_serial_write(void *opaque, hwaddr offset,
@@ -261,8 +280,7 @@ static void imx_serial_write(void *opaque, hwaddr offset,
Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
unsigned char ch;
-DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
-offset, (unsigned int)value, chr ? chr->label : "NODEV");
+trace_imx_serial_write(chr ? chr->label : "NODEV", offset, value);
switch (offset >> 2) {
case 0x10: /* UTXD */
@@ -374,9 +392,11 @@ static int imx_can_receive(void *opaque)
static void imx_put_data(void *opaque, uint32_t value)
{
IMXSerialState *s = (IMXSerialState *)opaque;
+Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
uint8_t rxtl = s->ufcr & TL_MASK;
-DPRINTF("received char\n");
+trace_imx_serial_put_data(chr ? chr->label : "NODEV", value);
+
imx_serial_rx_fifo_push(s, value);
if (fifo32_num_used(&s->rx_fifo) >= rxtl) {
s->usr1 |= USR1_RRDY;
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 59e1f734a7..92e002da7a 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -52,6 +52,11 @@ escc_sunkbd_event_out(int ch) "Translated keycode 0x%2.2x"
escc_kbd_command(int val) "Command %d"
escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d
buttons=0x%01x"
+# imx_serial.c
+imx_serial_read(const char *chrname, uint64_t addr, uint64_t value)
"%s:[0x%03" PRIu64 "] -> 0x%08" PRIx64
+imx_serial_write(const char *chrname, uint64_t addr, uint64_t value)
"%s:[0x%03" PRIu64 "] <- 0x%08" PRIx64
+imx_serial_put_data(const char *chrname, uint32_t value) "%s: 0x%" PRIx32
+
# pl011.c
pl011_irq_state(int level) "irq state %d"
pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x
value 0x%08x reg %s"
--
2.48.0
[PATCH v2 04/13] hw/pci-host/designware: Expose MSI IRQ
Fixes INTD and MSI interrupts poking the same IRQ line without keeping track of
each other's IRQ level. Furthermore, SoCs such as the i.MX 8M Plus don't share
the MSI IRQ with the INTx lines, so expose it as a dedicated pin.
Signed-off-by: Bernhard Beschow
---
include/hw/arm/fsl-imx6.h| 4 +++-
include/hw/arm/fsl-imx7.h| 4 +++-
include/hw/pci-host/designware.h | 1 +
hw/arm/fsl-imx6.c| 13 -
hw/arm/fsl-imx7.c| 13 -
hw/pci-host/designware.c | 7 +++
hw/arm/Kconfig | 2 ++
7 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index 61c593ffd2..9da32fc189 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -33,6 +33,7 @@
#include "hw/usb/chipidea.h"
#include "hw/usb/imx-usb-phy.h"
#include "hw/pci-host/designware.h"
+#include "hw/or-irq.h"
#include "exec/memory.h"
#include "cpu.h"
#include "qom/object.h"
@@ -73,6 +74,7 @@ struct FslIMX6State {
ChipideaState usb[FSL_IMX6_NUM_USBS];
IMXFECStateeth;
DesignwarePCIEHost pcie;
+OrIRQState pcie4_msi_irq;
MemoryRegion rom;
MemoryRegion caam;
MemoryRegion ocram;
@@ -457,7 +459,7 @@ struct FslIMX6State {
#define FSL_IMX6_PCIE1_IRQ 120
#define FSL_IMX6_PCIE2_IRQ 121
#define FSL_IMX6_PCIE3_IRQ 122
-#define FSL_IMX6_PCIE4_IRQ 123
+#define FSL_IMX6_PCIE4_MSI_IRQ 123
#define FSL_IMX6_DCIC1_IRQ 124
#define FSL_IMX6_DCIC2_IRQ 125
#define FSL_IMX6_MLB150_HIGH_IRQ 126
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index 411fa1c2e3..aa7818c499 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -36,6 +36,7 @@
#include "hw/net/imx_fec.h"
#include "hw/pci-host/designware.h"
#include "hw/usb/chipidea.h"
+#include "hw/or-irq.h"
#include "cpu.h"
#include "qom/object.h"
#include "qemu/units.h"
@@ -85,6 +86,7 @@ struct FslIMX7State {
IMX7GPRState gpr;
ChipideaState usb[FSL_IMX7_NUM_USBS];
DesignwarePCIEHost pcie;
+OrIRQState pcie4_msi_irq;
MemoryRegion rom;
MemoryRegion caam;
MemoryRegion ocram;
@@ -428,7 +430,7 @@ enum FslIMX7IRQs {
FSL_IMX7_PCI_INTA_IRQ = 125,
FSL_IMX7_PCI_INTB_IRQ = 124,
FSL_IMX7_PCI_INTC_IRQ = 123,
-FSL_IMX7_PCI_INTD_IRQ = 122,
+FSL_IMX7_PCI_INTD_MSI_IRQ = 122,
FSL_IMX7_UART7_IRQ= 126,
diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
index c484e377a8..bf8b278978 100644
--- a/include/hw/pci-host/designware.h
+++ b/include/hw/pci-host/designware.h
@@ -86,6 +86,7 @@ struct DesignwarePCIEHost {
MemoryRegion io;
qemu_irq irqs[4];
+qemu_irq msi;
} pci;
MemoryRegion mmio;
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index ac8c66e242..88b9ccff49 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -106,6 +106,8 @@ static void fsl_imx6_init(Object *obj)
object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
+object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq,
+TYPE_OR_IRQ);
}
static void fsl_imx6_realize(DeviceState *dev, Error **errp)
@@ -435,14 +437,23 @@ static void fsl_imx6_realize(DeviceState *dev, Error
**errp)
sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR);
+object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2,
+&error_abort);
+qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort);
+
+irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_MSI_IRQ);
+qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq);
+
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
-irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_IRQ);
+irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
+irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1);
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq);
/*
* PCIe PHY
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 05e3389fbe..004bf49937 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -150,6 +150,8 @@ static void fsl_imx7_init(Object *obj)
* PCIE
*/
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
+object_initialize_child(obj, "pcie4-msi-
[PATCH v2 12/13] hw/misc/imx6_src: Convert DPRINTF() to trace events
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
---
hw/misc/imx6_src.c | 23 +--
hw/misc/trace-events | 6 ++
2 files changed, 11 insertions(+), 18 deletions(-)
diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
index dc6a2b92ba..06cc46292e 100644
--- a/hw/misc/imx6_src.c
+++ b/hw/misc/imx6_src.c
@@ -17,18 +17,7 @@
#include "qemu/module.h"
#include "target/arm/arm-powerctl.h"
#include "hw/core/cpu.h"
-
-#ifndef DEBUG_IMX6_SRC
-#define DEBUG_IMX6_SRC 0
-#endif
-
-#define DPRINTF(fmt, args...) \
-do { \
-if (DEBUG_IMX6_SRC) { \
-fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX6_SRC, \
- __func__, ##args); \
-} \
-} while (0)
+#include "trace.h"
static const char *imx6_src_reg_name(uint32_t reg)
{
@@ -87,7 +76,7 @@ static void imx6_src_reset(DeviceState *dev)
{
IMX6SRCState *s = IMX6_SRC(dev);
-DPRINTF("\n");
+trace_imx6_src_reset();
memset(s->regs, 0, sizeof(s->regs));
@@ -111,7 +100,7 @@ static uint64_t imx6_src_read(void *opaque, hwaddr offset,
unsigned size)
}
-DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx6_src_reg_name(index), value);
+trace_imx6_src_read(imx6_src_reg_name(index), value);
return value;
}
@@ -134,8 +123,7 @@ static void imx6_clear_reset_bit(CPUState *cpu,
run_on_cpu_data data)
assert(bql_locked());
s->regs[SRC_SCR] = deposit32(s->regs[SRC_SCR], ri->reset_bit, 1, 0);
-DPRINTF("reg[%s] <= 0x%" PRIx32 "\n",
-imx6_src_reg_name(SRC_SCR), s->regs[SRC_SCR]);
+trace_imx6_clear_reset_bit(imx6_src_reg_name(SRC_SCR), s->regs[SRC_SCR]);
g_free(ri);
}
@@ -173,8 +161,7 @@ static void imx6_src_write(void *opaque, hwaddr offset,
uint64_t value,
return;
}
-DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx6_src_reg_name(index),
-(uint32_t)current_value);
+trace_imx6_src_write(imx6_src_reg_name(index), value);
change_mask = s->regs[index] ^ (uint32_t)current_value;
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 0f5d2b5666..cf1abe6928 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -253,6 +253,12 @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock =
%d) = %d"
ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
+# imx6_src.c
+imx6_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
+imx6_src_write(const char *reg_name, uint64_t value) "reg[%s] <= 0x%" PRIx64
+imx6_clear_reset_bit(const char *reg_name, uint32_t value) "reg[%s] <= 0x%"
PRIx32
+imx6_src_reset(void) ""
+
# imx7_src.c
imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
--
2.48.0
[PATCH v2 10/13] tests/qtest/libqos: Reuse TYPE_IMX_I2C define
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Fabiano Rosas
Signed-off-by: Bernhard Beschow
---
tests/qtest/libqos/arm-imx25-pdk-machine.c | 5 +++--
tests/qtest/libqos/i2c-imx.c | 4 ++--
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/tests/qtest/libqos/arm-imx25-pdk-machine.c
b/tests/qtest/libqos/arm-imx25-pdk-machine.c
index 8fe128fae8..2d8b754343 100644
--- a/tests/qtest/libqos/arm-imx25-pdk-machine.c
+++ b/tests/qtest/libqos/arm-imx25-pdk-machine.c
@@ -23,6 +23,7 @@
#include "libqos-malloc.h"
#include "qgraph.h"
#include "i2c.h"
+#include "hw/i2c/imx_i2c.h"
#define ARM_PAGE_SIZE4096
#define IMX25_PDK_RAM_START 0x8000
@@ -50,7 +51,7 @@ static void *imx25_pdk_get_driver(void *object, const char
*interface)
static QOSGraphObject *imx25_pdk_get_device(void *obj, const char *device)
{
QIMX25PDKMachine *machine = obj;
-if (!g_strcmp0(device, "imx.i2c")) {
+if (!g_strcmp0(device, TYPE_IMX_I2C)) {
return &machine->i2c_1.obj;
}
@@ -86,7 +87,7 @@ static void imx25_pdk_register_nodes(void)
.extra_device_opts = "bus=i2c-bus.0"
};
qos_node_create_machine("arm/imx25-pdk", qos_create_machine_arm_imx25_pdk);
-qos_node_contains("arm/imx25-pdk", "imx.i2c", &edge, NULL);
+qos_node_contains("arm/imx25-pdk", TYPE_IMX_I2C, &edge, NULL);
}
libqos_init(imx25_pdk_register_nodes);
diff --git a/tests/qtest/libqos/i2c-imx.c b/tests/qtest/libqos/i2c-imx.c
index 710cb926d6..6d868e4cc4 100644
--- a/tests/qtest/libqos/i2c-imx.c
+++ b/tests/qtest/libqos/i2c-imx.c
@@ -209,8 +209,8 @@ void imx_i2c_init(IMXI2C *s, QTestState *qts, uint64_t addr)
static void imx_i2c_register_nodes(void)
{
-qos_node_create_driver("imx.i2c", NULL);
-qos_node_produces("imx.i2c", "i2c-bus");
+qos_node_create_driver(TYPE_IMX_I2C, NULL);
+qos_node_produces(TYPE_IMX_I2C, "i2c-bus");
}
libqos_init(imx_i2c_register_nodes);
--
2.48.0
[PATCH v2 01/13] hw/sd/sdhci: Set SDHC_NIS_DMA bit when appropriate
In U-Boot, the fsl_esdhc[_imx] driver waits for both "transmit completed" and
"DMA" bits in esdhc_send_cmd_common() by means of DATA_COMPLETE constant. QEMU
currently misses to set the DMA bit which causes the driver to loop forever. Fix
that by setting the DMA bit if enabled when doing DMA block transfers.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
---
hw/sd/sdhci.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 299cd4bc1b..a958c11497 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -665,12 +665,13 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState
*s)
}
}
+if (s->norintstsen & SDHC_NISEN_DMA) {
+s->norintsts |= SDHC_NIS_DMA;
+}
+
if (s->blkcnt == 0) {
sdhci_end_transfer(s);
} else {
-if (s->norintstsen & SDHC_NISEN_DMA) {
-s->norintsts |= SDHC_NIS_DMA;
-}
sdhci_update_irq(s);
}
}
@@ -691,6 +692,10 @@ static void sdhci_sdma_transfer_single_block(SDHCIState *s)
}
s->blkcnt--;
+if (s->norintstsen & SDHC_NISEN_DMA) {
+s->norintsts |= SDHC_NIS_DMA;
+}
+
sdhci_end_transfer(s);
}
--
2.48.0
[PATCH v2 07/13] hw/sd/sd: Allow for inverting polarities of presence and write-protect GPIOs
Signed-off-by: Bernhard Beschow
---
hw/sd/sd.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index aa8d86e1af..a50e5c20c8 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -181,6 +181,8 @@ struct SDState {
qemu_irq inserted_cb;
QEMUTimer *ocr_power_timer;
bool enable;
+bool readonly_active_low;
+bool inserted_active_low;
uint8_t dat_lines;
bool cmd_line;
};
@@ -876,8 +878,8 @@ static void sd_reset(DeviceState *dev)
sd->cmd_line = true;
sd->multi_blk_cnt = 0;
-qemu_set_irq(sd->readonly_cb, sd_get_readonly(sd));
-qemu_set_irq(sd->inserted_cb, sd_get_inserted(sd));
+qemu_set_irq(sd->readonly_cb, sd_get_readonly(sd) ^
sd->readonly_active_low);
+qemu_set_irq(sd->inserted_cb, sd_get_inserted(sd) ^
sd->inserted_active_low);
}
static void sd_cardchange(void *opaque, bool load, Error **errp)
@@ -896,9 +898,9 @@ static void sd_cardchange(void *opaque, bool load, Error
**errp)
}
if (sd->me_no_qdev_me_kill_mammoth_with_rocks) {
-qemu_set_irq(sd->inserted_cb, inserted);
+qemu_set_irq(sd->inserted_cb, inserted ^ sd->inserted_active_low);
if (inserted) {
-qemu_set_irq(sd->readonly_cb, readonly);
+qemu_set_irq(sd->readonly_cb, readonly ^ sd->readonly_active_low);
}
} else {
sdbus = SD_BUS(qdev_get_parent_bus(dev));
@@ -2797,6 +2799,8 @@ static void emmc_realize(DeviceState *dev, Error **errp)
static const Property sdmmc_common_properties[] = {
DEFINE_PROP_DRIVE("drive", SDState, blk),
+DEFINE_PROP_BOOL("cd-active-low", SDState, inserted_active_low, false),
+DEFINE_PROP_BOOL("wp-active-low", SDState, readonly_active_low, false),
};
static const Property sd_properties[] = {
--
2.48.0
[PATCH v2 06/13] hw/sd/sd: Remove legacy sd_set_cb() in favor of GPIOs
Commit ce5dd27534b0 "hw/sd: Remove omap2_mmc device" removed the last user of
sd_set_cb(). Rework this functionality into GPIOs.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
---
include/hw/sd/sdcard_legacy.h | 1 -
hw/sd/sd.c| 31 ++-
2 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/include/hw/sd/sdcard_legacy.h b/include/hw/sd/sdcard_legacy.h
index 0dc3889555..a121232560 100644
--- a/include/hw/sd/sdcard_legacy.h
+++ b/include/hw/sd/sdcard_legacy.h
@@ -36,7 +36,6 @@ SDState *sd_init(BlockBackend *blk, bool is_spi);
int sd_do_command(SDState *card, SDRequest *request, uint8_t *response);
void sd_write_byte(SDState *card, uint8_t value);
uint8_t sd_read_byte(SDState *card);
-void sd_set_cb(SDState *card, qemu_irq readonly, qemu_irq insert);
/* sd_enable should not be used -- it is only used on the nseries boards,
* where it is part of a broken implementation of the MMC card slot switch
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 0330d432fd..aa8d86e1af 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -820,6 +820,16 @@ static inline uint64_t sd_addr_to_wpnum(uint64_t addr)
return addr >> (HWBLOCK_SHIFT + SECTOR_SHIFT + WPGROUP_SHIFT);
}
+static bool sd_get_inserted(SDState *sd)
+{
+return sd->blk && blk_is_inserted(sd->blk);
+}
+
+static bool sd_get_readonly(SDState *sd)
+{
+return sd->wp_switch;
+}
+
static void sd_reset(DeviceState *dev)
{
SDState *sd = SDMMC_COMMON(dev);
@@ -865,16 +875,9 @@ static void sd_reset(DeviceState *dev)
sd->dat_lines = 0xf;
sd->cmd_line = true;
sd->multi_blk_cnt = 0;
-}
-static bool sd_get_inserted(SDState *sd)
-{
-return sd->blk && blk_is_inserted(sd->blk);
-}
-
-static bool sd_get_readonly(SDState *sd)
-{
-return sd->wp_switch;
+qemu_set_irq(sd->readonly_cb, sd_get_readonly(sd));
+qemu_set_irq(sd->inserted_cb, sd_get_inserted(sd));
}
static void sd_cardchange(void *opaque, bool load, Error **errp)
@@ -1034,14 +1037,6 @@ SDState *sd_init(BlockBackend *blk, bool is_spi)
return sd;
}
-void sd_set_cb(SDState *sd, qemu_irq readonly, qemu_irq insert)
-{
-sd->readonly_cb = readonly;
-sd->inserted_cb = insert;
-qemu_set_irq(readonly, sd->blk ? !blk_is_writable(sd->blk) : 0);
-qemu_set_irq(insert, sd->blk ? blk_is_inserted(sd->blk) : 0);
-}
-
static void sd_blk_read(SDState *sd, uint64_t addr, uint32_t len)
{
trace_sdcard_read_block(addr, len);
@@ -2727,6 +2722,8 @@ static void sd_instance_init(Object *obj)
sd->last_cmd_name = "UNSET";
sd->enable = true;
sd->ocr_power_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sd_ocr_powerup, sd);
+qdev_init_gpio_out_named(DEVICE(sd), &sd->inserted_cb, "cd", 1);
+qdev_init_gpio_out_named(DEVICE(sd), &sd->readonly_cb, "wp", 1);
}
static void sd_instance_finalize(Object *obj)
--
2.48.0
[PATCH] target/riscv: Support Supm and Sspm as part of Zjpm v1.0
From: Alexey Baturo
The Zjpm v1.0 spec states there should be Supm and Sspm extensions that are
used in profile specification.
Enabling Supm extension enables both Ssnpm and Smnpm, while Sspm enables only
Smnpm.
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 23 +++
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dace670e5e..8c5801b87a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -202,10 +202,12 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm),
+ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm),
ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
+ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm),
ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
@@ -1612,6 +1614,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false),
MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
+MULTI_EXT_CFG_BOOL("sspm", ext_sspm, false),
+MULTI_EXT_CFG_BOOL("supm", ext_supm, false),
MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
@@ -2756,6 +2760,24 @@ static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = {
},
};
+static RISCVCPUImpliedExtsRule SUPM_IMPLIED = {
+.ext = CPU_CFG_OFFSET(ext_supm),
+.implied_multi_exts = {
+CPU_CFG_OFFSET(ext_ssnpm), CPU_CFG_OFFSET(ext_smnpm),
+
+RISCV_IMPLIED_EXTS_RULE_END
+},
+};
+
+static RISCVCPUImpliedExtsRule SSPM_IMPLIED = {
+.ext = CPU_CFG_OFFSET(ext_sspm),
+.implied_multi_exts = {
+CPU_CFG_OFFSET(ext_smnpm),
+
+RISCV_IMPLIED_EXTS_RULE_END
+},
+};
+
RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
&RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
&RVM_IMPLIED, &RVV_IMPLIED, NULL
@@ -2774,6 +2796,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]
= {
&ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
&ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
&ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED,
+&SUPM_IMPLIED, &SSPM_IMPLIED,
NULL
};
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index ee7c908710..76579b9b95 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -133,6 +133,8 @@ struct RISCVCPUConfig {
bool ext_ssnpm;
bool ext_smnpm;
bool ext_smmpm;
+bool ext_sspm;
+bool ext_supm;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
bool rvv_vl_half_avl;
--
2.39.5
Re: [PATCH v5 1/3] libqos/fw_cfg: refactor file directory iteraton to make it more reusable
On Fri, Jan 10, 2025 at 9:48 PM Philippe Mathieu-Daudé wrote: > > On 10/1/25 11:46, Ani Sinha wrote: > > fw-cfg file directory iteration code can be used by other functions that may > > want to implement fw-cfg file operations. Refactor it into a smaller helper > > so that it can be reused. > > > > No functional change. > > > > Signed-off-by: Ani Sinha > > --- > > tests/qtest/libqos/fw_cfg.c | 62 - > > 1 file changed, 40 insertions(+), 22 deletions(-) > > > > diff --git a/tests/qtest/libqos/fw_cfg.c b/tests/qtest/libqos/fw_cfg.c > > index 89f053ccac..b178d0b1b8 100644 > > --- a/tests/qtest/libqos/fw_cfg.c > > +++ b/tests/qtest/libqos/fw_cfg.c > > @@ -60,6 +60,38 @@ static void mm_fw_cfg_select(QFWCFG *fw_cfg, uint16_t > > key) > > qtest_writew(fw_cfg->qts, fw_cfg->base, key); > > } > > > > +static bool > > +find_pdir_entry(QFWCFG *fw_cfg, const char *filename, > > +uint16_t *sel, uint32_t *size) > > Please use QEMU coding style. btw, checkpatch did not catch this. I suggest we also fix checkpatch $ ./scripts/checkpatch.pl patches-v5/* Checking patches-v5/0001-libqos-fw_cfg-refactor-file-directory-iteraton-to-ma.patch... total: 0 errors, 0 warnings, 78 lines checked patches-v5/0001-libqos-fw_cfg-refactor-file-directory-iteraton-to-ma.patch has no obvious style problems and is ready for submission. Checking patches-v5/0002-tests-qtest-libqos-add-DMA-support-for-writing-and-r.patch... total: 0 errors, 0 warnings, 178 lines checked patches-v5/0002-tests-qtest-libqos-add-DMA-support-for-writing-and-r.patch has no obvious style problems and is ready for submission. Checking patches-v5/0003-tests-qtest-vmcoreinfo-add-a-unit-test-to-exercize-b.patch... total: 0 errors, 0 warnings, 111 lines checked patches-v5/0003-tests-qtest-vmcoreinfo-add-a-unit-test-to-exercize-b.patch has no obvious style problems and is ready for submission.
Re: [PATCH] MAINTAINERS: Update path to coreaudio.m
On Saturday, January 11, 2025 7:42:36 AM CET Akihiko Odaki wrote:
> Commit 8b46d7e2dc8e ("audio: Rename coreaudio extension to use
> Objective-C compiler") renamed coreaudio.c to coreaudio.m.
>
> Signed-off-by: Akihiko Odaki
> ---
Reviewed-by: Christian Schoenebeck
> MAINTAINERS | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 38a290e9c2ce..1e30c0f14057 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2786,7 +2786,7 @@ M: Marc-André Lureau
> S: Odd Fixes
> F: audio/
> X: audio/alsaaudio.c
> -X: audio/coreaudio.c
> +X: audio/coreaudio.m
> X: audio/dsound*
> X: audio/jackaudio.c
> X: audio/ossaudio.c
> @@ -2808,7 +2808,7 @@ M: Philippe Mathieu-Daudé
> R: Christian Schoenebeck
> R: Akihiko Odaki
> S: Odd Fixes
> -F: audio/coreaudio.c
> +F: audio/coreaudio.m
>
> DSound Audio backend
> M: Gerd Hoffmann
>
> ---
> base-commit: 38d0939b86e2eef6f6a622c6f1f7befda0146595
> change-id: 20250111-maintainers-28bbada9fd02
>
> Best regards,
>
Re: [PATCH v4 0/3] Enable clang build on Windows
Am 10.01.25 um 21:33 schrieb Pierrick Bouvier: For now, it was only possible to build plugins using GCC on Windows. However, windows-aarch64 only supports Clang. This biggest roadblock was to get rid of gcc_struct attribute, which is not supported by Clang. After investigation, we proved it was safe to drop it. Built and tested on Windows (all msys env)/Linux/MacOS for x86_64 and aarch64 hosts. v1 contained warning fixes and various bits that have been upstreamed already. The only bits left in this series are the gcc_struct removal, and fixing the plugins build with clang. This series is for 10.0, as we decided to not include the gcc_struct removal is 9.2 release. All patches are now reviewed, so this series can be pulled. I'll report that to MSYS2 too, so we can enable clang environments for QEMU. v1: https://patchew.org/QEMU/20241031040426.772604-1-pierrick.bouv...@linaro.org/ v2: - drop attribute gcc_struct instead of using -mno-ms-bitfields option - add a section about bitfields in documentation v3: - explain why gcc_struct attribute matters in packed structs in commit message - reword the bitfields documentation with suggestions given v4: - edit for bitfields doc requested by Philippe Pierrick Bouvier (3): win32: remove usage of attribute gcc_struct docs/devel/style: add a section about bitfield, and disallow them for packed structures plugins: enable linking with clang/lld docs/devel/style.rst | 20 +++ meson.build | 6 +++--- include/qemu/compiler.h | 7 +-- scripts/cocci-macro-file.h| 6 +- subprojects/libvhost-user/libvhost-user.h | 6 +- contrib/plugins/meson.build | 2 +- plugins/meson.build | 24 +++ tests/tcg/plugins/meson.build | 3 +-- 8 files changed, 48 insertions(+), 26 deletions(-) This nice series allows building QEMU for Windows with the LLVM cross compiler on my ARM64 machine, so you can add Tested-by: Stefan Weil I only needed a trivial additional fix in scripts/nsis.py for `make installer` because the usual GNU objdump and the LLVM objdump (or the cross x86_64-w64-mingw32-objdump in my test) produce slightly different output (indentation with \t, indentation with four spaces). I'll prepare a patch which eliminates the need for objdump, so no intermediate fix is needed for this. Stefan W.
[PULL v2 00/32] testing updates for 10.0 (tuxrun, libvirt, dockerfiles, misc)
The following changes since commit bc6afa1c711da5b4f37c9685a812c77b114d84cb: Merge tag 'pull-xenfv-20250109-1' of https://gitlab.com/dwmw2/qemu into staging (2025-01-09 08:39:32 -0500) are available in the Git repository at: https://gitlab.com/stsquad/qemu.git tags/pull-10.0-testing-updates-110125-1 for you to fetch changes up to ae0aef5e761ad6425c634f3d83b8cc5b52d1ce0a: MAINTAINERS: Remove myself from reviewers (2025-01-11 11:22:01 +) Testing updates for 10.0 - update the tuxrun images to the latest baseline - add the m68k tuxrun test - ensure qtest checks the result of clock_step operations - introduce new ztsd helper to functional tests - ensure aarch64_virt test exits early when no TCG - add new test to exercise virtio-vulkan - bump libvirt-ci to latest version - move riscv64 cross container from sid to trixie - remove workaround from mips containers now upstream updated - fix VM tests to use correct path for local QEMU binary - add ability to get a root debug shell on VM images - add keymap dependency to vnc tests - remove retiring maintainers from avocado and dockerfiles Alex Bennée (28): tests/functional: update the arm tuxrun tests tests/functional: update the i386 tuxrun tests tests/functional: add a m68k tuxrun tests tests/functional: update the mips32 tuxrun tests tests/functional: update the mips32el tuxrun tests tests/functional: update the mips64 tuxrun tests tests/functional: update the mips64el tuxrun tests tests/functional: update the ppc32 tuxrun tests tests/functional: update the ppc64 tuxrun tests tests/functional: update the riscv32 tuxrun tests tests/functional: update the riscv64 tuxrun tests tests/functional: update the s390x tuxrun tests tests/functional: update the sparc64 tuxrun tests tests/functional: update the x86_64 tuxrun tests tests/qtest: remove clock_steps from virtio tests system/qtest: properly feedback results of clock_[step|set] tests/functional: remove hacky sleep from the tests tests/functional: add zstd support to uncompress utility tests/functional: update tuxruntest to use uncompress utility tests/functional: remove unused kernel_command_line tests/functional: bail aarch64_virt tests early if missing TCG tests/functional: extend test_aarch64_virt with vulkan test tests/lcitool: bump to latest version of libvirt-ci tests/docker: move riscv64 cross container from sid to trixie tests/vm: fix build_path based path tests/vm: partially un-tabify help output tests/vm: allow interactive login as root pc-bios: ensure keymaps dependencies set vnc tests Daniel P. Berrangé (1): tests/lcitool: remove temp workaround for debian mips64el Philippe Mathieu-Daudé (1): dockerfiles: Remove 'MAINTAINER' entry in debian-tricore-cross.docker Pierrick Bouvier (1): tests/functional/aarch64: add tests for FEAT_RME Wainer dos Santos Moschetta (1): MAINTAINERS: Remove myself from reviewers MAINTAINERS| 3 +- system/qtest.c | 23 ++-- tests/qtest/libqos/virtio.c| 4 - .gitlab-ci.d/cirrus/freebsd-14.vars| 2 +- pc-bios/keymaps/meson.build| 17 ++- .../dockerfiles/debian-mips64el-cross.docker | 9 ++ .../docker/dockerfiles/debian-riscv64-cross.docker | 4 +- .../docker/dockerfiles/debian-tricore-cross.docker | 2 - tests/functional/meson.build | 5 + tests/functional/qemu_test/tuxruntest.py | 12 +-- tests/functional/qemu_test/uncompress.py | 24 + tests/functional/test_aarch64_rme_sbsaref.py | 69 tests/functional/test_aarch64_rme_virt.py | 98 + tests/functional/test_aarch64_virt.py | 119 + tests/functional/test_arm_tuxrun.py| 28 ++--- tests/functional/test_i386_tuxrun.py | 8 +- tests/functional/test_m68k_tuxrun.py | 34 ++ tests/functional/test_mips64_tuxrun.py | 8 +- tests/functional/test_mips64el_tuxrun.py | 8 +- tests/functional/test_mips_tuxrun.py | 8 +- tests/functional/test_mipsel_tuxrun.py | 8 +- tests/functional/test_ppc64_tuxrun.py | 16 +-- tests/functional/test_ppc_tuxrun.py| 8 +- tests/functional/test_riscv32_tuxrun.py| 8 +- tests/functional/test_riscv64_tuxrun.py| 16 +-- tests/functional/test_s390x_tuxrun.py | 8 +- tests/functional/test_sparc64_tuxrun.py| 8 +- tests/functional/test_x86_64_tuxrun.py | 8 +- test
Re: [RFC PATCH v3 04/11] contrib/plugins: add plugin showcasing new dicontinuity related API
Pierrick Bouvier writes:
> On 1/10/25 07:15, Alex Bennée wrote:
>> "Julian Ganz" writes:
>>
>>> Hi Alex,
>>>
>>> January 9, 2025 at 3:04 PM, "Alex Bennée" wrote:
Julian Ganz writes:
> We recently introduced new plugin API for registration of discontinuity
> related callbacks. This change introduces a minimal plugin showcasing
> the new API. It simply counts the occurances of interrupts, exceptions
> and host calls per CPU and reports the counts when exitting.
> ---
> contrib/plugins/meson.build | 3 +-
> contrib/plugins/traps.c | 96 +
> 2 files changed, 98 insertions(+), 1 deletion(-)
> create mode 100644 contrib/plugins/traps.c
>
> diff --git a/contrib/plugins/meson.build b/contrib/plugins/meson.build
> index 63a32c2b4f..9a3015e1c1 100644
> --- a/contrib/plugins/meson.build
> +++ b/contrib/plugins/meson.build
> @@ -1,5 +1,6 @@
> contrib_plugins = ['bbv', 'cache', 'cflow', 'drcov', 'execlog',
> 'hotblocks',
> - 'hotpages', 'howvec', 'hwprofile', 'ips', 'stoptrigger']
> + 'hotpages', 'howvec', 'hwprofile', 'ips', 'stoptrigger',
> + 'traps']
>
I wonder if this is better in tests/tcg/plugins? We need to do something
to ensure it gets covered by CI although we might want to be smarter
about running it together with a test binary that will actually pick up
something.
>>>
>>> The callback is intended as an example. The patch-series does contain a
>>> dedicated testing plugin. And iirc the contrib plugins are now built
>>> with the rest of qemu anyway?
>> They do - however we generate additional tests with
>> tests/tcg/plugins
>> with the existing multiarch linux-user and softmmu check-tcg tests. Its
>> a fairly dumb expansion though:
>># We need to ensure expand the run-plugin-TEST-with-PLUGIN
>># pre-requistes manually here as we can't use stems to handle it. We
>># only expand MULTIARCH_TESTS which are common on most of our targets
>># to avoid an exponential explosion as new tests are added. We also
>># add some special helpers the run-plugin- rules can use below.
>># In more, extra tests can be added using ADDITIONAL_PLUGINS_TESTS
>> variable.
>>ifneq ($(MULTIARCH_TESTS),)
>>$(foreach p,$(PLUGINS), \
>>$(foreach t,$(MULTIARCH_TESTS) $(ADDITIONAL_PLUGINS_TESTS),\
>>$(eval run-plugin-$(t)-with-$(p): $t $p) \
>>$(eval RUN_TESTS+=run-plugin-$(t)-with-$(p
>>endif # MULTIARCH_TESTS
>>endif # CONFIG_PLUGIN
>> We also have a hand-hacked test for validating memory
>> instrumentation:
>># Test plugin memory access instrumentation
>>run-plugin-test-plugin-mem-access-with-libmem.so: \
>>PLUGIN_ARGS=$(COMMA)print-accesses=true
>>run-plugin-test-plugin-mem-access-with-libmem.so: \
>>CHECK_PLUGIN_OUTPUT_COMMAND= \
>>$(SRC_PATH)/tests/tcg/multiarch/check-plugin-output.sh \
>>$(QEMU) $<
>>test-plugin-mem-access: CFLAGS+=-pthread -O0
>>test-plugin-mem-access: LDFLAGS+=-pthread -O0
>> That said as I mention in the reply to the cover letter the traps
>> stuff
>> might be better exercised with the functional test so could utilise a
>> plugin built in contrib just as easily.
>>
>
> I agree, as it was discussed in previous versions, we should add a
> functional test for this. I'm not sure if we should write a custom and
> complicated test, or simply boot and shutdown an existing image, and
> call it a day.
>
> Do you have any opinion on this Alex?
An existing image based test would be fine although I'd favour one that
had multiple exception types (e.g. something with firmware and
hypervisor transitions on Arm or equivalent on other arches.)
>
>>>
> +QEMU_PLUGIN_EXPORT
> +int qemu_plugin_install(qemu_plugin_id_t id, const qemu_info_t *info,
> + int argc, char **argv)
> +{
> + if (!info->system_emulation) {
> + fputs("trap plugin can only be used in system emulation mode.\n",
> + stderr);
> + return -1;
> + }
> +
> + max_vcpus = info->system.max_vcpus;
> + traps = qemu_plugin_scoreboard_new(sizeof(TrapCounters));
> + qemu_plugin_register_vcpu_init_cb(id, vcpu_init);
> + qemu_plugin_vcpu_for_each(id, vcpu_init);
>
Hmm at first glances this seems redundant - however I guess this is
covering the use case you load the plugin after the system is up and
running.
>>>
>>> Yep, but really that was just me being paranoid.
>>>
I wonder if you have unearthed a foot-gun in the API that is easy to
fall into? Maybe we should expand qemu_plugin_register_vcpu_init_cb to
call the call back immediately for existing vcpus?
>>>
>>> Would probably not hurt.
>>>
>>> Regards,
>>> Julian
>>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Re: [PULL 00/32] testing updates for 10.0 (tuxrun, libvirt, dockerfiles, misc)
Stefan Hajnoczi writes:
> On Fri, 10 Jan 2025 at 08:22, Alex Bennée wrote:
>>
>> The following changes since commit bc6afa1c711da5b4f37c9685a812c77b114d84cb:
>>
>> Merge tag 'pull-xenfv-20250109-1' of https://gitlab.com/dwmw2/qemu into
>> staging (2025-01-09 08:39:32 -0500)
>>
>> are available in the Git repository at:
>>
>> https://gitlab.com/stsquad/qemu.git tags/pull-10.0-testing-updates-100125-1
>>
>> for you to fetch changes up to 70b7c929ba39f15a94fbc63d9be88e8da907cc46:
>>
>> MAINTAINERS: Remove myself from reviewers (2025-01-10 11:18:38 +)
>>
>>
>> Testing updates for 10.0
>>
>> - update the tuxrun images to the latest baseline
>> - add the m68k tuxrun test
>> - ensure qtest checks the result of clock_step operations
>> - introduce new ztsd helper to functional tests
>> - ensure aarch64_virt test exits early when no TCG
>> - add new test to exercise virtio-vulkan
>
> Hi Alex,
> Please take a look at the following CI job failure and send a new
> revision of this pull request if something needs to be fixed:
> https://gitlab.com/qemu-project/qemu/-/jobs/8822037880#L593
Ahh the acceptance tests don't run automatically on my CI run. The
problem was the opensuse image doesn't see the DRI node. I've tweaked
the failure leg:
try:
self.vm.launch()
except VMLaunchFailure as excp:
if "old virglrenderer, blob resources unsupported" in excp.output:
self.skipTest("No blob support for virtio-gpu")
elif "old virglrenderer, venus unsupported" in excp.output:
self.skipTest("No venus support for virtio-gpu")
elif "egl: no drm render node available" in excp.output:
self.skipTest("Can't access host DRM render node")
else:
self.log.info(f"unhandled launch failure: {excp.output}")
raise excp
so it now catches that (and also fixes a small bug with the unhandled
case). I've posted v2 of the PR.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
[PATCH v2] checkpatch: Check .m, .build, .hx, .json and .plist
Check more text files: Objective-C, Meson, "hx", JSON, and property
list.
Signed-off-by: Akihiko Odaki
---
scripts/checkpatch.pl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 06d07e6c225c..94ac5230b48f 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -12,7 +12,7 @@ use Term::ANSIColor qw(:constants);
my $P = $0;
$P =~ s@.*/@@g;
-our $SrcFile= qr{\.(?:(h|c)(\.inc)?|cpp|s|S|pl|py|sh)$};
+our $SrcFile = qr{\.(?:(h|c|m)(\.inc)?|cpp|s|S|pl|py|sh|build|hx|json|plist)$};
my $V = '0.31';
---
base-commit: 38d0939b86e2eef6f6a622c6f1f7befda0146595
change-id: 20250111-checkpatch-26ea9d86c76a
Best regards,
--
Akihiko Odaki
Re: [PATCH] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache
On 11/8/24 8:01 AM, Jason Chien wrote:
This commit introduces a translation tag to avoid invalidating an entry
that should not be invalidated when IOMMU executes invalidation commands.
E.g. IOTINVAL.VMA with GV=0, AV=0, PSCV=1 invalidates both a mapping
of single stage translation and a mapping of nested translation with
the same PSCID, but only the former one should be invalidated.
Signed-off-by: Jason Chien
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/riscv-iommu.c | 205 ++---
1 file changed, 153 insertions(+), 52 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index ff9deefe37..ac6bbf91d6 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -64,8 +64,16 @@ struct RISCVIOMMUContext {
uint64_t msiptp;/* MSI redirection page table pointer */
};
+typedef enum RISCVIOMMUTransTag {
+RISCV_IOMMU_TRANS_TAG_BY, /* Bypass */
+RISCV_IOMMU_TRANS_TAG_SS, /* Single Stage */
+RISCV_IOMMU_TRANS_TAG_VG, /* G-stage only */
+RISCV_IOMMU_TRANS_TAG_VN, /* Nested translation */
+} RISCVIOMMUTransTag;
+
/* Address translation cache entry */
struct RISCVIOMMUEntry {
+RISCVIOMMUTransTag tag; /* Translation Tag */
uint64_t iova:44; /* IOVA Page Number */
uint64_t pscid:20; /* Process Soft-Context identifier */
uint64_t phys:44; /* Physical Page Number */
@@ -1228,7 +1236,7 @@ static gboolean riscv_iommu_iot_equal(gconstpointer v1,
gconstpointer v2)
RISCVIOMMUEntry *t1 = (RISCVIOMMUEntry *) v1;
RISCVIOMMUEntry *t2 = (RISCVIOMMUEntry *) v2;
return t1->gscid == t2->gscid && t1->pscid == t2->pscid &&
- t1->iova == t2->iova;
+ t1->iova == t2->iova && t1->tag == t2->tag;
}
static guint riscv_iommu_iot_hash(gconstpointer v)
@@ -1237,67 +1245,115 @@ static guint riscv_iommu_iot_hash(gconstpointer v)
return (guint)t->iova;
}
-/* GV: 1 PSCV: 1 AV: 1 */
+/* GV: 0 AV: 0 PSCV: 0 GVMA: 0 */
+/* GV: 0 AV: 0 GVMA: 1 */
+static
+void riscv_iommu_iot_inval_all(gpointer key, gpointer value, gpointer data)
+{
+RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value;
+RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data;
+if (iot->tag == arg->tag) {
+iot->perm = IOMMU_NONE;
+}
+}
+
+/* GV: 0 AV: 0 PSCV: 1 GVMA: 0 */
+static
+void riscv_iommu_iot_inval_pscid(gpointer key, gpointer value, gpointer data)
+{
+RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value;
+RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data;
+if (iot->tag == arg->tag &&
+iot->pscid == arg->pscid) {
+iot->perm = IOMMU_NONE;
+}
+}
+
+/* GV: 0 AV: 1 PSCV: 0 GVMA: 0 */
+static
+void riscv_iommu_iot_inval_iova(gpointer key, gpointer value, gpointer data)
+{
+RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value;
+RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data;
+if (iot->tag == arg->tag &&
+iot->iova == arg->iova) {
+iot->perm = IOMMU_NONE;
+}
+}
+
+/* GV: 0 AV: 1 PSCV: 1 GVMA: 0 */
static void riscv_iommu_iot_inval_pscid_iova(gpointer key, gpointer value,
gpointer data)
{
RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value;
RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data;
-if (iot->gscid == arg->gscid &&
+if (iot->tag == arg->tag &&
iot->pscid == arg->pscid &&
iot->iova == arg->iova) {
iot->perm = IOMMU_NONE;
}
}
-/* GV: 1 PSCV: 1 AV: 0 */
-static void riscv_iommu_iot_inval_pscid(gpointer key, gpointer value,
-gpointer data)
+/* GV: 1 AV: 0 PSCV: 0 GVMA: 0 */
+/* GV: 1 AV: 0 GVMA: 1 */
+static
+void riscv_iommu_iot_inval_gscid(gpointer key, gpointer value, gpointer data)
{
RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value;
RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data;
-if (iot->gscid == arg->gscid &&
-iot->pscid == arg->pscid) {
+if (iot->tag == arg->tag &&
+iot->gscid == arg->gscid) {
iot->perm = IOMMU_NONE;
}
}
-/* GV: 1 GVMA: 1 */
-static void riscv_iommu_iot_inval_gscid_gpa(gpointer key, gpointer value,
-gpointer data)
+/* GV: 1 AV: 0 PSCV: 1 GVMA: 0 */
+static void riscv_iommu_iot_inval_gscid_pscid(gpointer key, gpointer value,
+ gpointer data)
{
RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value;
RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data;
-if (iot->gscid == arg->gscid) {
-/* simplified cache, no GPA matching */
+if (iot->tag == arg->tag &&
+iot->gscid == arg->gscid &&
+iot->pscid == arg->pscid) {
iot->perm = IOMMU_NONE;
}
}
-/* GV: 1 GVMA: 0 */
-static void riscv_iommu_iot_inval_gscid(gpointer key, gpointer value,
-gpointer data)
+/* GV: 1 AV: 1 PSCV: 0 G
[PATCH] scripts/nsis.py: Run dependency check for each DLL file only once
Each DLL should only be checked once for dependencies, but
several hundred (781 in my test) unneeded checks were done.
Now the script is significantly faster (16 s in my build).
Signed-off-by: Stefan Weil
---
scripts/nsis.py | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/scripts/nsis.py b/scripts/nsis.py
index d0914c88a7..d0ac61f6ab 100644
--- a/scripts/nsis.py
+++ b/scripts/nsis.py
@@ -37,10 +37,10 @@ def find_deps(exe_or_dll, search_path, analyzed_deps):
analyzed_deps.add(dep)
# locate the dll dependencies recursively
-rdeps = find_deps(dll, search_path, analyzed_deps)
+analyzed_deps, rdeps = find_deps(dll, search_path, analyzed_deps)
deps.extend(rdeps)
-return deps
+return analyzed_deps, deps
def main():
parser = argparse.ArgumentParser(description="QEMU NSIS build helper.")
@@ -92,18 +92,18 @@ def main():
dlldir = os.path.join(destdir + prefix, "dll")
os.mkdir(dlldir)
+analyzed_deps = set()
for exe in glob.glob(os.path.join(destdir + prefix, "*.exe")):
signcode(exe)
# find all dll dependencies
-deps = set(find_deps(exe, search_path, set()))
+analyzed_deps, deps = find_deps(exe, search_path, analyzed_deps)
+deps = set(deps)
deps.remove(exe)
# copy all dlls to the DLLDIR
for dep in deps:
dllfile = os.path.join(dlldir, os.path.basename(dep))
-if (os.path.exists(dllfile)):
-continue
print("Copying '%s' to '%s'" % (dep, dllfile))
shutil.copy(dep, dllfile)
--
2.45.2
Re: [PATCH] MAINTAINERS: Update path to coreaudio.m
On 11/1/25 07:42, Akihiko Odaki wrote:
Commit 8b46d7e2dc8e ("audio: Rename coreaudio extension to use
Objective-C compiler") renamed coreaudio.c to coreaudio.m.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Oops, thanks!
Reviewed-by: Philippe Mathieu-Daudé
Queued.
Re: [PATCH v4 0/3] Enable clang build on Windows
On 10/1/25 21:37, Pierrick Bouvier wrote: On 1/10/25 12:33, Pierrick Bouvier wrote: For now, it was only possible to build plugins using GCC on Windows. However, windows-aarch64 only supports Clang. This biggest roadblock was to get rid of gcc_struct attribute, which is not supported by Clang. After investigation, we proved it was safe to drop it. Built and tested on Windows (all msys env)/Linux/MacOS for x86_64 and aarch64 hosts. v1 contained warning fixes and various bits that have been upstreamed already. The only bits left in this series are the gcc_struct removal, and fixing the plugins build with clang. This series is for 10.0, as we decided to not include the gcc_struct removal is 9.2 release. All patches are now reviewed, so this series can be pulled. I'll report that to MSYS2 too, so we can enable clang environments for QEMU. v1: https://patchew.org/QEMU/20241031040426.772604-1- pierrick.bouv...@linaro.org/ v2: - drop attribute gcc_struct instead of using -mno-ms-bitfields option - add a section about bitfields in documentation v3: - explain why gcc_struct attribute matters in packed structs in commit message - reword the bitfields documentation with suggestions given v4: - edit for bitfields doc requested by Philippe Pierrick Bouvier (3): win32: remove usage of attribute gcc_struct docs/devel/style: add a section about bitfield, and disallow them for packed structures plugins: enable linking with clang/lld docs/devel/style.rst | 20 +++ meson.build | 6 +++--- include/qemu/compiler.h | 7 +-- scripts/cocci-macro-file.h | 6 +- subprojects/libvhost-user/libvhost-user.h | 6 +- contrib/plugins/meson.build | 2 +- plugins/meson.build | 24 +++ tests/tcg/plugins/meson.build | 3 +-- 8 files changed, 48 insertions(+), 26 deletions(-) It would be nice if a maintainer could pull this, so we can get this merged upstream. That'd be Thomas or Alex I suppose.
