[PATCH] .gitignore: add .cache/ to .gitignore
$PROJECT/.cache/clangd/index is the intended location for project index data when using clangd as the language server. Ignore this directory to keep the git status clean. Signed-off-by: Wang, Lei --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 9726a778b3..8aab671265 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ /GNUmakefile /build/ +/.cache/ *.pyc .sdk .stgit-* -- 2.37.3
Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
On Tue, Sep 06, 2022 at 06:02:00PM +0530, Sunil V L wrote: > Hi Gerd, > > On Tue, Sep 06, 2022 at 12:41:28PM +0200, Gerd Hoffmann wrote: > > Hi, > > > > > 3)Make the EDK2 image size to match with what qemu flash expects > > > truncate -s 32M Build/RiscVVirt/DEBUG_GCC5/FV/RISCV_VIRT.fd > > > > Hmm, we have that kind of padding on arm too (64M for code and 64M for > > vars) and only a fraction of the space is actually used, which isn't > > exactly ideal. So not sure it is a good plan to repeat that on riscv. > > Yeah.. but it looks like limitation from qemu flash emulation. Do you mean > this limitation exists for arm in general on real flash also? Well, at least on x86 flash devices can have odd sizes. I don't think the qemu pflash emulation dictates anything here. I think the underlying problem we actually have in qemu is that the flash size indirectly dictates the memory layout. We pack the flash devices next to each other, on x86 downwards from 4G, on arm upwards from zero, not sure what risc-v is dong here. edk2 arm code expects the variable store being mapped at 64m. So QEMU_EFI.fd (which is actually 2M in size) gets padded to 64m, which has the desired effect that the next flash device (the varstore) is mapped at 64m. But also has the side effect that we map 62m of zeros into the guest address space ... The vars file is padded to 64m for consistency with the code. Not padding the vars file should have no bad side effects I think, except for live migration where the flash size change might cause compatibility problems. Not padding the code file needs some alternative way to specify the memory layout, to make sure the vars flash continues to be mapped at 64m even when the code flash is smaller. Cc'ed Pawel who investigates that right now. One possible option is to just hard-code the flash memory layout per machine type or per architecture. Another option would be to add some way to configure that on the command line. take care, Gerd
Re: Maximum QMP reply size
On Tue, Sep 06, 2022 at 03:38:54PM -0400, John Snow wrote: > Hi, I suspect I have asked this before, but I didn't write it down in > a comment, so I forget my justification... > > In the QMP lib, we need to set a buffering limit for how big a QMP > message can be -- In practice, I found that the largest possible > response was the QAPI schema reply, and I set the code to this: > > # Maximum allowable size of read buffer > _limit = (64 * 1024) > > However, I didn't document if this was a reasonable limit or just a > "worksforme" one. I assume that there's no hard limit for the protocol > or the implementation thereof in QEMU. Is there any kind of value here > that would be more sensible than another? > > I'm worried that if replies get bigger in the future (possibly in some > degenerate case I am presently unaware of) that the library default > will become nonsensical. > > Any pointers/tips? Beware of some of the blockdev commands, IIRC some of those could have huge replies, scaling based on the depth of the backing chains. While small in "normal" cases, people can do crazy things with 100's of backing chains. With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH v6 09/14] hw/ppc: set machine->fdt in pnv_reset()
On 9/5/22 01:34, Daniel Henrique Barboza wrote: This will enable support for the 'dumpdtb' QMP/HMP command for all powernv machines. Cc: Cédric Le Goater Cc: Frederic Barrat Signed-off-by: Daniel Henrique Barboza Reviewed-by: Cédric Le Goater Thanks, C. --- hw/ppc/pnv.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 354aa289d1..6a20c4811f 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -678,7 +678,13 @@ static void pnv_reset(MachineState *machine) qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); -g_free(fdt); +/* + * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free + * the existing machine->fdt to avoid leaking it during + * a reset. + */ +g_free(machine->fdt); +machine->fdt = fdt; } static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
Re: [PATCH 2/3] module: add Error arguments to module_load_one and module_load_qom_one
Hi, > For this module_load_qom_all() maybe Gerd has a bit more context on > was should be the error reporting here? Use case for module_load_qom_all() is someone enumerating the qom objects available. So we load all modules known to have all object types registered and can return a complete list. It could be that some of the known modules are not there. Consider a distro packaging modules which depend on shared libraries into optional sub-rpms, to reduce the dependency chain of core qemu. So, with core qemu installed and (some of) the sub-rpms not installed module_load_qom_all() will obviously fail to load some modules. But I don't think those errors should be reported. The object types implemented by the missing modules will also be missing from the object type list ... Example: hw-usb-host.so is not installed. => 'qemu -device help' should IMHO not report the module load error and just not list the 'usb-host' device. => 'qemu -device usb-host' should report the module load error. take care, Gerd
Re: [PATCH] accel: print an error message and exit if plugin not loaded
> > Ah I noticed only now... I just sent a series, the module_load_qom_all() > > then is maybe something to discuss further. > > > > Thanks, > > > > Claudio > > > > I noticed however that module_load_qom_all() does _not_ pass true for mayfail. > > You changed this behavior in: > > commit 9f4a0f0978cde9d8e27453b3f2d3679b53623c47 > Author: Gerd Hoffmann > Date: Thu Jun 24 12:38:17 2021 +0200 > > modules: use modinfo for qom load Oh. Not sure this was actually intentional or a cut+paste bug. The change looks unrelated. See also the other reply discussion missing modules + load_all() sent a few minutes ago. take care, Gerd
Re: Maximum QMP reply size
On Tue, Sep 06, 2022 at 03:38:54PM -0400, John Snow wrote: > Hi, I suspect I have asked this before, but I didn't write it down in > a comment, so I forget my justification... > > In the QMP lib, we need to set a buffering limit for how big a QMP > message can be -- In practice, I found that the largest possible > response was the QAPI schema reply, and I set the code to this: > > # Maximum allowable size of read buffer > _limit = (64 * 1024) > > However, I didn't document if this was a reasonable limit or just a > "worksforme" one. I assume that there's no hard limit for the protocol > or the implementation thereof in QEMU. Is there any kind of value here > that would be more sensible than another? As a reference, libvirt arbitrarily chose 10 MB as the QMP reply limit. It is huge enough it'll be hard to make a QMP reply exceed that, but also still tiny in the context of managing VMs on a host with GB's of RAM. NB, this doesn't mean we allocate 10 MB every time, it is just an upper bound - we only allocate what we actually need. With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH v3 2/2] x86: re-enable rng seeding via setup_data
On Tue, Sep 06, 2022 at 01:27:20PM +0200, Jason A. Donenfeld wrote:
> This reverts 3824e25db1 ("x86: disable rng seeding via setup_data"), but
> for 7.2 rather than 7.1, now that modifying setup_data is safe to do.
>
> Cc: Gerd Hoffmann
> Cc: Laurent Vivier
> Cc: Michael S. Tsirkin
> Cc: Paolo Bonzini
> Cc: Peter Maydell
> Cc: Philippe Mathieu-Daudé
> Cc: Richard Henderson
> Cc: Ard Biesheuvel
> Signed-off-by: Jason A. Donenfeld
Acked-by: Gerd Hoffmann
[PULL 04/44] target/riscv: move zmmul out of the experimental properties
From: Weiwei Li
- Zmmul is ratified and is now version 1.0
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20220710101546.3907-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cab74faaca..a3e4e2477f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1009,12 +1009,13 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
+
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
false),
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
-DEFINE_PROP_BOOL("x-zmmul", RISCVCPU, cfg.ext_zmmul, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
--
2.37.2
[PULL 19/44] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 10 ++
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
2 files changed, 11 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d1daa764b7..07ce671879 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1404,12 +1404,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
uint32_t vl = env->vl;\
uint32_t total_elems = env_archcpu(env)->cfg.vlen;\
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
+uint32_t vma = vext_vma(desc);\
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i));\
ETYPE s2 = *((ETYPE *)vs2 + H(i));\
if (!vm && !vext_elem_mask(v0, i)) { \
+/* set masked-off elements to 1s */ \
+if (vma) {\
+vext_set_elem_mask(vd, i, 1); \
+} \
continue; \
} \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
@@ -1462,11 +1467,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
uint32_t vl = env->vl; \
uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc);\
+uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) {\
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) {\
+/* set masked-off elements to 1s */ \
+if (vma) { \
+vext_set_elem_mask(vd, i, 1); \
+} \
continue; \
} \
vext_set_elem_mask(vd, i, \
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 83b85bb851..e6aa5295a1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1718,6 +1718,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = \
FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
+data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1),\
vreg_ofs(s, a->rs2), cpu_env, \
--
2.37.2
[PULL 09/44] target/riscv: Add check for csrs existed with U extension
From: Weiwei Li
Add umode/umode32 predicate for mcounteren, menvcfg/menvcfgh
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <20220718130955.11899-5-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7d4b6ceced..5c69dc838c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -339,6 +339,24 @@ static RISCVException hmode32(CPURISCVState *env, int
csrno)
}
+static RISCVException umode(CPURISCVState *env, int csrno)
+{
+if (riscv_has_ext(env, RVU)) {
+return RISCV_EXCP_NONE;
+}
+
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static RISCVException umode32(CPURISCVState *env, int csrno)
+{
+if (riscv_cpu_mxl(env) != MXL_RV32) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+return umode(env, csrno);
+}
+
/* Checks if PointerMasking registers could be accessed */
static RISCVException pointer_masking(CPURISCVState *env, int csrno)
{
@@ -3519,7 +3537,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MEDELEG] = { "medeleg",any, read_medeleg, write_medeleg },
[CSR_MIE] = { "mie",any, NULL, NULL, rmw_mie },
[CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
-[CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren,
+[CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren,
write_mcounteren },
[CSR_MSTATUSH]= { "mstatush", any32, read_mstatush,
@@ -3553,9 +3571,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
/* Execution environment configuration */
-[CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg,
+[CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
-[CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh,
+[CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
--
2.37.2
[PULL 05/44] hw/riscv: virt: pass random seed to fdt
From: "Jason A. Donenfeld"
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.
Cc: Alistair Francis
Signed-off-by: Jason A. Donenfeld
Reviewed-by: Bin Meng
Message-Id: <20220613115810.178210-1-ja...@zx2c4.com>
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index bc424dd2f5..f2ce5663a4 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
+#include "qemu/guest-random.h"
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/loader.h"
@@ -998,6 +999,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry
*memmap,
MachineState *mc = MACHINE(s);
uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
+uint8_t rng_seed[32];
if (mc->dtb) {
mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
@@ -1046,6 +1048,10 @@ update_bootargs:
if (cmdline && *cmdline) {
qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
}
+
+/* Pass seed to RNG */
+qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed,
sizeof(rng_seed));
}
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
--
2.37.2
[PULL 03/44] target/riscv: fix shifts shamt value for rv128c
From: Frédéric Pétrot
For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c
it stays 0 and is a hint instruction that does not change processor state.
For rv128c right shifts, the 6-bit shamt is in addition sign extended to
7 bits.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Weiwei Li
Reviewed-by: Richard Henderson
Message-Id: <20220710110451.245567-1-frederic.pet...@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis
---
target/riscv/insn16.decode | 7 ---
disas/riscv.c | 27 +--
target/riscv/translate.c | 20 ++--
3 files changed, 43 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 02c8f61b48..ccfe59f294 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -31,7 +31,8 @@
%imm_cb12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
%imm_cj12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
-%shimm_6bit 12:1 2:5 !function=ex_rvc_shifti
+%shlimm_6bit 12:1 2:5 !function=ex_rvc_shiftli
+%shrimm_6bit 12:1 2:5 !function=ex_rvc_shiftri
%uimm_6bit_lq 2:4 12:1 6:1 !function=ex_shift_4
%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
@@ -82,9 +83,9 @@
@c_addi16sp ... . . . .. &i imm=%imm_addi16sp rs1=2 rd=2
@c_shift... . .. ... . .. \
-&shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
+&shift rd=%rs1_3 rs1=%rs1_3 shamt=%shrimm_6bit
@c_shift2 ... . .. ... . .. \
-&shift rd=%rd rs1=%rd shamt=%shimm_6bit
+&shift rd=%rd rs1=%rd shamt=%shlimm_6bit
@c_andi ... . .. ... . .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
diff --git a/disas/riscv.c b/disas/riscv.c
index 7af6afc8fa..489c2ae5e8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2402,10 +2402,25 @@ static int32_t operand_sbimm12(rv_inst inst)
((inst << 56) >> 63) << 11;
}
-static uint32_t operand_cimmsh6(rv_inst inst)
+static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
{
-return ((inst << 51) >> 63) << 5 |
+int imm = ((inst << 51) >> 63) << 5 |
(inst << 57) >> 59;
+if (isa == rv128) {
+imm = imm ? imm : 64;
+}
+return imm;
+}
+
+static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
+{
+int imm = ((inst << 51) >> 63) << 5 |
+(inst << 57) >> 59;
+if (isa == rv128) {
+imm = imm | (imm & 32) << 1;
+imm = imm ? imm : 64;
+}
+return imm;
}
static int32_t operand_cimmi(rv_inst inst)
@@ -2529,7 +2544,7 @@ static uint32_t operand_rnum(rv_inst inst)
/* decode operands */
-static void decode_inst_operands(rv_decode *dec)
+static void decode_inst_operands(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
dec->codec = opcode_data[dec->op].codec;
@@ -2652,7 +2667,7 @@ static void decode_inst_operands(rv_decode *dec)
case rv_codec_cb_sh6:
dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
dec->rs2 = rv_ireg_zero;
-dec->imm = operand_cimmsh6(inst);
+dec->imm = operand_cimmshr6(inst, isa);
break;
case rv_codec_ci:
dec->rd = dec->rs1 = operand_crs1rd(inst);
@@ -2667,7 +2682,7 @@ static void decode_inst_operands(rv_decode *dec)
case rv_codec_ci_sh6:
dec->rd = dec->rs1 = operand_crs1rd(inst);
dec->rs2 = rv_ireg_zero;
-dec->imm = operand_cimmsh6(inst);
+dec->imm = operand_cimmshl6(inst, isa);
break;
case rv_codec_ci_16sp:
dec->rd = rv_ireg_sp;
@@ -3193,7 +3208,7 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa,
uint64_t pc, rv_inst inst)
dec.pc = pc;
dec.inst = inst;
decode_inst_opcode(&dec, isa);
-decode_inst_operands(&dec);
+decode_inst_operands(&dec, isa);
decode_inst_decompress(&dec, isa);
decode_inst_lift_pseudo(&dec);
format_inst(buf, buflen, 16, &dec);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f8af6daa70..6eeb728462 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -705,10 +705,26 @@ static int ex_rvc_register(DisasContext *ctx, int reg)
return 8 + reg;
}
-static int ex_rvc_shifti(DisasContext *ctx, int imm)
+static int ex_rvc_shiftli(DisasContext *ctx, int imm)
{
/* For RV128 a shamt of 0 means a shift by 64. */
-return imm ? imm : 64;
+if (get_ol(ctx) == MXL_RV128) {
+imm = imm ? imm : 64;
+}
+return imm;
+}
+
+static int ex_rvc_shiftri(DisasContext *ctx, int imm)
+{
+/*
+ * For RV128 a shamt of 0 means a shift by 64, furthermore, for right
+ * shifts, the shamt is sign-extended.
+ */
+if (get_ol(ctx) == MXL_RV128) {
+imm = imm | (imm & 32) << 1;
+imm = imm ? imm : 64;
+}
+return imm;
}
/* Include the auto-generated decoder for 32 bit insn *
[PULL 10/44] target/riscv: Fix checks in hmode/hmode32
From: Weiwei Li
Add check for the implicit dependence between H and S
Csrs only existed in RV32 will not trigger virtual instruction fault
when not in RV32 based on section 8.6.1 of riscv-privileged spec
(draft-20220717)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Message-Id: <20220718130955.11899-6-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 5 +
target/riscv/csr.c | 9 ++---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fb37ffac64..117d308ae5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -733,6 +733,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
+error_setg(errp, "H extension implicitly requires S-mode");
+return;
+}
+
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5c69dc838c..cf15aa67b7 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -311,8 +311,7 @@ static int aia_smode32(CPURISCVState *env, int csrno)
static RISCVException hmode(CPURISCVState *env, int csrno)
{
-if (riscv_has_ext(env, RVS) &&
-riscv_has_ext(env, RVH)) {
+if (riscv_has_ext(env, RVH)) {
/* Hypervisor extension is supported */
if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
env->priv == PRV_M) {
@@ -328,11 +327,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
static RISCVException hmode32(CPURISCVState *env, int csrno)
{
if (riscv_cpu_mxl(env) != MXL_RV32) {
-if (!riscv_cpu_virt_enabled(env)) {
-return RISCV_EXCP_ILLEGAL_INST;
-} else {
-return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-}
+return RISCV_EXCP_ILLEGAL_INST;
}
return hmode(env, csrno);
--
2.37.2
[PULL 02/44] target/riscv: Force disable extensions if priv spec version does not match
From: Anup Patel
We should disable extensions in riscv_cpu_realize() if minimum required
priv spec version is not satisfied. This also ensures that machines with
priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
extensions.
Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the device
tree")
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
Signed-off-by: Rahul Pathak
Message-Id: <20220630061150.905174-3-apa...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 150 -
1 file changed, 94 insertions(+), 56 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ac6f82ebd0..cab74faaca 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -43,9 +43,82 @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
struct isa_ext_data {
const char *name;
-bool enabled;
+bool multi_letter;
+int min_version;
+int ext_enable_offset;
};
+#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
+{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
+
+/**
+ * Here are the ordering rules of extension naming defined by RISC-V
+ * specification :
+ * 1. All extensions should be separated from other multi-letter extensions
+ *by an underscore.
+ * 2. The first letter following the 'Z' conventionally indicates the most
+ *closely related alphabetical extension category, IMAFDQLCBKJTPVH.
+ *If multiple 'Z' extensions are named, they should be ordered first
+ *by category, then alphabetically within a category.
+ * 3. Standard supervisor-level extensions (starts with 'S') should be
+ *listed after standard unprivileged extensions. If multiple
+ *supervisor-level extensions are listed, they should be ordered
+ *alphabetically.
+ * 4. Non-standard extensions (starts with 'X') must be listed after all
+ *standard extensions. They must be separated from other multi-letter
+ *extensions by an underscore.
+ */
+static const struct isa_ext_data isa_edata_arr[] = {
+ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
+ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v),
+ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
+ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
+ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
+ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
+ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
+ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
+ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
+ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
+ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
+ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb),
+ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc),
+ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx),
+ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs),
+ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk),
+ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn),
+ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd),
+ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne),
+ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh),
+ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr),
+ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks),
+ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed),
+ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh),
+ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
+ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
+ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
+ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
+ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
+ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
+ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
+ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
+};
+
+static bool isa_ext_is_enabled(RISCVCPU *cpu,
+ const struct isa_ext_data *edata)
+{
+bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
+
+return *ext_enabled;
+}
+
+static void isa_ext_update_enabled(RISCVCPU *cpu,
+ const struct isa_ext_data *edata, bool en)
+{
+bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
+
+*ext_enabled = en;
+}
+
const char * const riscv_int_regnames[] = {
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
@@ -530,7 +603,7 @@ static void riscv_cpu_re
[PULL 25/44] target/riscv: Add Zihintpause support
From: Dao Lu
Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.
Tested-by: Heiko Stuebner
Reviewed-by: Alistair Francis
Signed-off-by: Dao Lu
Message-Id: <20220725034728.2620750-2-da...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++-
target/riscv/cpu.c | 2 ++
target/riscv/insn_trans/trans_rvi.c.inc | 16
4 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 561d7fa92c..4be4b82a83 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -426,6 +426,7 @@ struct RISCVCPUConfig {
bool ext_zkt;
bool ext_ifencei;
bool ext_icsr;
+bool ext_zihintpause;
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4033565393..595fdcdad8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -149,7 +149,12 @@ srl 000 .. 101 . 0110011 @r
sra 010 .. 101 . 0110011 @r
or 000 .. 110 . 0110011 @r
and 000 .. 111 . 0110011 @r
-fence pred:4 succ:4 - 000 - 000
+
+{
+ pause 0001 0 000 0 000
+ fence pred:4 succ:4 - 000 - 000
+}
+
fence_i - 001 - 000
csrrw . 001 . 1110011 @csr
csrrs . 010 . 1110011 @csr
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 966e5f2dd7..d4635c7df4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -73,6 +73,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v),
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
+ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0,
ext_zihintpause),
ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
@@ -987,6 +988,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index ca8e3d1ea1..c49dbec0eb 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -792,6 +792,22 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
}
+static bool trans_pause(DisasContext *ctx, arg_pause *a)
+{
+if (!ctx->cfg_ptr->ext_zihintpause) {
+return false;
+}
+
+/*
+ * PAUSE is a no-op in QEMU,
+ * end the TB and return to main loop
+ */
+gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+tcg_gen_exit_tb(NULL, 0);
+ctx->base.is_jmp = DISAS_NORETURN;
+
+return true;
+}
static bool trans_fence(DisasContext *ctx, arg_fence *a)
{
--
2.37.2
[PULL 17/44] target/riscv: rvv: Add mask agnostic for vx instructions
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 3 +++
target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e3810d2bc3..6be3c4e739 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -899,10 +899,13 @@ static void do_vext_vx(void *vd, void *v0, target_long
s1, void *vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+uint32_t vma = vext_vma(desc);
uint32_t i;
for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+/* set masked-off elements to 1s */
+vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
continue;
}
fn(vd, s1, vs2, i);
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 0627eda0c0..07d86551a9 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1301,6 +1301,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1,
uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
+data = FIELD_DP32(data, VDATA, VMA, s->vma);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
@@ -1468,6 +1469,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm,
uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
+data = FIELD_DP32(data, VDATA, VMA, s->vma);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
--
2.37.2
[PULL 06/44] target/riscv: Add check for supported privilege mode combinations
From: Weiwei Li
There are 3 suggested privilege mode combinations listed in section 1.2
of the riscv-privileged spec(draft-20220717):
1) M, 2) M, U 3) M, S, U
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <20220718130955.11899-2-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a3e4e2477f..b919ad9056 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -721,6 +721,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
+error_setg(errp,
+ "Setting S extension without U extension is illegal");
+return;
+}
+
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
--
2.37.2
[PULL 26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()
From: Daniel Henrique Barboza
The 'fdt' param is not being used in riscv_setup_rom_reset_vec().
Simplify the API by removing it. While we're at it, remove the redundant
'return' statement at the end of function.
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Bin Meng
Cc: Vijai Kumar K
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220728181926.2123771-1-danielhb...@gmail.com>
Signed-off-by: Alistair Francis
---
include/hw/riscv/boot.h| 2 +-
hw/riscv/boot.c| 4 +---
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/shakti_c.c| 3 +--
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c| 2 +-
6 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index d2db29721a..a36f7618f5 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -51,7 +51,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine,
RISCVHartArrayState *harts
hwaddr saddr,
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
- uint64_t fdt_load_addr, void *fdt);
+ uint64_t fdt_load_addr);
void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
hwaddr rom_size,
uint32_t reset_vec_size,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 06b4fc5ac3..1ae7596873 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -286,7 +286,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine,
RISCVHartArrayState *harts
hwaddr start_addr,
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
- uint64_t fdt_load_addr, void *fdt)
+ uint64_t fdt_load_addr)
{
int i;
uint32_t start_addr_hi32 = 0x;
@@ -326,8 +326,6 @@ void riscv_setup_rom_reset_vec(MachineState *machine,
RISCVHartArrayState *harts
rom_base, &address_space_memory);
riscv_rom_copy_firmware_info(machine, rom_base, rom_size,
sizeof(reset_vec),
kernel_entry);
-
-return;
}
void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 10a5d0e501..7313153606 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -583,7 +583,7 @@ static void microchip_icicle_kit_machine_init(MachineState
*machine)
riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
- kernel_entry, fdt_load_addr, machine->fdt);
+ kernel_entry, fdt_load_addr);
}
}
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 90e2cf609f..e43cc9445c 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -66,8 +66,7 @@ static void shakti_c_machine_state_init(MachineState *mstate)
riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
shakti_c_memmap[SHAKTI_C_RAM].base,
shakti_c_memmap[SHAKTI_C_ROM].base,
- shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0,
- NULL);
+ shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0);
if (mstate->firmware) {
riscv_load_firmware(mstate->firmware,
shakti_c_memmap[SHAKTI_C_RAM].base,
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index e41b6aa9f0..5ba34543c8 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -308,7 +308,7 @@ static void spike_board_init(MachineState *machine)
riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
memmap[SPIKE_MROM].base,
memmap[SPIKE_MROM].size, kernel_entry,
- fdt_load_addr, s->fdt);
+ fdt_load_addr);
/* initialize HTIF using symbols found in load_kernel */
htif_mm_init(system_memory, mask_rom,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f2ce5663a4..c1e8e0fcaf 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1305,7 +1305,7 @@ static void virt_machine_done(Notifier *notifier, void
*data)
riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
virt_memmap[VIRT_MROM].base,
virt_memmap[VIRT_MROM].size, kernel_entry,
- fdt_load_addr, machine->fdt);
+ fdt_load_addr);
/*
* Only direct
[PULL 13/44] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V
From: Alexey Baturo
Fixes: 4302bef9e178 ("target/riscv: Calculate address according to XLEN")
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Message-Id: <20220717101543.478533-2-space.monkey.deliv...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6eeb728462..76da8db8a7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -544,7 +544,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
tcg_gen_addi_tl(addr, src1, imm);
if (ctx->pm_mask_enabled) {
-tcg_gen_and_tl(addr, addr, pm_mask);
+tcg_gen_andc_tl(addr, addr, pm_mask);
} else if (get_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
--
2.37.2
[PULL 08/44] target/riscv: Fix checkpatch warning may triggered in csr_ops table
From: Weiwei Li
Fix the lines with over 80 characters
Fix the lines which are obviously misalgined with other lines in the
same group
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <20220718130955.11899-4-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 441 -
1 file changed, 234 insertions(+), 207 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 235f2a011e..7d4b6ceced 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3461,20 +3461,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FRM] = { "frm", fs, read_frm, write_frm},
[CSR_FCSR] = { "fcsr", fs, read_fcsr,write_fcsr },
/* Vector CSRs */
-[CSR_VSTART] = { "vstart", vs,read_vstart, write_vstart,
- .min_priv_ver = PRIV_VERSION_1_12_0
},
-[CSR_VXSAT]= { "vxsat",vs,read_vxsat, write_vxsat,
- .min_priv_ver = PRIV_VERSION_1_12_0
},
-[CSR_VXRM] = { "vxrm", vs,read_vxrm,write_vxrm,
- .min_priv_ver = PRIV_VERSION_1_12_0
},
-[CSR_VCSR] = { "vcsr", vs,read_vcsr,write_vcsr,
- .min_priv_ver = PRIV_VERSION_1_12_0
},
-[CSR_VL] = { "vl", vs,read_vl,
- .min_priv_ver = PRIV_VERSION_1_12_0
},
-[CSR_VTYPE]= { "vtype",vs,read_vtype,
- .min_priv_ver = PRIV_VERSION_1_12_0
},
-[CSR_VLENB]= { "vlenb",vs,read_vlenb,
- .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
+[CSR_VXSAT]= { "vxsat",vs, read_vxsat, write_vxsat,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
+[CSR_VXRM] = { "vxrm", vs, read_vxrm,write_vxrm,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
+[CSR_VCSR] = { "vcsr", vs, read_vcsr,write_vcsr,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
+[CSR_VL] = { "vl", vs, read_vl,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
+[CSR_VTYPE]= { "vtype",vs, read_vtype,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
+[CSR_VLENB]= { "vlenb",vs, read_vlenb,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
/* User Timers and Counters */
[CSR_CYCLE]= { "cycle",ctr,read_hpmcounter },
[CSR_INSTRET] = { "instret", ctr,read_hpmcounter },
@@ -3493,10 +3493,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
-[CSR_MCYCLE]= { "mcycle",any, read_hpmcounter,
write_mhpmcounter},
-[CSR_MINSTRET] = { "minstret", any, read_hpmcounter,
write_mhpmcounter},
-[CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh,
write_mhpmcounterh},
-[CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh,
write_mhpmcounterh},
+[CSR_MCYCLE]= { "mcycle",any, read_hpmcounter,
+write_mhpmcounter},
+[CSR_MINSTRET] = { "minstret", any, read_hpmcounter,
+write_mhpmcounter},
+[CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh,
+write_mhpmcounterh },
+[CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh,
+write_mhpmcounterh },
/* Machine Information Registers */
[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
@@ -3505,23 +3509,25 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MHARTID] = { "mhartid", any, read_mhartid },
[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
-.min_priv_ver = PRIV_VERSION_1_12_0 },
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
/* Machine Trap Setup */
-[CSR_MSTATUS] = { "mstatus",any, read_mstatus,
write_mstatus, NULL,
- read_mstatus_i128
},
-[CSR_MISA]= { "misa", any, read_misa,write_misa,
NULL,
- read_misa_i128
},
-[CSR_MIDELEG] = { "mideleg",any, NULL,NULL,rmw_mideleg
},
-[CSR_MEDELEG] = { "medeleg",any, read_medeleg, write_medeleg
[PULL 01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
From: Anup Patel
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
Acked-by: dramforever
Message-Id: <20220630061150.905174-2-apa...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 5 +
target/riscv/instmap.h| 45 +++
target/riscv/cpu_helper.c | 252 +-
3 files changed, 296 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5c7acc055a..ffb1a18873 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -285,6 +285,11 @@ struct CPUArchState {
/* Signals whether the current exception occurred with two-stage address
translation active. */
bool two_stage_lookup;
+/*
+ * Signals whether the current exception occurred while doing two-stage
+ * address translation for the VS-stage page table walk.
+ */
+bool two_stage_indirect_lookup;
target_ulong scounteren;
target_ulong mcounteren;
diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h
index 40b6d2b64d..f877530576 100644
--- a/target/riscv/instmap.h
+++ b/target/riscv/instmap.h
@@ -184,6 +184,8 @@ enum {
OPC_RISC_CSRRWI = OPC_RISC_SYSTEM | (0x5 << 12),
OPC_RISC_CSRRSI = OPC_RISC_SYSTEM | (0x6 << 12),
OPC_RISC_CSRRCI = OPC_RISC_SYSTEM | (0x7 << 12),
+
+OPC_RISC_HLVHSV = OPC_RISC_SYSTEM | (0x4 << 12),
};
#define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
@@ -310,12 +312,20 @@ enum {
| (extract32(inst, 12, 8) << 12) \
| (sextract64(inst, 31, 1) << 20))
+#define GET_FUNCT3(inst) extract32(inst, 12, 3)
+#define GET_FUNCT7(inst) extract32(inst, 25, 7)
#define GET_RM(inst) extract32(inst, 12, 3)
#define GET_RS3(inst) extract32(inst, 27, 5)
#define GET_RS1(inst) extract32(inst, 15, 5)
#define GET_RS2(inst) extract32(inst, 20, 5)
#define GET_RD(inst) extract32(inst, 7, 5)
#define GET_IMM(inst) sextract64(inst, 20, 12)
+#define SET_RS1(inst, val) deposit32(inst, 15, 5, val)
+#define SET_RS2(inst, val) deposit32(inst, 20, 5, val)
+#define SET_RD(inst, val) deposit32(inst, 7, 5, val)
+#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val)
+#define SET_S_IMM(inst, val) \
+deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5)
/* RVC decoding macros */
#define GET_C_IMM(inst) (extract32(inst, 2, 5) \
@@ -346,6 +356,8 @@ enum {
| (extract32(inst, 5, 1) << 6))
#define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \
| (extract16(inst, 5, 2) << 6))
+#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst)
+#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst)
#define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \
| (extract32(inst, 11, 1) << 4) \
| (extract32(inst, 2, 1) << 5) \
@@ -366,4 +378,37 @@ enum {
#define GET_C_RS1S(inst)(8 + extract16(inst, 7, 3))
#define GET_C_RS2S(inst)(8 + extract16(inst, 2, 3))
+#define GET_C_FUNC(inst) extract32(inst, 13, 3)
+#define GET_C_OP(inst) extract32(inst, 0, 2)
+
+enum {
+/* RVC Quadrants */
+OPC_RISC_C_OP_QUAD0 = 0x0,
+OPC_RISC_C_OP_QUAD1 = 0x1,
+OPC_RISC_C_OP_QUAD2 = 0x2
+};
+
+enum {
+/* RVC Quadrant 0 */
+OPC_RISC_C_FUNC_ADDI4SPN = 0x0,
+OPC_RISC_C_FUNC_FLD_LQ = 0x1,
+OPC_RISC_C_FUNC_LW = 0x2,
+OPC_RISC_C_FUNC_FLW_LD = 0x3,
+OPC_RISC_C_FUNC_FSD_SQ = 0x5,
+OPC_RISC_C_FUNC_SW = 0x6,
+OPC_RISC_C_FUNC_FSW_SD = 0x7
+};
+
+enum {
+/* RVC Quadrant 2 */
+OPC_RISC_C_FUNC_SLLI_SLLI64 = 0x0,
+OPC_RISC_C_FUNC_FLDSP_LQSP = 0x1,
+OPC_RISC_C_FUNC_LWSP = 0x2,
+OPC_RISC_C_FUNC_FLWSP_LDSP = 0x3,
+OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD = 0x4,
+OPC_RISC_C_FUNC_FSDSP_SQSP = 0x5,
+OPC_RISC_C_FUNC_SWSP = 0x6,
+OPC_RISC_C_FUNC_FSWSP_SDSP = 0x7
+};
+
#endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 59b3680b1b..87daf7220f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -22,6 +22,7 @@
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "instmap.h"
#include "tcg/tcg-op.h"
#include "trace.h"
#include "semihosting/common-semi.h"
@@ -1053,7 +1054,8 @@ restart:
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
MMUAccessType access_type, bool pmp_violation,
-bool first_stage, bool two_stage)
+bool first_stage, bool two_stage,
+bool two_stage_indirect)
{
CPUState *cs = env_cpu(env);
int
[PULL 18/44] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 7 +++
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
2 files changed, 8 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6be3c4e739..d1daa764b7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1298,10 +1298,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
uint32_t esz = sizeof(TS1); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc);\
+uint32_t vma = vext_vma(desc);\
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+/* set masked-off elements to 1s */ \
+vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
@@ -1339,10 +1342,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
uint32_t total_elems = \
vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc); \
+uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) {\
if (!vm && !vext_elem_mask(v0, i)) {\
+/* set masked-off elements to 1s */ \
+vext_set_elems_1s(vd, vma, i * esz, \
+ (i + 1) * esz); \
continue; \
} \
TS2 s2 = *((TS2 *)vs2 + HS2(i));\
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 07d86551a9..83b85bb851 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1901,6 +1901,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1),\
vreg_ofs(s, a->rs2), cpu_env, \
--
2.37.2
[PULL 32/44] hw/riscv: virt: fix the plic's address cells
From: Conor Dooley
When optional AIA PLIC support was added the to the virt machine, the
address cells property was removed leading the issues with dt-validate
on a dump from the virt machine:
/stuff/qemu/qemu.dtb: plic@c00: '#address-cells' is a required property
From schema:
/stuff/linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
Add back the property to suppress the warning.
Reported-by: Rob Herring
Reviewed-by: Alistair Francis
Signed-off-by: Conor Dooley
Message-id: 20220810184612.157317-3-m...@conchuod.ie
Link:
https://lore.kernel.org/linux-riscv/20220803170552.ga2250266-r...@kernel.org/
Fixes: e6faee6585 ("hw/riscv: virt: Add optional AIA APLIC support to virt
machine")
Signed-off-by: Conor Dooley
Signed-off-by: Alistair Francis
---
include/hw/riscv/virt.h | 1 +
hw/riscv/virt.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 984e55c77f..be4ab8fe7f 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -111,6 +111,7 @@ enum {
#define FDT_PCI_ADDR_CELLS3
#define FDT_PCI_INT_CELLS 1
+#define FDT_PLIC_ADDR_CELLS 0
#define FDT_PLIC_INT_CELLS1
#define FDT_APLIC_INT_CELLS 2
#define FDT_IMSIC_INT_CELLS 0
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9d36133b74..f19758e1df 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -466,6 +466,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
qemu_fdt_add_subnode(mc->fdt, plic_name);
qemu_fdt_setprop_cell(mc->fdt, plic_name,
"#interrupt-cells", FDT_PLIC_INT_CELLS);
+qemu_fdt_setprop_cell(mc->fdt, plic_name,
+"#address-cells", FDT_PLIC_ADDR_CELLS);
qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
(char **)&plic_compat,
ARRAY_SIZE(plic_compat));
--
2.37.2
[PULL 20/44] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 07ce671879..597fa9c752 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2129,10 +2129,12 @@ static inline void
vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
CPURISCVState *env,
uint32_t vl, uint32_t vm, int vxrm,
- opivv2_rm_fn *fn)
+ opivv2_rm_fn *fn, uint32_t vma, uint32_t esz)
{
for (uint32_t i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+/* set masked-off elements to 1s */
+vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
continue;
}
fn(vd, vs1, vs2, i, env, vxrm);
@@ -2150,23 +2152,24 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+uint32_t vma = vext_vma(desc);
switch (env->vxrm) {
case 0: /* rnu */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 0, fn);
+ env, vl, vm, 0, fn, vma, esz);
break;
case 1: /* rne */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 1, fn);
+ env, vl, vm, 1, fn, vma, esz);
break;
case 2: /* rdn */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 2, fn);
+ env, vl, vm, 2, fn, vma, esz);
break;
default: /* rod */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, 3, fn);
+ env, vl, vm, 3, fn, vma, esz);
break;
}
/* set tail elements to 1s */
@@ -2250,10 +2253,12 @@ static inline void
vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
CPURISCVState *env,
uint32_t vl, uint32_t vm, int vxrm,
- opivx2_rm_fn *fn)
+ opivx2_rm_fn *fn, uint32_t vma, uint32_t esz)
{
for (uint32_t i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+/* set masked-off elements to 1s */
+vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
continue;
}
fn(vd, s1, vs2, i, env, vxrm);
@@ -2271,23 +2276,24 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void
*vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+uint32_t vma = vext_vma(desc);
switch (env->vxrm) {
case 0: /* rnu */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 0, fn);
+ env, vl, vm, 0, fn, vma, esz);
break;
case 1: /* rne */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 1, fn);
+ env, vl, vm, 1, fn, vma, esz);
break;
case 2: /* rdn */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 2, fn);
+ env, vl, vm, 2, fn, vma, esz);
break;
default: /* rod */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, 3, fn);
+ env, vl, vm, 3, fn, vma, esz);
break;
}
/* set tail elements to 1s */
--
2.37.2
[PULL 07/44] target/riscv: H extension depends on I extension
From: Weiwei Li
Add check for "H depends on an I base integer ISA with 32 x registers"
which is stated at the beginning of chapter 8 of the riscv-privileged
spec(draft-20220717)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <20220718130955.11899-3-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b919ad9056..fb37ffac64 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -727,6 +727,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
+error_setg(errp,
+ "H depends on an I base integer ISA with 32 x
registers");
+return;
+}
+
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
--
2.37.2
[PULL 00/44] riscv-to-apply queue
The following changes since commit 946e9bccf12f2bcc3ca471b820738fb22d14fc80: Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into staging (2022-09-06 08:31:24 -0400) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220907 for you to fetch changes up to f0551560b5c01b1dcbed1ac46ca0bd1155330f5f: target/riscv: Update the privilege field for sscofpmf CSRs (2022-09-07 09:19:15 +0200) First RISC-V PR for QEMU 7.2 * Update [m|h]tinst CSR in interrupt handling * Force disable extensions if priv spec version does not match * fix shifts shamt value for rv128c * move zmmul out of the experimental * virt: pass random seed to fdt * Add checks for supported extension combinations * Upgrade OpenSBI to v1.1 * Fix typo and restore Pointer Masking functionality for RISC-V * Add mask agnostic behaviour (rvv_ma_all_1s) for vector extension * Add Zihintpause support * opentitan: bump opentitan version * microchip_pfsoc: fix kernel panics due to missing peripherals * Remove additional priv version check for mcountinhibit * virt machine device tree improvements * Add xicondops in ISA entry * Use official extension names for AIA CSRs Alexey Baturo (1): target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V Anup Patel (3): target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() target/riscv: Force disable extensions if priv spec version does not match target/riscv: Use official extension names for AIA CSRs Atish Patra (9): target/riscv: Remove additional priv version check for mcountinhibit hw/intc: Move mtimer/mtimecmp to aclint target/riscv: Add stimecmp support target/riscv: Add vstimecmp support target/riscv: Add sscofpmf extension support target/riscv: Simplify counter predicate function target/riscv: Add few cache related PMU events hw/riscv: virt: Add PMU DT node to the device tree target/riscv: Update the privilege field for sscofpmf CSRs Bin Meng (2): roms/opensbi: Upgrade from v1.0 to v1.1 docs: List kvm as a supported accelerator on RISC-V Conor Dooley (5): hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals hw/riscv: virt: fix uart node name hw/riscv: virt: fix the plic's address cells hw/riscv: virt: fix syscon subnode paths hw/core: fix platform bus node name Daniel Henrique Barboza (1): hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() Dao Lu (1): target/riscv: Add Zihintpause support Frédéric Pétrot (1): target/riscv: fix shifts shamt value for rv128c Jason A. Donenfeld (1): hw/riscv: virt: pass random seed to fdt Rahul Pathak (1): target/riscv: Add xicondops in ISA entry Weiwei Li (8): target/riscv: move zmmul out of the experimental properties target/riscv: Add check for supported privilege mode combinations target/riscv: H extension depends on I extension target/riscv: Fix checkpatch warning may triggered in csr_ops table target/riscv: Add check for csrs existed with U extension target/riscv: Fix checks in hmode/hmode32 target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check target/riscv: Fix priority of csr related check in riscv_csrrw_check Wilfred Mallawa (1): hw/riscv: opentitan: bump opentitan version Yueh-Ting (eop) Chen (9): target/riscv: rvv: Add mask agnostic for vv instructions target/riscv: rvv: Add mask agnostic for vector load / store instructions target/riscv: rvv: Add mask agnostic for vx instructions target/riscv: rvv: Add mask agnostic for vector integer shift instructions target/riscv: rvv: Add mask agnostic for vector integer comparison instructions target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions target/riscv: rvv: Add mask agnostic for vector floating-point instructions target/riscv: rvv: Add mask agnostic for vector mask instructions target/riscv: rvv: Add mask agnostic for vector permutation instructions eopXD (1): target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior docs/about/build-platforms.rst |2 +- include/hw/intc/riscv_aclint.h |2 + include/hw/riscv/boot.h|2 +- include/hw/riscv/microchip_pfsoc.h | 14 +- include/hw/riscv/opentitan.h | 11 +- include/hw/riscv/virt.h|1 + include/hw/timer/ibex_timer.h |2 + target/riscv/cpu.h | 48 +- target/riscv/cpu_bits.h| 63 ++ target/riscv/instm
[PULL 37/44] hw/intc: Move mtimer/mtimecmp to aclint
From: Atish Patra
Historically, The mtime/mtimecmp has been part of the CPU because
they are per hart entities. However, they actually belong to aclint
which is a MMIO device.
Move them to the ACLINT device. This also emulates the real hardware
more closely.
Reviewed-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Signed-off-by: Atish Patra
Message-Id: <20220824221357.41070-2-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
include/hw/intc/riscv_aclint.h | 2 ++
include/hw/timer/ibex_timer.h | 2 ++
target/riscv/cpu.h | 2 --
hw/intc/riscv_aclint.c | 48 --
hw/timer/ibex_timer.c | 18 +
target/riscv/machine.c | 5 ++--
6 files changed, 47 insertions(+), 30 deletions(-)
diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h
index 26d4048687..693415eb6d 100644
--- a/include/hw/intc/riscv_aclint.h
+++ b/include/hw/intc/riscv_aclint.h
@@ -32,6 +32,8 @@ typedef struct RISCVAclintMTimerState {
/*< private >*/
SysBusDevice parent_obj;
uint64_t time_delta;
+uint64_t *timecmp;
+QEMUTimer **timers;
/*< public >*/
MemoryRegion mmio;
diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
index 1a0a28d5fa..41f5c82a92 100644
--- a/include/hw/timer/ibex_timer.h
+++ b/include/hw/timer/ibex_timer.h
@@ -33,6 +33,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER)
struct IbexTimerState {
/* */
SysBusDevice parent_obj;
+uint64_t mtimecmp;
+QEMUTimer *mtimer; /* Internal timer for M-mode interrupt */
/* */
MemoryRegion mmio;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 081cd05544..53335def23 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -307,7 +307,6 @@ struct CPUArchState {
/* temporary htif regs */
uint64_t mfromhost;
uint64_t mtohost;
-uint64_t timecmp;
/* physical memory protection */
pmp_table_t pmp_state;
@@ -362,7 +361,6 @@ struct CPUArchState {
float_status fp_status;
/* Fields from here on are preserved across CPU reset. */
-QEMUTimer *timer; /* Internal timer */
hwaddr kernel_addr;
hwaddr fdt_addr;
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index e7942c4e5a..eee04643cb 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -32,6 +32,7 @@
#include "hw/intc/riscv_aclint.h"
#include "qemu/timer.h"
#include "hw/irq.h"
+#include "migration/vmstate.h"
typedef struct riscv_aclint_mtimer_callback {
RISCVAclintMTimerState *s;
@@ -65,19 +66,22 @@ static void
riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
uint64_t rtc_r = cpu_riscv_read_rtc(mtimer);
-cpu->env.timecmp = value;
-if (cpu->env.timecmp <= rtc_r) {
+/* Compute the relative hartid w.r.t the socket */
+hartid = hartid - mtimer->hartid_base;
+
+mtimer->timecmp[hartid] = value;
+if (mtimer->timecmp[hartid] <= rtc_r) {
/*
* If we're setting an MTIMECMP value in the "past",
* immediately raise the timer interrupt
*/
-qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
+qemu_irq_raise(mtimer->timer_irqs[hartid]);
return;
}
/* otherwise, set up the future timer interrupt */
-qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
-diff = cpu->env.timecmp - rtc_r;
+qemu_irq_lower(mtimer->timer_irqs[hartid]);
+diff = mtimer->timecmp[hartid] - rtc_r;
/* back to ns (note args switched in muldiv64) */
uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
@@ -102,7 +106,7 @@ static void
riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
next = MIN(next, INT64_MAX);
}
-timer_mod(cpu->env.timer, next);
+timer_mod(mtimer->timers[hartid], next);
}
/*
@@ -133,11 +137,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque,
hwaddr addr,
"aclint-mtimer: invalid hartid: %zu", hartid);
} else if ((addr & 0x7) == 0) {
/* timecmp_lo for RV32/RV64 or timecmp for RV64 */
-uint64_t timecmp = env->timecmp;
+uint64_t timecmp = mtimer->timecmp[hartid];
return (size == 4) ? (timecmp & 0x) : timecmp;
} else if ((addr & 0x7) == 4) {
/* timecmp_hi */
-uint64_t timecmp = env->timecmp;
+uint64_t timecmp = mtimer->timecmp[hartid];
return (timecmp >> 32) & 0x;
} else {
qemu_log_mask(LOG_UNIMP,
@@ -177,7 +181,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr
addr,
} else if ((addr & 0x7) == 0) {
if (size == 4) {
/* timecmp_lo for RV32/RV64 */
-uint64_t timecmp_hi = env->timecmp >> 32;
+uint64_t timecmp_hi = mtimer->timecmp[hartid
[PULL 22/44] target/riscv: rvv: Add mask agnostic for vector mask instructions
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 11 +++
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
2 files changed, 14 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 315742c6b8..52518648bb 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4879,11 +4879,16 @@ static void vmsetm(void *vd, void *v0, void *vs2,
CPURISCVState *env,
uint32_t vl = env->vl;
uint32_t total_elems = env_archcpu(env)->cfg.vlen;
uint32_t vta_all_1s = vext_vta_all_1s(desc);
+uint32_t vma = vext_vma(desc);
int i;
bool first_mask_bit = false;
for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+/* set masked-off elements to 1s */
+if (vma) {
+vext_set_elem_mask(vd, i, 1);
+}
continue;
}
/* write a zero to all following active elements */
@@ -4944,11 +4949,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,
CPURISCVState *env, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc);\
+uint32_t vma = vext_vma(desc);\
uint32_t sum = 0; \
int i;\
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+/* set masked-off elements to 1s */ \
+vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
*((ETYPE *)vd + H(i)) = sum; \
@@ -4975,10 +4983,13 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState
*env, uint32_t desc) \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc);\
+uint32_t vma = vext_vma(desc);\
int i;\
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+/* set masked-off elements to 1s */ \
+vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
*((ETYPE *)vd + H(i)) = i;\
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 8ce3d28603..c1bd29329e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3275,6 +3275,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = \
FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
+data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2),\
cpu_env, s->cfg_ptr->vlen / 8, \
@@ -3313,6 +3314,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_gvec_3_ptr * const fns[4] = {
gen_helper_viota_m_b, gen_helper_viota_m_h,
gen_helper_viota_m_w, gen_helper_viota_m_d,
@@ -3343,6 +3345,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+data = F
[PULL 11/44] target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check
From: Weiwei Li
Just add 1 to the effective privledge level when in HS mode, then reuse
the check of 'effective_priv < csr_priv' in riscv_csrrw_check to replace
the privilege level related check in hmode. Then, hmode will only check
whether H extension is supported.
When accessing Hypervior CSRs:
1) If accessing from M privilege level, the check of
'effective_priv< csr_priv' passes, returns hmode(...) which will return
RISCV_EXCP_ILLEGAL_INST when H extension is not supported and return
RISCV_EXCP_NONE otherwise.
2) If accessing from HS privilege level, effective_priv will add 1,
the check passes and also returns hmode(...) too.
3) If accessing from VS/VU privilege level, the check fails, and
returns RISCV_EXCP_VIRT_INSTRUCTION_FAULT
4) If accessing from U privilege level, the check fails, and returns
RISCV_EXCP_ILLEGAL_INST
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-Id: <20220718130955.11899-7-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cf15aa67b7..0fb042b2fd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -312,13 +312,7 @@ static int aia_smode32(CPURISCVState *env, int csrno)
static RISCVException hmode(CPURISCVState *env, int csrno)
{
if (riscv_has_ext(env, RVH)) {
-/* Hypervisor extension is supported */
-if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-env->priv == PRV_M) {
-return RISCV_EXCP_NONE;
-} else {
-return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-}
+return RISCV_EXCP_NONE;
}
return RISCV_EXCP_ILLEGAL_INST;
@@ -3279,13 +3273,11 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
#if !defined(CONFIG_USER_ONLY)
int csr_priv, effective_priv = env->priv;
-if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
+if (riscv_has_ext(env, RVH) && env->priv == PRV_S &&
+!riscv_cpu_virt_enabled(env)) {
/*
- * We are in either HS or VS mode.
- * Add 1 to the effective privledge level to allow us to access the
- * Hypervisor CSRs. The `hmode` predicate will determine if access
- * should be allowed(HS) or if a virtual instruction exception should
be
- * raised(VS).
+ * We are in HS mode. Add 1 to the effective privledge level to
+ * allow us to access the Hypervisor CSRs.
*/
effective_priv++;
}
--
2.37.2
[PULL 12/44] roms/opensbi: Upgrade from v1.0 to v1.1
From: Bin Meng Upgrade OpenSBI from v1.0 to v1.1 and the pre-built bios images. The v1.1 release includes the following commits: 5b99603 lib: utils/ipi: Fix size check in aclint_mswi_cold_init() 6dde435 lib: utils/sys: Extend HTIF library to allow custom base address 8257262 platform: sifive_fu740: do not use a global in da9063_reset/shutdown fb688d9 platform: sifive_fu740: fix reset when watchdog is running 5d025eb lib: fix pointer of type 'void *' used in arithmetic 632f593 lib: sbi: Map only the counters enabled in hardware 3b7c204 lib: sbi: Disable interrupt during config matching a26dc60 lib: sbi: Disable interrupt and inhibit counting in M-mode during init 5d53b55 Makefile: fix build with binutils 2.38 6ad8917 lib: fix compilation when strings.h is included ce4c018 lib: utils/serial: Round UART8250 baud rate divisor to nearest integer 01250d0 include: sbi: Add AIA related CSR defines 8f96070 lib: sbi: Detect AIA CSRs at boot-time 65b4c7c lib: sbi: Use AIA CSRs for local interrupts when available 222132f lib: sbi: Add sbi_trap_set_external_irqfn() API 5f56314 lib: utils/irqchip: Allow multiple FDT irqchip drivers 1050940 include: sbi: Introduce nascent_init() platform callback 55e79f8 lib: sbi: Enable mie.MEIE bit for IPIs based on external interrupts. 9f73669 lib: utils/irqchip: Add IMSIC library 811da5c lib: utils/irqchip: Add FDT based driver for IMSIC 7127aaa lib: utils: Disable appropriate IMSIC DT nodes in fdt_fixups() 9979265 lib: utils/irqchip: Add APLIC initialization library 3461219 lib: utils/irqchip: Add FDT based driver for APLIC 8e2ef4f lib: utils: Disable appropriate APLIC DT nodes in fdt_fixups() 3a69cc1 lib: sbi: fix typo in is_region_subset f2ccf2f lib: sbi: verbose sbi_domain_root_add_memregion f3f4604 lib: sbi: Add a simple external interrupt handling framework 4998a71 lib: utils: serial: Initial commit of xlnx-uartlite 2dfbd3c lib: pmp_set/pmp_get moved errors from runtime to compile time b6b7220 firmware: Fix code for accessing hart_count and stack_size d552fc8 lib: Add error messages via conditional compilation for the future 555bdb1 include: Use static asserts for SBI_PLATFORM_xxx_OFFSET defines 1b42d3a include: Use static asserts for SBI_SCRATCH_xxx_OFFSET defines 7924a0b include: Use static asserts for FW_DYNAMIC_INFO_xxx_OFFSET defines 722f80d include: Add defines for [m|h|s]envcfg CSRs 31fecad lib: sbi: Detect menvcfg CSR at boot time 47d6765 lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR 794986f lib: sbi: Enable Svpbmt extension in the menvcfg CSR 499601a lib: sbi: Add Smstateen extension defines d44568a lib: sbi: Detect Smstateen CSRs at boot-time 3383d6a lib: irqchip/imsic: configure mstateen 5c5cbb5 lib: utils/serial: support 'reg-offset' property c1e47d0 include: correct the definition of MSTATUS_VS 9cd95e1 lib: sbi/hart: preserve csr validation value 4035ae9 docs: pmu: Improve the PMU DT bindings d62f6da lib: sbi: Implement Sstc extension 474a9d4 lib: sbi: Fix mstatus_init() for RV32 when Sscofpmf is not available e576b3e include: sbi: Define SBI_PMU_HW_EVENT_MAX to 256 b0c9df5 lib: sbi: Fix mhpmeventh access for rv32 in absence of sscofpmf 1a754bb lib: sbi: Detect and print privileged spec version 5a6be99 lib: sbi: Remove 's' and 'u' from misa_string() output 5b8b377 lib: sbi: Update the name of ISA string printed at boot time d4b563c lib: sbi: Remove MCOUNTEREN and SCOUNTEREN hart features dbc3d8f lib: sbi: Remove MCOUNTINHIBT hart feature 97a17c2 lib: sbi: Remove MENVCFG hart feature a6ab94f lib: sbi: Fix AIA feature detection cad6c91 lib: sbi: Convert hart features into hart extensions be4903a lib: sbi: Detect hart features only once for each hart 994ace3 lib: sbi: Add sbi_hart_update_extension() function 023f0ad lib: sbi_platform: Add callback to populate HART extensions f726f2d Makefile: Allow generated C source to be anywhere in build directory 7fb474b Makefile: Add support for generating C array at compile time 73cf511 lib: utils/reset: Generate FDT reset driver list at compile-time 1e62705 lib: utils/serial: Generate FDT serial driver list at compile-time bfeb305 lib: utils/timer: Generate FDT timer driver list at compile-time 3a69d12 lib: utils/irqchip: Generate FDT irqchip driver list at compile-time 4ee0c57 lib: utils/ipi: Generate FDT ipi driver list at compile-time 998ed43 lib: utils/i2c: Generate FDT i2c adapter driver list at compile-time 4eacd82 lib: utils/gpio: Generate FDT gpio driver list at compile-time a3a3c60 platform: generic: Generate platform override module list at compile-time 9a7a677 platform: generic: Move Sifive platform overrides into own directory 851c14d lib: utils/irqchip: fix typo when checking for CPU node 90a9dd2 lib: utils/fdt: introduce fdt_node_is_enabled() 616da52 lib: utils: check if CPU node is enabled 575bb4e platform: generic: check if CPU node is enabled 1bc67db lib: utils/fdt: rename fdt_parse_max_hart_id f067bb8 lib: sbi: fix system_opcode_insn fab0379 lib: utils/fdt: Require match data to be const 295e5
[PULL 40/44] target/riscv: Add sscofpmf extension support
From: Atish Patra
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension. As the extension doesn't have any
provision for the overflow bit for fixed counters, the fixed events
can also be monitoring using programmable counters. The underlying
counters for cycle and instruction counters are always running. Thus,
a separate timer device is programmed to handle the overflow.
Tested-by: Heiko Stuebner
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
Message-Id: <20220824221701.41932-2-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 25 +++
target/riscv/cpu_bits.h | 55 ++
target/riscv/pmu.h | 7 +
target/riscv/cpu.c | 12 ++
target/riscv/csr.c | 166 +-
target/riscv/machine.c | 1 +
target/riscv/pmu.c | 368 +++-
7 files changed, 623 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d895a0af2c..06751e1e3e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -136,6 +136,8 @@ typedef struct PMUCTRState {
/* Snapshort value of a counter in RV32 */
target_ulong mhpmcounterh_prev;
bool started;
+/* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */
+target_ulong irq_overflow_left;
} PMUCTRState;
struct CPUArchState {
@@ -301,6 +303,9 @@ struct CPUArchState {
/* PMU event selector configured values. First three are unused*/
target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
+/* PMU event selector configured values for RV32*/
+target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
+
target_ulong sscratch;
target_ulong mscratch;
@@ -447,6 +452,7 @@ struct RISCVCPUConfig {
bool ext_zmmul;
bool ext_smaia;
bool ext_ssaia;
+bool ext_sscofpmf;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
@@ -493,6 +499,12 @@ struct ArchCPU {
/* Configuration Settings */
RISCVCPUConfig cfg;
+
+QEMUTimer *pmu_timer;
+/* A bitmask of Available programmable counters */
+uint32_t pmu_avail_ctrs;
+/* Mapping of events to counters */
+GHashTable *pmu_event_ctr_map;
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
@@ -753,6 +765,19 @@ enum {
CSR_TABLE_SIZE = 0x1000
};
+/**
+ * The event id are encoded based on the encoding specified in the
+ * SBI specification v0.3
+ */
+
+enum riscv_pmu_event_idx {
+RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01,
+RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02,
+RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019,
+RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B,
+RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
+};
+
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 095dab19f5..7be12cac2e 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -390,6 +390,37 @@
#define CSR_MHPMEVENT29 0x33d
#define CSR_MHPMEVENT30 0x33e
#define CSR_MHPMEVENT31 0x33f
+
+#define CSR_MHPMEVENT3H 0x723
+#define CSR_MHPMEVENT4H 0x724
+#define CSR_MHPMEVENT5H 0x725
+#define CSR_MHPMEVENT6H 0x726
+#define CSR_MHPMEVENT7H 0x727
+#define CSR_MHPMEVENT8H 0x728
+#define CSR_MHPMEVENT9H 0x729
+#define CSR_MHPMEVENT10H0x72a
+#define CSR_MHPMEVENT11H0x72b
+#define CSR_MHPMEVENT12H0x72c
+#define CSR_MHPMEVENT13H0x72d
+#define CSR_MHPMEVENT14H0x72e
+#define CSR_MHPMEVENT15H0x72f
+#define CSR_MHPMEVENT16H0x730
+#define CSR_MHPMEVENT17H0x731
+#define CSR_MHPMEVENT18H0x732
+#define CSR_MHPMEVENT19H0x733
+#define CSR_MHPMEVENT20H0x734
+#define CSR_MHPMEVENT21H0x735
+#define CSR_MHPMEVENT22H0x736
+#define CSR_MHPMEVENT23H0x737
+#define CSR_MHPMEVENT24H0x738
+#define CSR_MHPMEVENT25H0x739
+#define CSR_MHPMEVENT26H0x73a
+#define CSR_MHPMEVENT27H0x73b
+#define CSR_MHPMEVENT28H0x73c
+#define CSR_MHPMEVENT29H0x73d
+#define CSR_MHPMEVENT30H0x73e
+#define CSR_MHPMEVENT31H0x73f
+
#define CSR_MHPMCOUNTER3H 0xb83
#define CSR_MHPMCOUNTER4H 0xb84
#define CSR_MHPMCOUNTER5H 0xb85
@@ -451,6 +482,7 @@
#define CSR_VSMTE 0x2c0
#define CSR_VSPMMASK0x2c1
#define CSR_VSPMBASE0x2c2
+#define CSR_SCOUNTOVF 0xda0
/* Crypto Extension */
#define CSR_SEED0x015
@@ -628,6 +660,7 @@ typedef enum RISCVException {
#define IRQ_VS_EXT 10
#define IRQ_M_EXT 11
#define IRQ_S_GEXT 12
+#define IRQ_PMU_OVF13
#define IRQ_LOCAL_MAX 16
#define IRQ_LOCAL_GUEST_MAX
[PULL 16/44] target/riscv: rvv: Add mask agnostic for vector load / store instructions
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 35 +
target/riscv/insn_trans/trans_rvv.c.inc | 5
2 files changed, 29 insertions(+), 11 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index de895050e0..e3810d2bc3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -283,14 +283,18 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
uint32_t esz = 1 << log2_esz;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+uint32_t vma = vext_vma(desc);
for (i = env->vstart; i < env->vl; i++, env->vstart++) {
-if (!vm && !vext_elem_mask(v0, i)) {
-continue;
-}
-
k = 0;
while (k < nf) {
+if (!vm && !vext_elem_mask(v0, i)) {
+/* set masked-off elements to 1s */
+vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz,
+ (i + k * max_elems + 1) * esz);
+k++;
+continue;
+}
target_ulong addr = base + stride * i + (k << log2_esz);
ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
k++;
@@ -482,15 +486,19 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t esz = 1 << log2_esz;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+uint32_t vma = vext_vma(desc);
/* load bytes from guest memory */
for (i = env->vstart; i < env->vl; i++, env->vstart++) {
-if (!vm && !vext_elem_mask(v0, i)) {
-continue;
-}
-
k = 0;
while (k < nf) {
+if (!vm && !vext_elem_mask(v0, i)) {
+/* set masked-off elements to 1s */
+vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz,
+ (i + k * max_elems + 1) * esz);
+k++;
+continue;
+}
abi_ptr addr = get_index_addr(base, i, vs2) + (k << log2_esz);
ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
k++;
@@ -579,6 +587,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
uint32_t esz = 1 << log2_esz;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+uint32_t vma = vext_vma(desc);
target_ulong addr, offset, remain;
/* probe every access*/
@@ -624,10 +633,14 @@ ProbeSuccess:
}
for (i = env->vstart; i < env->vl; i++) {
k = 0;
-if (!vm && !vext_elem_mask(v0, i)) {
-continue;
-}
while (k < nf) {
+if (!vm && !vext_elem_mask(v0, i)) {
+/* set masked-off elements to 1s */
+vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz,
+ (i + k * max_elems + 1) * esz);
+k++;
+continue;
+}
target_ulong addr = base + ((i * nf + k) << log2_esz);
ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
k++;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5ec113f6fd..0627eda0c0 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -712,6 +712,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a,
uint8_t eew)
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
}
@@ -777,6 +778,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a,
uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, 1);
/* Mask destination register are always tail-agnostic */
data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
+data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
}
@@ -866,6 +868,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a,
uint8_t eew)
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+data = FIELD_DP32(data, VDATA, VMA, s->vma);
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
@@ -996,6 +999,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a,
uint8_t eew)
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s-
[PULL 23/44] target/riscv: rvv: Add mask agnostic for vector permutation instructions
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 26 +++--
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 52518648bb..d224861c2c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -5018,11 +5018,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc);\
+uint32_t vma = vext_vma(desc);\
target_ulong offset = s1, i_min, i; \
\
i_min = MAX(env->vstart, offset); \
for (i = i_min; i < vl; i++) {\
if (!vm && !vext_elem_mask(v0, i)) { \
+/* set masked-off elements to 1s */ \
+vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
@@ -5047,13 +5050,17 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc);\
+uint32_t vma = vext_vma(desc);\
target_ulong i_max, i;\
\
i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \
for (i = env->vstart; i < i_max; ++i) { \
-if (vm || vext_elem_mask(v0, i)) {\
-*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
+if (!vm && !vext_elem_mask(v0, i)) { \
+/* set masked-off elements to 1s */ \
+vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
+continue; \
} \
+*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
} \
\
for (i = i_max; i < vl; ++i) {\
@@ -5083,10 +5090,13 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0,
target_ulong s1, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz);\
uint32_t vta = vext_vta(desc); \
+uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) {\
if (!vm && !vext_elem_mask(v0, i)) {\
+/* set masked-off elements to 1s */ \
+vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
continue; \
} \
if (i == 0) { \
@@ -5128,10 +5138,13 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0,
target_ulong s1, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
uint32_t vta = vext_vta(desc);\
+uint32_t vma = vext_vma(desc);\
uint32_t i; \
[PULL 15/44] target/riscv: rvv: Add mask agnostic for vv instructions
From: "Yueh-Ting (eop) Chen"
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between mask policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This is the first commit regarding the optional mask agnostic
behavior. Follow-up commits will add this optional behavior
for all rvv instructions.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 2 ++
target/riscv/internals.h| 5 +++--
target/riscv/cpu_helper.c | 2 ++
target/riscv/translate.c| 2 ++
target/riscv/vector_helper.c| 8
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
6 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ffb1a18873..561d7fa92c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -439,6 +439,7 @@ struct RISCVCPUConfig {
bool ext_zve64f;
bool ext_zmmul;
bool rvv_ta_all_1s;
+bool rvv_ma_all_1s;
uint32_t mvendorid;
uint64_t marchid;
@@ -596,6 +597,7 @@ FIELD(TB_FLAGS, XL, 20, 2)
FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
FIELD(TB_FLAGS, VTA, 24, 1)
+FIELD(TB_FLAGS, VMA, 25, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 193ce57a6d..5620fbffb6 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -26,8 +26,9 @@ FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
FIELD(VDATA, VTA, 4, 1)
FIELD(VDATA, VTA_ALL_1S, 5, 1)
-FIELD(VDATA, NF, 6, 4)
-FIELD(VDATA, WD, 6, 1)
+FIELD(VDATA, VMA, 6, 1)
+FIELD(VDATA, NF, 7, 4)
+FIELD(VDATA, WD, 7, 1)
/* float point classify helpers */
target_ulong fclass_h(uint64_t frs1);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87daf7220f..650574accf 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -68,6 +68,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong
*pc,
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
flags = FIELD_DP32(flags, TB_FLAGS, VTA,
FIELD_EX64(env->vtype, VTYPE, VTA));
+flags = FIELD_DP32(flags, TB_FLAGS, VMA,
+FIELD_EX64(env->vtype, VTYPE, VMA));
} else {
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 76da8db8a7..8925a44c6e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -95,6 +95,7 @@ typedef struct DisasContext {
int8_t lmul;
uint8_t sew;
uint8_t vta;
+uint8_t vma;
bool cfg_vta_all_1s;
target_ulong vstart;
bool vl_eq_vlmax;
@@ -1121,6 +1122,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
+ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s;
ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
ctx->vstart = env->vstart;
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a96fc49c71..de895050e0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -127,6 +127,11 @@ static inline uint32_t vext_vta(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, VTA);
}
+static inline uint32_t vext_vma(uint32_t desc)
+{
+return FIELD_EX32(simd_data(desc), VDATA, VMA);
+}
+
static inline uint32_t vext_vta_all_1s(uint32_t desc)
{
return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
@@ -812,10 +817,13 @@ static void do_vext_vv(void *vd, void *v0, void *vs1,
void *vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
+uint32_t vma = vext_vma(desc);
uint32_t i;
for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+/* set masked-off elements to 1s */
+vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz);
continue;
}
fn(vd, vs1, vs2, i);
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 6c0918
[PULL 24/44] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior
From: eopXD
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between mask policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This commit adds option 'rvv_ma_all_1s' is added to enable the
behavior, it is default as disabled.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id: <165570784143.17634.35095816584573691...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 117d308ae5..966e5f2dd7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1061,6 +1061,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string,
false),
DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
+DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.37.2
[PULL 14/44] docs: List kvm as a supported accelerator on RISC-V
From: Bin Meng
Since commit fbf43c7dbf18 ("target/riscv: enable riscv kvm accel"),
KVM accelerator is supported on RISC-V. Let's document it.
Signed-off-by: Bin Meng
Reviewed-by: Thomas Huth
Reviewed-by: Alistair Francis
Message-Id: <20220719082635.3741878-1-bin.m...@windriver.com>
Signed-off-by: Alistair Francis
---
docs/about/build-platforms.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/about/build-platforms.rst b/docs/about/build-platforms.rst
index 26028756d0..a2fee53248 100644
--- a/docs/about/build-platforms.rst
+++ b/docs/about/build-platforms.rst
@@ -46,7 +46,7 @@ Those hosts are officially supported, with various
accelerators:
* - PPC
- kvm, tcg
* - RISC-V
- - tcg
+ - kvm, tcg
* - s390x
- kvm, tcg
* - SPARC
--
2.37.2
[PULL 27/44] target/riscv: Fix priority of csr related check in riscv_csrrw_check
From: Weiwei Li
Normally, riscv_csrrw_check is called when executing Zicsr instructions.
And we can only do access control for existed CSRs. So the priority of
CSR related check, from highest to lowest, should be as follows:
1) check whether Zicsr is supported: raise RISCV_EXCP_ILLEGAL_INST if not
2) check whether csr is existed: raise RISCV_EXCP_ILLEGAL_INST if not
3) do access control: raise RISCV_EXCP_ILLEGAL_INST or RISCV_EXCP_VIRT_
INSTRUCTION_FAULT if not allowed
The predicates contain parts of function of both 2) and 3), So they need
to be placed in the middle of riscv_csrrw_check
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20220803123652.3700-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 44 +---
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0fb042b2fd..d81f466c80 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3270,6 +3270,30 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
int read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
+
+/* ensure the CSR extension is enabled. */
+if (!cpu->cfg.ext_icsr) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+if (env->priv_ver < csr_min_priv) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+/* check predicate */
+if (!csr_ops[csrno].predicate) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+if (write_mask && read_only) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+RISCVException ret = csr_ops[csrno].predicate(env, csrno);
+if (ret != RISCV_EXCP_NONE) {
+return ret;
+}
+
#if !defined(CONFIG_USER_ONLY)
int csr_priv, effective_priv = env->priv;
@@ -3290,25 +3314,7 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
-if (write_mask && read_only) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-
-/* ensure the CSR extension is enabled. */
-if (!cpu->cfg.ext_icsr) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-
-/* check predicate */
-if (!csr_ops[csrno].predicate) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-
-if (env->priv_ver < csr_min_priv) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-
-return csr_ops[csrno].predicate(env, csrno);
+return RISCV_EXCP_NONE;
}
static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
--
2.37.2
[PULL 30/44] target/riscv: Remove additional priv version check for mcountinhibit
From: Atish Patra
With .min_priv_version, additiona priv version check is uncessary
for mcountinhibit read/write functions.
Reviewed-by: Heiko Stuebner
Tested-by: Heiko Stuebner
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220816232321.558250-7-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 8
1 file changed, 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d81f466c80..4a7078f7d1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1494,10 +1494,6 @@ static RISCVException write_mtvec(CPURISCVState *env,
int csrno,
static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
target_ulong *val)
{
-if (env->priv_ver < PRIV_VERSION_1_11_0) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-
*val = env->mcountinhibit;
return RISCV_EXCP_NONE;
}
@@ -1508,10 +1504,6 @@ static RISCVException write_mcountinhibit(CPURISCVState
*env, int csrno,
int cidx;
PMUCTRState *counter;
-if (env->priv_ver < PRIV_VERSION_1_11_0) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-
env->mcountinhibit = val;
/* Check if any other counter is also monitoring cycles/instructions */
--
2.37.2
[PULL 21/44] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
From: "Yueh-Ting (eop) Chen"
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
Message-Id: <165570784143.17634.3509581658457369...@git.sr.ht>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 26 +
target/riscv/insn_trans/trans_rvv.c.inc | 12
2 files changed, 38 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 597fa9c752..315742c6b8 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3051,10 +3051,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
uint32_t total_elems =\
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc);\
+uint32_t vma = vext_vma(desc);\
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+/* set masked-off elements to 1s */ \
+vext_set_elems_1s(vd, vma, i * ESZ, \
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, vs1, vs2, i, env); \
@@ -3090,10 +3094,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1,
\
uint32_t total_elems =\
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc);\
+uint32_t vma = vext_vma(desc);\
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+/* set masked-off elements to 1s */ \
+vext_set_elems_1s(vd, vma, i * ESZ, \
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, s1, vs2, i, env); \
@@ -3665,6 +3673,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
uint32_t total_elems = \
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+uint32_t vma = vext_vma(desc); \
uint32_t i;\
\
if (vl == 0) { \
@@ -3672,6 +3681,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
} \
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+/* set masked-off elements to 1s */\
+vext_set_elems_1s(vd, vma, i * ESZ,\
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, vs2, i, env);\
@@ -4182,12 +4194,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
uint32_t vl = env->vl;\
uint32_t total_elems = env_archcpu(env)->cfg.vlen;\
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
+uint32_t vma = vext_vma(desc);\
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i));\
ETYPE s2 = *((ETYPE *)vs2 + H(i));\
if (!vm && !vext_elem_mask(v0, i)) { \
+/* set masked-off elements to 1s */ \
+if (vma) {\
+vext_set_elem_mask(vd, i, 1); \
+} \
continue; \
} \
vext_set_elem_mask(vd, i, \
@@ -4215,11 +4232,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void
*vs2, \
uint32_t vl = env->vl; \
uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
uint32_t vta_all_1
[PULL 33/44] hw/riscv: virt: fix syscon subnode paths
From: Conor Dooley
The reset and poweroff features of the syscon were originally added to
top level, which is a valid path for a syscon subnode. Subsequently a
reorganisation was carried out while implementing NUMA in which the
subnodes were moved into the /soc node. As /soc is a "simple-bus", this
path is invalid, and so dt-validate produces the following warnings:
/stuff/qemu/qemu.dtb: soc: poweroff: {'value': [[21845]], 'offset': [[0]],
'regmap': [[4]], 'compatible': ['syscon-poweroff']} should not be valid under
{'type': 'object'}
From schema:
/home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml
/stuff/qemu/qemu.dtb: soc: reboot: {'value': [[30583]], 'offset': [[0]],
'regmap': [[4]], 'compatible': ['syscon-reboot']} should not be valid under
{'type': 'object'}
From schema:
/home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml
Move the syscon subnodes back to the top level and silence the warnings.
Reported-by: Rob Herring
Signed-off-by: Conor Dooley
Reviewed-by: Alistair Francis
Message-id: 20220810184612.157317-4-m...@conchuod.ie
Link:
https://lore.kernel.org/linux-riscv/20220803170552.ga2250266-r...@kernel.org/
Fixes: 18df0b4695 ("hw/riscv: virt: Allow creating multiple NUMA sockets")
Signed-off-by: Conor Dooley
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f19758e1df..686341a0e2 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -897,7 +897,7 @@ static void create_fdt_reset(RISCVVirtState *s, const
MemMapEntry *memmap,
test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
g_free(name);
-name = g_strdup_printf("/soc/reboot");
+name = g_strdup_printf("/reboot");
qemu_fdt_add_subnode(mc->fdt, name);
qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
@@ -905,7 +905,7 @@ static void create_fdt_reset(RISCVVirtState *s, const
MemMapEntry *memmap,
qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
g_free(name);
-name = g_strdup_printf("/soc/poweroff");
+name = g_strdup_printf("/poweroff");
qemu_fdt_add_subnode(mc->fdt, name);
qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
--
2.37.2
[PULL 36/44] target/riscv: Use official extension names for AIA CSRs
From: Anup Patel
The arch review of AIA spec is completed and we now have official
extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode
AIA CSRs).
Refer, section 1.6 of the latest AIA v0.3.1 stable specification at
https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf)
Based on above, we update QEMU RISC-V to:
1) Have separate config options for Smaia and Ssaia extensions
which replace RISCV_FEATURE_AIA in CPU features
2) Not generate AIA INTC compatible string in virt machine
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Message-id: 20220820042958.377018-1-apa...@ventanamicro.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 4 ++--
hw/intc/riscv_imsic.c | 4 +++-
hw/riscv/virt.c | 13 ++---
target/riscv/cpu.c| 9 -
target/riscv/cpu_helper.c | 3 ++-
target/riscv/csr.c| 24 ++--
6 files changed, 31 insertions(+), 26 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4be4b82a83..081cd05544 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -85,7 +85,6 @@ enum {
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA,
-RISCV_FEATURE_AIA,
RISCV_FEATURE_DEBUG
};
@@ -439,6 +438,8 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
bool ext_zmmul;
+bool ext_smaia;
+bool ext_ssaia;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
@@ -459,7 +460,6 @@ struct RISCVCPUConfig {
bool mmu;
bool pmp;
bool epmp;
-bool aia;
bool debug;
uint64_t resetvec;
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index 8615e4cc1d..4d4d5b50ca 100644
--- a/hw/intc/riscv_imsic.c
+++ b/hw/intc/riscv_imsic.c
@@ -344,9 +344,11 @@ static void riscv_imsic_realize(DeviceState *dev, Error
**errp)
/* Force select AIA feature and setup CSR read-modify-write callback */
if (env) {
-riscv_set_feature(env, RISCV_FEATURE_AIA);
if (!imsic->mmode) {
+rcpu->cfg.ext_ssaia = true;
riscv_cpu_set_geilen(env, imsic->num_pages - 1);
+} else {
+rcpu->cfg.ext_smaia = true;
}
riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
riscv_imsic_rmw, imsic);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 686341a0e2..ff8c0df5cd 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -260,17 +260,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
qemu_fdt_add_subnode(mc->fdt, intc_name);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
intc_phandles[cpu]);
-if (riscv_feature(&s->soc[socket].harts[cpu].env,
- RISCV_FEATURE_AIA)) {
-static const char * const compat[2] = {
-"riscv,cpu-intc-aia", "riscv,cpu-intc"
-};
-qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible",
- (char **)&compat, ARRAY_SIZE(compat));
-} else {
-qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
-"riscv,cpu-intc");
-}
+qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+"riscv,cpu-intc");
qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e0d5941230..26d44df446 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -99,6 +99,8 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
+ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
+ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
@@ -666,10 +668,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
}
-if (cpu->cfg.aia) {
-riscv_set_feature(env, RISCV_FEATURE_AIA);
-}
-
if (cpu->cfg.debug) {
riscv_set_feature(env, RISCV_FEATURE_DEBUG);
}
@@ -1038,7 +1036,8 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
-DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
+DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
+DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia,
[PULL 35/44] target/riscv: Add xicondops in ISA entry
From: Rahul Pathak
XVentanaCondOps is Ventana custom extension. Add
its extension entry in the ISA Ext array
Signed-off-by: Rahul Pathak
Reviewed-by: Alistair Francis
Message-id: 20220816045408.1231135-1-rpat...@ventanamicro.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d4635c7df4..e0d5941230 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -102,6 +102,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
+ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0,
ext_XVentanaCondOps),
};
static bool isa_ext_is_enabled(RISCVCPU *cpu,
--
2.37.2
Re: sphinx-build is really slow, any way to improve that?
Peter Maydell writes: > On Tue, 6 Sept 2022 at 08:55, Daniel P. Berrangé wrote: >> >> On Mon, Sep 05, 2022 at 10:21:55PM +0100, Peter Maydell wrote: >> > On Mon, 5 Sept 2022 at 20:51, Claudio Fontana wrote: >> > > when I build qemu, there is a lot of time spent at the end of the build >> > > where one cpu goes 100% on sphinx-build. >> > > >> > > Is there some way to parallelize that? It seems it is the current >> > > bottleneck for rebuilds for me.. >> > >> > It's a big fat python program, so I suspect not, but >> > maybe I'm wrong. >> >> It annoys me too and I've had a look at what it is doing in the past and >> failed to find an obvious way to improve it. I fear this could be an >> inherant limitation of the way we use sphinx to build the docs as a >> complete manual, as compared to say treating each docs source file as >> a distinct standalone web page. > > IIRC sphinx really really wants to process the whole document tree > in one go. You can see this in the way that for example the > HTML build process creates HTML files for the top-level rst > files that are supposed to be only for the manpage -- it will > suck in and process everything, not just the files reachable > via whatever top level file you point it at. How do other projects deal with the resulting slowness? Could we avoid rerunning sphinx-build when documentation hasn't changed?
[PULL 28/44] hw/riscv: opentitan: bump opentitan version
From: Wilfred Mallawa
The following patch updates opentitan to match the new configuration,
as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c
Note: with this patch we now skip the usage of the opentitan
`boot_rom`. The Opentitan boot rom contains hw verification
for devies which we are currently not supporting in qemu. As of now,
the `boot_rom` has no major significance, however, would be good to
support in the future.
Tested by running utests from the latest tock [1]
(that supports this version of OT).
[1] https://github.com/tock/tock/pull/3056
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Message-Id: <20220812005229.358850-1-wilfred.mall...@opensource.wdc.com>
Signed-off-by: Alistair Francis
---
include/hw/riscv/opentitan.h | 11 ++-
hw/riscv/opentitan.c | 12
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 68892cd8e5..26d960f288 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -74,6 +74,7 @@ enum {
IBEX_DEV_TIMER,
IBEX_DEV_SENSOR_CTRL,
IBEX_DEV_OTP_CTRL,
+IBEX_DEV_LC_CTRL,
IBEX_DEV_PWRMGR,
IBEX_DEV_RSTMGR,
IBEX_DEV_CLKMGR,
@@ -105,11 +106,11 @@ enum {
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
-IBEX_TIMER_TIMEREXPIRED0_0= 126,
-IBEX_SPI_HOST0_ERR_IRQ= 150,
-IBEX_SPI_HOST0_SPI_EVENT_IRQ = 151,
-IBEX_SPI_HOST1_ERR_IRQ= 152,
-IBEX_SPI_HOST1_SPI_EVENT_IRQ = 153,
+IBEX_TIMER_TIMEREXPIRED0_0= 127,
+IBEX_SPI_HOST0_ERR_IRQ= 151,
+IBEX_SPI_HOST0_SPI_EVENT_IRQ = 152,
+IBEX_SPI_HOST1_ERR_IRQ= 153,
+IBEX_SPI_HOST1_SPI_EVENT_IRQ = 154,
};
#endif
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 4495a2c039..af13dbe3b1 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -29,9 +29,9 @@
#include "sysemu/sysemu.h"
static const MemMapEntry ibex_memmap[] = {
-[IBEX_DEV_ROM] ={ 0x8000, 16 * KiB },
-[IBEX_DEV_RAM] ={ 0x1000, 0x1 },
-[IBEX_DEV_FLASH] = { 0x2000, 0x8 },
+[IBEX_DEV_ROM] ={ 0x8000, 0x8000 },
+[IBEX_DEV_RAM] ={ 0x1000, 0x2 },
+[IBEX_DEV_FLASH] = { 0x2000, 0x10 },
[IBEX_DEV_UART] = { 0x4000, 0x1000 },
[IBEX_DEV_GPIO] = { 0x4004, 0x1000 },
[IBEX_DEV_SPI_DEVICE] = { 0x4005, 0x1000 },
@@ -40,6 +40,7 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_TIMER] = { 0x4010, 0x1000 },
[IBEX_DEV_SENSOR_CTRL] ={ 0x4011, 0x1000 },
[IBEX_DEV_OTP_CTRL] = { 0x4013, 0x4000 },
+[IBEX_DEV_LC_CTRL] ={ 0x4014, 0x1000 },
[IBEX_DEV_USBDEV] = { 0x4015, 0x1000 },
[IBEX_DEV_SPI_HOST0] = { 0x4030, 0x1000 },
[IBEX_DEV_SPI_HOST1] = { 0x4031, 0x1000 },
@@ -141,7 +142,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc,
Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
-object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080,
&error_abort);
+object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x2490,
+&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
/* Boot ROM */
@@ -253,6 +255,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc,
Error **errp)
memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
+create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl",
+memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
--
2.37.2
[PULL 34/44] hw/core: fix platform bus node name
From: Conor Dooley
"platform" is not a valid name for a bus node in dt-schema, so warnings
can be see in dt-validate on a dump of the riscv virt dtb:
/stuff/qemu/qemu.dtb: platform@400: $nodename:0: 'platform@400' does
not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
From schema:
/home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml
"platform-bus" is a valid name, so use that instead.
CC: Rob Herring
Fixes: 11d306b9df ("hw/arm/sysbus-fdt: helpers for platform bus nodes addition")
Reviewed-by: Alistair Francis
Signed-off-by: Conor Dooley
Message-id: 20220810184612.157317-5-m...@conchuod.ie
Signed-off-by: Alistair Francis
---
hw/core/sysbus-fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/core/sysbus-fdt.c b/hw/core/sysbus-fdt.c
index 19d22cbe73..edb0c49b19 100644
--- a/hw/core/sysbus-fdt.c
+++ b/hw/core/sysbus-fdt.c
@@ -539,7 +539,7 @@ void platform_bus_add_all_fdt_nodes(void *fdt, const char
*intc, hwaddr addr,
assert(fdt);
-node = g_strdup_printf("/platform@%"PRIx64, addr);
+node = g_strdup_printf("/platform-bus@%"PRIx64, addr);
/* Create a /platform node that we can put all devices into */
qemu_fdt_add_subnode(fdt, node);
--
2.37.2
[PULL 38/44] target/riscv: Add stimecmp support
From: Atish Patra
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220824221357.41070-3-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 5 ++
target/riscv/cpu_bits.h| 4 ++
target/riscv/time_helper.h | 30
target/riscv/cpu.c | 9
target/riscv/csr.c | 86 +
target/riscv/machine.c | 1 +
target/riscv/time_helper.c | 98 ++
target/riscv/meson.build | 3 +-
8 files changed, 235 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/time_helper.h
create mode 100644 target/riscv/time_helper.c
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 53335def23..d2529b757a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -308,6 +308,9 @@ struct CPUArchState {
uint64_t mfromhost;
uint64_t mtohost;
+/* Sstc CSRs */
+uint64_t stimecmp;
+
/* physical memory protection */
pmp_table_t pmp_state;
target_ulong mseccfg;
@@ -361,6 +364,7 @@ struct CPUArchState {
float_status fp_status;
/* Fields from here on are preserved across CPU reset. */
+QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
hwaddr kernel_addr;
hwaddr fdt_addr;
@@ -424,6 +428,7 @@ struct RISCVCPUConfig {
bool ext_ifencei;
bool ext_icsr;
bool ext_zihintpause;
+bool ext_sstc;
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 6be5a9e9f0..ac17cf1515 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -206,6 +206,10 @@
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
+/* Sstc supervisor CSRs */
+#define CSR_STIMECMP0x14D
+#define CSR_STIMECMPH 0x15D
+
/* Supervisor Protection and Translation */
#define CSR_SPTBR 0x180
#define CSR_SATP0x180
diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h
new file mode 100644
index 00..7b3cdcc350
--- /dev/null
+++ b/target/riscv/time_helper.h
@@ -0,0 +1,30 @@
+/*
+ * RISC-V timer header file.
+ *
+ * Copyright (c) 2022 Rivos Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see
[PULL 29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals
From: Conor Dooley
Booting using "Direct Kernel Boot" for PolarFire SoC & skipping u-boot
entirely is probably not advisable, but it does at least show signs of
life. Recent Linux kernel versions make use of peripherals that are
missing definitions in QEMU and lead to kernel panics. These issues
almost certain rear their head for other methods of booting, but I was
unable to figure out a suitable HSS version that is recent enough to
support these peripherals & works with QEMU.
With these peripherals added, booting a kernel with the following hangs
hangs waiting for the system controller's hwrng, but the kernel no
longer panics. With the Linux driver for hwrng disabled, it boots to
console.
qemu-system-riscv64 -M microchip-icicle-kit \
-m 2G -smp 5 \
-kernel $(vmlinux_bin) \
-dtb $(dtb)\
-initrd $(initramfs) \
-display none -serial null \
-serial stdio
More peripherals are added than strictly required to fix the panics in
the hopes of avoiding a replication of this problem in the future.
Some of the peripherals which are in the device tree for recent kernels
are implemented in the FPGA fabric. The eMMC/SD mux, which exists as
an unimplemented device is replaced by a wider entry. This updated
entry covers both the mux & the remainder of the FPGA fabric connected
to the MSS using Fabric Interrconnect (FIC) 3.
Link:
https://github.com/polarfire-soc/icicle-kit-reference-design#fabric-memory-map
Link:
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/SupportingCollateral/V1_4_Register_Map.zip
Signed-off-by: Conor Dooley
Reviewed-by: Alistair Francis
Message-Id: <20220813135127.2971754-1-m...@conchuod.ie>
Signed-off-by: Alistair Francis
---
include/hw/riscv/microchip_pfsoc.h | 14 ++-
hw/riscv/microchip_pfsoc.c | 67 +++---
2 files changed, 74 insertions(+), 7 deletions(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
index a0673f5f59..a757b240e0 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -88,8 +88,11 @@ enum {
MICROCHIP_PFSOC_L2LIM,
MICROCHIP_PFSOC_PLIC,
MICROCHIP_PFSOC_MMUART0,
+MICROCHIP_PFSOC_WDOG0,
MICROCHIP_PFSOC_SYSREG,
+MICROCHIP_PFSOC_AXISW,
MICROCHIP_PFSOC_MPUCFG,
+MICROCHIP_PFSOC_FMETER,
MICROCHIP_PFSOC_DDR_SGMII_PHY,
MICROCHIP_PFSOC_EMMC_SD,
MICROCHIP_PFSOC_DDR_CFG,
@@ -97,19 +100,28 @@ enum {
MICROCHIP_PFSOC_MMUART2,
MICROCHIP_PFSOC_MMUART3,
MICROCHIP_PFSOC_MMUART4,
+MICROCHIP_PFSOC_WDOG1,
+MICROCHIP_PFSOC_WDOG2,
+MICROCHIP_PFSOC_WDOG3,
+MICROCHIP_PFSOC_WDOG4,
MICROCHIP_PFSOC_SPI0,
MICROCHIP_PFSOC_SPI1,
+MICROCHIP_PFSOC_I2C0,
MICROCHIP_PFSOC_I2C1,
+MICROCHIP_PFSOC_CAN0,
+MICROCHIP_PFSOC_CAN1,
MICROCHIP_PFSOC_GEM0,
MICROCHIP_PFSOC_GEM1,
MICROCHIP_PFSOC_GPIO0,
MICROCHIP_PFSOC_GPIO1,
MICROCHIP_PFSOC_GPIO2,
+MICROCHIP_PFSOC_RTC,
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
+MICROCHIP_PFSOC_USB,
MICROCHIP_PFSOC_QSPI_XIP,
MICROCHIP_PFSOC_IOSCB,
-MICROCHIP_PFSOC_EMMC_SD_MUX,
+MICROCHIP_PFSOC_FABRIC_FIC3,
MICROCHIP_PFSOC_DRAM_LO,
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
MICROCHIP_PFSOC_DRAM_HI,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 7313153606..a821263d4f 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -100,8 +100,11 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
[MICROCHIP_PFSOC_L2LIM] = { 0x800, 0x200 },
[MICROCHIP_PFSOC_PLIC] ={ 0xc00, 0x400 },
[MICROCHIP_PFSOC_MMUART0] = { 0x2000, 0x1000 },
+[MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
+[MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
+[MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 },
[MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
[MICROCHIP_PFSOC_DDR_CFG] = { 0x2008,0x4 },
@@ -109,19 +112,28 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
+[MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 },
+[MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 },
+[MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 },
+[MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_SPI0] ={ 0x20108000, 0x1000 },
[MICROCHIP_PF
[PULL 39/44] target/riscv: Add vstimecmp support
From: Atish Patra
vstimecmp CSR allows the guest OS or to program the next guest timer
interrupt directly. Thus, hypervisor no longer need to inject the
timer interrupt to the guest if vstimecmp is used. This was ratified
as a part of the Sstc extension.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220824221357.41070-4-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 4 ++
target/riscv/cpu_bits.h| 4 ++
target/riscv/cpu_helper.c | 11 +++--
target/riscv/csr.c | 88 --
target/riscv/machine.c | 1 +
target/riscv/time_helper.c | 16 +++
6 files changed, 118 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d2529b757a..d895a0af2c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -311,6 +311,8 @@ struct CPUArchState {
/* Sstc CSRs */
uint64_t stimecmp;
+uint64_t vstimecmp;
+
/* physical memory protection */
pmp_table_t pmp_state;
target_ulong mseccfg;
@@ -365,6 +367,8 @@ struct CPUArchState {
/* Fields from here on are preserved across CPU reset. */
QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
+QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
+bool vstime_irq;
hwaddr kernel_addr;
hwaddr fdt_addr;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ac17cf1515..095dab19f5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -257,6 +257,10 @@
#define CSR_VSIP0x244
#define CSR_VSATP 0x280
+/* Sstc virtual CSRs */
+#define CSR_VSTIMECMP 0x24D
+#define CSR_VSTIMECMPH 0x25D
+
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 05c0c8d777..719c5d5d02 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -346,8 +346,9 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env)
{
uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
+uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0;
-return (env->mip | vsgein) & env->mie;
+return (env->mip | vsgein | vstip) & env->mie;
}
int riscv_cpu_mirq_pending(CPURISCVState *env)
@@ -606,7 +607,7 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask,
uint64_t value)
{
CPURISCVState *env = &cpu->env;
CPUState *cs = CPU(cpu);
-uint64_t gein, vsgein = 0, old = env->mip;
+uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
bool locked = false;
if (riscv_cpu_virt_enabled(env)) {
@@ -614,6 +615,10 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t
mask, uint64_t value)
vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
}
+/* No need to update mip for VSTIP */
+mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask;
+vstip = env->vstime_irq ? MIP_VSTIP : 0;
+
if (!qemu_mutex_iothread_locked()) {
locked = true;
qemu_mutex_lock_iothread();
@@ -621,7 +626,7 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask,
uint64_t value)
env->mip = (env->mip & ~mask) | (value & mask);
-if (env->mip | vsgein) {
+if (env->mip | vsgein | vstip) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 04b06a2389..1a35ac48cc 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -820,6 +820,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
{
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
+bool hmode_check = false;
if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -838,7 +839,18 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
-return smode(env, csrno);
+if (riscv_cpu_virt_enabled(env)) {
+if (!(get_field(env->hcounteren, COUNTEREN_TM) &
+ get_field(env->henvcfg, HENVCFG_STCE))) {
+return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+}
+}
+
+if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
+hmode_check = true;
+}
+
+return hmode_check ? hmode(env, csrno) : smode(env, csrno);
}
static RISCVException sstc_32(CPURISCVState *env, int csrno)
@@ -850,17 +862,72 @@ static RISCVException sstc_32(CPURISCVState *env, int
csrno)
return sstc(env, csrno);
}
+static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
+target_ulong *val)
+{
+*val = env->vstimecmp;
+
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
+target_ulong *val)
+{
+*val = env->vstimec
[PULL 42/44] target/riscv: Add few cache related PMU events
From: Atish Patra
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Reviewed-by: Alistair Francis
Tested-by: Heiko Stuebner
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
Message-Id: <20220824221701.41932-4-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 719c5d5d02..67e4c0efd2 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -21,11 +21,13 @@
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "cpu.h"
+#include "pmu.h"
#include "exec/exec-all.h"
#include "instmap.h"
#include "tcg/tcg-op.h"
#include "trace.h"
#include "semihosting/common-semi.h"
+#include "cpu_bits.h"
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
@@ -1189,6 +1191,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr
addr,
cpu_loop_exit_restore(cs, retaddr);
}
+
+static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
+{
+enum riscv_pmu_event_idx pmu_event_type;
+
+switch (access_type) {
+case MMU_INST_FETCH:
+pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
+break;
+case MMU_DATA_LOAD:
+pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
+break;
+case MMU_DATA_STORE:
+pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
+break;
+default:
+return;
+}
+
+riscv_pmu_incr_ctr(cpu, pmu_event_type);
+}
+
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
@@ -1287,6 +1311,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
}
}
} else {
+pmu_tlb_fill_incr_ctr(cpu, access_type);
/* Single stage lookup */
ret = get_physical_address(env, &pa, &prot, address, NULL,
access_type, mmu_idx, true, false, false);
--
2.37.2
[PULL 31/44] hw/riscv: virt: fix uart node name
From: Conor Dooley
"uart" is not a node name that complies with the dt-schema.
Change the node name to "serial" to ix warnings seen during
dt-validate on a dtbdump of the virt machine such as:
/stuff/qemu/qemu.dtb: uart@1000: $nodename:0: 'uart@1000' does not
match '^serial(@.*)?$'
From schema:
/stuff/linux/Documentation/devicetree/bindings/serial/8250.yaml
Reported-by: Rob Herring
Reviewed-by: Alistair Francis
Signed-off-by: Conor Dooley
Message-id: 20220810184612.157317-2-m...@conchuod.ie
Link:
https://lore.kernel.org/linux-riscv/20220803170552.ga2250266-r...@kernel.org/
Fixes: 04331d0b56 ("RISC-V VirtIO Machine")
Signed-off-by: Conor Dooley
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index c1e8e0fcaf..9d36133b74 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -918,7 +918,7 @@ static void create_fdt_uart(RISCVVirtState *s, const
MemMapEntry *memmap,
char *name;
MachineState *mc = MACHINE(s);
-name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
+name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base);
qemu_fdt_add_subnode(mc->fdt, name);
qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
qemu_fdt_setprop_cells(mc->fdt, name, "reg",
--
2.37.2
[PULL 41/44] target/riscv: Simplify counter predicate function
From: Atish Patra
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.
Simplify the predicate function so that we just handle things differently
between RV32/RV64 and S/HS mode.
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220824221701.41932-3-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 110 -
1 file changed, 9 insertions(+), 101 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 888ddfc4dd..2151e280a8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -75,6 +75,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index;
+target_ulong ctr_mask;
int base_csrno = CSR_CYCLE;
bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false;
@@ -83,122 +84,29 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
base_csrno += 0x80;
}
ctr_index = csrno - base_csrno;
+ctr_mask = BIT(ctr_index);
if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||
(csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {
goto skip_ext_pmu_check;
}
-if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index {
+if (!(cpu->pmu_avail_ctrs & ctr_mask)) {
/* No counter is enabled in PMU or the counter is out of range */
return RISCV_EXCP_ILLEGAL_INST;
}
skip_ext_pmu_check:
-if (env->priv == PRV_S) {
-switch (csrno) {
-case CSR_CYCLE:
-if (!get_field(env->mcounteren, COUNTEREN_CY)) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-break;
-case CSR_TIME:
-if (!get_field(env->mcounteren, COUNTEREN_TM)) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-break;
-case CSR_INSTRET:
-if (!get_field(env->mcounteren, COUNTEREN_IR)) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-break;
-case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
-if (!get_field(env->mcounteren, 1 << ctr_index)) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-break;
-}
-if (rv32) {
-switch (csrno) {
-case CSR_CYCLEH:
-if (!get_field(env->mcounteren, COUNTEREN_CY)) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-break;
-case CSR_TIMEH:
-if (!get_field(env->mcounteren, COUNTEREN_TM)) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-break;
-case CSR_INSTRETH:
-if (!get_field(env->mcounteren, COUNTEREN_IR)) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-break;
-case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
-if (!get_field(env->mcounteren, 1 << ctr_index)) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-break;
-}
-}
+if (((env->priv == PRV_S) && (!get_field(env->mcounteren, ctr_mask))) ||
+((env->priv == PRV_U) && (!get_field(env->scounteren, ctr_mask {
+return RISCV_EXCP_ILLEGAL_INST;
}
if (riscv_cpu_virt_enabled(env)) {
-switch (csrno) {
-case CSR_CYCLE:
-if (!get_field(env->hcounteren, COUNTEREN_CY) &&
-get_field(env->mcounteren, COUNTEREN_CY)) {
-return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-}
-break;
-case CSR_TIME:
-if (!get_field(env->hcounteren, COUNTEREN_TM) &&
-get_field(env->mcounteren, COUNTEREN_TM)) {
-return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-}
-break;
-case CSR_INSTRET:
-if (!get_field(env->hcounteren, COUNTEREN_IR) &&
-get_field(env->mcounteren, COUNTEREN_IR)) {
-return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-}
-break;
-case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
-if (!get_field(env->hcounteren, 1 << ctr_index) &&
- get_field(env->mcounteren, 1 << ctr_index)) {
-return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-}
-break;
-}
-if (rv32) {
-switch (csrno) {
-case CSR_CYCLEH:
-if (!get_field(env->hcounteren, COUNTEREN_CY) &&
-get_field(env->mcounteren, COUNTEREN_CY)) {
-return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-}
-break;
-case CSR_TIMEH:
-if (!get_field(env->hcounteren, COUNTEREN_TM) &&
-
Re: [PATCH] fw_cfg: Don't set callback_opaque NULL in fw_cfg_modify_bytes_read()
On Thu, 25 Aug 2022 17:18:42 +0100
Shameer Kolothum wrote:
> Hi
>
> On arm/virt platform, Chen Xiang reported a Guest crash while
> attempting the below steps,
>
> 1. Launch the Guest with nvdimm=on
> 2. Hot-add a NVDIMM dev
> 3. Reboot
> 4. Guest boots fine.
> 5. Reboot again.
> 6. Guest boot fails.
>
> QEMU_EFI reports the below error:
> ProcessCmdAddPointer: invalid pointer value in "etc/acpi/tables"
> OnRootBridgesConnected: InstallAcpiTables: Protocol Error
>
> Debugging shows that on first reboot(after hot-adding NVDIMM),
> Qemu updates the etc/table-loader len,
>
> qemu_ram_resize()
> fw_cfg_modify_file()
> fw_cfg_modify_bytes_read()
>
> And in fw_cfg_modify_bytes_read() we set the "callback_opaque" for
> the "key" entry to NULL. Because of this, on the second reboot,
> virt_acpi_build_update() is called with a NULL "build_state" and
> returns without updating the ACPI tables. This seems to be
> upsetting the firmware.
>
> To fix this, don't change the callback_opaque in fw_cfg_modify_bytes_read().
Fixes: bdbb5b1706d165 ("fw_cfg: add fw_cfg_machine_reset function")
Acked-by: Igor Mammedov
CCing Gerd to have a second set of eyes on it
> Reported-by: chenxiang
> Signed-off-by: Shameer Kolothum
> ---
> I am still not very convinced this is the root cause of the issue.
> Though it looks like setting callback_opaque to NULL while updating
> the file size is wrong, what puzzles me is that on the second reboot
> we don't have any ACPI table size changes and ideally firmware should
> see the updated tables from the first reboot itself.
>
> Please take a look and let me know.
>
> Thanks,
> Shameer
>
> ---
> hw/nvram/fw_cfg.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
> index d605f3f45a..dfe8404c01 100644
> --- a/hw/nvram/fw_cfg.c
> +++ b/hw/nvram/fw_cfg.c
> @@ -728,7 +728,6 @@ static void *fw_cfg_modify_bytes_read(FWCfgState *s,
> uint16_t key,
> ptr = s->entries[arch][key].data;
> s->entries[arch][key].data = data;
> s->entries[arch][key].len = len;
> -s->entries[arch][key].callback_opaque = NULL;
> s->entries[arch][key].allow_write = false;
As Christian have mentioned, this also looks bogus.
perhaps another patch to fix that as well.
> return ptr;
[PULL 43/44] hw/riscv: virt: Add PMU DT node to the device tree
From: Atish Patra
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Acked-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
Message-Id: <20220824221701.41932-5-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/pmu.h | 1 +
hw/riscv/virt.c| 16 +
target/riscv/pmu.c | 57 ++
3 files changed, 74 insertions(+)
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
index 036653627f..3004ce37b6 100644
--- a/target/riscv/pmu.h
+++ b/target/riscv/pmu.h
@@ -31,5 +31,6 @@ int riscv_pmu_init(RISCVCPU *cpu, int num_counters);
int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx);
int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
+void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_name);
int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ff8c0df5cd..befa9d2c26 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -30,6 +30,7 @@
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/core/sysbus-fdt.h"
+#include "target/riscv/pmu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
@@ -708,6 +709,20 @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
aplic_phandles[socket] = aplic_s_phandle;
}
+static void create_fdt_pmu(RISCVVirtState *s)
+{
+char *pmu_name;
+MachineState *mc = MACHINE(s);
+RISCVCPU hart = s->soc[0].harts[0];
+
+pmu_name = g_strdup_printf("/soc/pmu");
+qemu_fdt_add_subnode(mc->fdt, pmu_name);
+qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu");
+riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name);
+
+g_free(pmu_name);
+}
+
static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
bool is_32_bit, uint32_t *phandle,
uint32_t *irq_mmio_phandle,
@@ -1036,6 +1051,7 @@ static void create_fdt(RISCVVirtState *s, const
MemMapEntry *memmap,
create_fdt_flash(s, memmap);
create_fdt_fw_cfg(s, memmap);
+create_fdt_pmu(s);
update_bootargs:
if (cmdline && *cmdline) {
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index a5f504e53c..b8e56d2b7b 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -20,11 +20,68 @@
#include "cpu.h"
#include "pmu.h"
#include "sysemu/cpu-timers.h"
+#include "sysemu/device_tree.h"
#define RISCV_TIMEBASE_FREQ 10 /* 1Ghz */
#define MAKE_32BIT_MASK(shift, length) \
(((uint32_t)(~0UL) >> (32 - (length))) << (shift))
+/*
+ * To keep it simple, any event can be mapped to any programmable counters in
+ * QEMU. The generic cycle & instruction count events can also be monitored
+ * using programmable counters. In that case, mcycle & minstret must continue
+ * to provide the correct value as well. Heterogeneous PMU per hart is not
+ * supported yet. Thus, number of counters are same across all harts.
+ */
+void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name)
+{
+uint32_t fdt_event_ctr_map[20] = {};
+uint32_t cmask;
+
+/* All the programmable counters can map to any event */
+cmask = MAKE_32BIT_MASK(3, num_ctrs);
+
+ /*
+* The event encoding is specified in the SBI specification
+* Event idx is a 20bits wide number encoded as follows:
+* event_idx[19:16] = type
+* event_idx[15:0] = code
+* The code field in cache events are encoded as follows:
+* event_idx.code[15:3] = cache_id
+* event_idx.code[2:1] = op_id
+* event_idx.code[0:0] = result_id
+*/
+
+ /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */
+ fdt_event_ctr_map[0] = cpu_to_be32(0x0001);
+ fdt_event_ctr_map[1] = cpu_to_be32(0x0001);
+ fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0);
+
+ /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */
+ fdt_event_ctr_map[3] = cpu_to_be32(0x0002);
+ fdt_event_ctr_map[4] = cpu_to_be32(0x0002);
+ fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2);
+
+ /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */
+ fdt_event_ctr_map[6] = cpu_to_be32(0x00010019);
+ fdt_event_ctr_map[7] = cpu_to_be32(0x00010019);
+ fdt_event_ctr_map[8] = cpu_to_be32(cmask);
+
+ /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */
+ fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B);
+ fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B);
+ fdt_event_ctr_map[11] = cpu_to_be32(cmask);
+
+ /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */
+ fdt_event_ctr_ma
Re: [PATCH v3 3/5] acpi/nvdimm: define macro for NVDIMM Device _DSM
On Thu, 1 Sep 2022 11:27:19 +0800
Robert Hoo wrote:
> Since it will be heavily used in next patch, define macro
> NVDIMM_DEVICE_DSM_UUID for "4309AC30-0D11-11E4-9191-0800200C9A66", which is
> NVDIMM device specific method uuid defined in NVDIMM _DSM interface spec,
> Section 3. [1]
>
> No functional changes in this patch.
>
> [1] https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf
>
> Signed-off-by: Robert Hoo
> Reviewed-by: Jingqi Liu
Reviewed-by: Igor Mammedov
> ---
> hw/acpi/nvdimm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
> index 201317c611..afff911c1e 100644
> --- a/hw/acpi/nvdimm.c
> +++ b/hw/acpi/nvdimm.c
> @@ -922,6 +922,7 @@ void nvdimm_init_acpi_state(NVDIMMState *state,
> MemoryRegion *io,
> #define NVDIMM_DSM_RFIT_STATUS "RSTA"
>
> #define NVDIMM_QEMU_RSVD_UUID "648B9CF2-CDA1-4312-8AD9-49C4AF32BD62"
> +#define NVDIMM_DEVICE_DSM_UUID "4309AC30-0D11-11E4-9191-0800200C9A66"
>
> static void nvdimm_build_common_dsm(Aml *dev,
> NVDIMMState *nvdimm_state)
> @@ -1029,8 +1030,7 @@ static void nvdimm_build_common_dsm(Aml *dev,
> /* UUID for QEMU internal use */), expected_uuid));
> aml_append(elsectx, ifctx);
> elsectx2 = aml_else();
> -aml_append(elsectx2, aml_store(
> - aml_touuid("4309AC30-0D11-11E4-9191-0800200C9A66")
> +aml_append(elsectx2, aml_store(aml_touuid(NVDIMM_DEVICE_DSM_UUID)
> /* UUID for NVDIMM Devices */, expected_uuid));
> aml_append(elsectx, elsectx2);
> aml_append(method, elsectx);
Re: [PATCH] fw_cfg: Don't set callback_opaque NULL in fw_cfg_modify_bytes_read()
> > QEMU_EFI reports the below error:
> > ProcessCmdAddPointer: invalid pointer value in "etc/acpi/tables"
> > OnRootBridgesConnected: InstallAcpiTables: Protocol Error
> >
> > Debugging shows that on first reboot(after hot-adding NVDIMM),
> > Qemu updates the etc/table-loader len,
> >
> > qemu_ram_resize()
> > fw_cfg_modify_file()
> > fw_cfg_modify_bytes_read()
> >
> > And in fw_cfg_modify_bytes_read() we set the "callback_opaque" for
> > the "key" entry to NULL. Because of this, on the second reboot,
> > virt_acpi_build_update() is called with a NULL "build_state" and
> > returns without updating the ACPI tables. This seems to be
> > upsetting the firmware.
> >
> > To fix this, don't change the callback_opaque in fw_cfg_modify_bytes_read().
>
> Fixes: bdbb5b1706d165 ("fw_cfg: add fw_cfg_machine_reset function")
> Acked-by: Igor Mammedov
>
> CCing Gerd to have a second set of eyes on it
Hmm. Original patch clears both 'callback_opaque' and 'callback' (where
'callback' used to be what 'select_cb' is today I think). Not fully
sure what the motivation was for that. Maybe because using both
fw_cfg_modify*() calls and a callback for update-on-read for a given
entry looks pointless. Should that be the case there are better ways to
catch that, like having fw_cfg_modify_bytes_read() throw an error in
case select_cb is not NULL instead of silently clearing the callback.
In any case clearing callback_opaque only is obviously wrong, so
Acked-by: Gerd Hoffmann
take care,
Gerd
[PULL 44/44] target/riscv: Update the privilege field for sscofpmf CSRs
From: Atish Patra
The sscofpmf extension was ratified as a part of priv spec v1.12.
Mark the csr_ops accordingly.
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Message-Id: <20220824221701.41932-6-ati...@rivosinc.com>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 90 ++
1 file changed, 60 insertions(+), 30 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 2151e280a8..b96db1b62b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -4067,63 +4067,92 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
write_mhpmevent },
[CSR_MHPMEVENT3H]= { "mhpmevent3h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT4H]= { "mhpmevent4h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT5H]= { "mhpmevent5h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT6H]= { "mhpmevent6h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT7H]= { "mhpmevent7h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT8H]= { "mhpmevent8h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT9H]= { "mhpmevent9h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT10H] = { "mhpmevent10h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT11H] = { "mhpmevent11h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT12H] = { "mhpmevent12h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT13H] = { "mhpmevent13h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT14H] = { "mhpmevent14h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT15H] = { "mhpmevent15h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT16H] = { "mhpmevent16h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT17H] = { "mhpmevent17h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh },
+ write_mhpmeventh,
+ .min_priv_ver = PRIV_VERSION_1_12_0},
[CSR_MHPMEVENT18H] = { "mhpmevent18h",sscofpmf, read_mhpmeventh,
- write_mhpmeventh
Re: [PATCH v6 09/14] hw/ppc: set machine->fdt in pnv_reset()
On 05/09/2022 01:34, Daniel Henrique Barboza wrote: This will enable support for the 'dumpdtb' QMP/HMP command for all powernv machines. Cc: Cédric Le Goater Cc: Frederic Barrat Signed-off-by: Daniel Henrique Barboza --- LGTM Reviewed-by: Frederic Barrat Fred hw/ppc/pnv.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 354aa289d1..6a20c4811f 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -678,7 +678,13 @@ static void pnv_reset(MachineState *machine) qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); -g_free(fdt); +/* + * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free + * the existing machine->fdt to avoid leaking it during + * a reset. + */ +g_free(machine->fdt); +machine->fdt = fdt; } static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
Re: [PATCH 2/3] module: add Error arguments to module_load_one and module_load_qom_one
On 9/6/22 13:55, Claudio Fontana wrote:
> improve error handling during module load, by changing:
>
> bool module_load_one(const char *prefix, const char *lib_name);
> void module_load_qom_one(const char *type);
>
> to:
>
> bool module_load_one(const char *prefix, const char *name, Error **errp);
> bool module_load_qom_one(const char *type, Error **errp);
>
> module_load_qom_one has been introduced in:
>
> commit 28457744c345 ("module: qom module support"), which built on top of
> module_load_one, but discarded the bool return value. Restore it.
>
> Adapt all callers to emit errors, or ignore them, or fail hard,
> as appropriate in each context.
>
> Signed-off-by: Claudio Fontana
> ---
> audio/audio.c | 6 +-
> block.c | 12 +++-
> block/dmg.c | 10 ++-
> hw/core/qdev.c| 10 ++-
> include/qemu/module.h | 10 +--
> qom/object.c | 15 +++-
> softmmu/qtest.c | 6 +-
> ui/console.c | 19 +-
> util/module.c | 155 ++
> 9 files changed, 182 insertions(+), 61 deletions(-)
>
> diff --git a/audio/audio.c b/audio/audio.c
> index 76b8735b44..4f4bb10cce 100644
> --- a/audio/audio.c
> +++ b/audio/audio.c
> @@ -72,6 +72,7 @@ void audio_driver_register(audio_driver *drv)
> audio_driver *audio_driver_lookup(const char *name)
> {
> struct audio_driver *d;
> +Error *local_err = NULL;
>
> QLIST_FOREACH(d, &audio_drivers, next) {
> if (strcmp(name, d->name) == 0) {
> @@ -79,7 +80,10 @@ audio_driver *audio_driver_lookup(const char *name)
> }
> }
>
> -audio_module_load_one(name);
> +if (!audio_module_load_one(name, &local_err) && local_err) {
> +error_report_err(local_err);
> +}
> +
> QLIST_FOREACH(d, &audio_drivers, next) {
> if (strcmp(name, d->name) == 0) {
> return d;
> diff --git a/block.c b/block.c
> index bc85f46eed..85c3742d7a 100644
> --- a/block.c
> +++ b/block.c
> @@ -464,7 +464,11 @@ BlockDriver *bdrv_find_format(const char *format_name)
> /* The driver isn't registered, maybe we need to load a module */
> for (i = 0; i < (int)ARRAY_SIZE(block_driver_modules); ++i) {
> if (!strcmp(block_driver_modules[i].format_name, format_name)) {
> -block_module_load_one(block_driver_modules[i].library_name);
> +Error *local_err = NULL;
> +if (!block_module_load_one(block_driver_modules[i].library_name,
> + &local_err) && local_err) {
> +error_report_err(local_err);
> +}
> break;
> }
> }
> @@ -976,7 +980,11 @@ BlockDriver *bdrv_find_protocol(const char *filename,
> for (i = 0; i < (int)ARRAY_SIZE(block_driver_modules); ++i) {
> if (block_driver_modules[i].protocol_name &&
> !strcmp(block_driver_modules[i].protocol_name, protocol)) {
> -block_module_load_one(block_driver_modules[i].library_name);
> +Error *local_err = NULL;
> +if (!block_module_load_one(block_driver_modules[i].library_name,
> + &local_err) && local_err) {
> +error_report_err(local_err);
> +}
> break;
> }
> }
> diff --git a/block/dmg.c b/block/dmg.c
> index 98db18d82a..349b05d20b 100644
> --- a/block/dmg.c
> +++ b/block/dmg.c
> @@ -434,6 +434,7 @@ static int dmg_open(BlockDriverState *bs, QDict *options,
> int flags,
> uint64_t plist_xml_offset, plist_xml_length;
> int64_t offset;
> int ret;
> +Error *local_err = NULL;
>
> ret = bdrv_apply_auto_read_only(bs, NULL, errp);
> if (ret < 0) {
> @@ -446,8 +447,13 @@ static int dmg_open(BlockDriverState *bs, QDict
> *options, int flags,
> return -EINVAL;
> }
>
> -block_module_load_one("dmg-bz2");
> -block_module_load_one("dmg-lzfse");
> +if (!block_module_load_one("dmg-bz2", &local_err) && local_err) {
> +error_report_err(local_err);
> +}
> +local_err = NULL;
> +if (!block_module_load_one("dmg-lzfse", &local_err) && local_err) {
> +error_report_err(local_err);
> +}
>
> s->n_chunks = 0;
> s->offsets = s->lengths = s->sectors = s->sectorcounts = NULL;
> diff --git a/hw/core/qdev.c b/hw/core/qdev.c
> index 0806d8fcaa..5902c59c94 100644
> --- a/hw/core/qdev.c
> +++ b/hw/core/qdev.c
> @@ -148,7 +148,15 @@ bool qdev_set_parent_bus(DeviceState *dev, BusState
> *bus, Error **errp)
> DeviceState *qdev_new(const char *name)
> {
> if (!object_class_by_name(name)) {
> -module_load_qom_one(name);
> +Error *local_err = NULL;
> +if (!module_load_qom_one(name, &local_err)) {
> +if (local_err) {
> +error_report_err(local_err);
> +} else {
> +error_report("could not find a module for type '%s'", name);
> +}
> +
Re: [PATCH 2/3] module: add Error arguments to module_load_one and module_load_qom_one
On 9/7/22 09:36, Gerd Hoffmann wrote: > Hi, > >> For this module_load_qom_all() maybe Gerd has a bit more context on >> was should be the error reporting here? > > Use case for module_load_qom_all() is someone enumerating the qom > objects available. So we load all modules known to have all object > types registered and can return a complete list. > > It could be that some of the known modules are not there. Consider a > distro packaging modules which depend on shared libraries into optional > sub-rpms, to reduce the dependency chain of core qemu. So, with core > qemu installed and (some of) the sub-rpms not installed > module_load_qom_all() will obviously fail to load some modules. > > But I don't think those errors should be reported. The object types > implemented by the missing modules will also be missing from the object > type list ... > > Example: hw-usb-host.so is not installed. > > => 'qemu -device help' should IMHO not report the module load error > and just not list the 'usb-host' device. > => 'qemu -device usb-host' should report the module load error. > > take care, > Gerd > Hi Gerd, the thing is, we can distinguish between a module not being present (ENOENT, ENOTDIR), from a module being present, but failing to load. So the "module not there" thing does not need to be treated separately, because no warning/error will be emitted if the module is not there. It is up to the user/caller to decide what to do with the condition "module not there", error out and quit, continue on, etc. Thanks this helped, Claudio
Re: [PATCH v9 03/10] s390x/cpu topology: reporting the CPU topology to the guest
On Fri, 2022-09-02 at 09:55 +0200, Pierre Morel wrote:
> The guest can use the STSI instruction to get a buffer filled
> with the CPU topology description.
>
> Let us implement the STSI instruction for the basis CPU topology
> level, level 2.
>
> Signed-off-by: Pierre Morel
> ---
> hw/s390x/cpu-topology.c | 4 ++
> include/hw/s390x/cpu-topology.h | 5 ++
> target/s390x/cpu.h | 49 +++
> target/s390x/cpu_topology.c | 108
> target/s390x/kvm/kvm.c | 6 +-
> target/s390x/meson.build| 1 +
> 6 files changed, 172 insertions(+), 1 deletion(-)
> create mode 100644 target/s390x/cpu_topology.c
>
[...]
> diff --git a/target/s390x/cpu_topology.c b/target/s390x/cpu_topology.c
[...]
> +static char *fill_tle_cpu(char *p, uint64_t mask, int origin)
> +{
> +SysIBTl_cpu *tle = (SysIBTl_cpu *)p;
> +
> +tle->nl = 0;
> +tle->dedicated = 1;
> +tle->polarity = S390_TOPOLOGY_POLARITY_H;
> +tle->type = S390_TOPOLOGY_CPU_TYPE;
> +tle->origin = origin * 64;
origin is a multibyte field too, so needs a conversion too.
> +tle->mask = be64_to_cpu(mask);
> +return p + sizeof(*tle);
> +}
> +
[...]
Re: [PATCH v9 05/10] s390x/cpu: reporting drawers and books topology to the guest
On Fri, 2022-09-02 at 09:55 +0200, Pierre Morel wrote:
> The guest can ask for a topology report on drawer's or book's
> level.
> Let's implement the STSI instruction's handling for the corresponding
> selector values.
>
> Signed-off-by: Pierre Morel
> ---
> hw/s390x/cpu-topology.c | 19 +++---
> hw/s390x/s390-virtio-ccw.c | 2 ++
> include/hw/s390x/cpu-topology.h | 7 +++-
> target/s390x/cpu_topology.c | 64 +++--
> 4 files changed, 76 insertions(+), 16 deletions(-)
>
> diff --git a/hw/s390x/cpu-topology.c b/hw/s390x/cpu-topology.c
> index e2fd5c7e44..bb9ae63483 100644
> --- a/hw/s390x/cpu-topology.c
> +++ b/hw/s390x/cpu-topology.c
>
[...]
> @@ -99,13 +103,20 @@ static void s390_topology_realize(DeviceState *dev,
> Error **errp)
> S390Topology *topo = S390_CPU_TOPOLOGY(dev);
> int n;
>
> +topo->drawers = ms->smp.drawers;
> +topo->books = ms->smp.books;
> +topo->total_books = topo->books * topo->drawers;
> topo->sockets = ms->smp.sockets;
> +topo->total_sockets = topo->sockets * topo->books * topo->drawers;
> topo->cores = ms->smp.cores;
> -topo->tles = ms->smp.max_cpus;
>
> -n = topo->sockets;
> +n = topo->drawers;
> +topo->drawer = g_malloc0(n * sizeof(S390TopoContainer));
> +n *= topo->books;
> +topo->book = g_malloc0(n * sizeof(S390TopoContainer));
> +n *= topo->sockets;
> topo->socket = g_malloc0(n * sizeof(S390TopoContainer));
> -topo->tle = g_malloc0(topo->tles * sizeof(S390TopoTLE));
> +topo->tle = g_malloc0(n * sizeof(S390TopoTLE));
Same question here about using g_new0.
>
> qemu_mutex_init(&topo->topo_mutex);
> }
> diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
> index 15cefd104b..3f28e28d47 100644
> --- a/hw/s390x/s390-virtio-ccw.c
> +++ b/hw/s390x/s390-virtio-ccw.c
> @@ -626,6 +626,8 @@ static void ccw_machine_class_init(ObjectClass *oc, void
> *data)
> hc->unplug_request = s390_machine_device_unplug_request;
> nc->nmi_monitor_handler = s390_nmi;
> mc->default_ram_id = "s390.ram";
> +mc->smp_props.books_supported = true;
> +mc->smp_props.drawers_supported = true;
> }
>
> static inline bool machine_get_aes_key_wrap(Object *obj, Error **errp)
> diff --git a/include/hw/s390x/cpu-topology.h b/include/hw/s390x/cpu-topology.h
> index 0b7f3d10b2..4f8ac39ca0 100644
> --- a/include/hw/s390x/cpu-topology.h
> +++ b/include/hw/s390x/cpu-topology.h
> @@ -29,9 +29,14 @@ typedef struct S390TopoTLE {
>
> struct S390Topology {
> SysBusDevice parent_obj;
> +int total_books;
> +int total_sockets;
What are these used for? I'm not seeing anything.
> +int drawers;
> +int books;
> int sockets;
> int cores;
> -int tles;
You remove this in this patch and you didn't really need it before.
As far as I can tell it was just used for calculating the number of
tles to allocate and you could use a local variable instead.
So I would get rid of it in the patch that introduced it.
> +S390TopoContainer *drawer;
> +S390TopoContainer *book;
> S390TopoContainer *socket;
> S390TopoTLE *tle;
> QemuMutex topo_mutex;
> diff --git a/target/s390x/cpu_topology.c b/target/s390x/cpu_topology.c
> index 56865dafc6..305fbb9734 100644
> --- a/target/s390x/cpu_topology.c
> +++ b/target/s390x/cpu_topology.c
> @@ -37,19 +37,18 @@ static char *fill_tle_cpu(char *p, uint64_t mask, int
> origin)
> return p + sizeof(*tle);
> }
>
> -static char *s390_top_set_level2(S390Topology *topo, char *p)
> +static char *s390_top_set_level2(S390Topology *topo, char *p, int fs, int ns)
> {
I wouldn't hate more verbose names for fs and ns. start_socket,
num_socket maybe? Same for fb, nb, but it is your call, it's not really
hard to understand the code.
> -int i, origin;
> +int socket, origin;
> +uint64_t mask;
>
> -for (i = 0; i < topo->sockets; i++) {
> -if (!topo->socket[i].active_count) {
> +for (socket = fs; socket < fs + ns; socket++) {
> +if (!topo->socket[socket].active_count) {
> continue;
> }
> -p = fill_container(p, 1, i);
> +p = fill_container(p, 1, socket);
Have you considered using an enum for the level constants?
> for (origin = 0; origin < S390_TOPOLOGY_MAX_ORIGIN; origin++) {
> -uint64_t mask = 0L;
> -
> -mask = be64_to_cpu(topo->tle[i].mask[origin]);
> +mask = be64_to_cpu(topo->tle[socket].mask[origin]);
> if (mask) {
> p = fill_tle_cpu(p, mask, origin);
> }
> @@ -58,19 +57,63 @@ static char *s390_top_set_level2(S390Topology *topo, char
> *p)
> return p;
> }
>
> +static char *s390_top_set_level3(S390Topology *topo, char *p, int fb, int nb)
> +{
> +int book, fs = 0;
> +
> +for (book = fb; book < fb + nb; book++, fs += topo->sockets) {
> +if (!topo->book[book].active_count) {
> +cont
[PATCH v2 1/3] module: removed unused function argument "mayfail"
mayfail is always passed as false for every invocation throughout the program.
It controls whether to printf or not to printf an error on
g_module_open failure.
Remove this unused argument.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
include/qemu/module.h | 8
softmmu/qtest.c | 2 +-
util/module.c | 20 +---
3 files changed, 14 insertions(+), 16 deletions(-)
diff --git a/include/qemu/module.h b/include/qemu/module.h
index bd73607104..8c012bbe03 100644
--- a/include/qemu/module.h
+++ b/include/qemu/module.h
@@ -61,15 +61,15 @@ typedef enum {
#define fuzz_target_init(function) module_init(function, \
MODULE_INIT_FUZZ_TARGET)
#define migration_init(function) module_init(function, MODULE_INIT_MIGRATION)
-#define block_module_load_one(lib) module_load_one("block-", lib, false)
-#define ui_module_load_one(lib) module_load_one("ui-", lib, false)
-#define audio_module_load_one(lib) module_load_one("audio-", lib, false)
+#define block_module_load_one(lib) module_load_one("block-", lib)
+#define ui_module_load_one(lib) module_load_one("ui-", lib)
+#define audio_module_load_one(lib) module_load_one("audio-", lib)
void register_module_init(void (*fn)(void), module_init_type type);
void register_dso_module_init(void (*fn)(void), module_init_type type);
void module_call_init(module_init_type type);
-bool module_load_one(const char *prefix, const char *lib_name, bool mayfail);
+bool module_load_one(const char *prefix, const char *lib_name);
void module_load_qom_one(const char *type);
void module_load_qom_all(void);
void module_allow_arch(const char *arch);
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index f8acef2628..76eb7bac56 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qtest.c
@@ -756,7 +756,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
g_assert(words[1] && words[2]);
qtest_send_prefix(chr);
-if (module_load_one(words[1], words[2], false)) {
+if (module_load_one(words[1], words[2])) {
qtest_sendf(chr, "OK\n");
} else {
qtest_sendf(chr, "FAIL\n");
diff --git a/util/module.c b/util/module.c
index 8ddb0e18f5..8563edd626 100644
--- a/util/module.c
+++ b/util/module.c
@@ -144,7 +144,7 @@ static bool module_check_arch(const QemuModinfo *modinfo)
return true;
}
-static int module_load_file(const char *fname, bool mayfail, bool
export_symbols)
+static int module_load_file(const char *fname, bool export_symbols)
{
GModule *g_module;
void (*sym)(void);
@@ -172,10 +172,8 @@ static int module_load_file(const char *fname, bool
mayfail, bool export_symbols
}
g_module = g_module_open(fname, flags);
if (!g_module) {
-if (!mayfail) {
-fprintf(stderr, "Failed to open module: %s\n",
-g_module_error());
-}
+fprintf(stderr, "Failed to open module: %s\n",
+g_module_error());
ret = -EINVAL;
goto out;
}
@@ -208,7 +206,7 @@ out:
}
#endif
-bool module_load_one(const char *prefix, const char *lib_name, bool mayfail)
+bool module_load_one(const char *prefix, const char *lib_name)
{
bool success = false;
@@ -256,7 +254,7 @@ bool module_load_one(const char *prefix, const char
*lib_name, bool mayfail)
if (strcmp(modinfo->name, module_name) == 0) {
/* we depend on other module(s) */
for (sl = modinfo->deps; *sl != NULL; sl++) {
-module_load_one("", *sl, false);
+module_load_one("", *sl);
}
} else {
for (sl = modinfo->deps; *sl != NULL; sl++) {
@@ -287,7 +285,7 @@ bool module_load_one(const char *prefix, const char
*lib_name, bool mayfail)
for (i = 0; i < n_dirs; i++) {
fname = g_strdup_printf("%s/%s%s",
dirs[i], module_name, CONFIG_HOST_DSOSUF);
-ret = module_load_file(fname, mayfail, export_symbols);
+ret = module_load_file(fname, export_symbols);
g_free(fname);
fname = NULL;
/* Try loading until loaded a module file */
@@ -333,7 +331,7 @@ void module_load_qom_one(const char *type)
}
for (sl = modinfo->objs; *sl != NULL; sl++) {
if (strcmp(type, *sl) == 0) {
-module_load_one("", modinfo->name, false);
+module_load_one("", modinfo->name);
}
}
}
@@ -354,7 +352,7 @@ void module_load_qom_all(void)
if (!module_check_arch(modinfo)) {
continue;
}
-module_load_one("", modinfo->name, false);
+module_load_one("", modinfo->name);
}
module_loaded_qom_all = true;
}
@@ -370,7 +368,7 @@ void qemu_load_module_for_opts(const char *group)
}
for (sl = modinfo->opts; *sl != NULL; sl++) {
[PATCH v2 2/3] module: add Error arguments to module_load_one and module_load_qom_one
improve error handling during module load, by changing:
bool module_load_one(const char *prefix, const char *lib_name);
void module_load_qom_one(const char *type);
to:
bool module_load_one(const char *prefix, const char *name, Error **errp);
bool module_load_qom_one(const char *type, Error **errp);
module_load_qom_one has been introduced in:
commit 28457744c345 ("module: qom module support"), which built on top of
module_load_one, but discarded the bool return value. Restore it.
Adapt all callers to emit errors, or ignore them, or fail hard,
as appropriate in each context.
Signed-off-by: Claudio Fontana
---
audio/audio.c | 6 +-
block.c | 12 +++-
block/dmg.c | 10 ++-
hw/core/qdev.c| 10 ++-
include/qemu/module.h | 10 +--
qom/object.c | 15 +++-
softmmu/qtest.c | 6 +-
ui/console.c | 18 -
util/module.c | 155 ++
9 files changed, 181 insertions(+), 61 deletions(-)
diff --git a/audio/audio.c b/audio/audio.c
index 76b8735b44..4f4bb10cce 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -72,6 +72,7 @@ void audio_driver_register(audio_driver *drv)
audio_driver *audio_driver_lookup(const char *name)
{
struct audio_driver *d;
+Error *local_err = NULL;
QLIST_FOREACH(d, &audio_drivers, next) {
if (strcmp(name, d->name) == 0) {
@@ -79,7 +80,10 @@ audio_driver *audio_driver_lookup(const char *name)
}
}
-audio_module_load_one(name);
+if (!audio_module_load_one(name, &local_err) && local_err) {
+error_report_err(local_err);
+}
+
QLIST_FOREACH(d, &audio_drivers, next) {
if (strcmp(name, d->name) == 0) {
return d;
diff --git a/block.c b/block.c
index bc85f46eed..85c3742d7a 100644
--- a/block.c
+++ b/block.c
@@ -464,7 +464,11 @@ BlockDriver *bdrv_find_format(const char *format_name)
/* The driver isn't registered, maybe we need to load a module */
for (i = 0; i < (int)ARRAY_SIZE(block_driver_modules); ++i) {
if (!strcmp(block_driver_modules[i].format_name, format_name)) {
-block_module_load_one(block_driver_modules[i].library_name);
+Error *local_err = NULL;
+if (!block_module_load_one(block_driver_modules[i].library_name,
+ &local_err) && local_err) {
+error_report_err(local_err);
+}
break;
}
}
@@ -976,7 +980,11 @@ BlockDriver *bdrv_find_protocol(const char *filename,
for (i = 0; i < (int)ARRAY_SIZE(block_driver_modules); ++i) {
if (block_driver_modules[i].protocol_name &&
!strcmp(block_driver_modules[i].protocol_name, protocol)) {
-block_module_load_one(block_driver_modules[i].library_name);
+Error *local_err = NULL;
+if (!block_module_load_one(block_driver_modules[i].library_name,
+ &local_err) && local_err) {
+error_report_err(local_err);
+}
break;
}
}
diff --git a/block/dmg.c b/block/dmg.c
index 98db18d82a..349b05d20b 100644
--- a/block/dmg.c
+++ b/block/dmg.c
@@ -434,6 +434,7 @@ static int dmg_open(BlockDriverState *bs, QDict *options,
int flags,
uint64_t plist_xml_offset, plist_xml_length;
int64_t offset;
int ret;
+Error *local_err = NULL;
ret = bdrv_apply_auto_read_only(bs, NULL, errp);
if (ret < 0) {
@@ -446,8 +447,13 @@ static int dmg_open(BlockDriverState *bs, QDict *options,
int flags,
return -EINVAL;
}
-block_module_load_one("dmg-bz2");
-block_module_load_one("dmg-lzfse");
+if (!block_module_load_one("dmg-bz2", &local_err) && local_err) {
+error_report_err(local_err);
+}
+local_err = NULL;
+if (!block_module_load_one("dmg-lzfse", &local_err) && local_err) {
+error_report_err(local_err);
+}
s->n_chunks = 0;
s->offsets = s->lengths = s->sectors = s->sectorcounts = NULL;
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 0806d8fcaa..5902c59c94 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -148,7 +148,15 @@ bool qdev_set_parent_bus(DeviceState *dev, BusState *bus,
Error **errp)
DeviceState *qdev_new(const char *name)
{
if (!object_class_by_name(name)) {
-module_load_qom_one(name);
+Error *local_err = NULL;
+if (!module_load_qom_one(name, &local_err)) {
+if (local_err) {
+error_report_err(local_err);
+} else {
+error_report("could not find a module for type '%s'", name);
+}
+abort();
+}
}
return DEVICE(object_new(name));
}
diff --git a/include/qemu/module.h b/include/qemu/module.h
index 8c012bbe03..7893922aba 100644
--- a/include/qemu/module.h
+++ b/include/qemu/module.h
@@ -61,16 +61,16 @@ typedef enum {
#define fuzz_target_init(function) module_init(f
[PATCH v2 0/3] improve error handling for module load
while investigating a permission issue in accel, where accel-tcg-x86_64.so was not accessible, I noticed that no errors were produced regarding the module load failure. This series attempts to improve module_load_one and module_load_qom_one to handle the error cases better and produce some errors. Patch 1 is already reviewed and is about removing an unused existing argument "mayfail" from the call stack. Patch 2 is the real meat, and that one I would say is RFC. Will follow up with comments on the specific questions I have. Patch 3 finally adds a simple check in accel/, aborting if a module is not found, but relying on the existing error report from module_load_qom_one. v1 -> v2: * do not treat the display help text any differently and do report module load _errors_. If the module does not exist (ENOENT, ENOTDIR), no error will be produced. Claudio Fontana (3): module: removed unused function argument "mayfail" module: add Error arguments to module_load_one and module_load_qom_one accel: abort if we fail to load the accelerator plugin accel/accel-softmmu.c | 8 ++- audio/audio.c | 6 +- block.c | 12 +++- block/dmg.c | 10 ++- hw/core/qdev.c| 10 ++- include/qemu/module.h | 10 +-- qom/object.c | 15 +++- softmmu/qtest.c | 6 +- ui/console.c | 18 - util/module.c | 157 ++ 10 files changed, 188 insertions(+), 64 deletions(-) -- 2.26.2
[PATCH v2 3/3] accel: abort if we fail to load the accelerator plugin
if QEMU is configured with modules enabled, it is possible that the
load of an accelerator module will fail.
Abort in this case, relying on module_object_class_by_name to report
the specific load error if any.
Signed-off-by: Claudio Fontana
---
accel/accel-softmmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/accel/accel-softmmu.c b/accel/accel-softmmu.c
index 67276e4f52..9fa4849f2c 100644
--- a/accel/accel-softmmu.c
+++ b/accel/accel-softmmu.c
@@ -66,6 +66,7 @@ void accel_init_ops_interfaces(AccelClass *ac)
{
const char *ac_name;
char *ops_name;
+ObjectClass *oc;
AccelOpsClass *ops;
ac_name = object_class_get_name(OBJECT_CLASS(ac));
@@ -73,8 +74,13 @@ void accel_init_ops_interfaces(AccelClass *ac)
ops_name = g_strdup_printf("%s" ACCEL_OPS_SUFFIX, ac_name);
ops = ACCEL_OPS_CLASS(module_object_class_by_name(ops_name));
+oc = module_object_class_by_name(ops_name);
+if (!oc) {
+error_report("fatal: could not load module for type '%s'", ops_name);
+abort();
+}
g_free(ops_name);
-
+ops = ACCEL_OPS_CLASS(oc);
/*
* all accelerators need to define ops, providing at least a mandatory
* non-NULL create_vcpu_thread operation.
--
2.26.2
Re: Maximum QMP reply size
John Snow writes:
> Hi, I suspect I have asked this before, but I didn't write it down in
> a comment, so I forget my justification...
>
> In the QMP lib, we need to set a buffering limit for how big a QMP
> message can be -- In practice, I found that the largest possible
> response was the QAPI schema reply, and I set the code to this:
>
> # Maximum allowable size of read buffer
> _limit = (64 * 1024)
>
> However, I didn't document if this was a reasonable limit or just a
> "worksforme" one. I assume that there's no hard limit for the protocol
> or the implementation thereof in QEMU. Is there any kind of value here
> that would be more sensible than another?
>
> I'm worried that if replies get bigger in the future (possibly in some
> degenerate case I am presently unaware of) that the library default
> will become nonsensical.
>
> Any pointers/tips?
Peter and Daniel already provided some. I can add a bit of insight into
how QMP output works in QEMU, which may or may not help you.
QEMU executes one command after the other. A command's response
(success or failure) is a QDict. Which is then formatted as JSON and
appended to the monitor's output buffer.
Events work similarly.
The conversion to JSON does not limit the resulting string's size. If
it runs out of memory, QEMU dies.
The output buffer is also unbounded. It drains into the monitor's
character device.
If the QMP client sends enough commands without reading their responses,
QEMU can run out of memory and die.
Now I'm ready to go back to your question, which is about a *single*
message (QMP command response or event): nothing in QEMU limits the size
of the QMP output message text.
Weak consolation: I guess QEMU is somewhat likely to run out of memory
and die before your client software does. That's because QDict is a
pig: an empty one eats 4120 Bytes on my system. Compares unfavourable
to its text representation "{}".
Re: [PATCH REPOST] hw/i386/e820: remove legacy reserved entries for e820
On Wed, Aug 31, 2022 at 10:23 AM Ani Sinha wrote:
>
> e820 reserved entries were used before the dynamic entries with fw config
> files
> were intoduced. Please see the following change:
> 7d67110f2d9a6("pc: add etc/e820 fw_cfg file")
>
> Identical support was introduced into seabios as well with the following
> commit:
> ce39bd4031820 ("Add support for etc/e820 fw_cfg file")
>
> Both the above commits are now quite old. QEMU machines 1.7 and newer no
> longer
> use the reserved entries. Seabios uses fw config files and
> dynamic e820 entries by default and only falls back to using reserved entries
> when it has to work with old qemu (versions earlier than 1.7). Please see
> functions qemu_cfg_e820() and qemu_early_e820(). It is safe to remove legacy
> FW_CFG_E820_TABLE and associated code now as QEMU 7.0 has deprecated i440fx
> machines 1.7 and older. It would be incredibly rare to run the latest qemu
> version with a very old version of seabios that did not support fw config
> files
> for e820.
>
> As far as I could see, edk2/ovfm never supported reserved entries and uses fw
> config files from the beginning. So there should be no incompatibilities with
> ovfm as well.
>
> CC: Gerd Hoffmann
> Signed-off-by: Ani Sinha
> Acked-by: Gerd Hoffmann
michael, please pick this one as well for the next pull. thanks.
> ---
> hw/i386/e820_memory_layout.c | 20 +---
> hw/i386/e820_memory_layout.h | 8
> hw/i386/fw_cfg.c | 3 ---
> hw/i386/fw_cfg.h | 1 -
> hw/i386/microvm.c| 2 --
> 5 files changed, 1 insertion(+), 33 deletions(-)
>
> Please see:
> https://patchwork.ozlabs.org/project/qemu-devel/patch/20220420043904.1225153-1-...@anisinha.ca/
> for the previous post. Now that we are in 7.2 devel cycle, time to push
> this patch.
>
> diff --git a/hw/i386/e820_memory_layout.c b/hw/i386/e820_memory_layout.c
> index bcf9eaf837..06970ac44a 100644
> --- a/hw/i386/e820_memory_layout.c
> +++ b/hw/i386/e820_memory_layout.c
> @@ -11,29 +11,11 @@
> #include "e820_memory_layout.h"
>
> static size_t e820_entries;
> -struct e820_table e820_reserve;
> struct e820_entry *e820_table;
>
> int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
> {
> -int index = le32_to_cpu(e820_reserve.count);
> -struct e820_entry *entry;
> -
> -if (type != E820_RAM) {
> -/* old FW_CFG_E820_TABLE entry -- reservations only */
> -if (index >= E820_NR_ENTRIES) {
> -return -EBUSY;
> -}
> -entry = &e820_reserve.entry[index++];
> -
> -entry->address = cpu_to_le64(address);
> -entry->length = cpu_to_le64(length);
> -entry->type = cpu_to_le32(type);
> -
> -e820_reserve.count = cpu_to_le32(index);
> -}
> -
> -/* new "etc/e820" file -- include ram too */
> +/* new "etc/e820" file -- include ram and reserved entries */
> e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
> e820_table[e820_entries].address = cpu_to_le64(address);
> e820_table[e820_entries].length = cpu_to_le64(length);
> diff --git a/hw/i386/e820_memory_layout.h b/hw/i386/e820_memory_layout.h
> index 04f93780f9..7c239aa033 100644
> --- a/hw/i386/e820_memory_layout.h
> +++ b/hw/i386/e820_memory_layout.h
> @@ -16,20 +16,12 @@
> #define E820_NVS4
> #define E820_UNUSABLE 5
>
> -#define E820_NR_ENTRIES 16
> -
> struct e820_entry {
> uint64_t address;
> uint64_t length;
> uint32_t type;
> } QEMU_PACKED __attribute((__aligned__(4)));
>
> -struct e820_table {
> -uint32_t count;
> -struct e820_entry entry[E820_NR_ENTRIES];
> -} QEMU_PACKED __attribute((__aligned__(4)));
> -
> -extern struct e820_table e820_reserve;
> extern struct e820_entry *e820_table;
>
> int e820_add_entry(uint64_t address, uint64_t length, uint32_t type);
> diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c
> index a283785a8d..72a42f3c66 100644
> --- a/hw/i386/fw_cfg.c
> +++ b/hw/i386/fw_cfg.c
> @@ -36,7 +36,6 @@ const char *fw_cfg_arch_key_name(uint16_t key)
> {FW_CFG_ACPI_TABLES, "acpi_tables"},
> {FW_CFG_SMBIOS_ENTRIES, "smbios_entries"},
> {FW_CFG_IRQ0_OVERRIDE, "irq0_override"},
> -{FW_CFG_E820_TABLE, "e820_table"},
> {FW_CFG_HPET, "hpet"},
> };
>
> @@ -127,8 +126,6 @@ FWCfgState *fw_cfg_arch_create(MachineState *ms,
> #endif
> fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1);
>
> -fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
> - &e820_reserve, sizeof(e820_reserve));
> fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
> sizeof(struct e820_entry) * e820_get_num_entries());
>
> diff --git a/hw/i386/fw_cfg.h b/hw/i386/fw_cfg.h
> index 275f15c1c5..86ca7c1c0c 100644
> --- a/hw/i386/fw_cfg.h
> +++ b/hw/i386/fw_cfg.h
> @@ -17,7 +17,6 @@
> #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
> #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
> #define FW_CFG_IRQ
Re: [PATCH] migration/multifd: Remove redundant copy of page offsets during send
On 10.08.22 г. 13:39 ч., Nikolay Borisov wrote: All pages which are going to be migrated are first added to MultiFDSendParams::MultiFDPages_t::offset array by the main migration thread and are subsequently copied to MultiFDSendParams::normal by the multifd thread. This is really unnecessary as the MultiFDPages_t is guaranteed to be stable since its mutex is being held. Additionally, this somewhat simplifies the code as the migration pages are now kept in only 1 place during send, also the name 'offset' coupled with the context it's being used - usually added to the host pages makes it obvious that this is an offset. With this change normal/normal_num are no longer used in the multifd send path. Signed-off-by: Nikolay Borisov Ping
Re: [PATCH 05/20] ppc440_bamboo: Add missing 4 MiB valid memory size
On 8/19/22 18:55, BALATON Zoltan wrote:
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc/ppc440_bamboo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 2aac8a3fe9..2bd5e41140 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -51,7 +51,7 @@
#define PPC440EP_SDRAM_NR_BANKS 4
static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
-256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
+256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
};
static hwaddr entry;
Re: [PATCH 06/20] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
On 8/19/22 18:55, BALATON Zoltan wrote:
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan
It looks like a good clean up. At some point, I think we will need to
pass "MemoryRegion *sysmem" to the SDRAM model. Let's start with this
change and see how it evolves.
One small comment below
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc/ppc405.h | 2 --
hw/ppc/ppc405_boards.c | 10 --
hw/ppc/ppc405_uc.c | 11 ++-
hw/ppc/ppc440_bamboo.c | 10 +-
hw/ppc/ppc4xx_devs.c| 14 ++
include/hw/ppc/ppc4xx.h | 2 +-
6 files changed, 10 insertions(+), 39 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ca0972b88b..ad54dff542 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,9 +167,7 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
-Ppc4xxSdramBank ram_banks[2];
MemoryRegion *dram_mr;
-hwaddr ram_size;
PowerPCCPU cpu;
PPCUIC uic;
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 0a29ad97c7..a82b6c5c83 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -278,21 +278,11 @@ static void boot_from_kernel(MachineState *machine,
PowerPCCPU *cpu)
static void ppc405_init(MachineState *machine)
{
Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
-MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
MemoryRegion *sysmem = get_system_memory();
-if (machine->ram_size != mc->default_ram_size) {
-char *sz = size_to_str(mc->default_ram_size);
-error_report("Invalid RAM size, should be %s", sz);
-g_free(sz);
-exit(EXIT_FAILURE);
-}
-
object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
TYPE_PPC405_SOC);
-object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
- machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort);
object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", ,
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 461d18c8a5..4049fb98dc 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1070,15 +1070,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
-/* XXX 405EP has no ECC interrupt */
-s->ram_banks[0].base = 0;
-s->ram_banks[0].size = s->ram_size;
-memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
- "ppc405.sdram0", s->dram_mr,
- s->ram_banks[0].base, s->ram_banks[0].size);
-
+/* XXX 405EP has no ECC interrupt */
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks);
+ s->dram_mr);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1156,7 +1150,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
-DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 2bd5e41140..9b456f1819 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -50,10 +50,6 @@
#define PPC440EP_SDRAM_NR_BANKS 4
-static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
-256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
-};
-
static hwaddr entry;
static int bamboo_load_device_tree(hwaddr addr,
@@ -168,8 +164,6 @@ static void bamboo_init(MachineState *machine)
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
-Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
-PPC440EP_SDRAM_NR_BANKS);
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -204,11 +198,9 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
-ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
- ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BAN
[PATCH v3] audio: Add sndio backend
sndio is the native API used by OpenBSD, although it has been ported to
other *BSD's and Linux (packages for Ubuntu, Debian, Void, Arch, etc.).
Signed-off-by: Brad Smith
Signed-off-by: Alexandre Ratchov
---
References to the previous patch versions and related discussions are
here:
https://marc.info/?l=qemu-devel&m=163973393011543 (v2)
https://marc.info/?l=qemu-devel&m=163626248712444 (initial patch)
Here are the changes between v2 and v3 of this patch:
- fixed of typos in file-names in MAINTAINERS
- added Gerd Hoffmann to the M: entry in MAINTAINERS
- added missin S: entry in MAINTAINERS
- removed unused #include "qemu-common.h"
- bumped "Since:" version to 7.2 in qapi/audio.json
- regenerated scripts/meson-buildoptions.sh
- implement buffer_get_free() method, introduced by
commit 9833438ef624155de879d4ed57ecfcd3464a0bbe
audio: restore mixing-engine playback buffer size
Running "make update-buildoptions" triggered unrelated changes of
scripts/meson-buildoptions.sh, that I removed from the commit as they
are not related to sndio.
Tested on OpenBSD, still works as expected :-)
Regards,
Alexandre
MAINTAINERS | 7 +
audio/audio.c | 1 +
audio/audio_template.h| 2 +
audio/meson.build | 1 +
audio/sndioaudio.c| 565 ++
meson.build | 9 +-
meson_options.txt | 4 +-
qapi/audio.json | 25 +-
qemu-options.hx | 16 +
scripts/meson-buildoptions.sh | 7 +-
10 files changed, 632 insertions(+), 5 deletions(-)
create mode 100644 audio/sndioaudio.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 1729c0901c..2064efc856 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2438,6 +2438,7 @@ X: audio/jackaudio.c
X: audio/ossaudio.c
X: audio/paaudio.c
X: audio/sdlaudio.c
+X: audio/sndioaudio.c
X: audio/spiceaudio.c
F: qapi/audio.json
@@ -2482,6 +2483,12 @@ R: Thomas Huth
S: Odd Fixes
F: audio/sdlaudio.c
+Sndio Audio backend
+M: Gerd Hoffmann
+R: Alexandre Ratchov
+S: Odd Fixes
+F: audio/sndioaudio.c
+
Block layer core
M: Kevin Wolf
M: Hanna Reitz
diff --git a/audio/audio.c b/audio/audio.c
index 76b8735b44..d3a768007e 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -2029,6 +2029,7 @@ void audio_create_pdos(Audiodev *dev)
CASE(OSS, oss, Oss);
CASE(PA, pa, Pa);
CASE(SDL, sdl, Sdl);
+CASE(SNDIO, sndio, );
CASE(SPICE, spice, );
CASE(WAV, wav, );
diff --git a/audio/audio_template.h b/audio/audio_template.h
index 7192b19e73..81860cea62 100644
--- a/audio/audio_template.h
+++ b/audio/audio_template.h
@@ -336,6 +336,8 @@ AudiodevPerDirectionOptions *glue(audio_get_pdo_,
TYPE)(Audiodev *dev)
return qapi_AudiodevPaPerDirectionOptions_base(dev->u.pa.TYPE);
case AUDIODEV_DRIVER_SDL:
return qapi_AudiodevSdlPerDirectionOptions_base(dev->u.sdl.TYPE);
+case AUDIODEV_DRIVER_SNDIO:
+return dev->u.sndio.TYPE;
case AUDIODEV_DRIVER_SPICE:
return dev->u.spice.TYPE;
case AUDIODEV_DRIVER_WAV:
diff --git a/audio/meson.build b/audio/meson.build
index 3abee90860..34aed78342 100644
--- a/audio/meson.build
+++ b/audio/meson.build
@@ -17,6 +17,7 @@ foreach m : [
['pa', pulse, files('paaudio.c')],
['sdl', sdl, files('sdlaudio.c')],
['jack', jack, files('jackaudio.c')],
+ ['sndio', sndio, files('sndioaudio.c')],
['spice', spice, files('spiceaudio.c')]
]
if m[1].found()
diff --git a/audio/sndioaudio.c b/audio/sndioaudio.c
new file mode 100644
index 00..7c45276d36
--- /dev/null
+++ b/audio/sndioaudio.c
@@ -0,0 +1,565 @@
+/*
+ * SPDX-License-Identifier: ISC
+ *
+ * Copyright (c) 2019 Alexandre Ratchov
+ */
+
+/*
+ * TODO :
+ *
+ * Use a single device and open it in full-duplex rather than
+ * opening it twice (once for playback once for recording).
+ *
+ * This is the only way to ensure that playback doesn't drift with respect
+ * to recording, which is what guest systems expect.
+ */
+
+#include
+#include
+#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
+#include "audio.h"
+#include "trace.h"
+
+#define AUDIO_CAP "sndio"
+#include "audio_int.h"
+
+/* default latency in microseconds if no option is set */
+#define SNDIO_LATENCY_US 5
+
+typedef struct SndioVoice {
+union {
+HWVoiceOut out;
+HWVoiceIn in;
+} hw;
+struct sio_par par;
+struct sio_hdl *hdl;
+struct pollfd *pfds;
+struct pollindex {
+struct SndioVoice *self;
+int index;
+} *pindexes;
+unsigned char *buf;
+size_t buf_size;
+size_t sndio_pos;
+size_t qemu_pos;
+unsigned int mode;
+unsigned int nfds;
+bool enabled;
+} SndioVoice;
+
+typedef struct SndioConf {
+const char *devname;
+unsigned int latency;
+} SndioConf;
+
+/* needed for forward reference */
+static void sndio_poll_in(void *arg);
+static void sndio_poll_out(void *arg);
+
+/*
+ * stop pollin
Re: [PATCH 07/20] ppc4xx_sdram: QOM'ify
On 8/19/22 18:55, BALATON Zoltan wrote:
Change the ppc4xx_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
modelling the DDR SDRAM controller found in the 440EP (used on the
bamboo board) but also backward compatible with the older DDR
controllers on some 405 SoCs so we also use it for those now. This
likely does not cause problems for guests we run as the new features
are just not accessed but to model 405 SoC accurately some features
may have to be disabled or the model split between 440 and older.
Newer SoCs (regardless of their PPC core, e.g. 405EX) may have an
updated DDR2 SDRAM controller implemented by the ppc440_sdram model
(only partially, enough for the 460EX on the sam460ex) that is not yet
QOM'ified in this patch. That is intended to become ppc4xx-sdram-ddr2
when QOM'ified later.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc/ppc405.h | 3 +-
hw/ppc/ppc405_uc.c | 22 +
hw/ppc/ppc440_bamboo.c | 10 +++--
hw/ppc/ppc4xx_devs.c| 99 ++---
include/hw/ppc/ppc4xx.h | 27 +--
5 files changed, 98 insertions(+), 63 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ad54dff542..9a4312691e 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,8 +167,6 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
-MemoryRegion *dram_mr;
-
PowerPCCPU cpu;
PPCUIC uic;
Ppc405CpcState cpc;
@@ -182,6 +180,7 @@ struct Ppc405SoCState {
Ppc405PobState pob;
Ppc4xxPlbState plb;
Ppc4xxMalState mal;
+Ppc4xxSdramDdrState sdram;
};
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 4049fb98dc..9c266a21ad 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1013,6 +1013,9 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "plb", &s->plb, TYPE_PPC4xx_PLB);
object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
+
+object_initialize_child(obj, "sdram", &s->sdram, TYPE_PPC4xx_SDRAM_DDR);
+object_property_add_alias(obj, "dram", OBJECT(&s->sdram), "dram");
}
static void ppc405_reset(void *opaque)
@@ -1070,9 +1073,17 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
+/*
+ * We use the 440 DDR SDRAM controller which has more regs and features
+ * but it's compatible enough for now
+ */
+object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort);
+if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) {
+return;
+}
/* XXX 405EP has no ECC interrupt */
-ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->dram_mr);
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdram), 0,
+ qdev_get_gpio_in(DEVICE(&s->uic), 17));
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1147,12 +1158,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
/* Uses UIC IRQs 9, 15, 17 */
}
-static Property ppc405_soc_properties[] = {
-DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
- MemoryRegion *),
-DEFINE_PROP_END_OF_LIST(),
-};
-
static void ppc405_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -1160,7 +1165,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, void
*data)
dc->realize = ppc405_soc_realize;
/* Reason: only works as part of a ppc405 board/machine */
dc->user_creatable = false;
-device_class_set_props(dc, ppc405_soc_properties);
}
static const TypeInfo ppc405_types[] = {
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 9b456f1819..6052d3a2e0 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -48,8 +48,6 @@
#define PPC440EP_PCI_IO 0xe800
#define PPC440EP_PCI_IOLEN 0x0001
-#define PPC440EP_SDRAM_NR_BANKS 4
-
static hwaddr entry;
static int bamboo_load_device_tree(hwaddr addr,
@@ -198,9 +196,13 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
+dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR);
+object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
+ &error_abort);
+ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+object_unref(OBJECT(dev));
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
-ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BANKS, machine->ram);
+sysbus_conne
Re: [PATCH 08/20] ppc4xx_sdram: Drop extra zeros for readability
On 8/19/22 18:55, BALATON Zoltan wrote:
Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.
I would keep the 0x prefix though.
Thanks,
C.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 375834a52b..bfe7b2d3a6 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -49,31 +49,31 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr
ram_size)
switch (ram_size) {
case 4 * MiB:
-bcr = 0x;
+bcr = 0;
break;
case 8 * MiB:
-bcr = 0x0002;
+bcr = 0x2;
break;
case 16 * MiB:
-bcr = 0x0004;
+bcr = 0x4;
break;
case 32 * MiB:
-bcr = 0x0006;
+bcr = 0x6;
break;
case 64 * MiB:
-bcr = 0x0008;
+bcr = 0x8;
break;
case 128 * MiB:
-bcr = 0x000A;
+bcr = 0xA;
break;
case 256 * MiB:
-bcr = 0x000C;
+bcr = 0xC;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
ram_size);
-return 0x;
+return 0;
}
bcr |= ram_base & 0xFF80;
bcr |= 1;
@@ -104,7 +104,7 @@ static target_ulong sdram_size(uint32_t bcr)
static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
uint32_t bcr, int enabled)
{
-if (sdram->bank[i].bcr & 0x0001) {
+if (sdram->bank[i].bcr & 1) {
/* Unmap RAM */
trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
sdram_size(sdram->bank[i].bcr));
@@ -115,7 +115,7 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
object_unparent(OBJECT(&sdram->bank[i].container));
}
sdram->bank[i].bcr = bcr & 0xFFDEE001;
-if (enabled && (bcr & 0x0001)) {
+if (enabled && (bcr & 1)) {
trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr));
@@ -136,7 +136,7 @@ static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
-sdram_set_bcr(sdram, i, 0x, 0);
+sdram_set_bcr(sdram, i, 0, 0);
}
}
}
@@ -213,7 +213,7 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
break;
default:
/* Avoid gcc warning */
-ret = 0x;
+ret = 0;
break;
}
@@ -306,18 +306,18 @@ static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{
Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
-sdram->addr = 0x;
-sdram->bear = 0x;
-sdram->besr0 = 0x; /* No error */
-sdram->besr1 = 0x; /* No error */
-sdram->cfg = 0x;
-sdram->ecccfg = 0x; /* No ECC */
-sdram->eccesr = 0x; /* No error */
+sdram->addr = 0;
+sdram->bear = 0;
+sdram->besr0 = 0; /* No error */
+sdram->besr1 = 0; /* No error */
+sdram->cfg = 0;
+sdram->ecccfg = 0; /* No ECC */
+sdram->eccesr = 0; /* No error */
sdram->pmit = 0x07C0;
sdram->rtr = 0x05F0;
sdram->tr = 0x00854009;
/* We pre-initialize RAM banks */
-sdram->status = 0x;
+sdram->status = 0;
sdram->cfg = 0x0080;
}
Re: [PATCH 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse
On 8/19/22 18:55, BALATON Zoltan wrote:
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 3507c35b63..c33f91e134 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -561,26 +561,33 @@ static uint64_t sdram_size(uint32_t bcr)
return size;
}
+static void sdram_bank_map(Ppc4xxSdramBank *bank)
+{
+memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
I don't think we need to init the ->container memory region each time.
This could be done once and for all in the realize handler.
+memory_region_add_subregion(&bank->container, 0, &bank->ram);
+memory_region_add_subregion(get_system_memory(), bank->base,
+&bank->container);
+}
+
+static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
+{
+memory_region_del_subregion(get_system_memory(), &bank->container);
+memory_region_del_subregion(&bank->container, &bank->ram);
+object_unparent(OBJECT(&bank->container));
object_unparent could be dropped if the memory_region_init was called in
realize.
Also, memory_region_set_enabled() might be a better alternative.
Thanks,
C.
+}
+
static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
-memory_region_del_subregion(get_system_memory(),
-&sdram->bank[i].container);
-memory_region_del_subregion(&sdram->bank[i].container,
-&sdram->bank[i].ram);
-object_unparent(OBJECT(&sdram->bank[i].container));
+sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
+sdram->bank[i].base = sdram_base(bcr);
+sdram->bank[i].size = sdram_size(bcr);
if (enabled && (bcr & 1)) {
-memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_size(bcr));
-memory_region_add_subregion(&sdram->bank[i].container, 0,
-&sdram->bank[i].ram);
-memory_region_add_subregion(get_system_memory(),
-sdram_base(bcr),
-&sdram->bank[i].container);
+sdram_bank_map(&sdram->bank[i]);
}
}
Re: PING: Re: [PATCH v4 1/1] monitor: Support specified vCPU registers
* zhenwei pi (pizhen...@bytedance.com) wrote:
> PING!
It's OK, I've got it lined up for a pull I'll do in a few days time.
Dave
> On 8/15/22 20:00, Dr. David Alan Gilbert wrote:
> > * zhenwei pi (pizhen...@bytedance.com) wrote:
> > > Originally we have to get all the vCPU registers and parse the
> > > specified one. To improve the performance of this usage, allow user
> > > specified vCPU id to query registers.
> > >
> > > Run a VM with 16 vCPU, use bcc tool to track the latency of
> > > 'hmp_info_registers':
> > > 'info registers -a' uses about 3ms;
> > > 'info registers 12' uses about 150us.
> > >
> > > Cc: Darren Kenny
> > > Reviewed-by: Markus Armbruster
> > > Signed-off-by: zhenwei pi
> >
> > Reviewed-by: Dr. David Alan Gilbert
> >
> > > ---
> > > hmp-commands-info.hx | 8 +---
> > > monitor/misc.c | 10 --
> > > 2 files changed, 13 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx
> > > index 188d9ece3b..e012035541 100644
> > > --- a/hmp-commands-info.hx
> > > +++ b/hmp-commands-info.hx
> > > @@ -100,9 +100,11 @@ ERST
> > > {
> > > .name = "registers",
> > > -.args_type = "cpustate_all:-a",
> > > -.params = "[-a]",
> > > -.help = "show the cpu registers (-a: all - show register
> > > info for all cpus)",
> > > +.args_type = "cpustate_all:-a,vcpu:i?",
> > > +.params = "[-a|vcpu]",
> > > +.help = "show the cpu registers (-a: show register info
> > > for all cpus;"
> > > + " vcpu: specific vCPU to query; show the current
> > > CPU's registers if"
> > > + " no argument is specified)",
> > > .cmd= hmp_info_registers,
> > > },
> > > diff --git a/monitor/misc.c b/monitor/misc.c
> > > index 3d2312ba8d..6436a8786b 100644
> > > --- a/monitor/misc.c
> > > +++ b/monitor/misc.c
> > > @@ -307,6 +307,7 @@ int monitor_get_cpu_index(Monitor *mon)
> > > static void hmp_info_registers(Monitor *mon, const QDict *qdict)
> > > {
> > > bool all_cpus = qdict_get_try_bool(qdict, "cpustate_all", false);
> > > +int vcpu = qdict_get_try_int(qdict, "vcpu", -1);
> > > CPUState *cs;
> > > if (all_cpus) {
> > > @@ -315,13 +316,18 @@ static void hmp_info_registers(Monitor *mon, const
> > > QDict *qdict)
> > > cpu_dump_state(cs, NULL, CPU_DUMP_FPU);
> > > }
> > > } else {
> > > -cs = mon_get_cpu(mon);
> > > +cs = vcpu >= 0 ? qemu_get_cpu(vcpu) : mon_get_cpu(mon);
> > > if (!cs) {
> > > -monitor_printf(mon, "No CPU available\n");
> > > +if (vcpu >= 0) {
> > > +monitor_printf(mon, "CPU#%d not available\n", vcpu);
> > > +} else {
> > > +monitor_printf(mon, "No CPU available\n");
> > > +}
> > > return;
> > > }
> > > +monitor_printf(mon, "\nCPU#%d\n", cs->cpu_index);
> > > cpu_dump_state(cs, NULL, CPU_DUMP_FPU);
> > > }
> > > }
> > > --
> > > 2.20.1
> > >
>
> --
> zhenwei pi
>
--
Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
Re: [PATCH 10/20] ppc440_sdram: Implement enable bit in the DDR2 SDRAM controller
On 8/19/22 18:55, BALATON Zoltan wrote:
To allow removing the do_init hack we need to improve the DDR2 SDRAM
controller model to handle the enable/disable bit that it ignored so
far.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index c33f91e134..7c1513ff69 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -23,6 +23,7 @@
#include "sysemu/reset.h"
#include "ppc440.h"
#include "qom/object.h"
+#include "trace.h"
/*/
/* L2 Cache as SRAM */
@@ -484,6 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
/* SDRAM controller */
typedef struct ppc440_sdram_t {
uint32_t addr;
+uint32_t mcopt2;
int nbanks;
Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
@@ -581,12 +583,15 @@ static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
+trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
sdram->bank[i].base = sdram_base(bcr);
sdram->bank[i].size = sdram_size(bcr);
if (enabled && (bcr & 1)) {
+trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
sdram_bank_map(&sdram->bank[i]);
}
}
@@ -596,7 +601,7 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
-if (sdram->bank[i].size != 0) {
+if (sdram->bank[i].size) {
sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
@@ -605,6 +610,17 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
}
}
+static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+{
+int i;
+
+for (i = 0; i < sdram->nbanks; i++) {
+if (sdram->bank[i].size) {
+sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+}
+}
+}
+
static uint32_t dcr_read_sdram(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
@@ -636,7 +652,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
ret = 0x8000;
break;
case 0x21: /* SDRAM_MCOPT2 */
-ret = 0x0800;
+ret = sdram->mcopt2;
break;
case 0x40: /* SDRAM_MB0CF */
ret = 0x8001;
@@ -680,6 +696,19 @@ static void dcr_write_sdram(void *opaque, int dcrn,
uint32_t val)
switch (sdram->addr) {
case 0x00: /* B0CR */
break;
+case 0x21: /* SDRAM_MCOPT2 */
+if (!(sdram->mcopt2 & 0x0800) && (val & 0x0800)) {
+trace_ppc4xx_sdram_enable("enable");
+/* validate all RAM mappings */
+sdram_map_bcr(sdram);
+sdram->mcopt2 |= 0x0800;
+} else if ((sdram->mcopt2 & 0x0800) && !(val & 0x0800)) {
+trace_ppc4xx_sdram_enable("disable");
+/* invalidate all RAM mappings */
+sdram_unmap_bcr(sdram);
+sdram->mcopt2 &= ~0x0800;
+}
+break;
default:
break;
}
@@ -694,6 +723,7 @@ static void sdram_reset(void *opaque)
ppc440_sdram_t *sdram = opaque;
sdram->addr = 0;
+sdram->mcopt2 = 0x0800;
Introducing a define for the 0x0800 value would make the code easier
to read.
Thanks,
C.
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
Re: [PATCH 12/20] ppc440_sdram: Rename local variable for readibility
On 8/19/22 18:55, BALATON Zoltan wrote:
Rename local sdram variable in ppc440_sdram_init to s for readibility.
readability
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc/ppc440_uc.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index bd3d60f278..72eb75d3d2 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -729,40 +729,40 @@ static void sdram_reset(void *opaque)
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
Ppc4xxSdramBank ram_banks[])
{
-ppc440_sdram_t *sdram;
+ppc440_sdram_t *s;
int i;
-sdram = g_malloc0(sizeof(*sdram));
-sdram->nbanks = nbanks;
+s = g_malloc0(sizeof(*s));
+s->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
-sdram->bank[i].ram = ram_banks[i].ram;
-sdram->bank[i].base = ram_banks[i].base;
-sdram->bank[i].size = ram_banks[i].size;
+s->bank[i].ram = ram_banks[i].ram;
+s->bank[i].base = ram_banks[i].base;
+s->bank[i].size = ram_banks[i].size;
}
-qemu_register_reset(&sdram_reset, sdram);
+qemu_register_reset(&sdram_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R0BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R1BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R2BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R3BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONF1HB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_PLBADDULL,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONF1LL,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONFPATHB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_PLBADDUHB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
}
/*/
Re: [PATCH 13/20] ppc4xx_sdram: Rename functions to prevent name clashes
On 8/19/22 18:55, BALATON Zoltan wrote:
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Shouldn't we introduce class handlers instead ?
Thanks,
C.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 69 ++--
hw/ppc/ppc4xx_devs.c | 44 ++--
2 files changed, 57 insertions(+), 56 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 72eb75d3d2..b39c6dbbd2 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -502,7 +502,7 @@ enum {
SDRAM_PLBADDUHB = 0x50,
};
-static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
+static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -547,12 +547,12 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
return bcr;
}
-static inline hwaddr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_ddr2_base(uint32_t bcr)
{
return (bcr & 0xffe0) << 2;
}
-static uint64_t sdram_size(uint32_t bcr)
+static uint64_t sdram_ddr2_size(uint32_t bcr)
{
uint64_t size;
int sh;
@@ -578,50 +578,51 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
object_unparent(OBJECT(&bank->container));
}
-static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
- uint32_t bcr, int enabled)
+static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
+ uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
-trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
+ sdram_ddr2_size(sdram->bank[i].bcr));
sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
-sdram->bank[i].base = sdram_base(bcr);
-sdram->bank[i].size = sdram_size(bcr);
+sdram->bank[i].base = sdram_ddr2_base(bcr);
+sdram->bank[i].size = sdram_ddr2_size(bcr);
if (enabled && (bcr & 1)) {
-trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
sdram_bank_map(&sdram->bank[i]);
}
}
-static void sdram_map_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
-sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+sdram_ddr2_set_bcr(sdram, i,
+ sdram_ddr2_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
-sdram_set_bcr(sdram, i, 0, 0);
+sdram_ddr2_set_bcr(sdram, i, 0, 0);
}
}
}
-static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
-sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
}
}
}
-static uint32_t dcr_read_sdram(void *opaque, int dcrn)
+static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
uint32_t ret = 0;
@@ -632,8 +633,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
case SDRAM_R2BAS:
case SDRAM_R3BAS:
if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
-ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
-sdram->bank[dcrn - SDRAM_R0BAS].size);
+ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -674,7 +675,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
return ret;
}
-static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
+static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
ppc440_sdram_t *sdram = opaque;
@@ -700,12 +701,12 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
if (!(sdram->mcopt2 & 0x0800) && (val & 0x0800)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
-sdram_map_bcr(sdram);
+sdram_ddr2_map_bcr(sdram);
sdram->mcopt2 |= 0x0800;
} else if ((sdram->mcopt2 & 0x0800) && !(val & 0x0800)) {
trace_ppc4xx_sdram_enable("disable");
Re: [PATCH 15/20] ppc440_sdram: QOM'ify
On 8/19/22 18:55, BALATON Zoltan wrote:
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX)
may have this controller but we only emulate enough of it for the
sam460ex u-boot firmware.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc/ppc440.h | 2 -
hw/ppc/ppc440_uc.c | 115 +---
hw/ppc/sam460ex.c | 7 ++-
include/hw/ppc/ppc4xx.h | 14 +
4 files changed, 91 insertions(+), 47 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 29f6f14ed7..7c24db8504 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -16,8 +16,6 @@
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
-void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index e77d56225d..a75a1748bd 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -483,13 +483,6 @@ void ppc4xx_sdr_init(CPUPPCState *env)
/*/
/* SDRAM controller */
-typedef struct ppc440_sdram_t {
-uint32_t addr;
-uint32_t mcopt2;
-int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
-Ppc4xxSdramBank bank[4];
-} ppc440_sdram_t;
-
enum {
SDRAM_R0BAS = 0x40,
SDRAM_R1BAS,
@@ -578,7 +571,7 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
object_unparent(OBJECT(&bank->container));
}
-static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
+static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
@@ -596,7 +589,7 @@ static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
}
}
-static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
{
int i;
@@ -611,7 +604,7 @@ static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
}
}
-static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
{
int i;
@@ -624,7 +617,7 @@ static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
-ppc440_sdram_t *sdram = opaque;
+Ppc4xxSdramDdr2State *sdram = opaque;
uint32_t ret = 0;
switch (dcrn) {
@@ -677,7 +670,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
-ppc440_sdram_t *sdram = opaque;
+Ppc4xxSdramDdr2State *sdram = opaque;
switch (dcrn) {
case SDRAM_R0BAS:
@@ -719,52 +712,86 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn,
uint32_t val)
}
}
-static void sdram_ddr2_reset(void *opaque)
+static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
{
-ppc440_sdram_t *sdram = opaque;
+Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
sdram->addr = 0;
sdram->mcopt2 = 0;
}
-void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram)
+static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
{
-ppc440_sdram_t *s;
+Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
+Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
const ram_addr_t valid_bank_sizes[] = {
4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
32 * MiB, 16 * MiB, 8 * MiB, 0
};
-s = g_malloc0(sizeof(*s));
-s->nbanks = nbanks;
-ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes);
-qemu_register_reset(&sdram_ddr2_reset, s);
-ppc_dcr_register(env, SDRAM0_CFGADDR,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-ppc_dcr_register(env, SDRAM0_CFGDATA,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-
-ppc_dcr_register(env, SDRAM_R0BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-ppc_dcr_register(env, SDRAM_R1BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-ppc_dcr_register(env, SDRAM_R2BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-ppc_dcr_register(env, SDRAM_R3BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-ppc_dcr_register(env, SDRAM_CONF1HB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_
Re: [PATCH 14/20] ppc440_sdram: Move RAM size check to ppc440_sdram_init
On 8/19/22 18:55, BALATON Zoltan wrote:
Move the check for valid memory sizes from board to sdram contrller
controller
init. Board now only checks for additinal restrictions imposed by
additional
firmware then sdram init checks for valid sizes for SoC.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440.h| 4 ++--
hw/ppc/ppc440_uc.c | 15 +++
hw/ppc/sam460ex.c | 32 +---
3 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 7bd5cca1ab..29f6f14ed7 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -11,13 +11,13 @@
#ifndef PPC440_H
#define PPC440_H
-#include "hw/ppc/ppc4xx.h"
+#include "hw/ppc/ppc.h"
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank ram_banks[]);
+ MemoryRegion *ram);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index b39c6dbbd2..e77d56225d 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -486,7 +486,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
typedef struct ppc440_sdram_t {
uint32_t addr;
uint32_t mcopt2;
-int nbanks;
+int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
@@ -728,18 +728,17 @@ static void sdram_ddr2_reset(void *opaque)
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank ram_banks[])
+ MemoryRegion *ram)
{
ppc440_sdram_t *s;
-int i;
+const ram_addr_t valid_bank_sizes[] = {
+4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
+32 * MiB, 16 * MiB, 8 * MiB, 0
+};
s = g_malloc0(sizeof(*s));
s->nbanks = nbanks;
-for (i = 0; i < nbanks; i++) {
-s->bank[i].ram = ram_banks[i].ram;
-s->bank[i].base = ram_banks[i].base;
-s->bank[i].size = ram_banks[i].size;
-}
+ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes);
qemu_register_reset(&sdram_ddr2_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index dac329d482..9b850808a3 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -74,13 +74,6 @@
#define EBC_FREQ 11500
#define UART_FREQ 11059200
-/* The SoC could also handle 4 GiB but firmware does not work with that. */
-/* Maybe it overflows a signed 32 bit number somewhere? */
-static const ram_addr_t ppc460ex_sdram_bank_sizes[] = {
-2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
-32 * MiB, 0
-};
-
struct boot_info {
uint32_t dt_base;
uint32_t dt_size;
@@ -273,7 +266,6 @@ static void sam460ex_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
-Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1);
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
int i;
@@ -340,12 +332,22 @@ static void sam460ex_init(MachineState *machine)
}
/* SDRAM controller */
-/* put all RAM on first bank because board has one slot
- * and firmware only checks that */
-ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
-
+/* The SoC could also handle 4 GiB but firmware does not work with that. */
+if (machine->ram_size > 2 * GiB) {
+error_report("Memory over 2 GiB is not supported");
+exit(1);
+}
+/* Firmware needs at least 64 MiB */
+if (machine->ram_size < 64 * MiB) {
+error_report("Memory below 64 MiB is not supported");
+exit(1);
+}
These checks on the RAM size should be done by the SDRAM model.
May be it is addressed later in the patchset ?
C.
+/*
+ * Put all RAM on first bank because board has one slot
+ * and firmware only checks that
+ */
+ppc440_sdram_init(env, 1, machine->ram);
/* FIXME: does 460EX have ECC interrupts? */
-ppc440_sdram_init(env, 1, ram_banks);
/* Enable SDRAM memory regions as we may boot without firmware */
if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21) ||
ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x0800)) {
@@ -358,8 +360,8 @@ static void sam460ex_init(MachineState *machine)
qdev_get_gpio_in(uic[0], 2));
i2c = PPC4xx_I2C(dev)->bus;
/* SPD EEPROM on RAM module */
-spd_data = spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR2,
- ram_banks->size);
+
Re: [PULL 00/44] riscv-to-apply queue
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature
Re: [PULL 00/44] riscv-to-apply queue
On Wed, 7 Sept 2022 at 04:32, Alistair Francis via wrote: > > The following changes since commit 946e9bccf12f2bcc3ca471b820738fb22d14fc80: > > Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu > into staging (2022-09-06 08:31:24 -0400) > > are available in the Git repository at: > > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220907 Hi Alistair, Please update .git/config to separate the push URL from the fetch URL: [remote "github"] url = https://github.com/alistair23/qemu.git pushUrl = g...@gitlab.com:alistair23/qemu.git That way future pull requests will include an https URL that allows fetches without ssh or a GitHub account. Thanks! Stefan
Re: [PULL 00/11] OpenRISC updates for 7.2.0
On Sun, 4 Sept 2022 at 03:27, Stafford Horne wrote: > > The following changes since commit 61fd710b8da8aedcea9b4f197283dc38638e4b60: > > Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging > (2022-09-02 13:24:28 -0400) > > are available in the Git repository at: > > g...@github.com:stffrdhrn/qemu.git tags/pull-or1k-20220904 Hi Stafford, Please update .git/config to separate the push URL from the fetch URL: [remote "github"] url = https://github.com/stffrdhrn/qemu.git pushUrl = g...@gitlab.com:stffrdhrn/qemu.git That way future pull requests will include an https URL that allows fetches without ssh or a GitHub account. Thanks! Stefan
[PATCH] audio: add help option (?) for -audiodev
add a simple help option for -audiodev, so users can do
qemu -audiodev ?
to get the list of drivers available.
Signed-off-by: Claudio Fontana
---
audio/audio.c | 20
1 file changed, 20 insertions(+)
diff --git a/audio/audio.c b/audio/audio.c
index 4f4bb10cce..bd8c18c3cd 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -32,6 +32,7 @@
#include "qapi/qapi-visit-audio.h"
#include "qemu/cutils.h"
#include "qemu/module.h"
+#include "qemu/help_option.h"
#include "sysemu/sysemu.h"
#include "sysemu/replay.h"
#include "sysemu/runstate.h"
@@ -2105,10 +2106,29 @@ static void audio_validate_opts(Audiodev *dev, Error
**errp)
}
}
+static void audio_help(void)
+{
+int i;
+
+printf("Available audiodev types:\n");
+printf("none\n");
+
+for (i = 0; audio_prio_list[i]; i++) {
+audio_driver *driver = audio_driver_lookup(audio_prio_list[i]);
+if (driver) {
+printf("%s\n", driver->name);
+}
+}
+}
+
void audio_parse_option(const char *opt)
{
Audiodev *dev = NULL;
+if (is_help_option(opt)) {
+audio_help();
+exit(0);
+}
Visitor *v = qobject_input_visitor_new_str(opt, "driver", &error_fatal);
visit_type_Audiodev(v, NULL, &dev, &error_fatal);
visit_free(v);
--
2.26.2
Re: [PATCH 08/20] ppc4xx_sdram: Drop extra zeros for readability
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.
I would keep the 0x prefix though.
I'm not a fan of 0x0 or 0x prefix for numbers below 0xa as it's more
confusing than just having the simple number since these are the same in
decimal and hex so I always think it might be 0xC or something not just 0
when I see a prefix and have to double check. So unless there's a good
reaon to write them in hex it's simpler to only use the 0x when really
needed. Maybe if you really want the 0x I could keep it in the switch
below just for consistency with other cases there but wouldn't have them
elsewhere. Is it really not acceptable for you as in this patch?
Regards,
BALATON Zoltan
Thanks,
C.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 375834a52b..bfe7b2d3a6 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -49,31 +49,31 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr
ram_size)
switch (ram_size) {
case 4 * MiB:
-bcr = 0x;
+bcr = 0;
break;
case 8 * MiB:
-bcr = 0x0002;
+bcr = 0x2;
break;
case 16 * MiB:
-bcr = 0x0004;
+bcr = 0x4;
break;
case 32 * MiB:
-bcr = 0x0006;
+bcr = 0x6;
break;
case 64 * MiB:
-bcr = 0x0008;
+bcr = 0x8;
break;
case 128 * MiB:
-bcr = 0x000A;
+bcr = 0xA;
break;
case 256 * MiB:
-bcr = 0x000C;
+bcr = 0xC;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid RAM size 0x%" HWADDR_PRIx "\n",
__func__,
ram_size);
-return 0x;
+return 0;
}
bcr |= ram_base & 0xFF80;
bcr |= 1;
@@ -104,7 +104,7 @@ static target_ulong sdram_size(uint32_t bcr)
static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
uint32_t bcr, int enabled)
{
-if (sdram->bank[i].bcr & 0x0001) {
+if (sdram->bank[i].bcr & 1) {
/* Unmap RAM */
trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
sdram_size(sdram->bank[i].bcr));
@@ -115,7 +115,7 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram,
int i,
object_unparent(OBJECT(&sdram->bank[i].container));
}
sdram->bank[i].bcr = bcr & 0xFFDEE001;
-if (enabled && (bcr & 0x0001)) {
+if (enabled && (bcr & 1)) {
trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
memory_region_init(&sdram->bank[i].container, NULL,
"sdram-container",
sdram_size(bcr));
@@ -136,7 +136,7 @@ static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
sdram->bank[i].size),
1);
} else {
-sdram_set_bcr(sdram, i, 0x, 0);
+sdram_set_bcr(sdram, i, 0, 0);
}
}
}
@@ -213,7 +213,7 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int
dcrn)
break;
default:
/* Avoid gcc warning */
-ret = 0x;
+ret = 0;
break;
}
@@ -306,18 +306,18 @@ static void ppc4xx_sdram_ddr_reset(DeviceState
*dev)
{
Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
-sdram->addr = 0x;
-sdram->bear = 0x;
-sdram->besr0 = 0x; /* No error */
-sdram->besr1 = 0x; /* No error */
-sdram->cfg = 0x;
-sdram->ecccfg = 0x; /* No ECC */
-sdram->eccesr = 0x; /* No error */
+sdram->addr = 0;
+sdram->bear = 0;
+sdram->besr0 = 0; /* No error */
+sdram->besr1 = 0; /* No error */
+sdram->cfg = 0;
+sdram->ecccfg = 0; /* No ECC */
+sdram->eccesr = 0; /* No error */
sdram->pmit = 0x07C0;
sdram->rtr = 0x05F0;
sdram->tr = 0x00854009;
/* We pre-initialize RAM banks */
-sdram->status = 0x;
+sdram->status = 0;
sdram->cfg = 0x0080;
}
Re: [PATCH 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 3507c35b63..c33f91e134 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -561,26 +561,33 @@ static uint64_t sdram_size(uint32_t bcr)
return size;
}
+static void sdram_bank_map(Ppc4xxSdramBank *bank)
+{
+memory_region_init(&bank->container, NULL, "sdram-container",
bank->size);
I don't think we need to init the ->container memory region each time.
This could be done once and for all in the realize handler.
+memory_region_add_subregion(&bank->container, 0, &bank->ram);
+memory_region_add_subregion(get_system_memory(), bank->base,
+&bank->container);
+}
+
+static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
+{
+memory_region_del_subregion(get_system_memory(), &bank->container);
+memory_region_del_subregion(&bank->container, &bank->ram);
+object_unparent(OBJECT(&bank->container));
object_unparent could be dropped if the memory_region_init was called in
realize.
Also, memory_region_set_enabled() might be a better alternative.
I think these could be considered as a follow up later, I don't want to
change it now to avoid breaking it more as I've already managed to break
ref405ep as you found (this will be fixed in v2) so I'd not try to change
this in this series.
Regards,
BALATON Zoltan
Thanks,
C.
+}
+
static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
-memory_region_del_subregion(get_system_memory(),
-&sdram->bank[i].container);
-memory_region_del_subregion(&sdram->bank[i].container,
-&sdram->bank[i].ram);
-object_unparent(OBJECT(&sdram->bank[i].container));
+sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
+sdram->bank[i].base = sdram_base(bcr);
+sdram->bank[i].size = sdram_size(bcr);
if (enabled && (bcr & 1)) {
-memory_region_init(&sdram->bank[i].container, NULL,
"sdram-container",
- sdram_size(bcr));
-memory_region_add_subregion(&sdram->bank[i].container, 0,
-&sdram->bank[i].ram);
-memory_region_add_subregion(get_system_memory(),
-sdram_base(bcr),
-&sdram->bank[i].container);
+sdram_bank_map(&sdram->bank[i]);
}
}
Re: [PATCH 10/20] ppc440_sdram: Implement enable bit in the DDR2 SDRAM controller
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
To allow removing the do_init hack we need to improve the DDR2 SDRAM
controller model to handle the enable/disable bit that it ignored so
far.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index c33f91e134..7c1513ff69 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -23,6 +23,7 @@
#include "sysemu/reset.h"
#include "ppc440.h"
#include "qom/object.h"
+#include "trace.h"
/*/
/* L2 Cache as SRAM */
@@ -484,6 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
/* SDRAM controller */
typedef struct ppc440_sdram_t {
uint32_t addr;
+uint32_t mcopt2;
int nbanks;
Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
@@ -581,12 +583,15 @@ static void sdram_set_bcr(ppc440_sdram_t *sdram, int
i,
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
+trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
sdram->bank[i].base = sdram_base(bcr);
sdram->bank[i].size = sdram_size(bcr);
if (enabled && (bcr & 1)) {
+trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
sdram_bank_map(&sdram->bank[i]);
}
}
@@ -596,7 +601,7 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
-if (sdram->bank[i].size != 0) {
+if (sdram->bank[i].size) {
sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
@@ -605,6 +610,17 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
}
}
+static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+{
+int i;
+
+for (i = 0; i < sdram->nbanks; i++) {
+if (sdram->bank[i].size) {
+sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+}
+}
+}
+
static uint32_t dcr_read_sdram(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
@@ -636,7 +652,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
ret = 0x8000;
break;
case 0x21: /* SDRAM_MCOPT2 */
-ret = 0x0800;
+ret = sdram->mcopt2;
break;
case 0x40: /* SDRAM_MB0CF */
ret = 0x8001;
@@ -680,6 +696,19 @@ static void dcr_write_sdram(void *opaque, int dcrn,
uint32_t val)
switch (sdram->addr) {
case 0x00: /* B0CR */
break;
+case 0x21: /* SDRAM_MCOPT2 */
+if (!(sdram->mcopt2 & 0x0800) && (val & 0x0800)) {
+trace_ppc4xx_sdram_enable("enable");
+/* validate all RAM mappings */
+sdram_map_bcr(sdram);
+sdram->mcopt2 |= 0x0800;
+} else if ((sdram->mcopt2 & 0x0800) && !(val &
0x0800)) {
+trace_ppc4xx_sdram_enable("disable");
+/* invalidate all RAM mappings */
+sdram_unmap_bcr(sdram);
+sdram->mcopt2 &= ~0x0800;
+}
+break;
default:
break;
}
@@ -694,6 +723,7 @@ static void sdram_reset(void *opaque)
ppc440_sdram_t *sdram = opaque;
sdram->addr = 0;
+sdram->mcopt2 = 0x0800;
Introducing a define for the 0x0800 value would make the code easier
to read.
How about BIT(27) instead of a new define just for this one? Adding e
define would probably lead to a long name which results in split lines and
less redable code in the end.
Regards,
BALATON Zoltan
Thanks,
C.
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
Re: [PATCH 13/20] ppc4xx_sdram: Rename functions to prevent name clashes
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Shouldn't we introduce class handlers instead ?
What do you mean? Could you please explain more?
Regards,
BALATON Zoltan
Thanks,
C.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 69 ++--
hw/ppc/ppc4xx_devs.c | 44 ++--
2 files changed, 57 insertions(+), 56 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 72eb75d3d2..b39c6dbbd2 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -502,7 +502,7 @@ enum {
SDRAM_PLBADDUHB = 0x50,
};
-static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
+static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -547,12 +547,12 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr
ram_size)
return bcr;
}
-static inline hwaddr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_ddr2_base(uint32_t bcr)
{
return (bcr & 0xffe0) << 2;
}
-static uint64_t sdram_size(uint32_t bcr)
+static uint64_t sdram_ddr2_size(uint32_t bcr)
{
uint64_t size;
int sh;
@@ -578,50 +578,51 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
object_unparent(OBJECT(&bank->container));
}
-static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
- uint32_t bcr, int enabled)
+static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
+ uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
-trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
+ sdram_ddr2_size(sdram->bank[i].bcr));
sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
-sdram->bank[i].base = sdram_base(bcr);
-sdram->bank[i].size = sdram_size(bcr);
+sdram->bank[i].base = sdram_ddr2_base(bcr);
+sdram->bank[i].size = sdram_ddr2_size(bcr);
if (enabled && (bcr & 1)) {
-trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr),
sdram_ddr2_size(bcr));
sdram_bank_map(&sdram->bank[i]);
}
}
-static void sdram_map_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
-sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+sdram_ddr2_set_bcr(sdram, i,
+ sdram_ddr2_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
-sdram_set_bcr(sdram, i, 0, 0);
+sdram_ddr2_set_bcr(sdram, i, 0, 0);
}
}
}
-static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
-sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
}
}
}
-static uint32_t dcr_read_sdram(void *opaque, int dcrn)
+static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
uint32_t ret = 0;
@@ -632,8 +633,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
case SDRAM_R2BAS:
case SDRAM_R3BAS:
if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
-ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
-sdram->bank[dcrn - SDRAM_R0BAS].size);
+ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -674,7 +675,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
return ret;
}
-static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
+static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
ppc440_sdram_t *sdram = opaque;
@@ -700,12 +701,12 @@ static void dcr_write_sdram(void *opaque, int dcrn,
uint32_t val)
if (!(sdram->mcopt2 & 0x0800) && (val & 0x0800)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
-sdram_map_bcr(sdram);
+sdram_ddr2_map_bcr(sdram);
sdram->mcopt2 |= 0x0800;
} else if ((sdram->mc
Re: [PATCH 14/20] ppc440_sdram: Move RAM size check to ppc440_sdram_init
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
Move the check for valid memory sizes from board to sdram contrller
controller
init. Board now only checks for additinal restrictions imposed by
additional
Thanks for finding these spelling mistakes, looks like I was in a hurry...
firmware then sdram init checks for valid sizes for SoC.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440.h| 4 ++--
hw/ppc/ppc440_uc.c | 15 +++
hw/ppc/sam460ex.c | 32 +---
3 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 7bd5cca1ab..29f6f14ed7 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -11,13 +11,13 @@
#ifndef PPC440_H
#define PPC440_H
-#include "hw/ppc/ppc4xx.h"
+#include "hw/ppc/ppc.h"
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank ram_banks[]);
+ MemoryRegion *ram);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index b39c6dbbd2..e77d56225d 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -486,7 +486,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
typedef struct ppc440_sdram_t {
uint32_t addr;
uint32_t mcopt2;
-int nbanks;
+int nbanks; /* Banks to use from the 4, e.g. when board has less slots
*/
Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
@@ -728,18 +728,17 @@ static void sdram_ddr2_reset(void *opaque)
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank ram_banks[])
+ MemoryRegion *ram)
{
ppc440_sdram_t *s;
-int i;
+const ram_addr_t valid_bank_sizes[] = {
+4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 *
MiB,
+32 * MiB, 16 * MiB, 8 * MiB, 0
+};
s = g_malloc0(sizeof(*s));
s->nbanks = nbanks;
-for (i = 0; i < nbanks; i++) {
-s->bank[i].ram = ram_banks[i].ram;
-s->bank[i].base = ram_banks[i].base;
-s->bank[i].size = ram_banks[i].size;
-}
+ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes);
qemu_register_reset(&sdram_ddr2_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index dac329d482..9b850808a3 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -74,13 +74,6 @@
#define EBC_FREQ 11500
#define UART_FREQ 11059200
-/* The SoC could also handle 4 GiB but firmware does not work with that.
*/
-/* Maybe it overflows a signed 32 bit number somewhere? */
-static const ram_addr_t ppc460ex_sdram_bank_sizes[] = {
-2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
-32 * MiB, 0
-};
-
struct boot_info {
uint32_t dt_base;
uint32_t dt_size;
@@ -273,7 +266,6 @@ static void sam460ex_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
-Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1);
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
int i;
@@ -340,12 +332,22 @@ static void sam460ex_init(MachineState *machine)
}
/* SDRAM controller */
-/* put all RAM on first bank because board has one slot
- * and firmware only checks that */
-ppc4xx_sdram_banks(machine->ram, 1, ram_banks,
ppc460ex_sdram_bank_sizes);
-
+/* The SoC could also handle 4 GiB but firmware does not work with
that. */
+if (machine->ram_size > 2 * GiB) {
+error_report("Memory over 2 GiB is not supported");
+exit(1);
+}
+/* Firmware needs at least 64 MiB */
+if (machine->ram_size < 64 * MiB) {
+error_report("Memory below 64 MiB is not supported");
+exit(1);
+}
These checks on the RAM size should be done by the SDRAM model.
May be it is addressed later in the patchset ?
No, these are really board specific as the commenst say, they are imposed
by board firmware (as firmware fails with other valid RAM sizes for the
SoC) that's why these are here and the SoC size limits are checked in the
SDRAM controller model.
Regards,
BALATON Zoltan
C.
+/*
+ * Put all RAM on first bank because board has one slot
+ * and firmware only checks that
+ */
+ppc440_sdram_init(env, 1, machine->ram);
/* FIXME: does 460EX have ECC interrupts? */
-ppc440_sdram_init(env, 1, ram_banks);
/* Enable SDRAM memory regions as we may boot without firmware */
if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21) ||
Re: [PATCH v1 0/8] migration: introduce dirtylimit capability
在 2022/9/7 4:46, Peter Xu 写道:
On Fri, Sep 02, 2022 at 01:22:28AM +0800, huang...@chinatelecom.cn wrote:
From: Hyman Huang(黄勇)
v1:
- make parameter vcpu-dirty-limit experimental
- switch dirty limit off when cancel migrate
- add cancel logic in migration test
Please review, thanks,
Yong
Abstract
This series added a new migration capability called "dirtylimit". It can
be enabled when dirty ring is enabled, and it'll improve the vCPU performance
during the process of migration. It is based on the previous patchset:
https://lore.kernel.org/qemu-devel/cover.1656177590.git.huang...@chinatelecom.cn/
As mentioned in patchset "support dirty restraint on vCPU", dirtylimit way of
migration can make the read-process not be penalized. This series wires up the
vcpu dirty limit and wrappers as dirtylimit capability of migration. I introduce
two parameters vcpu-dirtylimit-period and vcpu-dirtylimit to implement the setup
of dirtylimit during live migration.
To validate the implementation, i tested a 32 vCPU vm live migration with such
model:
Only dirty vcpu0, vcpu1 with heavy memory workoad and leave the rest vcpus
untouched, running unixbench on the vpcu8-vcpu15 by setup the cpu affinity as
the following command:
taskset -c 8-15 ./Run -i 2 -c 8 {unixbench test item}
The following are results:
host cpu: Intel(R) Xeon(R) Platinum 8378A
host interface speed: 1000Mb/s
|-+++---|
| UnixBench test item | Normal | Dirtylimit | Auto-converge |
|-+++---|
| dhry2reg| 32800 | 32786 | 25292 |
| whetstone-double| 10326 | 10315 | 9847 |
| pipe| 15442 | 15271 | 14506 |
| context1| 7260 | 6235 | 4514 |
| spawn | 3663 | 3317 | 3249 |
| syscall | 4669 | 4667 | 3841 |
|-+++---|
From the data above we can draw a conclusion that vcpus that do not dirty
memory
in vm are almost unaffected during the dirtylimit migration, but the auto
converge
way does.
I also tested the total time of dirtylimit migration with variable dirty memory
size in vm.
senario 1:
host cpu: Intel(R) Xeon(R) Platinum 8378A
host interface speed: 1000Mb/s
|---++---|
| dirty memory size(MB) | Dirtylimit(ms) | Auto-converge(ms) |
|---++---|
| 60| 2014 | 2131 |
| 70| 5381 | 12590 |
| 90| 6037 | 33545 |
| 110 | 7660 | [*] |
|---++---|
[*]: This case means migration is not convergent.
senario 2:
host cpu: Intel(R) Xeon(R) CPU E5-2650
host interface speed: 1Mb/s
|---++---|
| dirty memory size(MB) | Dirtylimit(ms) | Auto-converge(ms) |
|---++---|
| 1600 | 15842 | 27548 |
| 2000 | 19026 | 38447 |
| 2400 | 19897 | 46381 |
| 2800 | 22338 | 57149 |
|---++---|
Above data shows that dirtylimit way of migration can also reduce the total
time of migration and it achieves convergence more easily in some case.
In addition to implement dirtylimit capability itself, this series
add 3 tests for migration, aiming at playing around for developer simply:
1. qtest for dirty limit migration
2. support dirty ring way of migration for guestperf tool
3. support dirty limit migration for guestperf tool
Yong,
I should have asked even earlier - just curious whether you have started
using this in production systems? It's definitely not required for any
patchset to be merged, but it'll be very useful (and supportive)
information to have if there's proper testing beds applied already.
Actually no when i posted the cover letter above, the qemu version in
our production is much lower than upstream, and the patchset is
different from here, i built test mode and did the test on my own in the
first time. But this feature is in the process of test conducted by
another professional test team, so once report is ready, i'll post it. :)
Thanks,
Re: [PATCH 06/20] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
On Wed, 7 Sep 2022, Cédric Le Goater wrote:
On 8/19/22 18:55, BALATON Zoltan wrote:
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan
It looks like a good clean up. At some point, I think we will need to
pass "MemoryRegion *sysmem" to the SDRAM model. Let's start with this
change and see how it evolves.
Not sure what you mean here, this and the QOM'ify patches later in the
series change it to pass the memory region from board to the dram property
of the SDRAM controller model. This allows the board to set any memory
region or alias as the SoC memory area.
One small comment below
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc/ppc405.h | 2 --
hw/ppc/ppc405_boards.c | 10 --
hw/ppc/ppc405_uc.c | 11 ++-
hw/ppc/ppc440_bamboo.c | 10 +-
hw/ppc/ppc4xx_devs.c| 14 ++
include/hw/ppc/ppc4xx.h | 2 +-
6 files changed, 10 insertions(+), 39 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ca0972b88b..ad54dff542 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,9 +167,7 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
-Ppc4xxSdramBank ram_banks[2];
MemoryRegion *dram_mr;
-hwaddr ram_size;
PowerPCCPU cpu;
PPCUIC uic;
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 0a29ad97c7..a82b6c5c83 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -278,21 +278,11 @@ static void boot_from_kernel(MachineState *machine,
PowerPCCPU *cpu)
static void ppc405_init(MachineState *machine)
{
Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
-MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
MemoryRegion *sysmem = get_system_memory();
-if (machine->ram_size != mc->default_ram_size) {
-char *sz = size_to_str(mc->default_ram_size);
-error_report("Invalid RAM size, should be %s", sz);
-g_free(sz);
-exit(EXIT_FAILURE);
-}
-
object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
TYPE_PPC405_SOC);
-object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
- machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort);
object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", ,
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 461d18c8a5..4049fb98dc 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1070,15 +1070,9 @@ static void ppc405_soc_realize(DeviceState *dev,
Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu),
PPC40x_INPUT_CINT));
/* SDRAM controller */
-/* XXX 405EP has no ECC interrupt */
-s->ram_banks[0].base = 0;
-s->ram_banks[0].size = s->ram_size;
-memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
- "ppc405.sdram0", s->dram_mr,
- s->ram_banks[0].base, s->ram_banks[0].size);
-
+/* XXX 405EP has no ECC interrupt */
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks);
+ s->dram_mr);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1156,7 +1150,6 @@ static void ppc405_soc_realize(DeviceState *dev,
Error **errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
-DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 2bd5e41140..9b456f1819 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -50,10 +50,6 @@
#define PPC440EP_SDRAM_NR_BANKS 4
-static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
-256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB,
0
-};
-
static hwaddr entry;
static int bamboo_load_device_tree(hwaddr addr,
@@ -168,8 +164,6 @@ static void bamboo_init(MachineState *machine)
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
-Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
-PPC440EP_SDRAM_NR_BANKS);
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -204,11 +198,9 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
-ppc4xx_sdram
[PULL 00/10] QAPI patches patches for 2022-09-07
The following changes since commit 946e9bccf12f2bcc3ca471b820738fb22d14fc80: Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into staging (2022-09-06 08:31:24 -0400) are available in the Git repository at: git://repo.or.cz/qemu/armbru.git tags/pull-qapi-2022-09-07 for you to fetch changes up to 6e7a37ffc230d06852f1a8893097331d39df77c9: qapi: fix examples of events missing timestamp (2022-09-07 15:10:13 +0200) QAPI patches patches for 2022-09-07 Victor Toso (10): qapi: fix example of query-ballon command qapi: fix example of query-vnc command qapi: fix example of query-dump-guest-memory-capability command qapi: fix example of BLOCK_JOB_READY event qapi: fix example of NIC_RX_FILTER_CHANGED event qapi: fix example of DEVICE_UNPLUG_GUEST_ERROR event qapi: fix example of MEM_UNPLUG_ERROR event qapi: fix examples of blockdev-add with qcow2 qapi: fix example of query-hotpluggable-cpus command qapi: fix examples of events missing timestamp qapi/block-core.json | 12 ++-- qapi/dump.json | 2 +- qapi/machine.json| 8 qapi/migration.json | 27 +++ qapi/net.json| 1 - qapi/qdev.json | 3 +-- qapi/ui.json | 4 ++-- 7 files changed, 37 insertions(+), 20 deletions(-) -- 2.37.2
[PULL 06/10] qapi: fix example of DEVICE_UNPLUG_GUEST_ERROR event
From: Victor Toso
Example output is missing a ',' delimiter and it has an extra ending
curly bracket. Fix it.
Problem was noticed when trying to load the example into python's json
library.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-7-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/qdev.json | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/qapi/qdev.json b/qapi/qdev.json
index 26cd10106b..2708fb4e99 100644
--- a/qapi/qdev.json
+++ b/qapi/qdev.json
@@ -150,10 +150,9 @@
#
# Example:
#
-# <- { "event": "DEVICE_UNPLUG_GUEST_ERROR"
+# <- { "event": "DEVICE_UNPLUG_GUEST_ERROR",
# "data": { "device": "core1",
#"path": "/machine/peripheral/core1" },
-# },
# "timestamp": { "seconds": 1615570772, "microseconds": 202844 } }
#
##
--
2.37.2
[PULL 09/10] qapi: fix example of query-hotpluggable-cpus command
From: Victor Toso
The example return type has the wrong member name. Fix it.
Problem was noticed when using the example as a test case for Go
bindings.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-10-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/machine.json | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index 4782eea2c3..abb2f48808 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -958,9 +958,9 @@
#
# -> { "execute": "query-hotpluggable-cpus" }
# <- {"return": [
-# { "props": { "core": 8 }, "type": "POWER8-spapr-cpu-core",
+# { "props": { "core-id": 8 }, "type": "POWER8-spapr-cpu-core",
#"vcpus-count": 1 },
-# { "props": { "core": 0 }, "type": "POWER8-spapr-cpu-core",
+# { "props": { "core-id": 0 }, "type": "POWER8-spapr-cpu-core",
#"vcpus-count": 1, "qom-path": "/machine/unattached/device[0]"}
#]}'
#
--
2.37.2
[PULL 05/10] qapi: fix example of NIC_RX_FILTER_CHANGED event
From: Victor Toso
Example output has an extra ending curly bracket. Fix it.
Problem was noticed when trying to load the example into python's json
library.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-6-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/net.json | 1 -
1 file changed, 1 deletion(-)
diff --git a/qapi/net.json b/qapi/net.json
index 75ba2cb989..dd088c09c5 100644
--- a/qapi/net.json
+++ b/qapi/net.json
@@ -757,7 +757,6 @@
# "data": { "name": "vnet0",
#"path": "/machine/peripheral/vnet0/virtio-backend" },
# "timestamp": { "seconds": 1368697518, "microseconds": 326866 } }
-#}
#
##
{ 'event': 'NIC_RX_FILTER_CHANGED',
--
2.37.2
[PULL 08/10] qapi: fix examples of blockdev-add with qcow2
From: Victor Toso
The examples use "qcow2" driver with the wrong member name for
BlockdevRef alternate type. This patch changes all wrong member names
from "file" to "data-file" which is the correct member name in
BlockdevOptionsQcow2 for the BlockdevRef field.
Problem was noticed when using the example as a test case for Go
bindings.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-9-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/block-core.json | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/qapi/block-core.json b/qapi/block-core.json
index 882b266532..f21fa235f2 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@ -1541,8 +1541,8 @@
# -> { "execute": "blockdev-add",
# "arguments": { "driver": "qcow2",
# "node-name": "node1534",
-# "file": { "driver": "file",
-# "filename": "hd1.qcow2" },
+# "data-file": { "driver": "file",
+#"filename": "hd1.qcow2" },
# "backing": null } }
#
# <- { "return": {} }
@@ -4378,7 +4378,7 @@
# "arguments": {
# "driver": "qcow2",
# "node-name": "test1",
-# "file": {
+# "data-file": {
# "driver": "file",
# "filename": "test.qcow2"
#}
@@ -4395,7 +4395,7 @@
# "cache": {
# "direct": true
#},
-#"file": {
+# "data-file": {
# "driver": "file",
# "filename": "/tmp/test.qcow2"
#},
@@ -4477,7 +4477,7 @@
# "arguments": {
# "driver": "qcow2",
# "node-name": "node0",
-# "file": {
+# "data-file": {
# "driver": "file",
# "filename": "test.qcow2"
# }
--
2.37.2
[PULL 02/10] qapi: fix example of query-vnc command
From: Victor Toso
Example output has an extra ',' delimiter in member "websocket" and it
lacks it in "family" member. Fix it.
Problem was noticed when trying to load the example into python's json
library.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-3-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/ui.json | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qapi/ui.json b/qapi/ui.json
index cf58ab4283..286c5731d1 100644
--- a/qapi/ui.json
+++ b/qapi/ui.json
@@ -667,8 +667,8 @@
# {
#"host":"127.0.0.1",
#"service":"50401",
-#"family":"ipv4"
-#"websocket":false,
+#"family":"ipv4",
+#"websocket":false
# }
# ]
# }
--
2.37.2
[PULL 07/10] qapi: fix example of MEM_UNPLUG_ERROR event
From: Victor Toso
Example output was missing ',' delimiter. Fix it.
Problem was noticed when trying to load the example into python's json
library.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-8-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/machine.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index 5f1f50d3ed..4782eea2c3 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -1416,7 +1416,7 @@
#
# Example:
#
-# <- { "event": "MEM_UNPLUG_ERROR"
+# <- { "event": "MEM_UNPLUG_ERROR",
# "data": { "device": "dimm1",
#"msg": "acpi: device unplug for unsupported device"
# },
--
2.37.2
[PULL 01/10] qapi: fix example of query-ballon command
From: Victor Toso
Example output has an extra ',' delimiter. Fix it.
Problem was noticed when trying to load the example into python's json
library.
Signed-off-by: Victor Toso
Message-Id: <20220901085840.22520-2-victort...@redhat.com>
Signed-off-by: Markus Armbruster
---
qapi/machine.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index 6afd1936b0..5f1f50d3ed 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -1074,7 +1074,7 @@
#
# -> { "execute": "query-balloon" }
# <- { "return": {
-# "actual": 1073741824,
+# "actual": 1073741824
# }
#}
#
--
2.37.2
