[PATCH 0/2] Decouple Xen-HVM from PIIX
hw/i386/xen/xen-hvm.c contains logic which is PIIX-specific. This makes xen-hvm.c depend on PIIX which can be avoided if PIIX logic was isolated in PIIX itself. Bernhard Beschow (2): hw/i386/xen/xen-hvm: Allow for stubbing xen_set_pci_link_route() hw/i386/xen/xen-hvm: Inline xen_piix_pci_write_config_client() and remove it hw/i386/xen/xen-hvm.c | 17 ++--- hw/isa/piix3.c | 15 ++- include/hw/xen/xen.h| 2 +- include/hw/xen/xen_common.h | 6 -- stubs/xen-hw-stub.c | 3 ++- 5 files changed, 19 insertions(+), 24 deletions(-) -- 2.36.1
[PATCH 1/2] hw/i386/xen/xen-hvm: Allow for stubbing xen_set_pci_link_route()
The only user of xen_set_pci_link_route() is
xen_piix_pci_write_config_client() which implements PIIX-specific logic in
the xen namespace. This makes xen-hvm depend on PIIX which could be
avoided if xen_piix_pci_write_config_client() was implemented in PIIX. In
order to do this, xen_set_pci_link_route() needs to be stubbable which
this patch addresses.
Signed-off-by: Bernhard Beschow
---
hw/i386/xen/xen-hvm.c | 7 ++-
include/hw/xen/xen.h| 1 +
include/hw/xen/xen_common.h | 6 --
stubs/xen-hw-stub.c | 5 +
4 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 0731f70410..204fda7949 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -161,11 +161,16 @@ void xen_piix_pci_write_config_client(uint32_t address,
uint32_t val, int len)
}
v &= 0xf;
if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
-xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
+xen_set_pci_link_route(address + i - PIIX_PIRQCA, v);
}
}
}
+int xen_set_pci_link_route(uint8_t link, uint8_t irq)
+{
+return xendevicemodel_set_pci_link_route(xen_dmod, xen_domid, link, irq);
+}
+
int xen_is_pirq_msi(uint32_t msi_data)
{
/* If vector is 0, the msi is remapped into a pirq, passed as
diff --git a/include/hw/xen/xen.h b/include/hw/xen/xen.h
index 0f9962b1c1..13bffaef53 100644
--- a/include/hw/xen/xen.h
+++ b/include/hw/xen/xen.h
@@ -21,6 +21,7 @@ extern enum xen_mode xen_mode;
extern bool xen_domid_restrict;
int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num);
+int xen_set_pci_link_route(uint8_t link, uint8_t irq);
void xen_piix3_set_irq(void *opaque, int irq_num, int level);
void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len);
void xen_hvm_inject_msi(uint64_t addr, uint32_t data);
diff --git a/include/hw/xen/xen_common.h b/include/hw/xen/xen_common.h
index 179741ff79..77ce17d8a4 100644
--- a/include/hw/xen/xen_common.h
+++ b/include/hw/xen/xen_common.h
@@ -316,12 +316,6 @@ static inline int xen_set_pci_intx_level(domid_t domid,
uint16_t segment,
device, intx, level);
}
-static inline int xen_set_pci_link_route(domid_t domid, uint8_t link,
- uint8_t irq)
-{
-return xendevicemodel_set_pci_link_route(xen_dmod, domid, link, irq);
-}
-
static inline int xen_inject_msi(domid_t domid, uint64_t msi_addr,
uint32_t msi_data)
{
diff --git a/stubs/xen-hw-stub.c b/stubs/xen-hw-stub.c
index 15f3921a76..743967623f 100644
--- a/stubs/xen-hw-stub.c
+++ b/stubs/xen-hw-stub.c
@@ -23,6 +23,11 @@ void xen_piix_pci_write_config_client(uint32_t address,
uint32_t val, int len)
{
}
+int xen_set_pci_link_route(uint8_t link, uint8_t irq)
+{
+return -1;
+}
+
void xen_hvm_inject_msi(uint64_t addr, uint32_t data)
{
}
--
2.36.1
[PATCH 2/2] hw/i386/xen/xen-hvm: Inline xen_piix_pci_write_config_client() and remove it
xen_piix_pci_write_config_client() is implemented in the xen sub tree and
uses PIIX constants internally, thus creating a direct dependency on
PIIX. Now that xen_set_pci_link_route() is stubbable, the logic of
xen_piix_pci_write_config_client() can be moved to PIIX which resolves
the dependency.
Signed-off-by: Bernhard Beschow
---
hw/i386/xen/xen-hvm.c | 18 --
hw/isa/piix3.c| 15 ++-
include/hw/xen/xen.h | 1 -
stubs/xen-hw-stub.c | 4
4 files changed, 14 insertions(+), 24 deletions(-)
diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 204fda7949..e4293d6d66 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -15,7 +15,6 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/i386/pc.h"
-#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/hw.h"
#include "hw/i386/apic-msidef.h"
@@ -149,23 +148,6 @@ void xen_piix3_set_irq(void *opaque, int irq_num, int
level)
irq_num & 3, level);
}
-void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
-{
-int i;
-
-/* Scan for updates to PCI link routes (0x60-0x63). */
-for (i = 0; i < len; i++) {
-uint8_t v = (val >> (8 * i)) & 0xff;
-if (v & 0x80) {
-v = 0;
-}
-v &= 0xf;
-if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
-xen_set_pci_link_route(address + i - PIIX_PIRQCA, v);
-}
-}
-}
-
int xen_set_pci_link_route(uint8_t link, uint8_t irq)
{
return xendevicemodel_set_pci_link_route(xen_dmod, xen_domid, link, irq);
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 6388558f92..48f9ab1096 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -138,7 +138,20 @@ static void piix3_write_config(PCIDevice *dev,
static void piix3_write_config_xen(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
-xen_piix_pci_write_config_client(address, val, len);
+int i;
+
+/* Scan for updates to PCI link routes (0x60-0x63). */
+for (i = 0; i < len; i++) {
+uint8_t v = (val >> (8 * i)) & 0xff;
+if (v & 0x80) {
+v = 0;
+}
+v &= 0xf;
+if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
+xen_set_pci_link_route(address + i - PIIX_PIRQCA, v);
+}
+}
+
piix3_write_config(dev, address, val, len);
}
diff --git a/include/hw/xen/xen.h b/include/hw/xen/xen.h
index 13bffaef53..afdf9c436a 100644
--- a/include/hw/xen/xen.h
+++ b/include/hw/xen/xen.h
@@ -23,7 +23,6 @@ extern bool xen_domid_restrict;
int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num);
int xen_set_pci_link_route(uint8_t link, uint8_t irq);
void xen_piix3_set_irq(void *opaque, int irq_num, int level);
-void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len);
void xen_hvm_inject_msi(uint64_t addr, uint32_t data);
int xen_is_pirq_msi(uint32_t msi_data);
diff --git a/stubs/xen-hw-stub.c b/stubs/xen-hw-stub.c
index 743967623f..34a22f2ad7 100644
--- a/stubs/xen-hw-stub.c
+++ b/stubs/xen-hw-stub.c
@@ -19,10 +19,6 @@ void xen_piix3_set_irq(void *opaque, int irq_num, int level)
{
}
-void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
-{
-}
-
int xen_set_pci_link_route(uint8_t link, uint8_t irq)
{
return -1;
--
2.36.1
Re: [PATCH v2 47/54] lasips2: switch over from update_irq() function to PS2 device gpio
On 24/06/2022 14:41, Mark Cave-Ayland wrote:
Add a qdev gpio input in lasips2_init() by taking the existing
lasips2_port_set_irq()
function, updating it accordingly and then renaming to lasips2_set_irq(). Use
these
new qdev gpio inputs to wire up the PS2 keyboard and mouse devices.
At the same time set update_irq() and update_arg to NULL in ps2_kbd_init() and
ps2_mouse_init() to ensure that any accidental attempt to use the legacy
update_irq()
function will cause a NULL pointer dereference.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
---
hw/input/lasips2.c | 30 ++
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index bd72505411..e1a8a7e34b 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -237,9 +237,19 @@ static const MemoryRegionOps lasips2_reg_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void lasips2_port_set_irq(void *opaque, int level)
+static void lasips2_set_kbd_irq(void *opaque, int n, int level)
{
-LASIPS2Port *port = opaque;
+LASIPS2State *s = LASIPS2(opaque);
+LASIPS2Port *port = &s->kbd;
+
+port->irq = level;
+lasips2_update_irq(port->parent);
+}
+
+static void lasips2_set_mouse_irq(void *opaque, int n, int level)
+{
+LASIPS2State *s = LASIPS2(opaque);
+LASIPS2Port *port = &s->mouse;
port->irq = level;
lasips2_update_irq(port->parent);
@@ -264,8 +274,14 @@ static void lasips2_realize(DeviceState *dev, Error **errp)
vmstate_register(NULL, s->base, &vmstate_lasips2, s);
-s->kbd.dev = ps2_kbd_init(lasips2_port_set_irq, &s->kbd);
-s->mouse.dev = ps2_mouse_init(lasips2_port_set_irq, &s->mouse);
+s->kbd.dev = ps2_kbd_init(NULL, NULL);
+qdev_connect_gpio_out(DEVICE(s->kbd.dev), PS2_DEVICE_IRQ,
+ qdev_get_gpio_in_named(dev, "ps2-kbd-input-irq",
+ 0));
+s->mouse.dev = ps2_mouse_init(NULL, NULL);
+qdev_connect_gpio_out(DEVICE(s->mouse.dev), PS2_DEVICE_IRQ,
+ qdev_get_gpio_in_named(dev, "ps2-mouse-input-irq",
+ 0));
}
static void lasips2_init(Object *obj)
@@ -286,6 +302,12 @@ static void lasips2_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mouse.reg);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+qdev_init_gpio_out(DEVICE(obj), &s->irq, 1);
I was just rebasing and testing part 2 of this series which flagged up that the
rebase on part 1 had inadvertently pulled the old qdev_init_gpio_out() back in again
on this patch. This line is no longer needed and should simply be removed.
I'll remove it locally and if everything still looks good after testing (including
gitlab CI) then I shall queue this series to my qemu-sparc branch and send an MR.
+qdev_init_gpio_in_named(DEVICE(obj), lasips2_set_kbd_irq,
+"ps2-kbd-input-irq", 1);
+qdev_init_gpio_in_named(DEVICE(obj), lasips2_set_mouse_irq,
+"ps2-mouse-input-irq", 1);
}
static Property lasips2_properties[] = {
ATB,
Mark.
Re: [PATCH] Align Raspberry Pi DMA interrupts with Linux DTS
On Fri, 24 Jun 2022 at 21:54, Andrey Makarov wrote:
>
> All Raspberry Pi models 1-3 (based on bcm2835) have
> Linux device tree (arch/arm/boot/dts/bcm2835-common.dtsi +25):
>
> /* dma channel 11-14 share one irq */
>
> which mismatched the Qemu model.
> In this patch channels 0--10 and 11--14 are handled separately.
Is there any hardware documentation that says whether QEMU or
the DTB is correct? The device tree is at best a secondary source...
> Signed-off-by: Andrey Makarov
> ---
> hw/arm/bcm2835_peripherals.c | 10 +-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
> index 48538c9360..3d808b0e31 100644
> --- a/hw/arm/bcm2835_peripherals.c
> +++ b/hw/arm/bcm2835_peripherals.c
> @@ -322,13 +322,21 @@ static void bcm2835_peripherals_realize(DeviceState
> *dev, Error **errp)
> memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET,
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1));
>
> -for (n = 0; n <= 12; n++) {
> +for (n = 0; n <= 10; n++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n,
> qdev_get_gpio_in_named(DEVICE(&s->ic),
>BCM2835_IC_GPU_IRQ,
>INTERRUPT_DMA0 + n));
> }
>
> +/* According to DTS, dma channels 11-14 share one irq */
> +for (n = 11; n <= 14; n++) {
> +sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n,
> + qdev_get_gpio_in_named(DEVICE(&s->ic),
> + BCM2835_IC_GPU_IRQ,
> + INTERRUPT_DMA0 + 11));
You can't connect multiple qemu_irq lines to one like this.
If the hardware behaves this way then you need to create
an OR gate, wire all the lines from the devices to the
OR gate inputs, and wire the OR gate output to the destination.
thanks
-- PMM
Re: [PATCH] tcg: Fix returned type in alloc_code_gen_buffer_splitwx_memfd()
On 6/24/22 20:32, Shaobo Song wrote:
This fixes a bug in POSIX-compliant environments. Since we had allocated
a buffer named 'tcg-jit' with read-write access protections we need a int
type to combine these access flags and return it, whereas we had inexplicably
return a bool type. It may cause an unnecessary protection change in
tcg_region_init().
Signed-off-by: Shaobo Song
---
tcg/region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/region.c b/tcg/region.c
index 71ea81d671..88d6bb273f 100644
--- a/tcg/region.c
+++ b/tcg/region.c
@@ -548,7 +548,7 @@ static int alloc_code_gen_buffer_anon(size_t size, int prot,
#ifdef CONFIG_POSIX
#include "qemu/memfd.h"
-static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp)
+static int alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp)
{
void *buf_rw = NULL, *buf_rx = MAP_FAILED;
int fd = -1;
Thanks, queued to tcg-next.
r~
Re: [PATCH] artist: set memory region owners for buffers to the artist device
On 6/24/22 18:08, Mark Cave-Ayland wrote:
> This fixes the output of "info qom-tree" so that the buffers appear as
> children
> of the artist device, rather than underneath the "unattached" container.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Helge Deller
Thanks!
Helge
> ---
> hw/display/artist.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/display/artist.c b/hw/display/artist.c
> index eadaef0d46..fde050c882 100644
> --- a/hw/display/artist.c
> +++ b/hw/display/artist.c
> @@ -1358,7 +1358,7 @@ static void artist_create_buffer(ARTISTState *s, const
> char *name,
> {
> struct vram_buffer *buf = s->vram_buffer + idx;
>
> -memory_region_init_ram(&buf->mr, NULL, name, width * height,
> +memory_region_init_ram(&buf->mr, OBJECT(s), name, width * height,
> &error_fatal);
> memory_region_add_subregion_overlap(&s->mem_as_root, *offset, &buf->mr,
> 0);
>
[PATCH v2] m68k: virt: pass RNG seed via bootinfo block
This commit wires up bootinfo's RNG seed attribute so that Linux VMs can
have their RNG seeded from the earliest possible time in boot, just like
the "rng-seed" device tree property on those platforms. The link
contains the corresponding Linux patch.
Link: https://lore.kernel.org/lkml/20220626111509.330159-1-ja...@zx2c4.com/
Based-on: <20220625152318.120849-1-ja...@zx2c4.com>
Reviewed-by: Laurent Vivier
Signed-off-by: Jason A. Donenfeld
---
hw/m68k/bootinfo.h | 16
hw/m68k/virt.c | 7 +++
.../standard-headers/asm-m68k/bootinfo-virt.h| 1 +
3 files changed, 24 insertions(+)
diff --git a/hw/m68k/bootinfo.h b/hw/m68k/bootinfo.h
index ff4e155a3c..bd8b212fd3 100644
--- a/hw/m68k/bootinfo.h
+++ b/hw/m68k/bootinfo.h
@@ -56,4 +56,20 @@
stb_phys(as, base++, 0); \
base = (base + 1) & ~1; \
} while (0)
+
+#define BOOTINFODATA(as, base, id, data, len) \
+do { \
+int i; \
+stw_phys(as, base, id); \
+base += 2; \
+stw_phys(as, base, \
+ (sizeof(struct bi_record) + len + 3) & ~1); \
+base += 2; \
+stw_phys(as, base, len); \
+base += 2; \
+for (i = 0; i < len; ++i) { \
+stb_phys(as, base++, data[i]); \
+} \
+base = (base + 1) & ~1; \
+} while (0)
#endif
diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c
index e215aa3d42..0aa383fa6b 100644
--- a/hw/m68k/virt.c
+++ b/hw/m68k/virt.c
@@ -9,6 +9,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
+#include "qemu/guest-random.h"
#include "sysemu/sysemu.h"
#include "cpu.h"
#include "hw/boards.h"
@@ -120,6 +121,7 @@ static void virt_init(MachineState *machine)
hwaddr io_base;
int i;
ResetInfo *reset_info;
+uint8_t rng_seed[32];
if (ram_size > 3399672 * KiB) {
/*
@@ -245,6 +247,11 @@ static void virt_init(MachineState *machine)
kernel_cmdline);
}
+ /* Pass seed to RNG. */
+ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+ BOOTINFODATA(cs->as, parameters_base, BI_VIRT_RNG_SEED,
+rng_seed, sizeof(rng_seed));
+
/* load initrd */
if (initrd_filename) {
initrd_size = get_image_size(initrd_filename);
diff --git a/include/standard-headers/asm-m68k/bootinfo-virt.h
b/include/standard-headers/asm-m68k/bootinfo-virt.h
index 81be1e0924..1b1ffd4705 100644
--- a/include/standard-headers/asm-m68k/bootinfo-virt.h
+++ b/include/standard-headers/asm-m68k/bootinfo-virt.h
@@ -12,6 +12,7 @@
#define BI_VIRT_GF_TTY_BASE0x8003
#define BI_VIRT_VIRTIO_BASE0x8004
#define BI_VIRT_CTRL_BASE 0x8005
+#define BI_VIRT_RNG_SEED 0x8006
#define VIRT_BOOTI_VERSION MK_BI_VERSION(2, 0)
--
2.35.1
Re: [PATCH 2/2] hw/i386/xen/xen-hvm: Inline xen_piix_pci_write_config_client() and remove it
On Sun, Jun 26, 2022 at 11:46:56AM +0200, Bernhard Beschow wrote:
> xen_piix_pci_write_config_client() is implemented in the xen sub tree and
> uses PIIX constants internally, thus creating a direct dependency on
> PIIX. Now that xen_set_pci_link_route() is stubbable, the logic of
> xen_piix_pci_write_config_client() can be moved to PIIX which resolves
> the dependency.
>
> Signed-off-by: Bernhard Beschow
Fine by me
Acked-by: Michael S. Tsirkin
> ---
> hw/i386/xen/xen-hvm.c | 18 --
> hw/isa/piix3.c| 15 ++-
> include/hw/xen/xen.h | 1 -
> stubs/xen-hw-stub.c | 4
> 4 files changed, 14 insertions(+), 24 deletions(-)
>
> diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
> index 204fda7949..e4293d6d66 100644
> --- a/hw/i386/xen/xen-hvm.c
> +++ b/hw/i386/xen/xen-hvm.c
> @@ -15,7 +15,6 @@
> #include "hw/pci/pci.h"
> #include "hw/pci/pci_host.h"
> #include "hw/i386/pc.h"
> -#include "hw/southbridge/piix.h"
> #include "hw/irq.h"
> #include "hw/hw.h"
> #include "hw/i386/apic-msidef.h"
> @@ -149,23 +148,6 @@ void xen_piix3_set_irq(void *opaque, int irq_num, int
> level)
> irq_num & 3, level);
> }
>
> -void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int
> len)
> -{
> -int i;
> -
> -/* Scan for updates to PCI link routes (0x60-0x63). */
> -for (i = 0; i < len; i++) {
> -uint8_t v = (val >> (8 * i)) & 0xff;
> -if (v & 0x80) {
> -v = 0;
> -}
> -v &= 0xf;
> -if (((address + i) >= PIIX_PIRQCA) && ((address + i) <=
> PIIX_PIRQCD)) {
> -xen_set_pci_link_route(address + i - PIIX_PIRQCA, v);
> -}
> -}
> -}
> -
> int xen_set_pci_link_route(uint8_t link, uint8_t irq)
> {
> return xendevicemodel_set_pci_link_route(xen_dmod, xen_domid, link, irq);
> diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
> index 6388558f92..48f9ab1096 100644
> --- a/hw/isa/piix3.c
> +++ b/hw/isa/piix3.c
> @@ -138,7 +138,20 @@ static void piix3_write_config(PCIDevice *dev,
> static void piix3_write_config_xen(PCIDevice *dev,
> uint32_t address, uint32_t val, int len)
> {
> -xen_piix_pci_write_config_client(address, val, len);
> +int i;
> +
> +/* Scan for updates to PCI link routes (0x60-0x63). */
> +for (i = 0; i < len; i++) {
> +uint8_t v = (val >> (8 * i)) & 0xff;
> +if (v & 0x80) {
> +v = 0;
> +}
> +v &= 0xf;
> +if (((address + i) >= PIIX_PIRQCA) && ((address + i) <=
> PIIX_PIRQCD)) {
> +xen_set_pci_link_route(address + i - PIIX_PIRQCA, v);
> +}
> +}
> +
> piix3_write_config(dev, address, val, len);
> }
>
> diff --git a/include/hw/xen/xen.h b/include/hw/xen/xen.h
> index 13bffaef53..afdf9c436a 100644
> --- a/include/hw/xen/xen.h
> +++ b/include/hw/xen/xen.h
> @@ -23,7 +23,6 @@ extern bool xen_domid_restrict;
> int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num);
> int xen_set_pci_link_route(uint8_t link, uint8_t irq);
> void xen_piix3_set_irq(void *opaque, int irq_num, int level);
> -void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int
> len);
> void xen_hvm_inject_msi(uint64_t addr, uint32_t data);
> int xen_is_pirq_msi(uint32_t msi_data);
>
> diff --git a/stubs/xen-hw-stub.c b/stubs/xen-hw-stub.c
> index 743967623f..34a22f2ad7 100644
> --- a/stubs/xen-hw-stub.c
> +++ b/stubs/xen-hw-stub.c
> @@ -19,10 +19,6 @@ void xen_piix3_set_irq(void *opaque, int irq_num, int
> level)
> {
> }
>
> -void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int
> len)
> -{
> -}
> -
> int xen_set_pci_link_route(uint8_t link, uint8_t irq)
> {
> return -1;
> --
> 2.36.1
Re: [PATCH] artist: set memory region owners for buffers to the artist device
On 26/06/2022 12:15, Helge Deller wrote: On 6/24/22 18:08, Mark Cave-Ayland wrote: This fixes the output of "info qom-tree" so that the buffers appear as children of the artist device, rather than underneath the "unattached" container. Signed-off-by: Mark Cave-Ayland Reviewed-by: Helge Deller Thanks! Helge Thanks Helge. I'll queue this to my qemu-sparc branch along with the ps2 QOM patches given that it's a trivial patch, and I'm already touching the lasips2 device which requires testing the HPPA B160L machine anyhow. ATB, Mark.
[PULL 02/55] ps2: QOMify PS2State
Make PS2State a new abstract PS2_DEVICE QOM type to represent the common
functionality shared between PS2 keyboard and mouse devices.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-3-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 67dd2eca84..514e55cbb6 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
+#include "hw/sysbus.h"
#include "hw/input/ps2.h"
#include "migration/vmstate.h"
#include "ui/console.h"
@@ -96,12 +97,17 @@ typedef struct {
} PS2Queue;
struct PS2State {
+SysBusDevice parent_obj;
+
PS2Queue queue;
int32_t write_cmd;
void (*update_irq)(void *, int);
void *update_arg;
};
+#define TYPE_PS2_DEVICE "ps2-device"
+OBJECT_DECLARE_SIMPLE_TYPE(PS2State, PS2_DEVICE)
+
typedef struct {
PS2State common;
int scan_enabled;
@@ -1277,3 +1283,25 @@ void *ps2_mouse_init(void (*update_irq)(void *, int),
void *update_arg)
qemu_register_reset(ps2_mouse_reset, s);
return s;
}
+
+static void ps2_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
+}
+
+static const TypeInfo ps2_info = {
+.name = TYPE_PS2_DEVICE,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(PS2State),
+.class_init= ps2_class_init,
+.abstract = true
+};
+
+static void ps2_register_types(void)
+{
+type_register_static(&ps2_info);
+}
+
+type_init(ps2_register_types)
--
2.30.2
[PULL 08/55] ps2: implement ps2_reset() for the PS2_DEVICE QOM type based upon ps2_common_reset()
The functionality of ps2_common_reset() can be moved into a new ps2_reset()
function
for the PS2_DEVICE QOM type. Update PS2DeviceClass to hold a reference to the
parent
reset function and update the PS2_KBD_DEVICE and PS2_MOUSE_DEVICE types to use
device_class_set_parent_reset() accordingly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-9-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 48 ++
include/hw/input/ps2.h | 2 ++
2 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index fd5236690a..f6f5514f0b 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -995,8 +995,10 @@ void ps2_write_mouse(PS2MouseState *s, int val)
}
}
-static void ps2_common_reset(PS2State *s)
+static void ps2_reset(DeviceState *dev)
{
+PS2State *s = PS2_DEVICE(dev);
+
s->write_cmd = -1;
ps2_reset_queue(s);
s->update_irq(s->update_arg, 0);
@@ -1028,26 +1030,28 @@ static void ps2_common_post_load(PS2State *s)
q->cwptr = ccount ? (q->rptr + ccount) & (PS2_BUFFER_SIZE - 1) : -1;
}
-static void ps2_kbd_reset(void *opaque)
+static void ps2_kbd_reset(DeviceState *dev)
{
-PS2KbdState *s = (PS2KbdState *) opaque;
-PS2State *ps2 = PS2_DEVICE(s);
+PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(dev);
+PS2KbdState *s = PS2_KBD_DEVICE(dev);
+
+trace_ps2_kbd_reset(s);
+ps2dc->parent_reset(dev);
-trace_ps2_kbd_reset(opaque);
-ps2_common_reset(ps2);
s->scan_enabled = 1;
s->translate = 0;
s->scancode_set = 2;
s->modifiers = 0;
}
-static void ps2_mouse_reset(void *opaque)
+static void ps2_mouse_reset(DeviceState *dev)
{
-PS2MouseState *s = (PS2MouseState *) opaque;
-PS2State *ps2 = PS2_DEVICE(s);
+PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(dev);
+PS2MouseState *s = PS2_MOUSE_DEVICE(dev);
+
+trace_ps2_mouse_reset(s);
+ps2dc->parent_reset(dev);
-trace_ps2_mouse_reset(opaque);
-ps2_common_reset(ps2);
s->mouse_status = 0;
s->mouse_resolution = 0;
s->mouse_sample_rate = 0;
@@ -1227,7 +1231,6 @@ void *ps2_kbd_init(void (*update_irq)(void *, int), void
*update_arg)
vmstate_register(NULL, 0, &vmstate_ps2_keyboard, s);
qemu_input_handler_register((DeviceState *)s,
&ps2_keyboard_handler);
-qemu_register_reset(ps2_kbd_reset, s);
return s;
}
@@ -1255,26 +1258,45 @@ void *ps2_mouse_init(void (*update_irq)(void *, int),
void *update_arg)
vmstate_register(NULL, 0, &vmstate_ps2_mouse, s);
qemu_input_handler_register((DeviceState *)s,
&ps2_mouse_handler);
-qemu_register_reset(ps2_mouse_reset, s);
return s;
}
+static void ps2_kbd_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+PS2DeviceClass *ps2dc = PS2_DEVICE_CLASS(klass);
+
+device_class_set_parent_reset(dc, ps2_kbd_reset, &ps2dc->parent_reset);
+}
+
static const TypeInfo ps2_kbd_info = {
.name = TYPE_PS2_KBD_DEVICE,
.parent= TYPE_PS2_DEVICE,
.instance_size = sizeof(PS2KbdState),
+.class_init= ps2_kbd_class_init
};
+static void ps2_mouse_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+PS2DeviceClass *ps2dc = PS2_DEVICE_CLASS(klass);
+
+device_class_set_parent_reset(dc, ps2_mouse_reset,
+ &ps2dc->parent_reset);
+}
+
static const TypeInfo ps2_mouse_info = {
.name = TYPE_PS2_MOUSE_DEVICE,
.parent= TYPE_PS2_DEVICE,
.instance_size = sizeof(PS2MouseState),
+.class_init= ps2_mouse_class_init
};
static void ps2_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+dc->reset = ps2_reset;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
diff --git a/include/hw/input/ps2.h b/include/hw/input/ps2.h
index aef892b5e6..4be27de316 100644
--- a/include/hw/input/ps2.h
+++ b/include/hw/input/ps2.h
@@ -35,6 +35,8 @@
struct PS2DeviceClass {
SysBusDeviceClass parent_class;
+
+DeviceReset parent_reset;
};
/*
--
2.30.2
[PULL 00/55] qemu-sparc queue 20220626
The following changes since commit 40d522490714b65e0856444277db6c14c5cc3796: Merge tag 'for-upstream' of git://repo.or.cz/qemu/kevin into staging (2022-06-24 10:52:46 -0700) are available in the Git repository at: https://github.com/mcayland/qemu.git tags/qemu-sparc-20220626 for you to fetch changes up to 39fbaeca096a9bf6cbe2af88572c1cb2aa62aa8c: artist: set memory region owners for buffers to the artist device (2022-06-26 18:40:28 +0100) qemu-sparc queue - This is the PS2 QOM part 1 series, along with the trivial artist patch Mark Cave-Ayland (55): ps2: checkpatch fixes ps2: QOMify PS2State ps2: QOMify PS2KbdState ps2: QOMify PS2MouseState ps2: move QOM type definitions from ps2.c to ps2.h ps2: improve function prototypes in ps2.c and ps2.h ps2: introduce PS2DeviceClass ps2: implement ps2_reset() for the PS2_DEVICE QOM type based upon ps2_common_reset() ps2: remove duplicate setting of scancode_set in ps2_kbd_init() ps2: implement ps2_kbd_realize() and use it to register ps2_keyboard_handler ps2: implement ps2_mouse_realize() and use it to register ps2_mouse_handler ps2: don't use vmstate_register() in ps2_kbd_init() ps2: don't use vmstate_register() in ps2_mouse_init() pl050: checkpatch fixes pl050: split pl050_update_irq() into separate pl050_set_irq() and pl050_update_irq() functions lasips2: spacing fixes lasips2: rename ps2dev_update_irq() to lasips2_port_set_irq() pckbd: checkpatch fixes pckbd: move KBDState from pckbd.c to i8042.h pckbd: move ISAKBDState from pckbd.c to i8042.h pckbd: introduce new I8042_MMIO QOM type pckbd: implement i8042_mmio_reset() for I8042_MMIO device pckbd: add mask qdev property to I8042_MMIO device pckbd: add size qdev property to I8042_MMIO device pckbd: implement i8042_mmio_realize() function pckbd: implement i8042_mmio_init() function pckbd: alter i8042_mm_init() to return a I8042_MMIO device pckbd: move mapping of I8042_MMIO registers to MIPS magnum machine pckbd: more vmstate_register() from i8042_mm_init() to i8042_mmio_realize() pckbd: move ps2_kbd_init() and ps2_mouse_init() to i8042_mmio_realize() ps2: make ps2_raise_irq() function static ps2: use ps2_raise_irq() instead of calling update_irq() directly ps2: introduce ps2_lower_irq() instead of calling update_irq() directly ps2: add gpio for output IRQ and optionally use it in ps2_raise_irq() and ps2_lower_irq() pckbd: replace irq_kbd and irq_mouse with qemu_irq array in KBDState pl050: switch over from update_irq() function to PS2 device gpio pl050: add QEMU interface comment lasips2: QOMify LASIPS2State lasips2: move lasips2 QOM types from lasips2.c to lasips2.h lasips2: rename lasips2_init() to lasips2_initfn() and update it to return the LASIPS2 device lasips2: implement lasips2_init() function lasips2: move mapping of LASIPS2 registers to HPPA machine lasips2: move initialisation of PS2 ports from lasi_initfn() to lasi_init() lasips2: add base property lasips2: implement lasips2_realize() lasips2: use sysbus IRQ for output IRQ lasips2: switch over from update_irq() function to PS2 device gpio lasips2: add QEMU interface comment pckbd: switch I8042_MMIO device from update_irq() function to PS2 device gpio pckbd: add QEMU interface comment for I8042_MMIO device pckbd: add i8042_reset() function to I8042 device pckbd: switch I8042 device from update_irq() function to PS2 device gpio pckbd: add QEMU interface comment for I8042 device ps2: remove update_irq() function and update_arg parameter artist: set memory region owners for buffers to the artist device hw/display/artist.c| 2 +- hw/hppa/machine.c | 11 +- hw/input/lasips2.c | 123 +++ hw/input/pckbd.c | 338 -- hw/input/pl050.c | 56 +++-- hw/input/ps2.c | 501 ++--- hw/mips/jazz.c | 11 +- include/hw/input/i8042.h | 75 ++- include/hw/input/lasips2.h | 39 +++- include/hw/input/ps2.h | 79 ++- 10 files changed, 846 insertions(+), 389 deletions(-)
[PULL 04/55] ps2: QOMify PS2MouseState
Make PS2MouseState into a new PS2_MOUSE_DEVICE QOM type which inherits from the
abstract PS2_DEVICE type.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-5-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 98 ++
1 file changed, 60 insertions(+), 38 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 14eb777c3f..ee7c36d4f2 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -123,8 +123,9 @@ struct PS2KbdState {
#define TYPE_PS2_KBD_DEVICE "ps2-kbd"
OBJECT_DECLARE_SIMPLE_TYPE(PS2KbdState, PS2_KBD_DEVICE)
-typedef struct {
-PS2State common;
+struct PS2MouseState {
+PS2State parent_obj;
+
uint8_t mouse_status;
uint8_t mouse_resolution;
uint8_t mouse_sample_rate;
@@ -136,7 +137,10 @@ typedef struct {
int mouse_dz;
int mouse_dw;
uint8_t mouse_buttons;
-} PS2MouseState;
+};
+
+#define TYPE_PS2_MOUSE_DEVICE "ps2-mouse"
+OBJECT_DECLARE_SIMPLE_TYPE(PS2MouseState, PS2_MOUSE_DEVICE)
static uint8_t translate_table[256] = {
0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58,
@@ -735,12 +739,13 @@ void ps2_keyboard_set_translation(void *opaque, int mode)
static int ps2_mouse_send_packet(PS2MouseState *s)
{
+PS2State *ps2 = PS2_DEVICE(s);
/* IMPS/2 and IMEX send 4 bytes, PS2 sends 3 bytes */
const int needed = s->mouse_type ? 4 : 3;
unsigned int b;
int dx1, dy1, dz1, dw1;
-if (PS2_QUEUE_SIZE - s->common.queue.count < needed) {
+if (PS2_QUEUE_SIZE - ps2->queue.count < needed) {
return 0;
}
@@ -760,9 +765,9 @@ static int ps2_mouse_send_packet(PS2MouseState *s)
dy1 = -127;
}
b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07);
-ps2_queue_noirq(&s->common, b);
-ps2_queue_noirq(&s->common, dx1 & 0xff);
-ps2_queue_noirq(&s->common, dy1 & 0xff);
+ps2_queue_noirq(ps2, b);
+ps2_queue_noirq(ps2, dx1 & 0xff);
+ps2_queue_noirq(ps2, dy1 & 0xff);
/* extra byte for IMPS/2 or IMEX */
switch (s->mouse_type) {
default:
@@ -776,7 +781,7 @@ static int ps2_mouse_send_packet(PS2MouseState *s)
} else if (dz1 < -127) {
dz1 = -127;
}
-ps2_queue_noirq(&s->common, dz1 & 0xff);
+ps2_queue_noirq(ps2, dz1 & 0xff);
s->mouse_dz -= dz1;
s->mouse_dw = 0;
break;
@@ -812,11 +817,11 @@ static int ps2_mouse_send_packet(PS2MouseState *s)
b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1);
s->mouse_dz -= dz1;
}
-ps2_queue_noirq(&s->common, b);
+ps2_queue_noirq(ps2, b);
break;
}
-ps2_raise_irq(&s->common);
+ps2_raise_irq(ps2);
trace_ps2_mouse_send_packet(s, dx1, dy1, dz1, b);
/* update deltas */
@@ -918,85 +923,86 @@ void ps2_mouse_fake_event(void *opaque)
void ps2_write_mouse(void *opaque, int val)
{
PS2MouseState *s = (PS2MouseState *)opaque;
+PS2State *ps2 = PS2_DEVICE(s);
trace_ps2_write_mouse(opaque, val);
-switch (s->common.write_cmd) {
+switch (ps2->write_cmd) {
default:
case -1:
/* mouse command */
if (s->mouse_wrap) {
if (val == AUX_RESET_WRAP) {
s->mouse_wrap = 0;
-ps2_queue(&s->common, AUX_ACK);
+ps2_queue(ps2, AUX_ACK);
return;
} else if (val != AUX_RESET) {
-ps2_queue(&s->common, val);
+ps2_queue(ps2, val);
return;
}
}
switch (val) {
case AUX_SET_SCALE11:
s->mouse_status &= ~MOUSE_STATUS_SCALE21;
-ps2_queue(&s->common, AUX_ACK);
+ps2_queue(ps2, AUX_ACK);
break;
case AUX_SET_SCALE21:
s->mouse_status |= MOUSE_STATUS_SCALE21;
-ps2_queue(&s->common, AUX_ACK);
+ps2_queue(ps2, AUX_ACK);
break;
case AUX_SET_STREAM:
s->mouse_status &= ~MOUSE_STATUS_REMOTE;
-ps2_queue(&s->common, AUX_ACK);
+ps2_queue(ps2, AUX_ACK);
break;
case AUX_SET_WRAP:
s->mouse_wrap = 1;
-ps2_queue(&s->common, AUX_ACK);
+ps2_queue(ps2, AUX_ACK);
break;
case AUX_SET_REMOTE:
s->mouse_status |= MOUSE_STATUS_REMOTE;
-ps2_queue(&s->common, AUX_ACK);
+ps2_queue(ps2, AUX_ACK);
break;
case AUX_GET_TYPE:
-ps2_queue_2(&s->common,
+ps2_queue_2(ps2,
AUX_ACK,
s->mouse_type);
break;
case AUX_SET_RES:
case AUX_SET_SAMPLE:
-s->common.write_cmd = val;
-ps2_queue(&s->common, AUX_ACK);
+ps2->write_cmd = val;
+ps2_queue(ps2, AUX_ACK);
break;
case AUX
[PULL 01/55] ps2: checkpatch fixes
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-2-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 154 +++--
1 file changed, 86 insertions(+), 68 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index c16df1de7a..67dd2eca84 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -34,41 +34,41 @@
#include "trace.h"
/* Keyboard Commands */
-#define KBD_CMD_SET_LEDS 0xED/* Set keyboard leds */
-#define KBD_CMD_ECHO 0xEE
-#define KBD_CMD_SCANCODE 0xF0/* Get/set scancode set */
-#define KBD_CMD_GET_ID 0xF2/* get keyboard ID */
-#define KBD_CMD_SET_RATE 0xF3/* Set typematic rate */
-#define KBD_CMD_ENABLE 0xF4/* Enable scanning */
-#define KBD_CMD_RESET_DISABLE 0xF5/* reset and disable scanning */
-#define KBD_CMD_RESET_ENABLE 0xF6/* reset and enable scanning */
-#define KBD_CMD_RESET 0xFF/* Reset */
+#define KBD_CMD_SET_LEDS0xED/* Set keyboard leds */
+#define KBD_CMD_ECHO0xEE
+#define KBD_CMD_SCANCODE0xF0/* Get/set scancode set */
+#define KBD_CMD_GET_ID 0xF2/* get keyboard ID */
+#define KBD_CMD_SET_RATE0xF3/* Set typematic rate */
+#define KBD_CMD_ENABLE 0xF4/* Enable scanning */
+#define KBD_CMD_RESET_DISABLE 0xF5/* reset and disable scanning */
+#define KBD_CMD_RESET_ENABLE0xF6/* reset and enable scanning */
+#define KBD_CMD_RESET 0xFF/* Reset */
#define KBD_CMD_SET_MAKE_BREAK 0xFC/* Set Make and Break mode */
#define KBD_CMD_SET_TYPEMATIC 0xFA/* Set Typematic Make and Break mode */
/* Keyboard Replies */
-#define KBD_REPLY_POR 0xAA/* Power on reset */
-#define KBD_REPLY_ID 0xAB/* Keyboard ID */
-#define KBD_REPLY_ACK 0xFA/* Command ACK */
-#define KBD_REPLY_RESEND 0xFE/* Command NACK, send the cmd again */
+#define KBD_REPLY_POR 0xAA/* Power on reset */
+#define KBD_REPLY_ID0xAB/* Keyboard ID */
+#define KBD_REPLY_ACK 0xFA/* Command ACK */
+#define KBD_REPLY_RESEND0xFE/* Command NACK, send the cmd again */
/* Mouse Commands */
-#define AUX_SET_SCALE110xE6/* Set 1:1 scaling */
-#define AUX_SET_SCALE210xE7/* Set 2:1 scaling */
-#define AUX_SET_RES0xE8/* Set resolution */
-#define AUX_GET_SCALE 0xE9/* Get scaling factor */
-#define AUX_SET_STREAM 0xEA/* Set stream mode */
-#define AUX_POLL 0xEB/* Poll */
-#define AUX_RESET_WRAP 0xEC/* Reset wrap mode */
-#define AUX_SET_WRAP 0xEE/* Set wrap mode */
-#define AUX_SET_REMOTE 0xF0/* Set remote mode */
-#define AUX_GET_TYPE 0xF2/* Get type */
-#define AUX_SET_SAMPLE 0xF3/* Set sample rate */
-#define AUX_ENABLE_DEV 0xF4/* Enable aux device */
-#define AUX_DISABLE_DEV0xF5/* Disable aux device */
-#define AUX_SET_DEFAULT0xF6
-#define AUX_RESET 0xFF/* Reset aux device */
-#define AUX_ACK0xFA/* Command byte ACK. */
+#define AUX_SET_SCALE11 0xE6/* Set 1:1 scaling */
+#define AUX_SET_SCALE21 0xE7/* Set 2:1 scaling */
+#define AUX_SET_RES 0xE8/* Set resolution */
+#define AUX_GET_SCALE 0xE9/* Get scaling factor */
+#define AUX_SET_STREAM 0xEA/* Set stream mode */
+#define AUX_POLL0xEB/* Poll */
+#define AUX_RESET_WRAP 0xEC/* Reset wrap mode */
+#define AUX_SET_WRAP0xEE/* Set wrap mode */
+#define AUX_SET_REMOTE 0xF0/* Set remote mode */
+#define AUX_GET_TYPE0xF2/* Get type */
+#define AUX_SET_SAMPLE 0xF3/* Set sample rate */
+#define AUX_ENABLE_DEV 0xF4/* Enable aux device */
+#define AUX_DISABLE_DEV 0xF5/* Disable aux device */
+#define AUX_SET_DEFAULT 0xF6
+#define AUX_RESET 0xFF/* Reset aux device */
+#define AUX_ACK 0xFA/* Command byte ACK. */
#define MOUSE_STATUS_REMOTE 0x40
#define MOUSE_STATUS_ENABLED0x20
@@ -436,8 +436,9 @@ static void ps2_keyboard_event(DeviceState *dev,
QemuConsole *src,
}
}
} else {
-if (qcode < qemu_input_map_qcode_to_atset1_len)
+if (qcode < qemu_input_map_qcode_to_atset1_len) {
keycode = qemu_input_map_qcode_to_atset1[qcode];
+}
if (keycode) {
if (keycode & 0xff00) {
ps2_put_keycode(s, keycode >> 8);
@@ -530,8 +531,9 @@ static void ps2_keyboard_event(DeviceState *dev,
QemuConsole *src,
}
}
} else {
-if (qcode < qemu_input_map_qcode_to_atset2_len)
+if (qcode < qemu_
[PULL 03/55] ps2: QOMify PS2KbdState
Make PS2KbdState into a new PS2_KBD_DEVICE QOM type which inherits from the
abstract PS2_DEVICE type.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-4-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 104 ++---
1 file changed, 65 insertions(+), 39 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 514e55cbb6..14eb777c3f 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -31,6 +31,7 @@
#include "ui/input.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
+#include "qapi/error.h"
#include "trace.h"
@@ -108,15 +109,19 @@ struct PS2State {
#define TYPE_PS2_DEVICE "ps2-device"
OBJECT_DECLARE_SIMPLE_TYPE(PS2State, PS2_DEVICE)
-typedef struct {
-PS2State common;
+struct PS2KbdState {
+PS2State parent_obj;
+
int scan_enabled;
int translate;
int scancode_set; /* 1=XT, 2=AT, 3=PS/2 */
int ledstate;
bool need_high_bit;
unsigned int modifiers; /* bitmask of MOD_* constants above */
-} PS2KbdState;
+};
+
+#define TYPE_PS2_KBD_DEVICE "ps2-kbd"
+OBJECT_DECLARE_SIMPLE_TYPE(PS2KbdState, PS2_KBD_DEVICE)
typedef struct {
PS2State common;
@@ -330,6 +335,7 @@ static void ps2_cqueue_reset(PS2State *s)
static void ps2_put_keycode(void *opaque, int keycode)
{
PS2KbdState *s = opaque;
+PS2State *ps = PS2_DEVICE(s);
trace_ps2_put_keycode(opaque, keycode);
qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER, NULL);
@@ -338,13 +344,13 @@ static void ps2_put_keycode(void *opaque, int keycode)
if (keycode == 0xf0) {
s->need_high_bit = true;
} else if (s->need_high_bit) {
-ps2_queue(&s->common, translate_table[keycode] | 0x80);
+ps2_queue(ps, translate_table[keycode] | 0x80);
s->need_high_bit = false;
} else {
-ps2_queue(&s->common, translate_table[keycode]);
+ps2_queue(ps, translate_table[keycode]);
}
} else {
-ps2_queue(&s->common, keycode);
+ps2_queue(ps, keycode);
}
}
@@ -617,96 +623,99 @@ static void ps2_set_ledstate(PS2KbdState *s, int ledstate)
static void ps2_reset_keyboard(PS2KbdState *s)
{
+PS2State *ps2 = PS2_DEVICE(s);
+
trace_ps2_reset_keyboard(s);
s->scan_enabled = 1;
s->scancode_set = 2;
-ps2_reset_queue(&s->common);
+ps2_reset_queue(ps2);
ps2_set_ledstate(s, 0);
}
void ps2_write_keyboard(void *opaque, int val)
{
PS2KbdState *s = (PS2KbdState *)opaque;
+PS2State *ps2 = PS2_DEVICE(s);
trace_ps2_write_keyboard(opaque, val);
-ps2_cqueue_reset(&s->common);
-switch (s->common.write_cmd) {
+ps2_cqueue_reset(ps2);
+switch (ps2->write_cmd) {
default:
case -1:
switch (val) {
case 0x00:
-ps2_cqueue_1(&s->common, KBD_REPLY_ACK);
+ps2_cqueue_1(ps2, KBD_REPLY_ACK);
break;
case 0x05:
-ps2_cqueue_1(&s->common, KBD_REPLY_RESEND);
+ps2_cqueue_1(ps2, KBD_REPLY_RESEND);
break;
case KBD_CMD_GET_ID:
/* We emulate a MF2 AT keyboard here */
-ps2_cqueue_3(&s->common, KBD_REPLY_ACK, KBD_REPLY_ID,
+ps2_cqueue_3(ps2, KBD_REPLY_ACK, KBD_REPLY_ID,
s->translate ? 0x41 : 0x83);
break;
case KBD_CMD_ECHO:
-ps2_cqueue_1(&s->common, KBD_CMD_ECHO);
+ps2_cqueue_1(ps2, KBD_CMD_ECHO);
break;
case KBD_CMD_ENABLE:
s->scan_enabled = 1;
-ps2_cqueue_1(&s->common, KBD_REPLY_ACK);
+ps2_cqueue_1(ps2, KBD_REPLY_ACK);
break;
case KBD_CMD_SCANCODE:
case KBD_CMD_SET_LEDS:
case KBD_CMD_SET_RATE:
case KBD_CMD_SET_MAKE_BREAK:
-s->common.write_cmd = val;
-ps2_cqueue_1(&s->common, KBD_REPLY_ACK);
+ps2->write_cmd = val;
+ps2_cqueue_1(ps2, KBD_REPLY_ACK);
break;
case KBD_CMD_RESET_DISABLE:
ps2_reset_keyboard(s);
s->scan_enabled = 0;
-ps2_cqueue_1(&s->common, KBD_REPLY_ACK);
+ps2_cqueue_1(ps2, KBD_REPLY_ACK);
break;
case KBD_CMD_RESET_ENABLE:
ps2_reset_keyboard(s);
s->scan_enabled = 1;
-ps2_cqueue_1(&s->common, KBD_REPLY_ACK);
+ps2_cqueue_1(ps2, KBD_REPLY_ACK);
break;
case KBD_CMD_RESET:
ps2_reset_keyboard(s);
-ps2_cqueue_2(&s->common,
+ps2_cqueue_2(ps2,
KBD_REPLY_ACK,
KBD_REPLY_POR);
break;
case KBD_CMD_SET_TYPEMATIC:
-ps2_cqueue_1(&s->common, KBD_REPLY_ACK);
+ps2_cqueue_1(ps2, KBD_REPLY_ACK);
break;
default:
-ps2_cqueue_1(&s->common,
[PULL 09/55] ps2: remove duplicate setting of scancode_set in ps2_kbd_init()
The default value for scancode_set is already set in ps2_kbd_reset() so there is no need to duplicate this in ps2_kbd_init(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Acked-by: Helge Deller Message-Id: <20220624134109.881989-10-mark.cave-ayl...@ilande.co.uk> --- hw/input/ps2.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/input/ps2.c b/hw/input/ps2.c index f6f5514f0b..8018e39b17 100644 --- a/hw/input/ps2.c +++ b/hw/input/ps2.c @@ -1227,7 +1227,6 @@ void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg) trace_ps2_kbd_init(s); ps2->update_irq = update_irq; ps2->update_arg = update_arg; -s->scancode_set = 2; vmstate_register(NULL, 0, &vmstate_ps2_keyboard, s); qemu_input_handler_register((DeviceState *)s, &ps2_keyboard_handler); -- 2.30.2
[PULL 10/55] ps2: implement ps2_kbd_realize() and use it to register ps2_keyboard_handler
Move the registration of ps2_keyboard_handler from ps2_kbd_init() to a new
ps2_kbd_realize() function. Since the abstract PS2_DEVICE parent class doesn't
have a realize() function then it is not necessary to store the reference to
it in PS2DeviceClass and use device_class_set_parent_realize().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-11-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 8018e39b17..62ea4c228b 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -1213,6 +1213,11 @@ static QemuInputHandler ps2_keyboard_handler = {
.event = ps2_keyboard_event,
};
+static void ps2_kbd_realize(DeviceState *dev, Error **errp)
+{
+qemu_input_handler_register(dev, &ps2_keyboard_handler);
+}
+
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg)
{
DeviceState *dev;
@@ -1228,8 +1233,7 @@ void *ps2_kbd_init(void (*update_irq)(void *, int), void
*update_arg)
ps2->update_irq = update_irq;
ps2->update_arg = update_arg;
vmstate_register(NULL, 0, &vmstate_ps2_keyboard, s);
-qemu_input_handler_register((DeviceState *)s,
-&ps2_keyboard_handler);
+
return s;
}
@@ -1265,6 +1269,7 @@ static void ps2_kbd_class_init(ObjectClass *klass, void
*data)
DeviceClass *dc = DEVICE_CLASS(klass);
PS2DeviceClass *ps2dc = PS2_DEVICE_CLASS(klass);
+dc->realize = ps2_kbd_realize;
device_class_set_parent_reset(dc, ps2_kbd_reset, &ps2dc->parent_reset);
}
--
2.30.2
[PULL 06/55] ps2: improve function prototypes in ps2.c and ps2.h
With the latest changes it is now possible to improve some of the function
prototypes in ps2.c and ps.h to use the appropriate PS2KbdState or
PS2MouseState type instead of being a void opaque.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-7-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 22 +-
include/hw/input/ps2.h | 8
2 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index f4bad9876a..3a770f3b78 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -581,12 +581,11 @@ static void ps2_reset_keyboard(PS2KbdState *s)
ps2_set_ledstate(s, 0);
}
-void ps2_write_keyboard(void *opaque, int val)
+void ps2_write_keyboard(PS2KbdState *s, int val)
{
-PS2KbdState *s = (PS2KbdState *)opaque;
PS2State *ps2 = PS2_DEVICE(s);
-trace_ps2_write_keyboard(opaque, val);
+trace_ps2_write_keyboard(s, val);
ps2_cqueue_reset(ps2);
switch (ps2->write_cmd) {
default:
@@ -675,10 +674,9 @@ void ps2_write_keyboard(void *opaque, int val)
* 1 = translated scancodes (used by qemu internally).
*/
-void ps2_keyboard_set_translation(void *opaque, int mode)
+void ps2_keyboard_set_translation(PS2KbdState *s, int mode)
{
-PS2KbdState *s = (PS2KbdState *)opaque;
-trace_ps2_keyboard_set_translation(opaque, mode);
+trace_ps2_keyboard_set_translation(s, mode);
s->translate = mode;
}
@@ -857,20 +855,18 @@ static void ps2_mouse_sync(DeviceState *dev)
}
}
-void ps2_mouse_fake_event(void *opaque)
+void ps2_mouse_fake_event(PS2MouseState *s)
{
-PS2MouseState *s = opaque;
-trace_ps2_mouse_fake_event(opaque);
+trace_ps2_mouse_fake_event(s);
s->mouse_dx++;
-ps2_mouse_sync(opaque);
+ps2_mouse_sync(DEVICE(s));
}
-void ps2_write_mouse(void *opaque, int val)
+void ps2_write_mouse(PS2MouseState *s, int val)
{
-PS2MouseState *s = (PS2MouseState *)opaque;
PS2State *ps2 = PS2_DEVICE(s);
-trace_ps2_write_mouse(opaque, val);
+trace_ps2_write_mouse(s, val);
switch (ps2->write_cmd) {
default:
case -1:
diff --git a/include/hw/input/ps2.h b/include/hw/input/ps2.h
index 7f2c3f6090..1a3321d77e 100644
--- a/include/hw/input/ps2.h
+++ b/include/hw/input/ps2.h
@@ -92,8 +92,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(PS2MouseState, PS2_MOUSE_DEVICE)
/* ps2.c */
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
-void ps2_write_mouse(void *, int val);
-void ps2_write_keyboard(void *, int val);
+void ps2_write_mouse(PS2MouseState *s, int val);
+void ps2_write_keyboard(PS2KbdState *s, int val);
uint32_t ps2_read_data(PS2State *s);
void ps2_queue_noirq(PS2State *s, int b);
void ps2_raise_irq(PS2State *s);
@@ -101,8 +101,8 @@ void ps2_queue(PS2State *s, int b);
void ps2_queue_2(PS2State *s, int b1, int b2);
void ps2_queue_3(PS2State *s, int b1, int b2, int b3);
void ps2_queue_4(PS2State *s, int b1, int b2, int b3, int b4);
-void ps2_keyboard_set_translation(void *opaque, int mode);
-void ps2_mouse_fake_event(void *opaque);
+void ps2_keyboard_set_translation(PS2KbdState *s, int mode);
+void ps2_mouse_fake_event(PS2MouseState *s);
int ps2_queue_empty(PS2State *s);
#endif /* HW_PS2_H */
--
2.30.2
[PULL 23/55] pckbd: add mask qdev property to I8042_MMIO device
This allows the KBDState mask value to be set using a qdev property rather
than directly in i8042_mm_init().
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-24-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 7b520d0eb4..c04a2c587e 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -673,11 +673,17 @@ static void i8042_mmio_reset(DeviceState *dev)
kbd_reset(ks);
}
+static Property i8042_mmio_properties[] = {
+DEFINE_PROP_UINT64("mask", MMIOKBDState, kbd.mask, UINT64_MAX),
+DEFINE_PROP_END_OF_LIST(),
+};
+
static void i8042_mmio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = i8042_mmio_reset;
+device_class_set_props(dc, i8042_mmio_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
@@ -689,12 +695,12 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
KBDState *s;
dev = qdev_new(TYPE_I8042_MMIO);
+qdev_prop_set_uint64(dev, "mask", mask);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s = &I8042_MMIO(dev)->kbd;
s->irq_kbd = kbd_irq;
s->irq_mouse = mouse_irq;
-s->mask = mask;
s->extended_state = true;
--
2.30.2
[PULL 14/55] pl050: checkpatch fixes
This patch also includes a couple of minor spacing updates.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-15-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pl050.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/hw/input/pl050.c b/hw/input/pl050.c
index d279b6c148..889a0674d3 100644
--- a/hw/input/pl050.c
+++ b/hw/input/pl050.c
@@ -53,8 +53,9 @@ static const VMStateDescription vmstate_pl050 = {
#define PL050_KMIC(1 << 1)
#define PL050_KMID(1 << 0)
-static const unsigned char pl050_id[] =
-{ 0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
+static const unsigned char pl050_id[] = {
+0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
+};
static void pl050_update(void *opaque, int level)
{
@@ -71,8 +72,10 @@ static uint64_t pl050_read(void *opaque, hwaddr offset,
unsigned size)
{
PL050State *s = (PL050State *)opaque;
-if (offset >= 0xfe0 && offset < 0x1000)
+
+if (offset >= 0xfe0 && offset < 0x1000) {
return pl050_id[(offset - 0xfe0) >> 2];
+}
switch (offset >> 2) {
case 0: /* KMICR */
@@ -88,16 +91,19 @@ static uint64_t pl050_read(void *opaque, hwaddr offset,
val = (val ^ (val >> 1)) & 1;
stat = PL050_TXEMPTY;
-if (val)
+if (val) {
stat |= PL050_RXPARITY;
-if (s->pending)
+}
+if (s->pending) {
stat |= PL050_RXFULL;
+}
return stat;
}
case 2: /* KMIDATA */
-if (s->pending)
+if (s->pending) {
s->last = ps2_read_data(s->dev);
+}
return s->last;
case 3: /* KMICLKDIV */
return s->clk;
@@ -114,6 +120,7 @@ static void pl050_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PL050State *s = (PL050State *)opaque;
+
switch (offset >> 2) {
case 0: /* KMICR */
s->cr = value;
--
2.30.2
[PULL 05/55] ps2: move QOM type definitions from ps2.c to ps2.h
Move the QOM type definitions into the ps2.h header file to allow the new QOM
types to be used by other devices.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-6-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 55 ---
include/hw/input/ps2.h | 58 +-
2 files changed, 57 insertions(+), 56 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index ee7c36d4f2..f4bad9876a 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -76,11 +76,6 @@
#define MOUSE_STATUS_ENABLED0x20
#define MOUSE_STATUS_SCALE210x10
-/*
- * PS/2 buffer size. Keep 256 bytes for compatibility with
- * older QEMU versions.
- */
-#define PS2_BUFFER_SIZE 256
#define PS2_QUEUE_SIZE 16 /* Queue size required by PS/2 protocol */
#define PS2_QUEUE_HEADROOM 8 /* Queue size for keyboard command replies */
@@ -92,56 +87,6 @@
#define MOD_SHIFT_R (1 << 4)
#define MOD_ALT_R (1 << 5)
-typedef struct {
-uint8_t data[PS2_BUFFER_SIZE];
-int rptr, wptr, cwptr, count;
-} PS2Queue;
-
-struct PS2State {
-SysBusDevice parent_obj;
-
-PS2Queue queue;
-int32_t write_cmd;
-void (*update_irq)(void *, int);
-void *update_arg;
-};
-
-#define TYPE_PS2_DEVICE "ps2-device"
-OBJECT_DECLARE_SIMPLE_TYPE(PS2State, PS2_DEVICE)
-
-struct PS2KbdState {
-PS2State parent_obj;
-
-int scan_enabled;
-int translate;
-int scancode_set; /* 1=XT, 2=AT, 3=PS/2 */
-int ledstate;
-bool need_high_bit;
-unsigned int modifiers; /* bitmask of MOD_* constants above */
-};
-
-#define TYPE_PS2_KBD_DEVICE "ps2-kbd"
-OBJECT_DECLARE_SIMPLE_TYPE(PS2KbdState, PS2_KBD_DEVICE)
-
-struct PS2MouseState {
-PS2State parent_obj;
-
-uint8_t mouse_status;
-uint8_t mouse_resolution;
-uint8_t mouse_sample_rate;
-uint8_t mouse_wrap;
-uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
-uint8_t mouse_detect_state;
-int mouse_dx; /* current values, needed for 'poll' mode */
-int mouse_dy;
-int mouse_dz;
-int mouse_dw;
-uint8_t mouse_buttons;
-};
-
-#define TYPE_PS2_MOUSE_DEVICE "ps2-mouse"
-OBJECT_DECLARE_SIMPLE_TYPE(PS2MouseState, PS2_MOUSE_DEVICE)
-
static uint8_t translate_table[256] = {
0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58,
0x64, 0x44, 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59,
diff --git a/include/hw/input/ps2.h b/include/hw/input/ps2.h
index 35d983897a..7f2c3f6090 100644
--- a/include/hw/input/ps2.h
+++ b/include/hw/input/ps2.h
@@ -25,13 +25,69 @@
#ifndef HW_PS2_H
#define HW_PS2_H
+#include "hw/sysbus.h"
+
#define PS2_MOUSE_BUTTON_LEFT 0x01
#define PS2_MOUSE_BUTTON_RIGHT 0x02
#define PS2_MOUSE_BUTTON_MIDDLE 0x04
#define PS2_MOUSE_BUTTON_SIDE 0x08
#define PS2_MOUSE_BUTTON_EXTRA 0x10
-typedef struct PS2State PS2State;
+/*
+ * PS/2 buffer size. Keep 256 bytes for compatibility with
+ * older QEMU versions.
+ */
+#define PS2_BUFFER_SIZE 256
+
+typedef struct {
+uint8_t data[PS2_BUFFER_SIZE];
+int rptr, wptr, cwptr, count;
+} PS2Queue;
+
+struct PS2State {
+SysBusDevice parent_obj;
+
+PS2Queue queue;
+int32_t write_cmd;
+void (*update_irq)(void *, int);
+void *update_arg;
+};
+
+#define TYPE_PS2_DEVICE "ps2-device"
+OBJECT_DECLARE_SIMPLE_TYPE(PS2State, PS2_DEVICE)
+
+struct PS2KbdState {
+PS2State parent_obj;
+
+int scan_enabled;
+int translate;
+int scancode_set; /* 1=XT, 2=AT, 3=PS/2 */
+int ledstate;
+bool need_high_bit;
+unsigned int modifiers; /* bitmask of MOD_* constants above */
+};
+
+#define TYPE_PS2_KBD_DEVICE "ps2-kbd"
+OBJECT_DECLARE_SIMPLE_TYPE(PS2KbdState, PS2_KBD_DEVICE)
+
+struct PS2MouseState {
+PS2State parent_obj;
+
+uint8_t mouse_status;
+uint8_t mouse_resolution;
+uint8_t mouse_sample_rate;
+uint8_t mouse_wrap;
+uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
+uint8_t mouse_detect_state;
+int mouse_dx; /* current values, needed for 'poll' mode */
+int mouse_dy;
+int mouse_dz;
+int mouse_dw;
+uint8_t mouse_buttons;
+};
+
+#define TYPE_PS2_MOUSE_DEVICE "ps2-mouse"
+OBJECT_DECLARE_SIMPLE_TYPE(PS2MouseState, PS2_MOUSE_DEVICE)
/* ps2.c */
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
--
2.30.2
[PULL 07/55] ps2: introduce PS2DeviceClass
This is in preparation for allowing the new PS2_KBD_DEVICE and PS2_MOUSE_DEVICE
QOM types to reference the parent PS2_DEVICE device reset() function.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-8-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 1 +
include/hw/input/ps2.h | 6 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 3a770f3b78..fd5236690a 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -1283,6 +1283,7 @@ static const TypeInfo ps2_info = {
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PS2State),
.class_init= ps2_class_init,
+.class_size= sizeof(PS2DeviceClass),
.abstract = true
};
diff --git a/include/hw/input/ps2.h b/include/hw/input/ps2.h
index 1a3321d77e..aef892b5e6 100644
--- a/include/hw/input/ps2.h
+++ b/include/hw/input/ps2.h
@@ -33,6 +33,10 @@
#define PS2_MOUSE_BUTTON_SIDE 0x08
#define PS2_MOUSE_BUTTON_EXTRA 0x10
+struct PS2DeviceClass {
+SysBusDeviceClass parent_class;
+};
+
/*
* PS/2 buffer size. Keep 256 bytes for compatibility with
* older QEMU versions.
@@ -54,7 +58,7 @@ struct PS2State {
};
#define TYPE_PS2_DEVICE "ps2-device"
-OBJECT_DECLARE_SIMPLE_TYPE(PS2State, PS2_DEVICE)
+OBJECT_DECLARE_TYPE(PS2State, PS2DeviceClass, PS2_DEVICE)
struct PS2KbdState {
PS2State parent_obj;
--
2.30.2
[PULL 15/55] pl050: split pl050_update_irq() into separate pl050_set_irq() and pl050_update_irq() functions
This will soon allow pl050_set_irq() to be used as a GPIO input function.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-16-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pl050.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/hw/input/pl050.c b/hw/input/pl050.c
index 889a0674d3..66f8c20d9f 100644
--- a/hw/input/pl050.c
+++ b/hw/input/pl050.c
@@ -57,15 +57,20 @@ static const unsigned char pl050_id[] = {
0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
};
-static void pl050_update(void *opaque, int level)
+static void pl050_update_irq(PL050State *s)
+{
+int level = (s->pending && (s->cr & 0x10) != 0)
+ || (s->cr & 0x08) != 0;
+
+qemu_set_irq(s->irq, level);
+}
+
+static void pl050_set_irq(void *opaque, int level)
{
PL050State *s = (PL050State *)opaque;
-int raise;
s->pending = level;
-raise = (s->pending && (s->cr & 0x10) != 0)
-|| (s->cr & 0x08) != 0;
-qemu_set_irq(s->irq, raise);
+pl050_update_irq(s);
}
static uint64_t pl050_read(void *opaque, hwaddr offset,
@@ -124,7 +129,7 @@ static void pl050_write(void *opaque, hwaddr offset,
switch (offset >> 2) {
case 0: /* KMICR */
s->cr = value;
-pl050_update(s, s->pending);
+pl050_update_irq(s);
/* ??? Need to implement the enable/disable bit. */
break;
case 2: /* KMIDATA */
@@ -159,9 +164,9 @@ static void pl050_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
if (s->is_mouse) {
-s->dev = ps2_mouse_init(pl050_update, s);
+s->dev = ps2_mouse_init(pl050_set_irq, s);
} else {
-s->dev = ps2_kbd_init(pl050_update, s);
+s->dev = ps2_kbd_init(pl050_set_irq, s);
}
}
--
2.30.2
[PULL 22/55] pckbd: implement i8042_mmio_reset() for I8042_MMIO device
This allows the I8042_MMIO reset function to be registered directly within the
DeviceClass rather than using qemu_register_reset() directly.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-23-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Peter Maydell
---
hw/input/pckbd.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 89a41ed566..7b520d0eb4 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -665,10 +665,19 @@ static const MemoryRegionOps i8042_mmio_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void i8042_mmio_reset(DeviceState *dev)
+{
+MMIOKBDState *s = I8042_MMIO(dev);
+KBDState *ks = &s->kbd;
+
+kbd_reset(ks);
+}
+
static void i8042_mmio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+dc->reset = i8042_mmio_reset;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
@@ -695,7 +704,6 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
-qemu_register_reset(kbd_reset, s);
}
static const TypeInfo i8042_mmio_info = {
--
2.30.2
[PULL 12/55] ps2: don't use vmstate_register() in ps2_kbd_init()
Since PS2_KBD_DEVICE is a qdev device then vmstate_ps2_keyboard can be
registered
using the DeviceClass vmsd field instead. There is no need to use
qdev_set_legacy_instance_id() to ensure migration compatibility since the first
2
parameters to vmstate_register() are NULL and 0 respectively.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-13-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index eae7df2096..97e9172ba5 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -1232,7 +1232,6 @@ void *ps2_kbd_init(void (*update_irq)(void *, int), void
*update_arg)
trace_ps2_kbd_init(s);
ps2->update_irq = update_irq;
ps2->update_arg = update_arg;
-vmstate_register(NULL, 0, &vmstate_ps2_keyboard, s);
return s;
}
@@ -1274,6 +1273,7 @@ static void ps2_kbd_class_init(ObjectClass *klass, void
*data)
dc->realize = ps2_kbd_realize;
device_class_set_parent_reset(dc, ps2_kbd_reset, &ps2dc->parent_reset);
+dc->vmsd = &vmstate_ps2_keyboard;
}
static const TypeInfo ps2_kbd_info = {
--
2.30.2
[PULL 26/55] pckbd: implement i8042_mmio_init() function
This enables use to set the required value of extended_state directly during
device init rather than in i8042_mm_init().
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-27-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Peter Maydell
---
hw/input/pckbd.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index bc51f7eedd..b8623d2f9a 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -684,6 +684,14 @@ static void i8042_mmio_realize(DeviceState *dev, Error
**errp)
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->region);
}
+static void i8042_mmio_init(Object *obj)
+{
+MMIOKBDState *s = I8042_MMIO(obj);
+KBDState *ks = &s->kbd;
+
+ks->extended_state = true;
+}
+
static Property i8042_mmio_properties[] = {
DEFINE_PROP_UINT64("mask", MMIOKBDState, kbd.mask, UINT64_MAX),
DEFINE_PROP_UINT32("size", MMIOKBDState, size, -1),
@@ -716,8 +724,6 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
s->irq_kbd = kbd_irq;
s->irq_mouse = mouse_irq;
-s->extended_state = true;
-
vmstate_register(NULL, 0, &vmstate_kbd, s);
region = &I8042_MMIO(dev)->region;
@@ -729,6 +735,7 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
static const TypeInfo i8042_mmio_info = {
.name = TYPE_I8042_MMIO,
.parent= TYPE_SYS_BUS_DEVICE,
+.instance_init = i8042_mmio_init,
.instance_size = sizeof(MMIOKBDState),
.class_init= i8042_mmio_class_init
};
--
2.30.2
[PULL 16/55] lasips2: spacing fixes
This helps improve the readability of lasips2.c.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-17-mark.cave-ayl...@ilande.co.uk>
---
hw/input/lasips2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index 94f18be4cd..2ac3433014 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -205,7 +205,6 @@ static uint64_t lasips2_reg_read(void *opaque, hwaddr addr,
unsigned size)
break;
case REG_PS2_STATUS:
-
ret = LASIPS2_STATUS_DATSHD | LASIPS2_STATUS_CLKSHD;
if (port->control & LASIPS2_CONTROL_DIAG) {
@@ -238,9 +237,9 @@ static uint64_t lasips2_reg_read(void *opaque, hwaddr addr,
unsigned size)
__func__, addr);
break;
}
+
trace_lasips2_reg_read(size, port->id, addr,
lasips2_read_reg_name(addr), ret);
-
return ret;
}
@@ -257,6 +256,7 @@ static const MemoryRegionOps lasips2_reg_ops = {
static void ps2dev_update_irq(void *opaque, int level)
{
LASIPS2Port *port = opaque;
+
port->irq = level;
lasips2_update_irq(port->parent);
}
--
2.30.2
[PULL 19/55] pckbd: move KBDState from pckbd.c to i8042.h
This allows the QOM types in pckbd.c to be used elsewhere by simply including
i8042.h.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-20-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 24
include/hw/input/i8042.h | 25 +
2 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index c18a1a7fae..7b14cd007e 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -146,30 +146,6 @@
#define KBD_OBSRC_MOUSE 0x02
#define KBD_OBSRC_CTRL 0x04
-typedef struct KBDState {
-uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
-uint8_t status;
-uint8_t mode;
-uint8_t outport;
-uint32_t migration_flags;
-uint32_t obsrc;
-bool outport_present;
-bool extended_state;
-bool extended_state_loaded;
-/* Bitmask of devices with data available. */
-uint8_t pending;
-uint8_t obdata;
-uint8_t cbdata;
-uint8_t pending_tmp;
-void *kbd;
-void *mouse;
-QEMUTimer *throttle_timer;
-
-qemu_irq irq_kbd;
-qemu_irq irq_mouse;
-qemu_irq a20_out;
-hwaddr mask;
-} KBDState;
/*
* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
diff --git a/include/hw/input/i8042.h b/include/hw/input/i8042.h
index e070f546e4..84b5aa7f23 100644
--- a/include/hw/input/i8042.h
+++ b/include/hw/input/i8042.h
@@ -11,6 +11,31 @@
#include "hw/isa/isa.h"
#include "qom/object.h"
+typedef struct KBDState {
+uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
+uint8_t status;
+uint8_t mode;
+uint8_t outport;
+uint32_t migration_flags;
+uint32_t obsrc;
+bool outport_present;
+bool extended_state;
+bool extended_state_loaded;
+/* Bitmask of devices with data available. */
+uint8_t pending;
+uint8_t obdata;
+uint8_t cbdata;
+uint8_t pending_tmp;
+void *kbd;
+void *mouse;
+QEMUTimer *throttle_timer;
+
+qemu_irq irq_kbd;
+qemu_irq irq_mouse;
+qemu_irq a20_out;
+hwaddr mask;
+} KBDState;
+
#define TYPE_I8042 "i8042"
OBJECT_DECLARE_SIMPLE_TYPE(ISAKBDState, I8042)
--
2.30.2
[PULL 11/55] ps2: implement ps2_mouse_realize() and use it to register ps2_mouse_handler
Move the registration of ps2_mouse_handler from ps2_mouse_init() to a new
ps2_mouse_realize() function. Since the abstract PS2_DEVICE parent class doesn't
have a realize() function then it is not necessary to store the reference to
it in PS2DeviceClass and use device_class_set_parent_realize().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-12-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 62ea4c228b..eae7df2096 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -1244,6 +1244,11 @@ static QemuInputHandler ps2_mouse_handler = {
.sync = ps2_mouse_sync,
};
+static void ps2_mouse_realize(DeviceState *dev, Error **errp)
+{
+qemu_input_handler_register(dev, &ps2_mouse_handler);
+}
+
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg)
{
DeviceState *dev;
@@ -1259,8 +1264,6 @@ void *ps2_mouse_init(void (*update_irq)(void *, int),
void *update_arg)
ps2->update_irq = update_irq;
ps2->update_arg = update_arg;
vmstate_register(NULL, 0, &vmstate_ps2_mouse, s);
-qemu_input_handler_register((DeviceState *)s,
-&ps2_mouse_handler);
return s;
}
@@ -1285,6 +1288,7 @@ static void ps2_mouse_class_init(ObjectClass *klass, void
*data)
DeviceClass *dc = DEVICE_CLASS(klass);
PS2DeviceClass *ps2dc = PS2_DEVICE_CLASS(klass);
+dc->realize = ps2_mouse_realize;
device_class_set_parent_reset(dc, ps2_mouse_reset,
&ps2dc->parent_reset);
}
--
2.30.2
[PULL 13/55] ps2: don't use vmstate_register() in ps2_mouse_init()
Since PS2_MOUSE_DEVICE is a qdev device then vmstate_ps2_mouse can be registered
using the DeviceClass vmsd field instead. There is no need to use
qdev_set_legacy_instance_id() to ensure migration compatibility since the first
2
parameters to vmstate_register() are NULL and 0 respectively.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-14-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 97e9172ba5..9c046ac500 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -1262,7 +1262,6 @@ void *ps2_mouse_init(void (*update_irq)(void *, int),
void *update_arg)
trace_ps2_mouse_init(s);
ps2->update_irq = update_irq;
ps2->update_arg = update_arg;
-vmstate_register(NULL, 0, &vmstate_ps2_mouse, s);
return s;
}
@@ -1291,6 +1290,7 @@ static void ps2_mouse_class_init(ObjectClass *klass, void
*data)
dc->realize = ps2_mouse_realize;
device_class_set_parent_reset(dc, ps2_mouse_reset,
&ps2dc->parent_reset);
+dc->vmsd = &vmstate_ps2_mouse;
}
static const TypeInfo ps2_mouse_info = {
--
2.30.2
[PULL 30/55] pckbd: move ps2_kbd_init() and ps2_mouse_init() to i8042_mmio_realize()
Move ps2_kbd_init() and ps2_mouse_init() from i8042_mm_init() to i8042_mmio_realize() to further reduce the initialisation logic done in i8042_mm_init(). Signed-off-by: Mark Cave-Ayland Acked-by: Helge Deller Reviewed-by: Peter Maydell Message-Id: <20220624134109.881989-31-mark.cave-ayl...@ilande.co.uk> --- hw/input/pckbd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index 1ab76793ea..72843f770e 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -685,6 +685,9 @@ static void i8042_mmio_realize(DeviceState *dev, Error **errp) /* Note we can't use dc->vmsd without breaking migration compatibility */ vmstate_register(NULL, 0, &vmstate_kbd, ks); + +ks->kbd = ps2_kbd_init(kbd_update_kbd_irq, ks); +ks->mouse = ps2_mouse_init(kbd_update_aux_irq, ks); } static void i8042_mmio_init(Object *obj) @@ -726,9 +729,6 @@ MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, s->irq_kbd = kbd_irq; s->irq_mouse = mouse_irq; -s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); -s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); - return I8042_MMIO(dev); } -- 2.30.2
[PULL 17/55] lasips2: rename ps2dev_update_irq() to lasips2_port_set_irq()
This better reflects that the IRQ input opaque is a LASIPS2Port structure
and not a PS2_DEVICE.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-18-mark.cave-ayl...@ilande.co.uk>
---
hw/input/lasips2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index 2ac3433014..adfde1684f 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -253,7 +253,7 @@ static const MemoryRegionOps lasips2_reg_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void ps2dev_update_irq(void *opaque, int level)
+static void lasips2_port_set_irq(void *opaque, int level)
{
LASIPS2Port *port = opaque;
@@ -275,8 +275,8 @@ void lasips2_init(MemoryRegion *address_space,
vmstate_register(NULL, base, &vmstate_lasips2, s);
-s->kbd.dev = ps2_kbd_init(ps2dev_update_irq, &s->kbd);
-s->mouse.dev = ps2_mouse_init(ps2dev_update_irq, &s->mouse);
+s->kbd.dev = ps2_kbd_init(lasips2_port_set_irq, &s->kbd);
+s->mouse.dev = ps2_mouse_init(lasips2_port_set_irq, &s->mouse);
memory_region_init_io(&s->kbd.reg, NULL, &lasips2_reg_ops, &s->kbd,
"lasips2-kbd", 0x100);
--
2.30.2
[PULL 20/55] pckbd: move ISAKBDState from pckbd.c to i8042.h
This allows the QOM types in pckbd.c to be used elsewhere by simply including
i8042.h.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-21-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 10 --
include/hw/input/i8042.h | 10 ++
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 7b14cd007e..f99e10cfcf 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -686,16 +686,6 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
qemu_register_reset(kbd_reset, s);
}
-struct ISAKBDState {
-ISADevice parent_obj;
-
-KBDState kbd;
-bool kbd_throttle;
-MemoryRegion io[2];
-uint8_t kbd_irq;
-uint8_t mouse_irq;
-};
-
void i8042_isa_mouse_fake_event(ISAKBDState *isa)
{
KBDState *s = &isa->kbd;
diff --git a/include/hw/input/i8042.h b/include/hw/input/i8042.h
index 84b5aa7f23..a246250d1f 100644
--- a/include/hw/input/i8042.h
+++ b/include/hw/input/i8042.h
@@ -39,6 +39,16 @@ typedef struct KBDState {
#define TYPE_I8042 "i8042"
OBJECT_DECLARE_SIMPLE_TYPE(ISAKBDState, I8042)
+struct ISAKBDState {
+ISADevice parent_obj;
+
+KBDState kbd;
+bool kbd_throttle;
+MemoryRegion io[2];
+uint8_t kbd_irq;
+uint8_t mouse_irq;
+};
+
#define I8042_A20_LINE "a20"
--
2.30.2
[PULL 31/55] ps2: make ps2_raise_irq() function static
This function is no longer used outside of ps2.c and so can be declared static.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-32-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 2 +-
include/hw/input/ps2.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 9c046ac500..24c9853d37 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -172,7 +172,7 @@ void ps2_queue_noirq(PS2State *s, int b)
q->count++;
}
-void ps2_raise_irq(PS2State *s)
+static void ps2_raise_irq(PS2State *s)
{
s->update_irq(s->update_arg, 1);
}
diff --git a/include/hw/input/ps2.h b/include/hw/input/ps2.h
index 4be27de316..410ec66baf 100644
--- a/include/hw/input/ps2.h
+++ b/include/hw/input/ps2.h
@@ -102,7 +102,6 @@ void ps2_write_mouse(PS2MouseState *s, int val);
void ps2_write_keyboard(PS2KbdState *s, int val);
uint32_t ps2_read_data(PS2State *s);
void ps2_queue_noirq(PS2State *s, int b);
-void ps2_raise_irq(PS2State *s);
void ps2_queue(PS2State *s, int b);
void ps2_queue_2(PS2State *s, int b1, int b2);
void ps2_queue_3(PS2State *s, int b1, int b2, int b3);
--
2.30.2
[PULL 18/55] pckbd: checkpatch fixes
Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Acked-by: Helge Deller Message-Id: <20220624134109.881989-19-mark.cave-ayl...@ilande.co.uk> --- hw/input/pckbd.c | 150 ++- 1 file changed, 97 insertions(+), 53 deletions(-) diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index 45c40fe3f3..c18a1a7fae 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -39,49 +39,86 @@ #include "trace.h" -/* Keyboard Controller Commands */ -#define KBD_CCMD_READ_MODE 0x20/* Read mode bits */ -#define KBD_CCMD_WRITE_MODE0x60/* Write mode bits */ -#define KBD_CCMD_GET_VERSION 0xA1/* Get controller version */ -#define KBD_CCMD_MOUSE_DISABLE 0xA7/* Disable mouse interface */ -#define KBD_CCMD_MOUSE_ENABLE 0xA8/* Enable mouse interface */ -#define KBD_CCMD_TEST_MOUSE0xA9/* Mouse interface test */ -#define KBD_CCMD_SELF_TEST 0xAA/* Controller self test */ -#define KBD_CCMD_KBD_TEST 0xAB/* Keyboard interface test */ -#define KBD_CCMD_KBD_DISABLE 0xAD/* Keyboard interface disable */ -#define KBD_CCMD_KBD_ENABLE0xAE/* Keyboard interface enable */ -#define KBD_CCMD_READ_INPORT0xC0/* read input port */ -#define KBD_CCMD_READ_OUTPORT 0xD0/* read output port */ -#define KBD_CCMD_WRITE_OUTPORT 0xD1/* write output port */ -#define KBD_CCMD_WRITE_OBUF0xD2 -#define KBD_CCMD_WRITE_AUX_OBUF0xD3/* Write to output buffer as if - initiated by the auxiliary device */ -#define KBD_CCMD_WRITE_MOUSE 0xD4/* Write the following byte to the mouse */ -#define KBD_CCMD_DISABLE_A200xDD/* HP vectra only ? */ -#define KBD_CCMD_ENABLE_A20 0xDF/* HP vectra only ? */ -#define KBD_CCMD_PULSE_BITS_3_0 0xF0/* Pulse bits 3-0 of the output port P2. */ -#define KBD_CCMD_RESET 0xFE/* Pulse bit 0 of the output port P2 = CPU reset. */ -#define KBD_CCMD_NO_OP 0xFF/* Pulse no bits of the output port P2. */ +/* Keyboard Controller Commands */ + +/* Read mode bits */ +#define KBD_CCMD_READ_MODE 0x20 +/* Write mode bits */ +#define KBD_CCMD_WRITE_MODE0x60 +/* Get controller version */ +#define KBD_CCMD_GET_VERSION 0xA1 +/* Disable mouse interface */ +#define KBD_CCMD_MOUSE_DISABLE 0xA7 +/* Enable mouse interface */ +#define KBD_CCMD_MOUSE_ENABLE 0xA8 +/* Mouse interface test */ +#define KBD_CCMD_TEST_MOUSE0xA9 +/* Controller self test */ +#define KBD_CCMD_SELF_TEST 0xAA +/* Keyboard interface test */ +#define KBD_CCMD_KBD_TEST 0xAB +/* Keyboard interface disable */ +#define KBD_CCMD_KBD_DISABLE 0xAD +/* Keyboard interface enable */ +#define KBD_CCMD_KBD_ENABLE0xAE +/* read input port */ +#define KBD_CCMD_READ_INPORT 0xC0 +/* read output port */ +#define KBD_CCMD_READ_OUTPORT 0xD0 +/* write output port */ +#define KBD_CCMD_WRITE_OUTPORT 0xD1 +#define KBD_CCMD_WRITE_OBUF0xD2 +/* Write to output buffer as if initiated by the auxiliary device */ +#define KBD_CCMD_WRITE_AUX_OBUF0xD3 +/* Write the following byte to the mouse */ +#define KBD_CCMD_WRITE_MOUSE 0xD4 +/* HP vectra only ? */ +#define KBD_CCMD_DISABLE_A20 0xDD +/* HP vectra only ? */ +#define KBD_CCMD_ENABLE_A200xDF +/* Pulse bits 3-0 of the output port P2. */ +#define KBD_CCMD_PULSE_BITS_3_00xF0 +/* Pulse bit 0 of the output port P2 = CPU reset. */ +#define KBD_CCMD_RESET 0xFE +/* Pulse no bits of the output port P2. */ +#define KBD_CCMD_NO_OP 0xFF /* Status Register Bits */ -#define KBD_STAT_OBF 0x01/* Keyboard output buffer full */ -#define KBD_STAT_IBF 0x02/* Keyboard input buffer full */ -#define KBD_STAT_SELFTEST 0x04/* Self test successful */ -#define KBD_STAT_CMD 0x08/* Last write was a command write (0=data) */ -#define KBD_STAT_UNLOCKED 0x10/* Zero if keyboard locked */ -#define KBD_STAT_MOUSE_OBF 0x20/* Mouse output buffer full */ -#define KBD_STAT_GTO 0x40/* General receive/xmit timeout */ -#define KBD_STAT_PERR 0x80/* Parity error */ + +/* Keyboard output buffer full */ +#define KBD_STAT_OBF 0x01 +/* Keyboard input buffer full */ +#define KBD_STAT_IBF 0x02 +/* Self test successful */ +#define KBD_STAT_SELFTEST 0x04 +/* Last write was a command write (0=data) */ +#define KBD_STAT_CMD 0x08 +/* Zero if keyboard locked */ +#define KBD_STAT_UNLOCKED 0x10 +/* Mouse output buffer full */ +#define KBD_STAT_MOUSE_OBF 0x20 +/* General receive/xmit timeout */ +#define KBD_STAT_GTO 0x40 +/* Parity error */ +#define KBD_STAT_PERR 0x80 /* Controller Mode Register Bits */ -#define KBD_MODE_KBD_INT 0x01/* Keyboard data generate IRQ1 */ -#define KBD_MODE_MOUSE_INT 0x02/* Mouse data generate IRQ12 */ -#define KBD_MODE_SYS
[PULL 25/55] pckbd: implement i8042_mmio_realize() function
Move the initialisation of the register memory region to the I8042_MMIO device
realize function and expose it using sysbus_init_mmio().
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-26-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 14 +-
include/hw/input/i8042.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index a70442e0f8..bc51f7eedd 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -673,6 +673,17 @@ static void i8042_mmio_reset(DeviceState *dev)
kbd_reset(ks);
}
+static void i8042_mmio_realize(DeviceState *dev, Error **errp)
+{
+MMIOKBDState *s = I8042_MMIO(dev);
+KBDState *ks = &s->kbd;
+
+memory_region_init_io(&s->region, OBJECT(dev), &i8042_mmio_ops, ks,
+ "i8042", s->size);
+
+sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->region);
+}
+
static Property i8042_mmio_properties[] = {
DEFINE_PROP_UINT64("mask", MMIOKBDState, kbd.mask, UINT64_MAX),
DEFINE_PROP_UINT32("size", MMIOKBDState, size, -1),
@@ -683,6 +694,7 @@ static void i8042_mmio_class_init(ObjectClass *klass, void
*data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+dc->realize = i8042_mmio_realize;
dc->reset = i8042_mmio_reset;
device_class_set_props(dc, i8042_mmio_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
@@ -708,7 +720,7 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
vmstate_register(NULL, 0, &vmstate_kbd, s);
-memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);
+region = &I8042_MMIO(dev)->region;
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
diff --git a/include/hw/input/i8042.h b/include/hw/input/i8042.h
index ac4098b957..59d695a9dd 100644
--- a/include/hw/input/i8042.h
+++ b/include/hw/input/i8042.h
@@ -58,6 +58,7 @@ struct MMIOKBDState {
KBDState kbd;
uint32_t size;
+MemoryRegion region;
};
#define I8042_A20_LINE "a20"
--
2.30.2
[PULL 21/55] pckbd: introduce new I8042_MMIO QOM type
Currently i8042_mm_init() creates a new KBDState directly which is used by the
MIPS
magnum machine. Introduce a new I8042_MMIO QOM type that will soon be used to
allow the MIPS magnum machine to be wired up using standard qdev GPIOs.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-22-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 22 +-
include/hw/input/i8042.h | 10 ++
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index f99e10cfcf..89a41ed566 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -665,11 +665,23 @@ static const MemoryRegionOps i8042_mmio_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void i8042_mmio_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
+}
+
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
MemoryRegion *region, ram_addr_t size,
hwaddr mask)
{
-KBDState *s = g_new0(KBDState, 1);
+DeviceState *dev;
+KBDState *s;
+
+dev = qdev_new(TYPE_I8042_MMIO);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+s = &I8042_MMIO(dev)->kbd;
s->irq_kbd = kbd_irq;
s->irq_mouse = mouse_irq;
@@ -686,6 +698,13 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
qemu_register_reset(kbd_reset, s);
}
+static const TypeInfo i8042_mmio_info = {
+.name = TYPE_I8042_MMIO,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(MMIOKBDState),
+.class_init= i8042_mmio_class_init
+};
+
void i8042_isa_mouse_fake_event(ISAKBDState *isa)
{
KBDState *s = &isa->kbd;
@@ -841,6 +860,7 @@ static const TypeInfo i8042_info = {
static void i8042_register_types(void)
{
type_register_static(&i8042_info);
+type_register_static(&i8042_mmio_info);
}
type_init(i8042_register_types)
diff --git a/include/hw/input/i8042.h b/include/hw/input/i8042.h
index a246250d1f..b7df9ace6e 100644
--- a/include/hw/input/i8042.h
+++ b/include/hw/input/i8042.h
@@ -9,6 +9,7 @@
#define HW_INPUT_I8042_H
#include "hw/isa/isa.h"
+#include "hw/sysbus.h"
#include "qom/object.h"
typedef struct KBDState {
@@ -49,6 +50,15 @@ struct ISAKBDState {
uint8_t mouse_irq;
};
+#define TYPE_I8042_MMIO "i8042-mmio"
+OBJECT_DECLARE_SIMPLE_TYPE(MMIOKBDState, I8042_MMIO)
+
+struct MMIOKBDState {
+SysBusDevice parent_obj;
+
+KBDState kbd;
+};
+
#define I8042_A20_LINE "a20"
--
2.30.2
[PULL 36/55] pl050: switch over from update_irq() function to PS2 device gpio
Add a new pl050_init() function which initialises a qdev input gpio for handling
incoming PS2 IRQs, and then wire up the PS2 device to use it. At the same time
set update_irq() and update_arg to NULL in ps2_kbd_init() and ps2_mouse_init()
to ensure that any accidental attempt to use the legacy update_irq() function
will
cause a NULL pointer dereference.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-37-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Peter Maydell
---
hw/input/pl050.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/hw/input/pl050.c b/hw/input/pl050.c
index 66f8c20d9f..c665a4fc99 100644
--- a/hw/input/pl050.c
+++ b/hw/input/pl050.c
@@ -65,7 +65,7 @@ static void pl050_update_irq(PL050State *s)
qemu_set_irq(s->irq, level);
}
-static void pl050_set_irq(void *opaque, int level)
+static void pl050_set_irq(void *opaque, int n, int level)
{
PL050State *s = (PL050State *)opaque;
@@ -164,10 +164,12 @@ static void pl050_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
if (s->is_mouse) {
-s->dev = ps2_mouse_init(pl050_set_irq, s);
+s->dev = ps2_mouse_init(NULL, NULL);
} else {
-s->dev = ps2_kbd_init(pl050_set_irq, s);
+s->dev = ps2_kbd_init(NULL, NULL);
}
+qdev_connect_gpio_out(DEVICE(s->dev), PS2_DEVICE_IRQ,
+ qdev_get_gpio_in_named(dev, "ps2-input-irq", 0));
}
static void pl050_keyboard_init(Object *obj)
@@ -196,6 +198,11 @@ static const TypeInfo pl050_mouse_info = {
.instance_init = pl050_mouse_init,
};
+static void pl050_init(Object *obj)
+{
+qdev_init_gpio_in_named(DEVICE(obj), pl050_set_irq, "ps2-input-irq", 1);
+}
+
static void pl050_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -207,6 +214,7 @@ static void pl050_class_init(ObjectClass *oc, void *data)
static const TypeInfo pl050_type_info = {
.name = TYPE_PL050,
.parent= TYPE_SYS_BUS_DEVICE,
+.instance_init = pl050_init,
.instance_size = sizeof(PL050State),
.abstract = true,
.class_init= pl050_class_init,
--
2.30.2
[PULL 32/55] ps2: use ps2_raise_irq() instead of calling update_irq() directly
This consolidates the logic of raising the PS2 IRQ into one single function.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-33-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 24c9853d37..a14281bc54 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -557,7 +557,7 @@ uint32_t ps2_read_data(PS2State *s)
s->update_irq(s->update_arg, 0);
/* reassert IRQs if data left */
if (q->count) {
-s->update_irq(s->update_arg, 1);
+ps2_raise_irq(s);
}
}
return val;
--
2.30.2
[PULL 24/55] pckbd: add size qdev property to I8042_MMIO device
This will soon be used to set the size of the register memory region using a
qdev property.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-25-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 2 ++
include/hw/input/i8042.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index c04a2c587e..a70442e0f8 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -675,6 +675,7 @@ static void i8042_mmio_reset(DeviceState *dev)
static Property i8042_mmio_properties[] = {
DEFINE_PROP_UINT64("mask", MMIOKBDState, kbd.mask, UINT64_MAX),
+DEFINE_PROP_UINT32("size", MMIOKBDState, size, -1),
DEFINE_PROP_END_OF_LIST(),
};
@@ -696,6 +697,7 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
dev = qdev_new(TYPE_I8042_MMIO);
qdev_prop_set_uint64(dev, "mask", mask);
+qdev_prop_set_uint32(dev, "size", size);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s = &I8042_MMIO(dev)->kbd;
diff --git a/include/hw/input/i8042.h b/include/hw/input/i8042.h
index b7df9ace6e..ac4098b957 100644
--- a/include/hw/input/i8042.h
+++ b/include/hw/input/i8042.h
@@ -57,6 +57,7 @@ struct MMIOKBDState {
SysBusDevice parent_obj;
KBDState kbd;
+uint32_t size;
};
#define I8042_A20_LINE "a20"
--
2.30.2
[PULL 27/55] pckbd: alter i8042_mm_init() to return a I8042_MMIO device
This exposes the I8042_MMIO device to the caller to allow the register memory
region to be mapped outside of i8042_mm_init().
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-28-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 8 +---
include/hw/input/i8042.h | 6 +++---
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index b8623d2f9a..702dab056c 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -708,9 +708,9 @@ static void i8042_mmio_class_init(ObjectClass *klass, void
*data)
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
-void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- MemoryRegion *region, ram_addr_t size,
- hwaddr mask)
+MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
+MemoryRegion *region, ram_addr_t size,
+hwaddr mask)
{
DeviceState *dev;
KBDState *s;
@@ -730,6 +730,8 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
+
+return I8042_MMIO(dev);
}
static const TypeInfo i8042_mmio_info = {
diff --git a/include/hw/input/i8042.h b/include/hw/input/i8042.h
index 59d695a9dd..d05cd33e3c 100644
--- a/include/hw/input/i8042.h
+++ b/include/hw/input/i8042.h
@@ -64,9 +64,9 @@ struct MMIOKBDState {
#define I8042_A20_LINE "a20"
-void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- MemoryRegion *region, ram_addr_t size,
- hwaddr mask);
+MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
+MemoryRegion *region, ram_addr_t size,
+hwaddr mask);
void i8042_isa_mouse_fake_event(ISAKBDState *isa);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out);
--
2.30.2
[PULL 45/55] lasips2: implement lasips2_realize()
Move ps2_kbd_init() and ps2_mouse_init() from lasips2_initfn() to
lasips2_realize.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-46-mark.cave-ayl...@ilande.co.uk>
---
hw/input/lasips2.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index 81beb5b614..49405191cb 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -256,13 +256,17 @@ LASIPS2State *lasips2_initfn(hwaddr base, qemu_irq irq)
s = LASIPS2(dev);
s->irq = irq;
+return s;
+}
+
+static void lasips2_realize(DeviceState *dev, Error **errp)
+{
+LASIPS2State *s = LASIPS2(dev);
-vmstate_register(NULL, base, &vmstate_lasips2, s);
+vmstate_register(NULL, s->base, &vmstate_lasips2, s);
s->kbd.dev = ps2_kbd_init(lasips2_port_set_irq, &s->kbd);
s->mouse.dev = ps2_mouse_init(lasips2_port_set_irq, &s->mouse);
-
-return s;
}
static void lasips2_init(Object *obj)
@@ -292,6 +296,7 @@ static void lasips2_class_init(ObjectClass *klass, void
*data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+dc->realize = lasips2_realize;
device_class_set_props(dc, lasips2_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
--
2.30.2
[PULL 34/55] ps2: add gpio for output IRQ and optionally use it in ps2_raise_irq() and ps2_lower_irq()
Define the gpio for the PS2 output IRQ in ps2_init() and add logic to optionally
use it in ps2_raise_irq() and ps2_lower_irq() if the gpio is connected. If the
gpio is not connected then call the legacy update_irq() function as before.
This allows the incremental conversion of devices from the legacy update_irq()
function to use gpios instead.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-35-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 21 +++--
include/hw/input/ps2.h | 4
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index bc0bcf1789..98c6206fb8 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
+#include "hw/irq.h"
#include "hw/sysbus.h"
#include "hw/input/ps2.h"
#include "migration/vmstate.h"
@@ -174,12 +175,20 @@ void ps2_queue_noirq(PS2State *s, int b)
static void ps2_raise_irq(PS2State *s)
{
-s->update_irq(s->update_arg, 1);
+if (qemu_irq_is_connected(s->irq)) {
+qemu_set_irq(s->irq, 1);
+} else {
+s->update_irq(s->update_arg, 1);
+}
}
static void ps2_lower_irq(PS2State *s)
{
-s->update_irq(s->update_arg, 0);
+if (qemu_irq_is_connected(s->irq)) {
+qemu_set_irq(s->irq, 0);
+} else {
+s->update_irq(s->update_arg, 0);
+}
}
void ps2_queue(PS2State *s, int b)
@@ -1305,6 +1314,13 @@ static const TypeInfo ps2_mouse_info = {
.class_init= ps2_mouse_class_init
};
+static void ps2_init(Object *obj)
+{
+PS2State *s = PS2_DEVICE(obj);
+
+qdev_init_gpio_out(DEVICE(obj), &s->irq, 1);
+}
+
static void ps2_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1316,6 +1332,7 @@ static void ps2_class_init(ObjectClass *klass, void *data)
static const TypeInfo ps2_info = {
.name = TYPE_PS2_DEVICE,
.parent= TYPE_SYS_BUS_DEVICE,
+.instance_init = ps2_init,
.instance_size = sizeof(PS2State),
.class_init= ps2_class_init,
.class_size= sizeof(PS2DeviceClass),
diff --git a/include/hw/input/ps2.h b/include/hw/input/ps2.h
index 410ec66baf..5422aee9aa 100644
--- a/include/hw/input/ps2.h
+++ b/include/hw/input/ps2.h
@@ -50,11 +50,15 @@ typedef struct {
int rptr, wptr, cwptr, count;
} PS2Queue;
+/* Output IRQ */
+#define PS2_DEVICE_IRQ 0
+
struct PS2State {
SysBusDevice parent_obj;
PS2Queue queue;
int32_t write_cmd;
+qemu_irq irq;
void (*update_irq)(void *, int);
void *update_arg;
};
--
2.30.2
[PULL 29/55] pckbd: more vmstate_register() from i8042_mm_init() to i8042_mmio_realize()
Note in this case it is not possible to register a (new) VMStateDescription in the DeviceClass without breaking migration compatibility for the MIPS magnum machine. Signed-off-by: Mark Cave-Ayland Acked-by: Helge Deller Message-Id: <20220624134109.881989-30-mark.cave-ayl...@ilande.co.uk> Reviewed-by: Peter Maydell --- hw/input/pckbd.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index 8708595eed..1ab76793ea 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -682,6 +682,9 @@ static void i8042_mmio_realize(DeviceState *dev, Error **errp) "i8042", s->size); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->region); + +/* Note we can't use dc->vmsd without breaking migration compatibility */ +vmstate_register(NULL, 0, &vmstate_kbd, ks); } static void i8042_mmio_init(Object *obj) @@ -723,8 +726,6 @@ MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, s->irq_kbd = kbd_irq; s->irq_mouse = mouse_irq; -vmstate_register(NULL, 0, &vmstate_kbd, s); - s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); -- 2.30.2
[PULL 28/55] pckbd: move mapping of I8042_MMIO registers to MIPS magnum machine
Now that the register memory region is exposed as a SysBus memory region, move
the mapping of the I8042_MMIO registers from i8042_mm_init() to the MIPS magnum
machine (which is its only user).
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-29-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 5 +
hw/mips/jazz.c | 11 +++
include/hw/input/i8042.h | 3 +--
3 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 702dab056c..8708595eed 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -709,8 +709,7 @@ static void i8042_mmio_class_init(ObjectClass *klass, void
*data)
}
MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
-MemoryRegion *region, ram_addr_t size,
-hwaddr mask)
+ram_addr_t size, hwaddr mask)
{
DeviceState *dev;
KBDState *s;
@@ -726,8 +725,6 @@ MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq
mouse_irq,
vmstate_register(NULL, 0, &vmstate_kbd, s);
-region = &I8042_MMIO(dev)->region;
-
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 96dc6ab32d..1eb8bd5018 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -136,11 +136,11 @@ static void mips_jazz_init(MachineState *machine,
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
MemoryRegion *rtc = g_new(MemoryRegion, 1);
-MemoryRegion *i8042 = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev, *rc4030;
+MMIOKBDState *i8042;
SysBusDevice *sysbus;
ISABus *isa_bus;
ISADevice *pit;
@@ -361,9 +361,12 @@ static void mips_jazz_init(MachineState *machine,
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
-i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
- i8042, 0x1000, 0x1);
-memory_region_add_subregion(address_space, 0x80005000, i8042);
+i8042 = i8042_mm_init(qdev_get_gpio_in(rc4030, 6),
+ qdev_get_gpio_in(rc4030, 7),
+ 0x1000, 0x1);
+memory_region_add_subregion(address_space, 0x80005000,
+sysbus_mmio_get_region(SYS_BUS_DEVICE(i8042),
+ 0));
/* Serial ports */
serial_mm_init(address_space, 0x80006000, 0,
diff --git a/include/hw/input/i8042.h b/include/hw/input/i8042.h
index d05cd33e3c..9d1f8af964 100644
--- a/include/hw/input/i8042.h
+++ b/include/hw/input/i8042.h
@@ -65,8 +65,7 @@ struct MMIOKBDState {
MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
-MemoryRegion *region, ram_addr_t size,
-hwaddr mask);
+ram_addr_t size, hwaddr mask);
void i8042_isa_mouse_fake_event(ISAKBDState *isa);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out);
--
2.30.2
[PULL 46/55] lasips2: use sysbus IRQ for output IRQ
This enables the IRQ to be wired up using sysbus_connect_irq() in
lasips2_initfn().
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-47-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Peter Maydell
---
hw/input/lasips2.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index 49405191cb..bd72505411 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -247,16 +247,15 @@ static void lasips2_port_set_irq(void *opaque, int level)
LASIPS2State *lasips2_initfn(hwaddr base, qemu_irq irq)
{
-LASIPS2State *s;
DeviceState *dev;
dev = qdev_new(TYPE_LASIPS2);
qdev_prop_set_uint64(dev, "base", base);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-s = LASIPS2(dev);
-s->irq = irq;
-return s;
+sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
+
+return LASIPS2(dev);
}
static void lasips2_realize(DeviceState *dev, Error **errp)
@@ -285,6 +284,8 @@ static void lasips2_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->kbd.reg);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mouse.reg);
+
+sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
}
static Property lasips2_properties[] = {
--
2.30.2
[PULL 38/55] lasips2: QOMify LASIPS2State
Currently lasip2_init() creates a new LASIPS2State directly which is used by
the HPPA
machine. Introduce a new LASIPS2 QOM type that will soon be used to allow the
HPPA
machine to be wired up using standard qdev GPIOs.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-39-mark.cave-ayl...@ilande.co.uk>
---
hw/input/lasips2.c | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index adfde1684f..db0a791e6c 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
#include "hw/input/ps2.h"
#include "hw/input/lasips2.h"
#include "exec/hwaddr.h"
@@ -31,6 +32,7 @@
#include "exec/address-spaces.h"
#include "migration/vmstate.h"
#include "hw/irq.h"
+#include "qapi/error.h"
struct LASIPS2State;
@@ -45,11 +47,16 @@ typedef struct LASIPS2Port {
bool irq;
} LASIPS2Port;
-typedef struct LASIPS2State {
+struct LASIPS2State {
+SysBusDevice parent_obj;
+
LASIPS2Port kbd;
LASIPS2Port mouse;
qemu_irq irq;
-} LASIPS2State;
+};
+
+#define TYPE_LASIPS2 "lasips2"
+OBJECT_DECLARE_SIMPLE_TYPE(LASIPS2State, LASIPS2)
static const VMStateDescription vmstate_lasips2 = {
.name = "lasips2",
@@ -265,8 +272,11 @@ void lasips2_init(MemoryRegion *address_space,
hwaddr base, qemu_irq irq)
{
LASIPS2State *s;
+DeviceState *dev;
-s = g_new0(LASIPS2State, 1);
+dev = qdev_new(TYPE_LASIPS2);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+s = LASIPS2(dev);
s->irq = irq;
s->mouse.id = 1;
@@ -286,3 +296,16 @@ void lasips2_init(MemoryRegion *address_space,
"lasips2-mouse", 0x100);
memory_region_add_subregion(address_space, base + 0x100, &s->mouse.reg);
}
+
+static const TypeInfo lasips2_info = {
+.name = TYPE_LASIPS2,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(LASIPS2State)
+};
+
+static void lasips2_register_types(void)
+{
+type_register_static(&lasips2_info);
+}
+
+type_init(lasips2_register_types)
--
2.30.2
[PULL 33/55] ps2: introduce ps2_lower_irq() instead of calling update_irq() directly
This consolidates the logic of lowering the PS2 IRQ into one single function.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-34-mark.cave-ayl...@ilande.co.uk>
---
hw/input/ps2.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index a14281bc54..bc0bcf1789 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -177,6 +177,11 @@ static void ps2_raise_irq(PS2State *s)
s->update_irq(s->update_arg, 1);
}
+static void ps2_lower_irq(PS2State *s)
+{
+s->update_irq(s->update_arg, 0);
+}
+
void ps2_queue(PS2State *s, int b)
{
if (PS2_QUEUE_SIZE - s->queue.count < 1) {
@@ -554,7 +559,7 @@ uint32_t ps2_read_data(PS2State *s)
q->cwptr = -1;
}
/* reading deasserts IRQ */
-s->update_irq(s->update_arg, 0);
+ps2_lower_irq(s);
/* reassert IRQs if data left */
if (q->count) {
ps2_raise_irq(s);
@@ -1001,7 +1006,7 @@ static void ps2_reset(DeviceState *dev)
s->write_cmd = -1;
ps2_reset_queue(s);
-s->update_irq(s->update_arg, 0);
+ps2_lower_irq(s);
}
static void ps2_common_post_load(PS2State *s)
--
2.30.2
[PULL 40/55] lasips2: rename lasips2_init() to lasips2_initfn() and update it to return the LASIPS2 device
When QOMifying a device it is typical to use _init() as the suffix for an
instance_init function, however this name is already in use by the legacy
LASIPS2
wrapper function. Eventually the wrapper function will be removed, but for now
rename it to lasips2_initfn() to avoid a naming collision.
At the same time update lasips2_initfn() return the LASIPS2 device so that it
can later be accessed using qdev APIs by the HPPA machine.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-41-mark.cave-ayl...@ilande.co.uk>
---
hw/hppa/machine.c | 4 ++--
hw/input/lasips2.c | 6 --
include/hw/input/lasips2.h | 3 ++-
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 63b9dd2396..72677aeb2a 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -280,8 +280,8 @@ static void machine_hppa_init(MachineState *machine)
}
/* PS/2 Keyboard/Mouse */
-lasips2_init(addr_space, LASI_PS2KBD_HPA,
- qdev_get_gpio_in(lasi_dev, LASI_IRQ_PS2KBD_HPA));
+lasips2_initfn(addr_space, LASI_PS2KBD_HPA,
+ qdev_get_gpio_in(lasi_dev, LASI_IRQ_PS2KBD_HPA));
/* register power switch emulation */
qemu_register_powerdown_notifier(&hppa_system_powerdown_notifier);
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index 2caa80bd3c..85da4081e3 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -245,8 +245,8 @@ static void lasips2_port_set_irq(void *opaque, int level)
lasips2_update_irq(port->parent);
}
-void lasips2_init(MemoryRegion *address_space,
- hwaddr base, qemu_irq irq)
+LASIPS2State *lasips2_initfn(MemoryRegion *address_space,
+ hwaddr base, qemu_irq irq)
{
LASIPS2State *s;
DeviceState *dev;
@@ -272,6 +272,8 @@ void lasips2_init(MemoryRegion *address_space,
memory_region_init_io(&s->mouse.reg, NULL, &lasips2_reg_ops, &s->mouse,
"lasips2-mouse", 0x100);
memory_region_add_subregion(address_space, base + 0x100, &s->mouse.reg);
+
+return s;
}
static const TypeInfo lasips2_info = {
diff --git a/include/hw/input/lasips2.h b/include/hw/input/lasips2.h
index ddcea74c14..5a35c22f73 100644
--- a/include/hw/input/lasips2.h
+++ b/include/hw/input/lasips2.h
@@ -33,6 +33,7 @@ struct LASIPS2State {
#define TYPE_LASIPS2 "lasips2"
OBJECT_DECLARE_SIMPLE_TYPE(LASIPS2State, LASIPS2)
-void lasips2_init(MemoryRegion *address_space, hwaddr base, qemu_irq irq);
+LASIPS2State *lasips2_initfn(MemoryRegion *address_space, hwaddr base,
+ qemu_irq irq);
#endif /* HW_INPUT_LASIPS2_H */
--
2.30.2
[PULL 39/55] lasips2: move lasips2 QOM types from lasips2.c to lasips2.h
This allows the QOM types in lasips2.c to be used elsewhere by simply including
lasips2.h.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-40-mark.cave-ayl...@ilande.co.uk>
---
hw/input/lasips2.c | 23 ---
include/hw/input/lasips2.h | 22 ++
2 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index db0a791e6c..2caa80bd3c 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -35,29 +35,6 @@
#include "qapi/error.h"
-struct LASIPS2State;
-typedef struct LASIPS2Port {
-struct LASIPS2State *parent;
-MemoryRegion reg;
-void *dev;
-uint8_t id;
-uint8_t control;
-uint8_t buf;
-bool loopback_rbne;
-bool irq;
-} LASIPS2Port;
-
-struct LASIPS2State {
-SysBusDevice parent_obj;
-
-LASIPS2Port kbd;
-LASIPS2Port mouse;
-qemu_irq irq;
-};
-
-#define TYPE_LASIPS2 "lasips2"
-OBJECT_DECLARE_SIMPLE_TYPE(LASIPS2State, LASIPS2)
-
static const VMStateDescription vmstate_lasips2 = {
.name = "lasips2",
.version_id = 0,
diff --git a/include/hw/input/lasips2.h b/include/hw/input/lasips2.h
index 0cd7b59064..ddcea74c14 100644
--- a/include/hw/input/lasips2.h
+++ b/include/hw/input/lasips2.h
@@ -8,8 +8,30 @@
#define HW_INPUT_LASIPS2_H
#include "exec/hwaddr.h"
+#include "hw/sysbus.h"
+
+struct LASIPS2State;
+typedef struct LASIPS2Port {
+struct LASIPS2State *parent;
+MemoryRegion reg;
+void *dev;
+uint8_t id;
+uint8_t control;
+uint8_t buf;
+bool loopback_rbne;
+bool irq;
+} LASIPS2Port;
+
+struct LASIPS2State {
+SysBusDevice parent_obj;
+
+LASIPS2Port kbd;
+LASIPS2Port mouse;
+qemu_irq irq;
+};
#define TYPE_LASIPS2 "lasips2"
+OBJECT_DECLARE_SIMPLE_TYPE(LASIPS2State, LASIPS2)
void lasips2_init(MemoryRegion *address_space, hwaddr base, qemu_irq irq);
--
2.30.2
[PULL 35/55] pckbd: replace irq_kbd and irq_mouse with qemu_irq array in KBDState
This allows both IRQs to be declared as a single qdev gpio array.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-36-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 12 ++--
include/hw/input/i8042.h | 6 --
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 72843f770e..5d7c969fc6 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -170,8 +170,8 @@ static void kbd_update_irq_lines(KBDState *s)
}
}
}
-qemu_set_irq(s->irq_kbd, irq_kbd_level);
-qemu_set_irq(s->irq_mouse, irq_mouse_level);
+qemu_set_irq(s->irqs[I8042_KBD_IRQ], irq_kbd_level);
+qemu_set_irq(s->irqs[I8042_MOUSE_IRQ], irq_mouse_level);
}
static void kbd_deassert_irq(KBDState *s)
@@ -726,8 +726,8 @@ MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq
mouse_irq,
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s = &I8042_MMIO(dev)->kbd;
-s->irq_kbd = kbd_irq;
-s->irq_mouse = mouse_irq;
+s->irqs[I8042_KBD_IRQ] = kbd_irq;
+s->irqs[I8042_MOUSE_IRQ] = mouse_irq;
return I8042_MMIO(dev);
}
@@ -813,8 +813,8 @@ static void i8042_realizefn(DeviceState *dev, Error **errp)
return;
}
-s->irq_kbd = isa_get_irq(isadev, isa_s->kbd_irq);
-s->irq_mouse = isa_get_irq(isadev, isa_s->mouse_irq);
+s->irqs[I8042_KBD_IRQ] = isa_get_irq(isadev, isa_s->kbd_irq);
+s->irqs[I8042_MOUSE_IRQ] = isa_get_irq(isadev, isa_s->mouse_irq);
isa_register_ioport(isadev, isa_s->io + 0, 0x60);
isa_register_ioport(isadev, isa_s->io + 1, 0x64);
diff --git a/include/hw/input/i8042.h b/include/hw/input/i8042.h
index 9d1f8af964..4ba2664377 100644
--- a/include/hw/input/i8042.h
+++ b/include/hw/input/i8042.h
@@ -12,6 +12,9 @@
#include "hw/sysbus.h"
#include "qom/object.h"
+#define I8042_KBD_IRQ 0
+#define I8042_MOUSE_IRQ1
+
typedef struct KBDState {
uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
uint8_t status;
@@ -31,8 +34,7 @@ typedef struct KBDState {
void *mouse;
QEMUTimer *throttle_timer;
-qemu_irq irq_kbd;
-qemu_irq irq_mouse;
+qemu_irq irqs[2];
qemu_irq a20_out;
hwaddr mask;
} KBDState;
--
2.30.2
[PULL 42/55] lasips2: move mapping of LASIPS2 registers to HPPA machine
Now that the register memory regions are exposed as SysBus memory regions, move
the mapping of the LASIPS2 registers from lasips2_initfn() to the HPPA machine
(which is its only user).
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-43-mark.cave-ayl...@ilande.co.uk>
---
hw/hppa/machine.c | 11 +--
hw/input/lasips2.c | 7 +--
include/hw/input/lasips2.h | 3 +--
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 72677aeb2a..44ecd446c3 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -280,8 +280,15 @@ static void machine_hppa_init(MachineState *machine)
}
/* PS/2 Keyboard/Mouse */
-lasips2_initfn(addr_space, LASI_PS2KBD_HPA,
- qdev_get_gpio_in(lasi_dev, LASI_IRQ_PS2KBD_HPA));
+dev = DEVICE(lasips2_initfn(LASI_PS2KBD_HPA,
+qdev_get_gpio_in(lasi_dev,
+ LASI_IRQ_PS2KBD_HPA)));
+memory_region_add_subregion(addr_space, LASI_PS2KBD_HPA,
+sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
+ 0));
+memory_region_add_subregion(addr_space, LASI_PS2KBD_HPA + 0x100,
+sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
+ 1));
/* register power switch emulation */
qemu_register_powerdown_notifier(&hppa_system_powerdown_notifier);
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index 8d3a2d88e8..84e7a1feee 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -245,8 +245,7 @@ static void lasips2_port_set_irq(void *opaque, int level)
lasips2_update_irq(port->parent);
}
-LASIPS2State *lasips2_initfn(MemoryRegion *address_space,
- hwaddr base, qemu_irq irq)
+LASIPS2State *lasips2_initfn(hwaddr base, qemu_irq irq)
{
LASIPS2State *s;
DeviceState *dev;
@@ -265,10 +264,6 @@ LASIPS2State *lasips2_initfn(MemoryRegion *address_space,
s->kbd.dev = ps2_kbd_init(lasips2_port_set_irq, &s->kbd);
s->mouse.dev = ps2_mouse_init(lasips2_port_set_irq, &s->mouse);
-memory_region_add_subregion(address_space, base, &s->kbd.reg);
-
-memory_region_add_subregion(address_space, base + 0x100, &s->mouse.reg);
-
return s;
}
diff --git a/include/hw/input/lasips2.h b/include/hw/input/lasips2.h
index 5a35c22f73..b9723073e1 100644
--- a/include/hw/input/lasips2.h
+++ b/include/hw/input/lasips2.h
@@ -33,7 +33,6 @@ struct LASIPS2State {
#define TYPE_LASIPS2 "lasips2"
OBJECT_DECLARE_SIMPLE_TYPE(LASIPS2State, LASIPS2)
-LASIPS2State *lasips2_initfn(MemoryRegion *address_space, hwaddr base,
- qemu_irq irq);
+LASIPS2State *lasips2_initfn(hwaddr base, qemu_irq irq);
#endif /* HW_INPUT_LASIPS2_H */
--
2.30.2
[PULL 55/55] artist: set memory region owners for buffers to the artist device
This fixes the output of "info qom-tree" so that the buffers appear as children
of the artist device, rather than underneath the "unattached" container.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20220624160839.886649-1-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Helge Deller
---
hw/display/artist.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/display/artist.c b/hw/display/artist.c
index eadaef0d46..fde050c882 100644
--- a/hw/display/artist.c
+++ b/hw/display/artist.c
@@ -1358,7 +1358,7 @@ static void artist_create_buffer(ARTISTState *s, const
char *name,
{
struct vram_buffer *buf = s->vram_buffer + idx;
-memory_region_init_ram(&buf->mr, NULL, name, width * height,
+memory_region_init_ram(&buf->mr, OBJECT(s), name, width * height,
&error_fatal);
memory_region_add_subregion_overlap(&s->mem_as_root, *offset, &buf->mr, 0);
--
2.30.2
[PULL 49/55] pckbd: switch I8042_MMIO device from update_irq() function to PS2 device gpio
Define a new qdev input gpio for handling incoming PS2 IRQs, and then wire up
the
PS2 keyboard and mouse devices to use it. At the same time set update_irq() and
update_arg to NULL in ps2_kbd_init() and ps2_mouse_init() to ensure that any
accidental attempt to use the legacy update_irq() function will cause a NULL
pointer dereference.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-50-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 38 --
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 5d7c969fc6..ee306428a3 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -665,6 +665,22 @@ static const MemoryRegionOps i8042_mmio_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void i8042_mmio_set_kbd_irq(void *opaque, int n, int level)
+{
+MMIOKBDState *s = I8042_MMIO(opaque);
+KBDState *ks = &s->kbd;
+
+kbd_update_kbd_irq(ks, level);
+}
+
+static void i8042_mmio_set_mouse_irq(void *opaque, int n, int level)
+{
+MMIOKBDState *s = I8042_MMIO(opaque);
+KBDState *ks = &s->kbd;
+
+kbd_update_aux_irq(ks, level);
+}
+
static void i8042_mmio_reset(DeviceState *dev)
{
MMIOKBDState *s = I8042_MMIO(dev);
@@ -686,8 +702,14 @@ static void i8042_mmio_realize(DeviceState *dev, Error
**errp)
/* Note we can't use dc->vmsd without breaking migration compatibility */
vmstate_register(NULL, 0, &vmstate_kbd, ks);
-ks->kbd = ps2_kbd_init(kbd_update_kbd_irq, ks);
-ks->mouse = ps2_mouse_init(kbd_update_aux_irq, ks);
+ks->kbd = ps2_kbd_init(NULL, NULL);
+qdev_connect_gpio_out(DEVICE(ks->kbd), PS2_DEVICE_IRQ,
+ qdev_get_gpio_in_named(dev, "ps2-kbd-input-irq",
+ 0));
+ks->mouse = ps2_mouse_init(NULL, NULL);
+qdev_connect_gpio_out(DEVICE(ks->mouse), PS2_DEVICE_IRQ,
+ qdev_get_gpio_in_named(dev, "ps2-mouse-input-irq",
+ 0));
}
static void i8042_mmio_init(Object *obj)
@@ -696,6 +718,12 @@ static void i8042_mmio_init(Object *obj)
KBDState *ks = &s->kbd;
ks->extended_state = true;
+
+qdev_init_gpio_out(DEVICE(obj), ks->irqs, 2);
+qdev_init_gpio_in_named(DEVICE(obj), i8042_mmio_set_kbd_irq,
+"ps2-kbd-input-irq", 1);
+qdev_init_gpio_in_named(DEVICE(obj), i8042_mmio_set_mouse_irq,
+"ps2-mouse-input-irq", 1);
}
static Property i8042_mmio_properties[] = {
@@ -718,16 +746,14 @@ MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq
mouse_irq,
ram_addr_t size, hwaddr mask)
{
DeviceState *dev;
-KBDState *s;
dev = qdev_new(TYPE_I8042_MMIO);
qdev_prop_set_uint64(dev, "mask", mask);
qdev_prop_set_uint32(dev, "size", size);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-s = &I8042_MMIO(dev)->kbd;
-s->irqs[I8042_KBD_IRQ] = kbd_irq;
-s->irqs[I8042_MOUSE_IRQ] = mouse_irq;
+qdev_connect_gpio_out(dev, I8042_KBD_IRQ, kbd_irq);
+qdev_connect_gpio_out(dev, I8042_MOUSE_IRQ, mouse_irq);
return I8042_MMIO(dev);
}
--
2.30.2
[PULL 43/55] lasips2: move initialisation of PS2 ports from lasi_initfn() to lasi_init()
This can be improved once the ps2_kbd_init() and ps2_mouse_init() functions have
been removed, but for now move the existing logic from lasi_initfn() to
lasi_init(). At the same time explicitly set keyboard port id to 0, even if it
isn't technically required.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-44-mark.cave-ayl...@ilande.co.uk>
---
hw/input/lasips2.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index 84e7a1feee..bd89c03996 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -255,9 +255,6 @@ LASIPS2State *lasips2_initfn(hwaddr base, qemu_irq irq)
s = LASIPS2(dev);
s->irq = irq;
-s->mouse.id = 1;
-s->kbd.parent = s;
-s->mouse.parent = s;
vmstate_register(NULL, base, &vmstate_lasips2, s);
@@ -271,6 +268,11 @@ static void lasips2_init(Object *obj)
{
LASIPS2State *s = LASIPS2(obj);
+s->kbd.id = 0;
+s->mouse.id = 1;
+s->kbd.parent = s;
+s->mouse.parent = s;
+
memory_region_init_io(&s->kbd.reg, obj, &lasips2_reg_ops, &s->kbd,
"lasips2-kbd", 0x100);
memory_region_init_io(&s->mouse.reg, obj, &lasips2_reg_ops, &s->mouse,
--
2.30.2
[PULL 37/55] pl050: add QEMU interface comment
This describes the PL050 device interface implemented within QEMU. Signed-off-by: Mark Cave-Ayland Message-Id: <20220624134109.881989-38-mark.cave-ayl...@ilande.co.uk> Reviewed-by: Peter Maydell --- hw/input/pl050.c | 8 1 file changed, 8 insertions(+) diff --git a/hw/input/pl050.c b/hw/input/pl050.c index c665a4fc99..ffaa72dea4 100644 --- a/hw/input/pl050.c +++ b/hw/input/pl050.c @@ -7,6 +7,14 @@ * This code is licensed under the GPL. */ +/* + * QEMU interface: + * + sysbus MMIO region 0: MemoryRegion defining the PL050 registers + * + Named GPIO input "ps2-input-irq": set to 1 if the downstream PS2 device + * has asserted its irq + * + sysbus IRQ 0: PL050 output irq + */ + #include "qemu/osdep.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -- 2.30.2
[PULL 53/55] pckbd: add QEMU interface comment for I8042 device
This describes the I8042 device interface implemented within QEMU.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20220624134109.881989-54-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Peter Maydell
---
include/hw/input/i8042.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/hw/input/i8042.h b/include/hw/input/i8042.h
index d4747b62b8..ca933d8e1b 100644
--- a/include/hw/input/i8042.h
+++ b/include/hw/input/i8042.h
@@ -39,6 +39,16 @@ typedef struct KBDState {
hwaddr mask;
} KBDState;
+/*
+ * QEMU interface:
+ * + Named GPIO input "ps2-kbd-input-irq": set to 1 if the downstream PS2
+ * keyboard device has asserted its irq
+ * + Named GPIO input "ps2-mouse-input-irq": set to 1 if the downstream PS2
+ * mouse device has asserted its irq
+ * + Named GPIO output "a20": A20 line for x86 PCs
+ * + Unnamed GPIO output 0-1: i8042 output irqs for keyboard (0) or mouse (1)
+ */
+
#define TYPE_I8042 "i8042"
OBJECT_DECLARE_SIMPLE_TYPE(ISAKBDState, I8042)
--
2.30.2
[PULL 41/55] lasips2: implement lasips2_init() function
Move the initialisation of the keyboard and mouse memory regions to
lasips2_init()
and expose them as SysBus memory regions.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-42-mark.cave-ayl...@ilande.co.uk>
---
hw/input/lasips2.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index 85da4081e3..8d3a2d88e8 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -265,20 +265,30 @@ LASIPS2State *lasips2_initfn(MemoryRegion *address_space,
s->kbd.dev = ps2_kbd_init(lasips2_port_set_irq, &s->kbd);
s->mouse.dev = ps2_mouse_init(lasips2_port_set_irq, &s->mouse);
-memory_region_init_io(&s->kbd.reg, NULL, &lasips2_reg_ops, &s->kbd,
- "lasips2-kbd", 0x100);
memory_region_add_subregion(address_space, base, &s->kbd.reg);
-memory_region_init_io(&s->mouse.reg, NULL, &lasips2_reg_ops, &s->mouse,
- "lasips2-mouse", 0x100);
memory_region_add_subregion(address_space, base + 0x100, &s->mouse.reg);
return s;
}
+static void lasips2_init(Object *obj)
+{
+LASIPS2State *s = LASIPS2(obj);
+
+memory_region_init_io(&s->kbd.reg, obj, &lasips2_reg_ops, &s->kbd,
+ "lasips2-kbd", 0x100);
+memory_region_init_io(&s->mouse.reg, obj, &lasips2_reg_ops, &s->mouse,
+ "lasips2-mouse", 0x100);
+
+sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->kbd.reg);
+sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mouse.reg);
+}
+
static const TypeInfo lasips2_info = {
.name = TYPE_LASIPS2,
.parent= TYPE_SYS_BUS_DEVICE,
+.instance_init = lasips2_init,
.instance_size = sizeof(LASIPS2State)
};
--
2.30.2
[PULL 48/55] lasips2: add QEMU interface comment
This describes the LASI PS2 device interface implemented within QEMU. Signed-off-by: Mark Cave-Ayland Message-Id: <20220624134109.881989-49-mark.cave-ayl...@ilande.co.uk> Reviewed-by: Peter Maydell --- include/hw/input/lasips2.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/include/hw/input/lasips2.h b/include/hw/input/lasips2.h index 7e4437b925..03f0c9e9f9 100644 --- a/include/hw/input/lasips2.h +++ b/include/hw/input/lasips2.h @@ -4,6 +4,20 @@ * Copyright (c) 2019 Sven Schnelle * */ + +/* + * QEMU interface: + * + sysbus MMIO region 0: MemoryRegion defining the LASI PS2 keyboard + * registers + * + sysbus MMIO region 1: MemoryRegion defining the LASI PS2 mouse + * registers + * + sysbus IRQ 0: LASI PS2 output irq + * + Named GPIO input "ps2-kbd-input-irq": set to 1 if the downstream PS2 + * keyboard device has asserted its irq + * + Named GPIO input "ps2-mouse-input-irq": set to 1 if the downstream PS2 + * mouse device has asserted its irq + */ + #ifndef HW_INPUT_LASIPS2_H #define HW_INPUT_LASIPS2_H -- 2.30.2
[PULL 44/55] lasips2: add base property
This is in preparation for handling vmstate_register() within the device.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-45-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Peter Maydell
---
hw/input/lasips2.c | 17 -
include/hw/input/lasips2.h | 1 +
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index bd89c03996..81beb5b614 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -251,6 +251,7 @@ LASIPS2State *lasips2_initfn(hwaddr base, qemu_irq irq)
DeviceState *dev;
dev = qdev_new(TYPE_LASIPS2);
+qdev_prop_set_uint64(dev, "base", base);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s = LASIPS2(dev);
@@ -282,11 +283,25 @@ static void lasips2_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mouse.reg);
}
+static Property lasips2_properties[] = {
+DEFINE_PROP_UINT64("base", LASIPS2State, base, UINT64_MAX),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void lasips2_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+device_class_set_props(dc, lasips2_properties);
+set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
+}
+
static const TypeInfo lasips2_info = {
.name = TYPE_LASIPS2,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_init = lasips2_init,
-.instance_size = sizeof(LASIPS2State)
+.instance_size = sizeof(LASIPS2State),
+.class_init= lasips2_class_init,
};
static void lasips2_register_types(void)
diff --git a/include/hw/input/lasips2.h b/include/hw/input/lasips2.h
index b9723073e1..7e4437b925 100644
--- a/include/hw/input/lasips2.h
+++ b/include/hw/input/lasips2.h
@@ -25,6 +25,7 @@ typedef struct LASIPS2Port {
struct LASIPS2State {
SysBusDevice parent_obj;
+hwaddr base;
LASIPS2Port kbd;
LASIPS2Port mouse;
qemu_irq irq;
--
2.30.2
[PULL 50/55] pckbd: add QEMU interface comment for I8042_MMIO device
This describes the I8042_MMIO device interface implemented within QEMU.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20220624134109.881989-51-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Peter Maydell
---
include/hw/input/i8042.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/hw/input/i8042.h b/include/hw/input/i8042.h
index 4ba2664377..d4747b62b8 100644
--- a/include/hw/input/i8042.h
+++ b/include/hw/input/i8042.h
@@ -52,6 +52,17 @@ struct ISAKBDState {
uint8_t mouse_irq;
};
+/*
+ * QEMU interface:
+ * + sysbus MMIO region 0: MemoryRegion defining the command/status/data
+ * registers (access determined by mask property and access type)
+ * + Named GPIO input "ps2-kbd-input-irq": set to 1 if the downstream PS2
+ * keyboard device has asserted its irq
+ * + Named GPIO input "ps2-mouse-input-irq": set to 1 if the downstream PS2
+ * mouse device has asserted its irq
+ * + Unnamed GPIO output 0-1: i8042 output irqs for keyboard (0) or mouse (1)
+ */
+
#define TYPE_I8042_MMIO "i8042-mmio"
OBJECT_DECLARE_SIMPLE_TYPE(MMIOKBDState, I8042_MMIO)
--
2.30.2
[PULL 47/55] lasips2: switch over from update_irq() function to PS2 device gpio
Add a qdev gpio input in lasips2_init() by taking the existing
lasips2_port_set_irq()
function, updating it accordingly and then renaming to lasips2_set_irq(). Use
these
new qdev gpio inputs to wire up the PS2 keyboard and mouse devices.
At the same time set update_irq() and update_arg to NULL in ps2_kbd_init() and
ps2_mouse_init() to ensure that any accidental attempt to use the legacy
update_irq()
function will cause a NULL pointer dereference.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Message-Id: <20220624134109.881989-48-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Peter Maydell
---
hw/input/lasips2.c | 29 +
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index bd72505411..a6e14e0e6b 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -237,9 +237,19 @@ static const MemoryRegionOps lasips2_reg_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void lasips2_port_set_irq(void *opaque, int level)
+static void lasips2_set_kbd_irq(void *opaque, int n, int level)
{
-LASIPS2Port *port = opaque;
+LASIPS2State *s = LASIPS2(opaque);
+LASIPS2Port *port = &s->kbd;
+
+port->irq = level;
+lasips2_update_irq(port->parent);
+}
+
+static void lasips2_set_mouse_irq(void *opaque, int n, int level)
+{
+LASIPS2State *s = LASIPS2(opaque);
+LASIPS2Port *port = &s->mouse;
port->irq = level;
lasips2_update_irq(port->parent);
@@ -264,8 +274,14 @@ static void lasips2_realize(DeviceState *dev, Error **errp)
vmstate_register(NULL, s->base, &vmstate_lasips2, s);
-s->kbd.dev = ps2_kbd_init(lasips2_port_set_irq, &s->kbd);
-s->mouse.dev = ps2_mouse_init(lasips2_port_set_irq, &s->mouse);
+s->kbd.dev = ps2_kbd_init(NULL, NULL);
+qdev_connect_gpio_out(DEVICE(s->kbd.dev), PS2_DEVICE_IRQ,
+ qdev_get_gpio_in_named(dev, "ps2-kbd-input-irq",
+ 0));
+s->mouse.dev = ps2_mouse_init(NULL, NULL);
+qdev_connect_gpio_out(DEVICE(s->mouse.dev), PS2_DEVICE_IRQ,
+ qdev_get_gpio_in_named(dev, "ps2-mouse-input-irq",
+ 0));
}
static void lasips2_init(Object *obj)
@@ -286,6 +302,11 @@ static void lasips2_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mouse.reg);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+qdev_init_gpio_in_named(DEVICE(obj), lasips2_set_kbd_irq,
+"ps2-kbd-input-irq", 1);
+qdev_init_gpio_in_named(DEVICE(obj), lasips2_set_mouse_irq,
+"ps2-mouse-input-irq", 1);
}
static Property lasips2_properties[] = {
--
2.30.2
[PULL 52/55] pckbd: switch I8042 device from update_irq() function to PS2 device gpio
Define a new qdev input gpio for handling incoming PS2 IRQs, and then wire up
the
PS2 keyboard and mouse devices to use it. At the same time set update_irq() and
update_arg to NULL in ps2_kbd_init() and ps2_mouse_init() to ensure that any
accidental attempt to use the legacy update_irq() function will cause a NULL
pointer dereference.
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-53-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 37 +
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index ff76c0636d..18f27abc58 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -808,6 +808,23 @@ static const MemoryRegionOps i8042_cmd_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
+static void i8042_set_kbd_irq(void *opaque, int n, int level)
+{
+ISAKBDState *s = I8042(opaque);
+KBDState *ks = &s->kbd;
+
+kbd_update_kbd_irq(ks, level);
+}
+
+static void i8042_set_mouse_irq(void *opaque, int n, int level)
+{
+ISAKBDState *s = I8042(opaque);
+KBDState *ks = &s->kbd;
+
+kbd_update_aux_irq(ks, level);
+}
+
+
static void i8042_reset(DeviceState *dev)
{
ISAKBDState *s = I8042(dev);
@@ -827,6 +844,12 @@ static void i8042_initfn(Object *obj)
"i8042-cmd", 1);
qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
+
+qdev_init_gpio_out(DEVICE(obj), s->irqs, 2);
+qdev_init_gpio_in_named(DEVICE(obj), i8042_set_kbd_irq,
+"ps2-kbd-input-irq", 1);
+qdev_init_gpio_in_named(DEVICE(obj), i8042_set_mouse_irq,
+"ps2-mouse-input-irq", 1);
}
static void i8042_realizefn(DeviceState *dev, Error **errp)
@@ -847,14 +870,20 @@ static void i8042_realizefn(DeviceState *dev, Error
**errp)
return;
}
-s->irqs[I8042_KBD_IRQ] = isa_get_irq(isadev, isa_s->kbd_irq);
-s->irqs[I8042_MOUSE_IRQ] = isa_get_irq(isadev, isa_s->mouse_irq);
+isa_connect_gpio_out(isadev, I8042_KBD_IRQ, isa_s->kbd_irq);
+isa_connect_gpio_out(isadev, I8042_MOUSE_IRQ, isa_s->mouse_irq);
isa_register_ioport(isadev, isa_s->io + 0, 0x60);
isa_register_ioport(isadev, isa_s->io + 1, 0x64);
-s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
-s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
+s->kbd = ps2_kbd_init(NULL, NULL);
+qdev_connect_gpio_out(DEVICE(s->kbd), PS2_DEVICE_IRQ,
+ qdev_get_gpio_in_named(dev, "ps2-kbd-input-irq",
+ 0));
+s->mouse = ps2_mouse_init(NULL, NULL);
+qdev_connect_gpio_out(DEVICE(s->mouse), PS2_DEVICE_IRQ,
+ qdev_get_gpio_in_named(dev, "ps2-mouse-input-irq",
+ 0));
if (isa_s->kbd_throttle && !isa_s->kbd.extended_state) {
warn_report(TYPE_I8042 ": can't enable kbd-throttle without"
" extended-state, disabling kbd-throttle");
--
2.30.2
[PULL 51/55] pckbd: add i8042_reset() function to I8042 device
This means that it is no longer necessary to call qemu_register_reset() manually
within i8042_realizefn().
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-52-mark.cave-ayl...@ilande.co.uk>
---
hw/input/pckbd.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index ee306428a3..ff76c0636d 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -808,6 +808,14 @@ static const MemoryRegionOps i8042_cmd_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
+static void i8042_reset(DeviceState *dev)
+{
+ISAKBDState *s = I8042(dev);
+KBDState *ks = &s->kbd;
+
+kbd_reset(ks);
+}
+
static void i8042_initfn(Object *obj)
{
ISAKBDState *isa_s = I8042(obj);
@@ -854,7 +862,6 @@ static void i8042_realizefn(DeviceState *dev, Error **errp)
s->throttle_timer = timer_new_us(QEMU_CLOCK_VIRTUAL,
kbd_throttle_timeout, s);
}
-qemu_register_reset(kbd_reset, s);
}
static void i8042_build_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -900,6 +907,7 @@ static void i8042_class_initfn(ObjectClass *klass, void
*data)
AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
device_class_set_props(dc, i8042_properties);
+dc->reset = i8042_reset;
dc->realize = i8042_realizefn;
dc->vmsd = &vmstate_kbd_isa;
adevc->build_dev_aml = i8042_build_aml;
--
2.30.2
[PULL 54/55] ps2: remove update_irq() function and update_arg parameter
Now that all the PS2 devices have been converted to use GPIOs the update_irq()
callback function and the update_arg parameter can be removed.
This allows these arguments to be completely removed from ps2_kbd_init() and
ps2_mouse_init(), along with the transitional logic that was added to
ps2_raise_irq() and ps2_lower_irq().
Signed-off-by: Mark Cave-Ayland
Acked-by: Helge Deller
Reviewed-by: Peter Maydell
Message-Id: <20220624134109.881989-55-mark.cave-ayl...@ilande.co.uk>
---
hw/input/lasips2.c | 4 ++--
hw/input/pckbd.c | 8
hw/input/pl050.c | 4 ++--
hw/input/ps2.c | 25 -
include/hw/input/ps2.h | 6 ++
5 files changed, 14 insertions(+), 33 deletions(-)
diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c
index a6e14e0e6b..9223cb0af4 100644
--- a/hw/input/lasips2.c
+++ b/hw/input/lasips2.c
@@ -274,11 +274,11 @@ static void lasips2_realize(DeviceState *dev, Error
**errp)
vmstate_register(NULL, s->base, &vmstate_lasips2, s);
-s->kbd.dev = ps2_kbd_init(NULL, NULL);
+s->kbd.dev = ps2_kbd_init();
qdev_connect_gpio_out(DEVICE(s->kbd.dev), PS2_DEVICE_IRQ,
qdev_get_gpio_in_named(dev, "ps2-kbd-input-irq",
0));
-s->mouse.dev = ps2_mouse_init(NULL, NULL);
+s->mouse.dev = ps2_mouse_init();
qdev_connect_gpio_out(DEVICE(s->mouse.dev), PS2_DEVICE_IRQ,
qdev_get_gpio_in_named(dev, "ps2-mouse-input-irq",
0));
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index 18f27abc58..9184411c3e 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -702,11 +702,11 @@ static void i8042_mmio_realize(DeviceState *dev, Error
**errp)
/* Note we can't use dc->vmsd without breaking migration compatibility */
vmstate_register(NULL, 0, &vmstate_kbd, ks);
-ks->kbd = ps2_kbd_init(NULL, NULL);
+ks->kbd = ps2_kbd_init();
qdev_connect_gpio_out(DEVICE(ks->kbd), PS2_DEVICE_IRQ,
qdev_get_gpio_in_named(dev, "ps2-kbd-input-irq",
0));
-ks->mouse = ps2_mouse_init(NULL, NULL);
+ks->mouse = ps2_mouse_init();
qdev_connect_gpio_out(DEVICE(ks->mouse), PS2_DEVICE_IRQ,
qdev_get_gpio_in_named(dev, "ps2-mouse-input-irq",
0));
@@ -876,11 +876,11 @@ static void i8042_realizefn(DeviceState *dev, Error
**errp)
isa_register_ioport(isadev, isa_s->io + 0, 0x60);
isa_register_ioport(isadev, isa_s->io + 1, 0x64);
-s->kbd = ps2_kbd_init(NULL, NULL);
+s->kbd = ps2_kbd_init();
qdev_connect_gpio_out(DEVICE(s->kbd), PS2_DEVICE_IRQ,
qdev_get_gpio_in_named(dev, "ps2-kbd-input-irq",
0));
-s->mouse = ps2_mouse_init(NULL, NULL);
+s->mouse = ps2_mouse_init();
qdev_connect_gpio_out(DEVICE(s->mouse), PS2_DEVICE_IRQ,
qdev_get_gpio_in_named(dev, "ps2-mouse-input-irq",
0));
diff --git a/hw/input/pl050.c b/hw/input/pl050.c
index ffaa72dea4..209cc001cf 100644
--- a/hw/input/pl050.c
+++ b/hw/input/pl050.c
@@ -172,9 +172,9 @@ static void pl050_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
if (s->is_mouse) {
-s->dev = ps2_mouse_init(NULL, NULL);
+s->dev = ps2_mouse_init();
} else {
-s->dev = ps2_kbd_init(NULL, NULL);
+s->dev = ps2_kbd_init();
}
qdev_connect_gpio_out(DEVICE(s->dev), PS2_DEVICE_IRQ,
qdev_get_gpio_in_named(dev, "ps2-input-irq", 0));
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index 98c6206fb8..59bac28ac8 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -175,20 +175,12 @@ void ps2_queue_noirq(PS2State *s, int b)
static void ps2_raise_irq(PS2State *s)
{
-if (qemu_irq_is_connected(s->irq)) {
-qemu_set_irq(s->irq, 1);
-} else {
-s->update_irq(s->update_arg, 1);
-}
+qemu_set_irq(s->irq, 1);
}
static void ps2_lower_irq(PS2State *s)
{
-if (qemu_irq_is_connected(s->irq)) {
-qemu_set_irq(s->irq, 0);
-} else {
-s->update_irq(s->update_arg, 0);
-}
+qemu_set_irq(s->irq, 0);
}
void ps2_queue(PS2State *s, int b)
@@ -1232,21 +1224,16 @@ static void ps2_kbd_realize(DeviceState *dev, Error
**errp)
qemu_input_handler_register(dev, &ps2_keyboard_handler);
}
-void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg)
+void *ps2_kbd_init(void)
{
DeviceState *dev;
PS2KbdState *s;
-PS2State *ps2;
dev = qdev_new(TYPE_PS2_KBD_DEVICE);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s = PS2_KBD_DEVICE(dev);
-ps2 = PS2_DEVICE(s);
trace_ps2_kbd_init(s);
-ps2->upda
[RFC v3 0/5] *** Add support for zoned device ***
*** This patch series adds support for zoned device to virtio-blk emulation. Zoned Storage can support sequential writes, which reduces write amplification in SSD, leading to higher write throughput and increased capacity. v3: - add block layer APIs resembling Linux ZoneBlockDevice ioctls (developing) *** Sam Li (5): block: add block layer APIs resembling Linux ZonedBlockDevice ioctls. qemu-io: add zoned block device operations. file-posix: introduce get_sysfs_long_val for zoned device information. file-posix: introduce get_sysfs_str_val for device zoned model. qemu-iotests: add zone operation tests. block/block-backend.c | 56 + block/coroutines.h| 5 + block/file-posix.c| 325 +- block/io.c| 21 ++ include/block/block-common.h | 43 +++- include/block/block-io.h | 13 ++ include/block/block_int-common.h | 20 ++ qemu-io-cmds.c| 121 +++ tests/qemu-iotests/tests/zoned.sh | 49 + 9 files changed, 645 insertions(+), 8 deletions(-) create mode 100755 tests/qemu-iotests/tests/zoned.sh -- 2.35.3
[RFC v3 4/5] file-posix: introduce get_sysfs_str_val for device zoned model.
---
block/file-posix.c | 60
include/block/block-common.h | 4 +--
2 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/block/file-posix.c b/block/file-posix.c
index 73c2cdfbca..74c0245e0f 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -1277,6 +1277,66 @@ out:
#endif
}
+/*
+ * Convert the zoned attribute file in sysfs to internal value.
+ */
+static zone_model get_sysfs_str_val(int fd, struct stat *st) {
+#ifdef CONFIG_LINUX
+char buf[32];
+char *sysfspath = NULL;
+int ret;
+int sysfd = -1;
+
+if (S_ISCHR(st->st_mode)) {
+if (ioctl(fd, SG_GET_SG_TABLESIZE, &ret) == 0) {
+return ret;
+}
+return -ENOTSUP;
+}
+
+if (!S_ISBLK(st->st_mode)) {
+return -ENOTSUP;
+}
+
+sysfspath = g_strdup_printf("/sys/dev/block/%u:%u/queue/zoned",
+major(st->st_rdev), minor(st->st_rdev));
+sysfd = open(sysfspath, O_RDONLY);
+if (sysfd == -1) {
+ret = -errno;
+goto out;
+}
+do {
+ret = read(sysfd, buf, sizeof(buf) - 1);
+} while (ret == -1 && errno == EINTR);
+if (ret < 0) {
+ret = -errno;
+goto out;
+} else if (ret == 0) {
+ret = -EIO;
+goto out;
+}
+buf[ret] = 0;
+
+/* The file is ended with '\n' */
+if (strcmp(buf, "host-managed\n") == 0) {
+return BLK_Z_HM;
+} else if (strcmp(buf, "host-aware\n") == 0) {
+return BLK_Z_HA;
+} else {
+return -ENOTSUP;
+}
+
+out:
+if (sysfd != -1) {
+close(sysfd);
+}
+g_free(sysfspath);
+return ret;
+#else
+return -ENOTSUP;
+#endif
+}
+
static int hdev_get_max_segments(int fd, struct stat *st) {
int ret;
ret = get_sysfs_long_val(fd, st, "max_segments");
diff --git a/include/block/block-common.h b/include/block/block-common.h
index 78cddeeda5..35e00afe8e 100644
--- a/include/block/block-common.h
+++ b/include/block/block-common.h
@@ -56,8 +56,8 @@ typedef enum zone_op {
} zone_op;
typedef enum zone_model {
-BLK_Z_HM,
-BLK_Z_HA,
+BLK_Z_HM = 0x1,
+BLK_Z_HA = 0x2,
} zone_model;
typedef enum BlkZoneCondition {
--
2.35.3
[RFC v3 2/5] qemu-io: add zoned block device operations.
---
block/io.c | 21 +++
include/block/block-io.h | 13 +
qemu-io-cmds.c | 121 +++
3 files changed, 155 insertions(+)
diff --git a/block/io.c b/block/io.c
index 789e6373d5..656a1b7271 100644
--- a/block/io.c
+++ b/block/io.c
@@ -3258,6 +3258,27 @@ out:
return co.ret;
}
+int bdrv_co_zone_report(BlockDriverState *bs, int64_t offset,
+int64_t len, int64_t *nr_zones,
+BlockZoneDescriptor *zones)
+{
+if (!bs->drv->bdrv_co_zone_report) {
+return -ENOTSUP;
+}
+
+return bs->drv->bdrv_co_zone_report(bs, offset, len, nr_zones, zones);
+}
+
+int bdrv_co_zone_mgmt(BlockDriverState *bs, enum zone_op op,
+int64_t offset, int64_t len)
+{
+if (!bs->drv->bdrv_co_zone_mgmt) {
+return -ENOTSUP;
+}
+
+return bs->drv->bdrv_co_zone_mgmt(bs, op, offset, len);
+}
+
void *qemu_blockalign(BlockDriverState *bs, size_t size)
{
IO_CODE();
diff --git a/include/block/block-io.h b/include/block/block-io.h
index 62c84f0519..c85c174579 100644
--- a/include/block/block-io.h
+++ b/include/block/block-io.h
@@ -80,6 +80,13 @@ int bdrv_co_ioctl(BlockDriverState *bs, int req, void *buf);
/* Ensure contents are flushed to disk. */
int coroutine_fn bdrv_co_flush(BlockDriverState *bs);
+/* Report zone information of zone block device. */
+int coroutine_fn bdrv_co_zone_report(BlockDriverState *bs, int64_t offset,
+ int64_t len, int64_t *nr_zones,
+ BlockZoneDescriptor *zones);
+int coroutine_fn bdrv_co_zone_mgmt(BlockDriverState *bs, zone_op op,
+int64_t offset, int64_t len);
+
int bdrv_co_pdiscard(BdrvChild *child, int64_t offset, int64_t bytes);
bool bdrv_can_write_zeroes_with_unmap(BlockDriverState *bs);
int bdrv_block_status(BlockDriverState *bs, int64_t offset,
@@ -290,6 +297,12 @@ bdrv_readv_vmstate(BlockDriverState *bs, QEMUIOVector
*qiov, int64_t pos);
int generated_co_wrapper
bdrv_writev_vmstate(BlockDriverState *bs, QEMUIOVector *qiov, int64_t pos);
+int generated_co_wrapper blk_zone_report(BlockBackend *blk, int64_t offset,
+ int64_t len, int64_t *nr_zones,
+ BlockZoneDescriptor *zones);
+int generated_co_wrapper blk_zone_mgmt(BlockBackend *blk, enum zone_op op,
+int64_t offset, int64_t len);
+
/**
* bdrv_parent_drained_begin_single:
*
diff --git a/qemu-io-cmds.c b/qemu-io-cmds.c
index 2f0d8ac25a..3f2592b9f5 100644
--- a/qemu-io-cmds.c
+++ b/qemu-io-cmds.c
@@ -1706,6 +1706,122 @@ static const cmdinfo_t flush_cmd = {
.oneline= "flush all in-core file state to disk",
};
+static int zone_report_f(BlockBackend *blk, int argc, char **argv)
+{
+int ret;
+int64_t offset, len, nr_zones;
+int i = 0;
+
+++optind;
+offset = cvtnum(argv[optind]);
+++optind;
+len = cvtnum(argv[optind]);
+++optind;
+nr_zones = cvtnum(argv[optind]);
+
+g_autofree BlockZoneDescriptor *zones = g_new(BlockZoneDescriptor,
nr_zones);
+ret = blk_zone_report(blk, offset, len, &nr_zones, zones);
+while (i < nr_zones) {
+fprintf(stdout, "start: 0x%lx, len 0x%lx, cap 0x%lx, wptr 0x%lx, "
+"zcond:%u, [type: %u]\n",
+zones[i].start, zones[i].length, zones[i].cap, zones[i].wp,
+zones[i].cond, zones[i].type);
+++i;
+}
+return ret;
+}
+
+static const cmdinfo_t zone_report_cmd = {
+.name = "zone_report",
+.altname = "f",
+.cfunc = zone_report_f,
+.argmin = 3,
+.argmax = 3,
+.args = "offset [offset..] len [len..] number [num..]",
+.oneline = "report a number of zones",
+};
+
+static int zone_open_f(BlockBackend *blk, int argc, char **argv)
+{
+int64_t offset, len;
+++optind;
+offset = cvtnum(argv[optind]);
+++optind;
+len = cvtnum(argv[optind]);
+return blk_zone_mgmt(blk, zone_open, offset, len);
+}
+
+static const cmdinfo_t zone_open_cmd = {
+.name = "zone_open",
+.altname = "f",
+.cfunc = zone_open_f,
+.argmin = 2,
+.argmax = 2,
+.args = "offset [offset..] len [len..]",
+.oneline = "explicit open a range of zones in zone block device",
+};
+
+static int zone_close_f(BlockBackend *blk, int argc, char **argv)
+{
+int64_t offset, len;
+++optind;
+offset = cvtnum(argv[optind]);
+++optind;
+len = cvtnum(argv[optind]);
+return blk_zone_mgmt(blk, zone_close, offset, len);
+}
+
+static const cmdinfo_t zone_close_cmd = {
+.name = "zone_close",
+.altname = "f",
+.cfunc = zone_close_f,
+.argmin = 2,
+.argmax = 2,
+.args = "offset [offset..] len [len..]",
+.oneline = "close a range of zones in zone block device",
+};
+
+static int zone_finish_f(BlockBackend *blk, int argc, char **arg
[RFC v3 1/5] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls.
By adding zone management operations in BlockDriver, storage
controller emulation can use the new block layer APIs including
zone_report and zone_mgmt(open, close, finish, reset).
---
block/block-backend.c| 56
block/coroutines.h | 5 +
block/file-posix.c | 238 +++
include/block/block-common.h | 43 +-
include/block/block_int-common.h | 20 +++
5 files changed, 361 insertions(+), 1 deletion(-)
diff --git a/block/block-backend.c b/block/block-backend.c
index e0e1aff4b1..786f964d02 100644
--- a/block/block-backend.c
+++ b/block/block-backend.c
@@ -1810,6 +1810,62 @@ int blk_flush(BlockBackend *blk)
return ret;
}
+/*
+ * Return zone_report from BlockDriver. Offset can be any number within
+ * the zone size. No alignment for offset and len.
+ */
+int coroutine_fn blk_co_zone_report(BlockBackend *blk, int64_t offset,
+ int64_t len, int64_t *nr_zones,
+ BlockZoneDescriptor *zones)
+{
+int ret;
+BlockDriverState *bs;
+IO_CODE();
+
+blk_inc_in_flight(blk); /* increase before waiting */
+blk_wait_while_drained(blk);
+bs = blk_bs(blk);
+
+ret = blk_check_byte_request(blk, offset, len);
+if (ret < 0) {
+return ret;
+}
+
+bdrv_inc_in_flight(bs);
+ret = bdrv_co_zone_report(blk->root->bs, offset, len,
+ nr_zones, zones);
+bdrv_dec_in_flight(bs);
+blk_dec_in_flight(blk);
+return ret;
+}
+
+/*
+ * Return zone_mgmt from BlockDriver.
+ * Offset is the start of a zone and len is aligned to zones.
+ */
+int coroutine_fn blk_co_zone_mgmt(BlockBackend *blk, enum zone_op op,
+int64_t offset, int64_t len)
+{
+int ret;
+BlockDriverState *bs;
+IO_CODE();
+
+blk_inc_in_flight(blk);
+blk_wait_while_drained(blk);
+bs = blk_bs(blk);
+
+ret = blk_check_byte_request(blk, offset, len);
+if (ret < 0) {
+return ret;
+}
+
+bdrv_inc_in_flight(bs);
+ret = bdrv_co_zone_mgmt(blk->root->bs, op, offset, len);
+bdrv_dec_in_flight(bs);
+blk_dec_in_flight(blk);
+return ret;
+}
+
void blk_drain(BlockBackend *blk)
{
BlockDriverState *bs = blk_bs(blk);
diff --git a/block/coroutines.h b/block/coroutines.h
index 830ecaa733..a114d7bc30 100644
--- a/block/coroutines.h
+++ b/block/coroutines.h
@@ -80,6 +80,11 @@ int coroutine_fn
blk_co_do_pdiscard(BlockBackend *blk, int64_t offset, int64_t bytes);
int coroutine_fn blk_co_do_flush(BlockBackend *blk);
+int coroutine_fn blk_co_zone_report(BlockBackend *blk, int64_t offset,
+int64_t len, int64_t *nr_zones,
+BlockZoneDescriptor *zones);
+int coroutine_fn blk_co_zone_mgmt(BlockBackend *blk, enum zone_op op,
+int64_t offset, int64_t len);
/*
diff --git a/block/file-posix.c b/block/file-posix.c
index 48cd096624..1b8b0d351f 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -67,6 +67,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -216,6 +217,11 @@ typedef struct RawPosixAIOData {
PreallocMode prealloc;
Error **errp;
} truncate;
+struct {
+int64_t *nr_zones;
+BlockZoneDescriptor *zones;
+} zone_report;
+zone_op op;
};
} RawPosixAIOData;
@@ -1801,6 +1807,135 @@ static off_t copy_file_range(int in_fd, off_t *in_off,
int out_fd,
}
#endif
+/*
+ * parse_zone - Fill a zone descriptor
+ */
+static inline void parse_zone(struct BlockZoneDescriptor *zone,
+ struct blk_zone *blkz) {
+zone->start = blkz->start;
+zone->length = blkz->len;
+zone->cap = blkz->capacity;
+zone->wp = blkz->wp - blkz->start;
+zone->type = blkz->type;
+zone->cond = blkz->cond;
+}
+
+static int handle_aiocb_zone_report(void *opaque) {
+RawPosixAIOData *aiocb = opaque;
+int fd = aiocb->aio_fildes;
+int64_t *nr_zones = aiocb->zone_report.nr_zones;
+BlockZoneDescriptor *zones = aiocb->zone_report.zones;
+int64_t offset = aiocb->aio_offset;
+int64_t len = aiocb->aio_nbytes;
+
+struct blk_zone *blkz;
+int64_t rep_size, nrz;
+int ret, n = 0, i = 0;
+
+nrz = *nr_zones;
+if (len == -1) {
+return -errno;
+}
+rep_size = sizeof(struct blk_zone_report) + nrz * sizeof(struct blk_zone);
+g_autofree struct blk_zone_report *rep = g_new(struct blk_zone_report,
nrz);
+offset = offset / 512; /* get the unit of the start sector: sector size is
512 bytes. */
+printf("start to report zone with offset: 0x%lx\n", offset);
+
+blkz = (struct blk_zone *)(rep + 1);
+while (n < nrz) {
+memset(rep, 0, rep_size);
+rep->sector = offset;
+rep->nr_zones = nrz;
+
+ret = ioctl(fd, BLKREPORTZONE, rep);
+if (ret != 0) {
+ret = -errno;
+error_report("%d: ioct
[RFC v3 5/5] qemu-iotests: add zone operation tests.
--- tests/qemu-iotests/tests/zoned.sh | 49 +++ 1 file changed, 49 insertions(+) create mode 100755 tests/qemu-iotests/tests/zoned.sh diff --git a/tests/qemu-iotests/tests/zoned.sh b/tests/qemu-iotests/tests/zoned.sh new file mode 100755 index 00..262c0b5427 --- /dev/null +++ b/tests/qemu-iotests/tests/zoned.sh @@ -0,0 +1,49 @@ +#!/usr/bin/env bash +# +# Test zone management operations. +# + +QEMU_IO="build/qemu-io" +IMG="--image-opts driver=zoned_host_device,filename=/dev/nullb0" +QEMU_IO_OPTIONS=$QEMU_IO_OPTIONS_NO_FMT + +echo "Testing a null_blk device" +echo "Simple cases: if the operations work" +sudo modprobe null_blk nr_devices=1 zoned=1 +# hidden issues: +# 1. memory allocation error of "unaligned tcache chunk detected" when the nr_zone=1 in zone report +# 2. qemu-io: after report 10 zones, the program failed at double free error and exited. +echo "report the first zone" +sudo $QEMU_IO $IMG -c "zone_report 0 0 1" +echo "report: the first 10 zones" +sudo $QEMU_IO $IMG -c "zone_report 0 0 10" + +echo "open the first zone" +sudo $QEMU_IO $IMG -c "zone_open 0 0x8" +echo "report after:" +sudo $QEMU_IO $IMG -c "zone_report 0 0 1" +echo "open the last zone" +sudo $QEMU_IO $IMG -c "zone_open 0x3e7000 0x8" +echo "report after:" +sudo $QEMU_IO $IMG -c "zone_report 0x3e7000 0 2" + +echo "close the first zone" +sudo $QEMU_IO $IMG -c "zone_close 0 0x8" +echo "report after:" +sudo $QEMU_IO $IMG -c "zone_report 0 0 1" +echo "close the last zone" +sudo $QEMU_IO $IMG -c "zone_close 0x3e7000 0x8" +echo "report after:" +sudo $QEMU_IO $IMG -c "zone_report 0x3e7000 0 2" + + +echo "reset the second zone" +sudo $QEMU_IO $IMG -c "zone_reset 0x8 0x8" +echo "After resetting a zone:" +sudo $QEMU_IO $IMG -c "zone_report 0x8 0 5" + +# success, all done +sudo rmmod null_blk +echo "*** done" +#rm -f $seq.full +status=0 -- 2.35.3
[RFC v3 3/5] file-posix: introduce get_sysfs_long_val for zoned device information.
Use sysfs attribute files to get the zoned device information in case
that ioctl() commands of zone management interface won't work. It can
return long type of value like chunk_sectors, zoned_append_max_bytes,
max_open_zones, max_active_zones.
---
block/file-posix.c | 37 +
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/block/file-posix.c b/block/file-posix.c
index 1b8b0d351f..73c2cdfbca 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -1216,15 +1216,19 @@ static int hdev_get_max_hw_transfer(int fd, struct stat
*st)
#endif
}
-static int hdev_get_max_segments(int fd, struct stat *st)
-{
+/*
+ * Get zoned device information (chunk_sectors, zoned_append_max_bytes,
+ * max_open_zones, max_active_zones) through sysfs attribute files.
+ */
+static long get_sysfs_long_val(int fd, struct stat *st,
+ const char *attribute) {
#ifdef CONFIG_LINUX
char buf[32];
const char *end;
char *sysfspath = NULL;
int ret;
int sysfd = -1;
-long max_segments;
+long val;
if (S_ISCHR(st->st_mode)) {
if (ioctl(fd, SG_GET_SG_TABLESIZE, &ret) == 0) {
@@ -1237,8 +1241,9 @@ static int hdev_get_max_segments(int fd, struct stat *st)
return -ENOTSUP;
}
-sysfspath = g_strdup_printf("/sys/dev/block/%u:%u/queue/max_segments",
-major(st->st_rdev), minor(st->st_rdev));
+sysfspath = g_strdup_printf("/sys/dev/block/%u:%u/queue/%s",
+major(st->st_rdev), minor(st->st_rdev),
+attribute);
sysfd = open(sysfspath, O_RDONLY);
if (sysfd == -1) {
ret = -errno;
@@ -1256,9 +1261,9 @@ static int hdev_get_max_segments(int fd, struct stat *st)
}
buf[ret] = 0;
/* The file is ended with '\n', pass 'end' to accept that. */
-ret = qemu_strtol(buf, &end, 10, &max_segments);
+ret = qemu_strtol(buf, &end, 10, &val);
if (ret == 0 && end && *end == '\n') {
-ret = max_segments;
+ret = val;
}
out:
@@ -1272,6 +1277,15 @@ out:
#endif
}
+static int hdev_get_max_segments(int fd, struct stat *st) {
+int ret;
+ret = get_sysfs_long_val(fd, st, "max_segments");
+if (ret < 0) {
+return -1;
+}
+return ret;
+}
+
static void raw_refresh_limits(BlockDriverState *bs, Error **errp)
{
BDRVRawState *s = bs->opaque;
@@ -1872,6 +1886,7 @@ static int handle_aiocb_zone_report(void *opaque) {
static int handle_aiocb_zone_mgmt(void *opaque) {
RawPosixAIOData *aiocb = opaque;
+BlockDriverState *s = aiocb->bs;
int fd = aiocb->aio_fildes;
int64_t offset = aiocb->aio_offset;
int64_t len = aiocb->aio_nbytes;
@@ -1884,11 +1899,9 @@ static int handle_aiocb_zone_mgmt(void *opaque) {
int64_t zone_size_mask;
int ret;
-ret = ioctl(fd, BLKGETZONESZ, &zone_size);
-if (ret) {
-return -1;
-}
-
+g_autofree struct stat *file = g_new(struct stat, 1);
+stat(s->filename, file);
+zone_size = get_sysfs_long_val(fd, file, "chunk_sectors");
zone_size_mask = zone_size - 1;
if (offset & zone_size_mask) {
error_report("offset is not the start of a zone");
--
2.35.3
Re: [PATCH] hw/riscv: boot: Reduce FDT address alignment constraints
On Thu, Jun 23, 2022 at 3:45 PM Atish Kumar Patra wrote: > > On Wed, Jun 22, 2022 at 9:15 PM Alistair Francis wrote: > > > > On Wed, Jun 8, 2022 at 4:41 PM Bin Meng wrote: > > > > > > +Atish > > > > > > On Wed, Jun 8, 2022 at 2:20 PM Alistair Francis > > > wrote: > > > > > > > > From: Alistair Francis > > > > > > > > We previously stored the device tree at a 16MB alignment from the end of > > > > memory (or 3GB). This means we need at least 16MB of memory to be able > > > > to do this. We don't actually need the FDT to be 16MB aligned, so let's > > > > drop it down to 2MB so that we can support systems with less memory, > > > > while also allowing FDT size expansion. > > > > > > > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/992 > > > > Signed-off-by: Alistair Francis > > > > --- > > > > hw/riscv/boot.c | 4 ++-- > > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > > > index 57a41df8e9..e476d8f491 100644 > > > > --- a/hw/riscv/boot.c > > > > +++ b/hw/riscv/boot.c > > > > @@ -226,11 +226,11 @@ uint64_t riscv_load_fdt(hwaddr dram_base, > > > > uint64_t mem_size, void *fdt) > > > > /* > > > > * We should put fdt as far as possible to avoid kernel/initrd > > > > overwriting > > > > * its content. But it should be addressable by 32 bit system as > > > > well. > > > > - * Thus, put it at an 16MB aligned address that less than fdt size > > > > from the > > > > + * Thus, put it at an 2MB aligned address that less than fdt size > > > > from the > > > > * end of dram or 3GB whichever is lesser. > > > > */ > > > > temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : > > > > dram_end; > > > > -fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB); > > > > +fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); > > > > > > > > > > @Atish Patra may have some pointers about the 16MiB alignment > > > requirement. > > > > Sorry. I missed this patch for some reason. 16MiB alignment was just > chosen as a safe option. > We couldn't put it at the end of DRAM and I just wanted to place it at > a reasonable distance. > > 2MB should be totally okay. Can I get a review or Ack :) Alistair > > > Any thoughts? > > > > Alistair > > > > > > > > Regards, > > > Bin
Re: [PATCH v6 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
On Sat, Jun 11, 2022 at 6:06 PM Anup Patel wrote:
>
> We should write transformed instruction encoding of the trapped
> instruction in [m|h]tinst CSR at time of taking trap as defined
> by the RISC-V privileged specification v1.12.
>
> Signed-off-by: Anup Patel
> ---
> target/riscv/cpu.h| 3 +
> target/riscv/cpu_helper.c | 214 --
> target/riscv/instmap.h| 45
> 3 files changed, 256 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7d6397acdf..cac9e1876c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -271,6 +271,9 @@ struct CPUArchState {
> /* Signals whether the current exception occurred with two-stage address
> translation active. */
> bool two_stage_lookup;
> +/* Signals whether the current exception occurred while doing two-stage
> + address translation for the VS-stage page table walk. */
Wrong comment style, otherwise
Reviewed-by: Alistair Francis
I can fix this up when I apply the series (unless you need to spin a
new version)
Alistair
> +bool two_stage_indirect_lookup;
>
> target_ulong scounteren;
> target_ulong mcounteren;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 4a6700c890..3c8ebecf84 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -22,6 +22,7 @@
> #include "qemu/main-loop.h"
> #include "cpu.h"
> #include "exec/exec-all.h"
> +#include "instmap.h"
> #include "tcg/tcg-op.h"
> #include "trace.h"
> #include "semihosting/common-semi.h"
> @@ -1057,7 +1058,8 @@ restart:
>
> static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
> MMUAccessType access_type, bool
> pmp_violation,
> -bool first_stage, bool two_stage)
> +bool first_stage, bool two_stage,
> +bool two_stage_indirect)
> {
> CPUState *cs = env_cpu(env);
> int page_fault_exceptions, vm;
> @@ -1107,6 +1109,7 @@ static void raise_mmu_exception(CPURISCVState *env,
> target_ulong address,
> }
> env->badaddr = address;
> env->two_stage_lookup = two_stage;
> +env->two_stage_indirect_lookup = two_stage_indirect;
> }
>
> hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> @@ -1152,6 +1155,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs,
> hwaddr physaddr,
> env->badaddr = addr;
> env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
> riscv_cpu_two_stage_lookup(mmu_idx);
> +env->two_stage_indirect_lookup = false;
> cpu_loop_exit_restore(cs, retaddr);
> }
>
> @@ -1177,6 +1181,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr
> addr,
> env->badaddr = addr;
> env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
> riscv_cpu_two_stage_lookup(mmu_idx);
> +env->two_stage_indirect_lookup = false;
> cpu_loop_exit_restore(cs, retaddr);
> }
>
> @@ -1192,6 +1197,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> bool pmp_violation = false;
> bool first_stage_error = true;
> bool two_stage_lookup = false;
> +bool two_stage_indirect_error = false;
> int ret = TRANSLATE_FAIL;
> int mode = mmu_idx;
> /* default TLB page size */
> @@ -1229,6 +1235,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> */
> if (ret == TRANSLATE_G_STAGE_FAIL) {
> first_stage_error = false;
> +two_stage_indirect_error = true;
> access_type = MMU_DATA_LOAD;
> }
>
> @@ -1312,12 +1319,182 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> raise_mmu_exception(env, address, access_type, pmp_violation,
> first_stage_error,
> riscv_cpu_virt_enabled(env) ||
> -riscv_cpu_two_stage_lookup(mmu_idx));
> +riscv_cpu_two_stage_lookup(mmu_idx),
> +two_stage_indirect_error);
> cpu_loop_exit_restore(cs, retaddr);
> }
>
> return true;
> }
> +
> +static target_ulong riscv_transformed_insn(CPURISCVState *env,
> + target_ulong insn,
> + bool addr_offset_nonzero,
> + target_ulong taddr)
> +{
> +target_ulong xinsn = 0, xinsn_access_bits = 0;
> +
> +/*
> + * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to
> + * be uncompressed. The Quadrant 1 of RVC instruction space need
> + * not be transformed because these instructions won't generate
> + * any load/store trap.
> + */
> +
> +if ((insn & 0x3) != 0x3) {
> +/* Transform 16bit instruction into 32bit
Re: [PATCH v6 4/4] target/riscv: Force disable extensions if priv spec version does not match
On Sat, Jun 11, 2022 at 6:07 PM Anup Patel wrote:
>
> We should disable extensions in riscv_cpu_realize() if minimum required
> priv spec version is not satisfied. This also ensures that machines with
> priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
> extensions.
>
> Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the device
> tree")
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 144 +++--
> 1 file changed, 88 insertions(+), 56 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8db0f0bd49..a17bc98662 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -43,9 +43,82 @@ static const char riscv_single_letter_exts[] =
> "IEMAFDQCPVH";
>
> struct isa_ext_data {
> const char *name;
> -bool enabled;
> +bool multi_letter;
> +int min_version;
> +int ext_enable_offset;
> };
>
> +#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
> +{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
> +
> +/**
> + * Here are the ordering rules of extension naming defined by RISC-V
> + * specification :
> + * 1. All extensions should be separated from other multi-letter extensions
> + *by an underscore.
> + * 2. The first letter following the 'Z' conventionally indicates the most
> + *closely related alphabetical extension category, IMAFDQLCBKJTPVH.
> + *If multiple 'Z' extensions are named, they should be ordered first
> + *by category, then alphabetically within a category.
> + * 3. Standard supervisor-level extensions (starts with 'S') should be
> + *listed after standard unprivileged extensions. If multiple
> + *supervisor-level extensions are listed, they should be ordered
> + *alphabetically.
> + * 4. Non-standard extensions (starts with 'X') must be listed after all
> + *standard extensions. They must be separated from other multi-letter
> + *extensions by an underscore.
> + */
> +static const struct isa_ext_data isa_edata_arr[] = {
> +ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
> +ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v),
> +ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
> +ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
> +ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
> +ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
> +ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
> +ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
> +ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
> +ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
> +ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
> +ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb),
> +ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc),
> +ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx),
> +ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs),
> +ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk),
> +ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn),
> +ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd),
> +ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne),
> +ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh),
> +ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr),
> +ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks),
> +ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed),
> +ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh),
> +ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
> +ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
> +ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
> +ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
> +ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
> +ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
> +ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
> +ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
> +};
> +
> +static bool isa_ext_is_enabled(RISCVCPU *cpu,
> + const struct isa_ext_data *edata)
> +{
> +bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
> +
> +return *ext_enabled;
> +}
> +
> +static void isa_ext_update_enabled(RISCVCPU *cpu,
> + const struct isa_ext_data *edata, bool en)
> +{
> +bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
> +
> +*ext_enabled = en;
> +}
> +
> const char * const riscv_int_regnames[] = {
>"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
>
Intermittent meson failures on msys2
Hi guys, There's an occasional failure on msys2, where meson fails to capture the output of a build script. E.g. https://gitlab.com/qemu-project/qemu/-/jobs/2642051161 FAILED: ui/input-keymap-qcode-to-linux.c.inc "C:/GitLab-Runner/builds/qemu-project/qemu/msys64/mingw64/bin/python3.exe" "C:/GitLab-Runner/builds/qemu-project/qemu/meson/meson.py" "--internal" "exe" "--capture" "ui/input-keymap-qcode-to-linux.c.inc" "--" "C:/GitLab-Runner/builds/qemu-project/qemu/msys64/mingw64/bin/python3.exe" "../ui/keycodemapdb/tools/keymap-gen" "code-map" "--lang" "glib2" "--varname" "qemu_input_map_qcode_to_linux" "../ui/keycodemapdb/data/keymaps.csv" "qcode" "linux" [301/1665] Generating input-keymap-qcode-to-qnum.c.inc with a custom command (wrapped by meson to capture output) ninja: build stopped: subcommand failed. https://gitlab.com/qemu-project/qemu/-/jobs/2625836697 FAILED: ui/shader/texture-blit-frag.h "C:/GitLab-Runner/builds/qemu-project/qemu/msys64/mingw64/bin/python3.exe" "C:/GitLab-Runner/builds/qemu-project/qemu/meson/meson.py" "--internal" "exe" "--capture" "ui/shader/texture-blit-frag.h" "--" "perl" "C:/GitLab-Runner/builds/qemu-project/qemu/scripts/shaderinclude.pl" "../ui/shader/texture-blit.frag" [313/1663] Generating texture-blit-vert.h with a custom command (wrapped by meson to capture output) ninja: build stopped: subcommand failed. Could you have a look please? r~
Re: [PATCH v6 0/4] QEMU RISC-V nested virtualization fixes
On Sat, Jun 11, 2022 at 6:20 PM Anup Patel wrote: > > This series does fixes and improvements to have nested virtualization > on QEMU RISC-V. > > These patches can also be found in riscv_nested_fixes_v6 branch at: > https://github.com/avpatel/qemu.git > > The RISC-V nested virtualization was tested on QEMU RISC-V using > Xvisor RISC-V which has required hypervisor support to run another > hypervisor as Guest/VM. > > Changes since v5: > - Correctly set "Addr. Offset" for misaligned load/store traps in PATCH3 > - Use offsetof() instead of pointer in PATCH4 > > Changes since v4: > - Updated commit description in PATCH1, PATCH2, and PATCH4 > - Use "const" for local array in PATCH5 > > Changes since v3: > - Updated PATCH3 to set special pseudoinstructions in htinst for >guest page faults which result due to VS-stage page table walks > - Updated warning message in PATCH4 > > Changes since v2: > - Dropped the patch which are already in Alistair's next branch > - Set "Addr. Offset" in the transformed instruction for PATCH3 > - Print warning in riscv_cpu_realize() if we are disabling an >extension due to privilege spec verions mismatch for PATCH4 > > Changes since v1: > - Set write_gva to env->two_stage_lookup which ensures that for >HS-mode to HS-mode trap write_gva is true only for HLV/HSV >instructions > - Included "[PATCH 0/3] QEMU RISC-V priv spec version fixes" >patches in this series for easy review > - Re-worked PATCH7 to force disable extensions if required >priv spec version is not staisfied > - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine > > Anup Patel (4): > target/riscv: Don't force update priv spec version to latest > target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or > higher > target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() > target/riscv: Force disable extensions if priv spec version does not > match Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c| 154 --- > target/riscv/cpu.h| 3 + > target/riscv/cpu_bits.h | 3 + > target/riscv/cpu_helper.c | 214 -- > target/riscv/csr.c| 2 + > target/riscv/instmap.h| 45 > 6 files changed, 356 insertions(+), 65 deletions(-) > > -- > 2.34.1 > >
QEMU Disassembler
Hello all, How can I call the QEMU disassembler to run on an argument set of bytes?
virgl avocado hang
Hi Mark, +def test_virtio_vga_virgl(self): +""" +:avocado: tags=arch:x86_64 +:avocado: tags=device:virtio-vga +""" +kernel_command_line = ( +self.KERNEL_COMMON_COMMAND_LINE + "console=ttyS0 rdinit=/bin/bash" +) +# FIXME: should check presence of virtio, virgl etc This little nugget really must be fixed. The observed behaviour is an indefinite hang in avocado, waiting for qemu, which is in zombie state. A manual kill -INT to the parent wakes it up like so: (159/184) tests/avocado/virtio-gpu.py:VirtioGPUx86.test_virtio_vga_virgl: CANCEL: VirGL not enabled? (1264.25 s) r~
[PATCH v10 0/4] cutils: Introduce bundle mechanism
Developers often run QEMU without installing. The bundle mechanism allows to look up files which should be present in installation even in such a situation. It is a general mechanism and can find any files located relative to the installation tree. The build tree must have a new directory, qemu-bundle, to represent what files the installation tree would have for reference by the executables. Note that this abandons compatibility with Windows older than 8 to use PathCchSkipRoot(). The extended support for the prior version, 7 ended more than 2 years ago, and it is unlikely that anyone would like to run the latest QEMU on such an old system. v10: * Update destdir_join() in scripts/symlink-install-tree.py with the latest implementation from Meson: https://github.com/mesonbuild/meson/pull/10531 v9: * Update _WIN32_WINNT in include/qemu/osdep.h (Thomas Huth) v8: * Pass absolute paths to get_relocated_path() (Paolo Bonzini) * Use meson introspection (Paolo Bonzini) * Drop "qga: Relocate a path emitted in the help text" as it is no longer relevant for the bundle mechanism. v7: Properly fix --firmwarepath (Daniel P. Berrangé) v6: Reuse get_relocated_path() in find_bundle() (Paolo Bonzini) v5: * Prefer qemu-bundle if it exists. (Daniel P. Berrangé) * Check install_blobs option before installing BIOSes (Paolo Bonzini) * Add common code to set up qemu-bundle to the top level meson.build (Paolo Bonzini) v4: * Add Daniel P. Berrangé to CC. Hopefully this helps merging his patch: https://mail.gnu.org/archive/html/qemu-devel/2022-06/msg02276.html * Rebased to the latest QEMU. v3: * Note that the bundle mechanism is for any files located relative to the installation tree including but not limited to datadir. (Peter Maydell) * Fix "bridge" typo (Philippe Mathieu-Daudé) v2: Rebased to the latest QEMU. Akihiko Odaki (3): cutils: Introduce bundle mechanism datadir: Use bundle mechanism module: Use bundle mechanism Paolo Bonzini (1): tests/vm: do not specify -bios option .travis.yml | 2 +- docs/about/build-platforms.rst | 2 +- include/qemu/cutils.h | 18 +++-- include/qemu/osdep.h| 2 +- meson.build | 4 ++ pc-bios/keymaps/meson.build | 21 +++--- pc-bios/meson.build | 13 ++- scripts/oss-fuzz/build.sh | 2 +- scripts/symlink-install-tree.py | 34 + softmmu/datadir.c | 22 +-- tests/qtest/fuzz/fuzz.c | 15 tests/vm/fedora | 1 - tests/vm/freebsd| 1 - tests/vm/netbsd | 1 - tests/vm/openbsd| 1 - util/cutils.c | 68 +++-- util/meson.build| 1 + util/module.c | 1 - 18 files changed, 115 insertions(+), 94 deletions(-) create mode 100755 scripts/symlink-install-tree.py -- 2.32.1 (Apple Git-133)
[PATCH v10 1/4] tests/vm: do not specify -bios option
From: Paolo Bonzini
When running from the build tree, the executable is able to find
the BIOS on its own; when running from the source tree, a firmware
blob should already be installed and there is no guarantee that
the one in the source tree works with the QEMU that is being used for
the installation.
Just remove the -bios option, since it is unnecessary and in fact
there are other x86 VM tests that do not bother specifying it.
Signed-off-by: Paolo Bonzini
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Thomas Huth
Signed-off-by: Akihiko Odaki
Message-Id: <20220616083025.116902-1-pbonz...@redhat.com>
---
tests/vm/fedora | 1 -
tests/vm/freebsd | 1 -
tests/vm/netbsd | 1 -
tests/vm/openbsd | 1 -
4 files changed, 4 deletions(-)
diff --git a/tests/vm/fedora b/tests/vm/fedora
index 92b78d6e2c9..12eca919a08 100755
--- a/tests/vm/fedora
+++ b/tests/vm/fedora
@@ -79,7 +79,6 @@ class FedoraVM(basevm.BaseVM):
self.exec_qemu_img("create", "-f", "qcow2", img_tmp, self.size)
self.print_step("Booting installer")
self.boot(img_tmp, extra_args = [
-"-bios", "pc-bios/bios-256k.bin",
"-machine", "graphics=off",
"-device", "VGA",
"-cdrom", iso
diff --git a/tests/vm/freebsd b/tests/vm/freebsd
index 805db759d67..cd1fabde523 100755
--- a/tests/vm/freebsd
+++ b/tests/vm/freebsd
@@ -95,7 +95,6 @@ class FreeBSDVM(basevm.BaseVM):
self.print_step("Booting installer")
self.boot(img_tmp, extra_args = [
-"-bios", "pc-bios/bios-256k.bin",
"-machine", "graphics=off",
"-device", "VGA",
"-cdrom", iso
diff --git a/tests/vm/netbsd b/tests/vm/netbsd
index 45aa9a7fda7..aa883ec23c9 100755
--- a/tests/vm/netbsd
+++ b/tests/vm/netbsd
@@ -86,7 +86,6 @@ class NetBSDVM(basevm.BaseVM):
self.print_step("Booting installer")
self.boot(img_tmp, extra_args = [
-"-bios", "pc-bios/bios-256k.bin",
"-machine", "graphics=off",
"-cdrom", iso
])
diff --git a/tests/vm/openbsd b/tests/vm/openbsd
index 13c82542140..6f1b6f5b98a 100755
--- a/tests/vm/openbsd
+++ b/tests/vm/openbsd
@@ -82,7 +82,6 @@ class OpenBSDVM(basevm.BaseVM):
self.print_step("Booting installer")
self.boot(img_tmp, extra_args = [
-"-bios", "pc-bios/bios-256k.bin",
"-machine", "graphics=off",
"-device", "VGA",
"-cdrom", iso
--
2.32.1 (Apple Git-133)
[PATCH v10 4/4] module: Use bundle mechanism
Before this change, the directory of the executable was being added to
resolve modules in the build tree. However, get_relocated_path() can now
resolve them with the new bundle mechanism.
Signed-off-by: Akihiko Odaki
---
util/module.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/util/module.c b/util/module.c
index 6bb4ad915a1..8ddb0e18f51 100644
--- a/util/module.c
+++ b/util/module.c
@@ -274,7 +274,6 @@ bool module_load_one(const char *prefix, const char
*lib_name, bool mayfail)
dirs[n_dirs++] = g_strdup_printf("%s", search_dir);
}
dirs[n_dirs++] = get_relocated_path(CONFIG_QEMU_MODDIR);
-dirs[n_dirs++] = g_strdup(qemu_get_exec_dir());
#ifdef CONFIG_MODULE_UPGRADES
version_dir = g_strcanon(g_strdup(QEMU_PKGVERSION),
--
2.32.1 (Apple Git-133)
[PATCH v10 2/4] cutils: Introduce bundle mechanism
Developers often run QEMU without installing. The bundle mechanism
allows to look up files which should be present in installation even in
such a situation.
It is a general mechanism and can find any files in the installation
tree. The build tree will have a new directory, qemu-bundle, to
represent what files the installation tree would have for reference by
the executables.
Note that it abandons compatibility with Windows older than 8. The
extended support for the prior version, 7 ended more than 2 years ago,
and it is unlikely that someone would like to run the latest QEMU on
such an old system.
Signed-off-by: Akihiko Odaki
Suggested-by: Paolo Bonzini
---
docs/about/build-platforms.rst | 2 +-
include/qemu/cutils.h | 18 +++--
include/qemu/osdep.h| 2 +-
meson.build | 4 ++
scripts/symlink-install-tree.py | 34 +
util/cutils.c | 68 +++--
util/meson.build| 1 +
7 files changed, 103 insertions(+), 26 deletions(-)
create mode 100755 scripts/symlink-install-tree.py
diff --git a/docs/about/build-platforms.rst b/docs/about/build-platforms.rst
index 1958edb4305..ebde20f9815 100644
--- a/docs/about/build-platforms.rst
+++ b/docs/about/build-platforms.rst
@@ -88,7 +88,7 @@ Windows
The project aims to support the two most recent versions of Windows that are
still supported by the vendor. The minimum Windows API that is currently
-targeted is "Windows 7", so theoretically the QEMU binaries can still be run
+targeted is "Windows 8", so theoretically the QEMU binaries can still be run
on older versions of Windows, too. However, such old versions of Windows are
not tested anymore, so it is recommended to use one of the latest versions of
Windows instead.
diff --git a/include/qemu/cutils.h b/include/qemu/cutils.h
index d3e532b64c8..92c436d8c70 100644
--- a/include/qemu/cutils.h
+++ b/include/qemu/cutils.h
@@ -224,9 +224,21 @@ const char *qemu_get_exec_dir(void);
* @dir: the directory (typically a `CONFIG_*DIR` variable) to be relocated.
*
* Returns a path for @dir that uses the directory of the running executable
- * as the prefix. For example, if `bindir` is `/usr/bin` and @dir is
- * `/usr/share/qemu`, the function will append `../share/qemu` to the
- * directory that contains the running executable and return the result.
+ * as the prefix.
+ *
+ * When a directory named `qemu-bundle` exists in the directory of the running
+ * executable, the path to the directory will be prepended to @dir. For
+ * example, if the directory of the running executable is `/qemu/build` @dir
+ * is `/usr/share/qemu`, the result will be
+ * `/qemu/build/qemu-bundle/usr/share/qemu`. The directory is expected to exist
+ * in the build tree.
+ *
+ * Otherwise, the directory of the running executable will be used as the
+ * prefix and it appends the relative path from `bindir` to @dir. For example,
+ * if the directory of the running executable is `/opt/qemu/bin`, `bindir` is
+ * `/usr/bin` and @dir is `/usr/share/qemu`, the result will be
+ * `/opt/qemu/bin/../share/qemu`.
+ *
* The returned string should be freed by the caller.
*/
char *get_relocated_path(const char *dir);
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index b1c161c035a..84f8b9d0243 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -75,7 +75,7 @@ QEMU_EXTERN_C int daemon(int, int);
#ifdef _WIN32
/* as defined in sdkddkver.h */
#ifndef _WIN32_WINNT
-#define _WIN32_WINNT 0x0601 /* Windows 7 API (should be in sync with glib) */
+#define _WIN32_WINNT 0x0602 /* Windows 8 API (should be in sync with glib) */
#endif
/* reduces the number of implicitly included headers */
#ifndef WIN32_LEAN_AND_MEAN
diff --git a/meson.build b/meson.build
index 9efcb175d16..c49f5ebfc37 100644
--- a/meson.build
+++ b/meson.build
@@ -7,6 +7,8 @@ add_test_setup('quick', exclude_suites: ['slow', 'thorough'],
is_default: true)
add_test_setup('slow', exclude_suites: ['thorough'], env: ['G_TEST_SLOW=1',
'SPEED=slow'])
add_test_setup('thorough', env: ['G_TEST_SLOW=1', 'SPEED=thorough'])
+meson.add_postconf_script('scripts/symlink-install-tree.py')
+
not_found = dependency('', required: false)
keyval = import('keyval')
ss = import('sourceset')
@@ -356,10 +358,12 @@ nvmm =not_found
hvf = not_found
midl = not_found
widl = not_found
+pathcch = not_found
host_dsosuf = '.so'
if targetos == 'windows'
midl = find_program('midl', required: false)
widl = find_program('widl', required: false)
+ pathcch = cc.find_library('pathcch')
socket = cc.find_library('ws2_32')
winmm = cc.find_library('winmm')
diff --git a/scripts/symlink-install-tree.py b/scripts/symlink-install-tree.py
new file mode 100755
index 000..59cf7e939f1
--- /dev/null
+++ b/scripts/symlink-install-tree.py
@@ -0,0 +1,34 @@
+#!/usr/bin/env python3
+
+from pathlib import PurePath
+import errno
+import json
+import os
+import subprocess
+
[PATCH v10 3/4] datadir: Use bundle mechanism
softmmu/datadir.c had its own implementation to find files in the
build tree, but now bundle mechanism provides the unified
implementation which works for datadir and the other files.
Signed-off-by: Akihiko Odaki
---
.travis.yml | 2 +-
pc-bios/keymaps/meson.build | 21 ++---
pc-bios/meson.build | 13 +++--
scripts/oss-fuzz/build.sh | 2 +-
softmmu/datadir.c | 22 +-
tests/qtest/fuzz/fuzz.c | 15 ---
6 files changed, 12 insertions(+), 63 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index 9afc4a54b8f..4fdc9a67855 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -223,7 +223,7 @@ jobs:
- BUILD_RC=0 && make -j${JOBS} || BUILD_RC=$?
- |
if [ "$BUILD_RC" -eq 0 ] ; then
- mv pc-bios/s390-ccw/*.img pc-bios/ ;
+ mv pc-bios/s390-ccw/*.img qemu-bundle/usr/local/share/qemu ;
${TEST_CMD} ;
else
$(exit $BUILD_RC);
diff --git a/pc-bios/keymaps/meson.build b/pc-bios/keymaps/meson.build
index 44247a12b54..2837eb34f4e 100644
--- a/pc-bios/keymaps/meson.build
+++ b/pc-bios/keymaps/meson.build
@@ -40,9 +40,9 @@ else
endif
cp = find_program('cp')
-t = []
-foreach km, args: keymaps
- if native_qemu_keymap.found()
+if native_qemu_keymap.found()
+ t = []
+ foreach km, args: keymaps
# generate with qemu-kvm
t += custom_target(km,
build_by_default: true,
@@ -50,20 +50,11 @@ foreach km, args: keymaps
command: [native_qemu_keymap, '-f', '@OUTPUT@',
args.split()],
install: true,
install_dir: qemu_datadir / 'keymaps')
- else
-# copy from source tree
-t += custom_target(km,
- build_by_default: true,
- input: km,
- output: km,
- command: [cp, '@INPUT@', '@OUTPUT@'],
- install: true,
- install_dir: qemu_datadir / 'keymaps')
- endif
-endforeach
+ endforeach
-if native_qemu_keymap.found()
alias_target('update-keymaps', t)
+else
+ install_data(keymaps.keys(), install_dir: qemu_datadir / 'keymaps')
endif
install_data(['sl', 'sv'], install_dir: qemu_datadir / 'keymaps')
diff --git a/pc-bios/meson.build b/pc-bios/meson.build
index 41ba1c0ec7b..388e0db6e40 100644
--- a/pc-bios/meson.build
+++ b/pc-bios/meson.build
@@ -85,16 +85,9 @@ blobs = [
'vof-nvram.bin',
]
-ln_s = [find_program('ln', required: true), '-sf']
-foreach f : blobs
- roms += custom_target(f,
-build_by_default: have_system,
-output: f,
-input: files('meson.build'),# dummy input
-install: get_option('install_blobs'),
-install_dir: qemu_datadir,
-command: [ ln_s, meson.project_source_root() / 'pc-bios' / f,
'@OUTPUT@' ])
-endforeach
+if get_option('install_blobs')
+ install_data(blobs, install_dir: qemu_datadir)
+endif
subdir('descriptors')
subdir('keymaps')
diff --git a/scripts/oss-fuzz/build.sh b/scripts/oss-fuzz/build.sh
index 98b56e05210..16316b25662 100755
--- a/scripts/oss-fuzz/build.sh
+++ b/scripts/oss-fuzz/build.sh
@@ -88,7 +88,7 @@ if [ "$GITLAB_CI" != "true" ]; then
fi
# Copy over the datadir
-cp -r ../pc-bios/ "$DEST_DIR/pc-bios"
+cp -r ../pc-bios/ "$DEST_DIR/data"
targets=$(./qemu-fuzz-i386 | awk '$1 ~ /\*/ {print $2}')
base_copy="$DEST_DIR/qemu-fuzz-i386-target-$(echo "$targets" | head -n 1)"
diff --git a/softmmu/datadir.c b/softmmu/datadir.c
index 160cac999a6..697cffea932 100644
--- a/softmmu/datadir.c
+++ b/softmmu/datadir.c
@@ -83,26 +83,6 @@ void qemu_add_data_dir(char *path)
data_dir[data_dir_idx++] = path;
}
-/*
- * Find a likely location for support files using the location of the binary.
- * When running from the build tree this will be "$bindir/pc-bios".
- * Otherwise, this is CONFIG_QEMU_DATADIR (possibly relocated).
- *
- * The caller must use g_free() to free the returned data when it is
- * no longer required.
- */
-static char *find_datadir(void)
-{
-g_autofree char *dir = NULL;
-
-dir = g_build_filename(qemu_get_exec_dir(), "pc-bios", NULL);
-if (g_file_test(dir, G_FILE_TEST_IS_DIR)) {
-return g_steal_pointer(&dir);
-}
-
-return get_relocated_path(CONFIG_QEMU_DATADIR);
-}
-
void qemu_add_default_firmwarepath(void)
{
char **dirs;
@@ -116,7 +96,7 @@ void qemu_add_default_firmwarepath(void)
g_strfreev(dirs);
/* try to find datadir relative to the executable path */
-qemu_add_data_dir(find_datadir());
+qemu_add_data_dir(get_relocated_path(CONFIG_QEMU_DATADIR));
}
void qemu_list_data_dirs(void)
diff --git a/tests/qtest/fuzz/fuzz.c b/tests/qtest/fuzz/fuzz.c
index 0ad4ba9e94d..2062b40d82b 100644
--- a/tests/qtest/fuzz/fuzz.c
+++ b/tests/qtest/fuzz/fuzz.c
@@ -174,21 +174,6 @@ int LLVMFuzzerInitialize(int *a
Re: [PULL v2 10/20] libvduse: Add VDUSE (vDPA Device in Userspace) library
Kevin Wolf writes:
> From: Xie Yongji
>
> VDUSE [1] is a linux framework that makes it possible to implement
> software-emulated vDPA devices in userspace. This adds a library
> as a subproject to help implementing VDUSE backends in QEMU.
>
> [1] https://www.kernel.org/doc/html/latest/userspace-api/vduse.html
>
> Signed-off-by: Xie Yongji
> Message-Id: <20220523084611.91-6-xieyon...@bytedance.com>
> Reviewed-by: Stefan Hajnoczi
> Signed-off-by: Kevin Wolf
> ---
> meson_options.txt |2 +
> subprojects/libvduse/include/atomic.h |1 +
> subprojects/libvduse/include/compiler.h |1 +
> subprojects/libvduse/libvduse.h | 235
> subprojects/libvduse/libvduse.c | 1150 +++
> MAINTAINERS |5 +
> meson.build | 15 +
> scripts/meson-buildoptions.sh |3 +
> subprojects/libvduse/linux-headers/linux|1 +
> subprojects/libvduse/meson.build| 10 +
> subprojects/libvduse/standard-headers/linux |1 +
> 11 files changed, 1424 insertions(+)
> create mode 12 subprojects/libvduse/include/atomic.h
> create mode 12 subprojects/libvduse/include/compiler.h
> create mode 100644 subprojects/libvduse/libvduse.h
> create mode 100644 subprojects/libvduse/libvduse.c
> create mode 12 subprojects/libvduse/linux-headers/linux
> create mode 100644 subprojects/libvduse/meson.build
> create mode 12 subprojects/libvduse/standard-headers/linux
>
> diff --git a/meson_options.txt b/meson_options.txt
> index f3e2f22c1e..23a9f440f7 100644
> --- a/meson_options.txt
> +++ b/meson_options.txt
> @@ -257,6 +257,8 @@ option('virtfs', type: 'feature', value: 'auto',
> description: 'virtio-9p support')
> option('virtiofsd', type: 'feature', value: 'auto',
> description: 'build virtiofs daemon (virtiofsd)')
> +option('libvduse', type: 'feature', value: 'auto',
> + description: 'build VDUSE Library')
>
> option('capstone', type: 'feature', value: 'auto',
> description: 'Whether and how to find the capstone library')
> diff --git a/subprojects/libvduse/include/atomic.h
> b/subprojects/libvduse/include/atomic.h
> new file mode 12
> index 00..8c2be64f7b
> --- /dev/null
> +++ b/subprojects/libvduse/include/atomic.h
> @@ -0,0 +1 @@
> +../../../include/qemu/atomic.h
> \ No newline at end of file
> diff --git a/subprojects/libvduse/include/compiler.h
> b/subprojects/libvduse/include/compiler.h
> new file mode 12
> index 00..de7b70697c
> --- /dev/null
> +++ b/subprojects/libvduse/include/compiler.h
> @@ -0,0 +1 @@
> +../../../include/qemu/compiler.h
> \ No newline at end of file
> diff --git a/subprojects/libvduse/libvduse.h b/subprojects/libvduse/libvduse.h
> new file mode 100644
> index 00..6c2fe98213
> --- /dev/null
> +++ b/subprojects/libvduse/libvduse.h
> @@ -0,0 +1,235 @@
> +/*
> + * VDUSE (vDPA Device in Userspace) library
> + *
> + * Copyright (C) 2022 Bytedance Inc. and/or its affiliates. All rights
> reserved.
> + *
> + * Author:
> + * Xie Yongji
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> + * later. See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef LIBVDUSE_H
> +#define LIBVDUSE_H
> +
> +#include
> +#include
> +
> +#define VIRTQUEUE_MAX_SIZE 1024
> +
> +/* VDUSE device structure */
> +typedef struct VduseDev VduseDev;
> +
> +/* Virtqueue structure */
> +typedef struct VduseVirtq VduseVirtq;
> +
> +/* Some operation of VDUSE backend */
> +typedef struct VduseOps {
> +/* Called when virtqueue can be processed */
> +void (*enable_queue)(VduseDev *dev, VduseVirtq *vq);
> +/* Called when virtqueue processing should be stopped */
> +void (*disable_queue)(VduseDev *dev, VduseVirtq *vq);
> +} VduseOps;
> +
> +/* Describing elements of the I/O buffer */
> +typedef struct VduseVirtqElement {
> +/* Descriptor table index */
> +unsigned int index;
> +/* Number of physically-contiguous device-readable descriptors */
> +unsigned int out_num;
> +/* Number of physically-contiguous device-writable descriptors */
> +unsigned int in_num;
> +/* Array to store physically-contiguous device-writable descriptors */
> +struct iovec *in_sg;
> +/* Array to store physically-contiguous device-readable descriptors */
> +struct iovec *out_sg;
> +} VduseVirtqElement;
> +
> +
> +/**
> + * vduse_get_virtio_features:
> + *
> + * Get supported virtio features
> + *
> + * Returns: supported feature bits
> + */
> +uint64_t vduse_get_virtio_features(void);
> +
> +/**
> + * vduse_queue_get_dev:
> + * @vq: specified virtqueue
> + *
> + * Get corresponding VDUSE device from the virtqueue.
> + *
> + * Returns: a pointer to VDUSE device on success, NULL on failure.
> + */
> +VduseDev *vduse_queue_get_dev(VduseVirtq *vq);
> +
> +/**
> + * vduse_queue_get_fd:
> + * @vq: specified vir
Re: [PATCH qemu v2 1/2] ppc: Define SETFIELD for the ppc target
On 6/25/22 06:12, Daniel Henrique Barboza wrote:
Alexey,
The newer version of this patch is having trouble with Gitlab runners, as
you can read in my feedback there.
I've tested this one just in case. The same problems happen. E.g. for the
cross-armel-system runner:
In file included from ../hw/intc/pnv_xive.c:14:
../hw/intc/pnv_xive.c: In function ‘pnv_xive_block_id’:
/builds/danielhb/qemu/target/ppc/cpu.h:45:33: error: conversion from
‘long long unsigned int’ to ‘long unsigned int’ changes value from
‘4222124650659840’ to ‘0’ [-Werror=overflow]
45 | #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) |
PPC_BIT(bs))
|
^~~
/builds/danielhb/qemu/target/ppc/cpu.h:51:42: note: in definition of
macro ‘GETFIELD’
51 | (((word) & (mask)) >> __builtin_ctzl(mask))
| ^~~~
../hw/intc/pnv_xive_regs.h:77:41: note: in expansion of macro ‘PPC_BITMASK’
77 | #define PC_TCTXT_CHIPID PPC_BITMASK(12, 15)
| ^~~
../hw/intc/pnv_xive.c:80:24: note: in expansion of macro ‘PC_TCTXT_CHIPID’
80 | blk = GETFIELD(PC_TCTXT_CHIPID, cfg_val);
| ^~~
../hw/intc/pnv_xive.c: In function ‘pnv_xive_vst_addr’:
/builds/danielhb/qemu/target/ppc/cpu.h:45:33: error: conversion from
‘long long unsigned int’ to ‘long unsigned int’ changes value from
‘13835058055282163712’ to ‘0’ [-Werror=overflow]
45 | #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) |
PPC_BIT(bs))
|
^~~
/builds/danielhb/qemu/target/ppc/cpu.h:51:42: note: in definition of
macro ‘GETFIELD’
51 | (((word) & (mask)) >> __builtin_ctzl(mask))
| ^~~~
../hw/intc/pnv_xive_regs.h:230:33: note: in expansion of macro
‘PPC_BITMASK’
230 | #define VSD_MODE PPC_BITMASK(0, 1)
| ^~~
../hw/intc/pnv_xive.c:226:18: note: in expansion of macro ‘VSD_MODE’
226 | if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) {
| ^~~~
../hw/intc/pnv_xive.c: In function ‘pnv_xive_end_update’:
Link:
https://gitlab.com/danielhb/qemu/-/jobs/2637716673
I don´t know how to deal with that.
For the record: if this is too troublesome to fix, I am ok with just
consolidating
the GETFIELD and SETFIELD inlines we already have, under cpu.h, keeping
them exactly
as they are today (functions, not macros).
Thanks,
Daniel
On 6/17/22 03:07, Alexey Kardashevskiy wrote:
It keeps repeating, move it to the header. This uses __builtin_ctzl() to
allow using the macros in #define.
Signed-off-by: Alexey Kardashevskiy
---
include/hw/pci-host/pnv_phb3_regs.h | 16
target/ppc/cpu.h | 5 +
hw/intc/pnv_xive.c | 20
hw/intc/pnv_xive2.c | 20
hw/pci-host/pnv_phb4.c | 16
5 files changed, 5 insertions(+), 72 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb3_regs.h
b/include/hw/pci-host/pnv_phb3_regs.h
index a174ef1f7045..38f8ce9d7406 100644
--- a/include/hw/pci-host/pnv_phb3_regs.h
+++ b/include/hw/pci-host/pnv_phb3_regs.h
@@ -12,22 +12,6 @@
#include "qemu/host-utils.h"
-/*
- * QEMU version of the GETFIELD/SETFIELD macros
- *
- * These are common with the PnvXive model.
- */
-static inline uint64_t GETFIELD(uint64_t mask, uint64_t word)
-{
- return (word & mask) >> ctz64(mask);
-}
-
-static inline uint64_t SETFIELD(uint64_t mask, uint64_t word,
- uint64_t value)
-{
- return (word & ~mask) | ((value << ctz64(mask)) & mask);
-}
-
/*
* PBCQ XSCOM registers
*/
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 6d78078f379d..9a1f1ea3 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -47,6 +47,11 @@
PPC_BIT32(bs))
#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) |
PPC_BIT8(bs))
+#define GETFIELD(mask, word) \
+ (((word) & (mask)) >> __builtin_ctzl(mask))
Replacing __builtin_ctzl with __builtin_ctzll seems fixing it though, do
you have a quick way to test this? Gitlab's CI takes time :)
https://gitlab.com/aik1/qemu/-/pipelines/573497191 is the current run.
Thanks,
--
Alexey
Re: [PATCH v3 1/1] target/riscv: Add Zihintpause support
On Wed, Jun 22, 2022 at 2:17 AM Dao Lu wrote:
>
> From what I know that's generally the way reservations are handled:
> if the forward progress requirements aren't met then the implementation
> is free to break any outstanding reservations (the hardware is always
> free to do that to a degree, but once forward progress is gone it can
> always do that). So this is legal, as would be not breaking the reservation.
I'm thinking let's not break the reservation. That way we are
consistent with the fence instruction. If we do want to clear the
reservation then we should do it for fence as well.
Alistair
>
> I don't have a strong opinion on this and am fine about changing it if
> anyone does.
>
> Thanks,
> Dao
>
> On Mon, Jun 20, 2022 at 4:39 PM Alistair Francis wrote:
> >
> > On Thu, Jun 9, 2022 at 2:42 PM Dao Lu wrote:
> > >
> > > Added support for RISC-V PAUSE instruction from Zihintpause extension,
> > > enabled by default.
> > >
> > > Tested-by: Heiko Stuebner
> > > Signed-off-by: Dao Lu
> > > ---
> > > target/riscv/cpu.c | 2 ++
> > > target/riscv/cpu.h | 1 +
> > > target/riscv/insn32.decode | 7 ++-
> > > target/riscv/insn_trans/trans_rvi.c.inc | 18 ++
> > > 4 files changed, 27 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index ccacdee215..183fb37fdf 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -825,6 +825,7 @@ static Property riscv_cpu_properties[] = {
> > > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> > > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> > > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> > > +DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
> > > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> > > DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> > > DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> > > @@ -996,6 +997,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char
> > > **isa_str, int max_str_len)
> > > *extensions by an underscore.
> > > */
> > > struct isa_ext_data isa_edata_arr[] = {
> > > +ISA_EDATA_ENTRY(zihintpause, ext_zihintpause),
> > > ISA_EDATA_ENTRY(zfh, ext_zfh),
> > > ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> > > ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > index fe6c9a2c92..e466a04a59 100644
> > > --- a/target/riscv/cpu.h
> > > +++ b/target/riscv/cpu.h
> > > @@ -394,6 +394,7 @@ struct RISCVCPUConfig {
> > > bool ext_counters;
> > > bool ext_ifencei;
> > > bool ext_icsr;
> > > +bool ext_zihintpause;
> > > bool ext_svinval;
> > > bool ext_svnapot;
> > > bool ext_svpbmt;
> > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > > index 4033565393..595fdcdad8 100644
> > > --- a/target/riscv/insn32.decode
> > > +++ b/target/riscv/insn32.decode
> > > @@ -149,7 +149,12 @@ srl 000 .. 101 . 0110011 @r
> > > sra 010 .. 101 . 0110011 @r
> > > or 000 .. 110 . 0110011 @r
> > > and 000 .. 111 . 0110011 @r
> > > -fence pred:4 succ:4 - 000 - 000
> > > +
> > > +{
> > > + pause 0001 0 000 0 000
> > > + fence pred:4 succ:4 - 000 - 000
> > > +}
> > > +
> > > fence_i - 001 - 000
> > > csrrw . 001 . 1110011 @csr
> > > csrrs . 010 . 1110011 @csr
> > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> > > b/target/riscv/insn_trans/trans_rvi.c.inc
> > > index f1342f30f8..ca75e05f4b 100644
> > > --- a/target/riscv/insn_trans/trans_rvi.c.inc
> > > +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> > > @@ -796,6 +796,24 @@ static bool trans_srad(DisasContext *ctx, arg_srad
> > > *a)
> > > return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
> > > }
> > >
> > > +static bool trans_pause(DisasContext *ctx, arg_pause *a)
> > > +{
> > > +if (!ctx->cfg_ptr->ext_zihintpause) {
> > > +return false;
> > > +}
> > > +
> > > +/*
> > > + * PAUSE is a no-op in QEMU,
> > > + * however we need to clear the reservation,
> > > + * end the TB and return to main loop
> > > + */
> > > +tcg_gen_movi_tl(load_res, -1);
> >
> > I'm not clear why we need to clear the load_res? We don't do it for
> > fence instruction
> >
> > Alistair
> >
> > > +gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> > > +tcg_gen_exit_tb(NULL, 0);
> > > +ctx->base.is_jmp = DISAS_NORETURN;
> > > +
> > > +return true;
> > > +}
> > >
> > > static bool trans_fence(DisasContext *ctx, arg_fence *a)
> > > {
> > > --
> > > 2.25.1
> > >
> > >
Re: [RFC PATCH v3] RISC-V: Add Zawrs ISA extension support
On Fri, Jun 24, 2022 at 1:31 AM Christoph Muellner
wrote:
>
> This patch adds support for the Zawrs ISA extension.
> Given the current (incomplete) implementation of reservation sets
> there seems to be no way to provide a full emulation of the WRS
> instruction (wake on reservation set invalidation or timeout or
> interrupt). Therefore, we just pretend that an interrupt occured,
> exit the execution loop and finally continue execution.
>
> The specification can be found here:
> https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
>
> Note, that the Zawrs extension is not frozen or ratified yet.
> Therefore this patch is an RFC and not intended to get merged.
>
> Changes since v2:
> * Adjustments according to a specification change
> * Inline REQUIRE_ZAWRS() since it has only one user
>
> Changes since v1:
> * Adding zawrs to the ISA string that is passed to the kernel
>
> Signed-off-by: Christoph Müllner
> ---
> target/riscv/cpu.c | 2 +
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 4 ++
> target/riscv/insn_trans/trans_rvzawrs.c.inc | 54 +
> target/riscv/translate.c| 1 +
> 5 files changed, 62 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvzawrs.c.inc
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 05e6521351..6cb00fadff 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -882,6 +882,7 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> +DEFINE_PROP_BOOL("zawrs", RISCVCPU, cfg.ext_zawrs, true),
Would this be enabled by default?
> DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> @@ -1075,6 +1076,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char
> **isa_str, int max_str_len)
> ISA_EDATA_ENTRY(zicsr, ext_icsr),
> ISA_EDATA_ENTRY(zifencei, ext_ifencei),
> ISA_EDATA_ENTRY(zmmul, ext_zmmul),
> +ISA_EDATA_ENTRY(zawrs, ext_zawrs),
> ISA_EDATA_ENTRY(zfh, ext_zfh),
> ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7d6397acdf..a22bc0fa09 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -380,6 +380,7 @@ struct RISCVCPUConfig {
> bool ext_h;
> bool ext_j;
> bool ext_v;
> +bool ext_zawrs;
> bool ext_zba;
> bool ext_zbb;
> bool ext_zbc;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 4033565393..513ea227fe 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -711,6 +711,10 @@ vsetvli 0 ... . 111 . 1010111
> @r2_zimm11
> vsetivli11 .. . 111 . 1010111 @r2_zimm10
> vsetvl 100 . . 111 . 1010111 @r
>
> +# *** Zawrs Standard Extension ***
> +wrs_nto1101 0 000 0 1110011
> +wrs_sto00011101 0 000 0 1110011
> +
> # *** RV32 Zba Standard Extension ***
> sh1add 001 .. 010 . 0110011 @r
> sh2add 001 .. 100 . 0110011 @r
> diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc
> b/target/riscv/insn_trans/trans_rvzawrs.c.inc
> new file mode 100644
> index 00..d0df56378e
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
> @@ -0,0 +1,54 @@
> +/*
> + * RISC-V translation routines for the RISC-V Zawrs Extension.
> + *
> + * Copyright (c) 2022 Christoph Muellner, christoph.muell...@vrull.io
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> with
> + * this program. If not, see
Re: [PATCH] Add some documentation for "dtb" devices tree blobs
On Sun, Jun 26, 2022 at 8:40 AM Simon Sapin wrote:
>
> Signed-off-by: Simon Sapin
Reviewed-by: Alistair Francis
Alistair
> ---
> docs/specs/device-trees.rst| 57 ++
> docs/specs/index.rst | 1 +
> docs/system/arm/virt.rst | 5 +-
> docs/system/arm/xlnx-versal-virt.rst | 3 +-
> docs/system/ppc/ppce500.rst| 3 +-
> docs/system/riscv/microchip-icicle-kit.rst | 3 +-
> docs/system/riscv/sifive_u.rst | 3 +-
> docs/system/riscv/virt.rst | 3 +-
> qemu-options.hx| 5 ++
> 9 files changed, 77 insertions(+), 6 deletions(-)
> create mode 100644 docs/specs/device-trees.rst
>
> diff --git docs/specs/device-trees.rst docs/specs/device-trees.rst
> new file mode 100644
> index 00..8160342124
> --- /dev/null
> +++ docs/specs/device-trees.rst
> @@ -0,0 +1,57 @@
> +
> +Device Trees
> +
> +
> +On some targets, guests can find out what devices are emulated and how to
> access them
> +through a *Device Tree Blob* (dtb), also called *Flattened Device Tree*
> (fdt).
> +The dtb can be passed by the user through the ``-dtb file`` command-line
> options,
> +or automatically generated by QEMU.
> +
> +Host: dumping the dtb
> +=
> +
> +The (possibly generated) dtb can be written to a file with
> +the ``dumpdtb`` property of the ``machine`` command-line option.
> +Then `dtc `_ can convert it to Device Tree Source
> text "dts" format
> +For example::
> +
> +qemu-system-riscv32 -machine virt,dumpdtb=rv32-virt.dtb
> +dtc -q rv32-virt.dtb -o rv32-virt.dts
> +head -n 7 rv32-virt.dts
> +
> +::
> +
> +qemu-system-riscv32: info: dtb dumped to rv32-virt.dtb. Exiting.
> +/dts-v1/;
> +
> +/ {
> +#address-cells = <0x02>;
> +#size-cells = <0x02>;
> +compatible = "riscv-virtio";
> +model = "riscv-virtio,qemu";
> +
> +Guest: finding the dtb
> +==
> +
> +On startup, the dtb is memory-mapped and its address is passed to the guest
> +in a target-specific way:
> +
> +* Arm: :ref:`arm-baremetal`
> +* **TODO**: document other targets
> +
> +Resources
> +=
> +
> +* `Devicetree Specification `_
> + - `Device Tree Usage `_
> +
> +* `Device Tree Compiler `_:
> +
> + - ``dtc`` CLI tool (package name might be ``device-tree-compiler``)
> + - ``libfdt`` C library
> +
> +* ``fdt`` `Rust library `_
> diff --git docs/specs/index.rst docs/specs/index.rst
> index a58d9311cb..3bd69305e2 100644
> --- docs/specs/index.rst
> +++ docs/specs/index.rst
> @@ -8,6 +8,7 @@ guest hardware that is specific to QEMU.
> .. toctree::
> :maxdepth: 2
>
> + device-trees
> ppc-xive
> ppc-spapr-xive
> ppc-spapr-numa
> diff --git docs/system/arm/virt.rst docs/system/arm/virt.rst
> index 3d1058a80c..04a90df613 100644
> --- docs/system/arm/virt.rst
> +++ docs/system/arm/virt.rst
> @@ -153,10 +153,13 @@ need::
>CONFIG_DRM=y
>CONFIG_DRM_VIRTIO_GPU=y
>
> +.. _arm-baremetal:
> +
> Hardware configuration information for bare-metal programming
> "
>
> -The ``virt`` board automatically generates a device tree blob ("dtb")
> +The ``virt`` board automatically generates a
> +:doc:`device tree blob ("dtb") `
> which it passes to the guest. This provides information about the
> addresses, interrupt lines and other configuration of the various devices
> in the system. Guest code can rely on and hard-code the following
> diff --git docs/system/arm/xlnx-versal-virt.rst
> docs/system/arm/xlnx-versal-virt.rst
> index 92ad10d2da..3387c74bfa 100644
> --- docs/system/arm/xlnx-versal-virt.rst
> +++ docs/system/arm/xlnx-versal-virt.rst
> @@ -53,7 +53,8 @@ to use the ``-kernel`` command line option.
>
> Users can load firmware or boot-loaders with the ``-device loader`` options.
>
> -When loading an OS, QEMU generates a DTB and selects an appropriate address
> +When loading an OS, QEMU generates a :doc:`DTB `
> +and selects an appropriate address
> where it gets loaded. This DTB will be passed to the kernel in register x0.
>
> If there's no ``-kernel`` option, we generate a DTB and place it at 0x1000
> diff --git docs/system/ppc/ppce500.rst docs/system/ppc/ppce500.rst
> index 9beef39171..24fd91a084 100644
> --- docs/system/ppc/ppce500.rst
> +++ docs/system/ppc/ppce500.rst
> @@ -24,7 +24,8 @@ The ``ppce500`` machine supports the following devices:
> Hardware configuration information
> --
>
> -The ``ppce500`` machine automatically generates a device tree blob ("dtb")
> +The ``ppce500`` machine automatically ge
Re: Booting bare-metal RISC-V virt (Was: [PATCH] Add some documentation for "dtb" devices tree blobs)
On Sun, Jun 26, 2022 at 9:04 AM Simon Sapin wrote: > > On 26/06/2022 00:34, Simon Sapin wrote: > > +On startup, the dtb is memory-mapped and its address is passed to the guest > > +in a target-specific way: > > + > > +* Arm: :ref:`arm-baremetal` > > +* **TODO**: document other targets > > Hello, Hello > > My current interest is playing with bare-metal / freestanding RISC-V, using > QEMU as a > reference emulator. Based on various blog posts, reading QEMU source code, > and lots > of trial-and-error I’ve managed to get something running[1] but it wasn’t > easy. Written in Rust as well, nice! I'm sorry to hear that you had so much trouble getting started with RISC-V QEMU. We do try to make it easy, but everyone is busy and documentation usually ends up being the last thing we do. > > In comparison, the docs for Arm virt have a very helpful section[2] for this > scenario. I would like to contribute similar docs for RISC-V virt but I’d need > confirmation of the information to put in it: > > * Through `dumpdtb` I see that flash memory starts at address 0x2_000_, > and RAM > at 0x8_000_. Is this information that guest code can rely on and > hard-code? What > details can or cannot be similarly relied on? Good question. So first up, you can see all of the memory mappings in the hw/riscv/virt.c file, if you find that easier than dumping device trees. We have previously kept the addresses backwards compatible. So that software for an older virt machine will work on a newer one. There is currently talks about changing the virt machine memory layout in a breaking way and versioning in the current one though. So I don't really have a good answer for you. I would recommend reading as much as possible from the device tree dynamically at boot. In general though we don't want to break people, we just might have to make changes in the future to allow for new functionality. > > * With `qemu-system-riscv32 -machine virt -bios none -kernel something.elf -s > -S`, > GDB shows that execution starts at the lowest address of RAM, not of flash > like I > expected. Then what is emulated flash for? If you supply a flash image we will start executing from flash automatically. > > * What’s the difference between a bios and a kernel? The previous command is > based on > a blog post but I don’t fully quite the details. For a bare metal setup like yours there isn't really a difference. We use -bios to specify the OpenSBI firmware and -kernel to specify a Linux kernel. For your use you can use `-bios none -kernel ...` > > * I see in source code[3] that QEMU passes some arguments to the firmware. > Register > a0 gets the hart ID, a1 is the dtb address, but what’s in a2? a2 stores the "dynamic firmware info" which is used by OpenSBI. The riscv_rom_copy_firmware_info() copies the data to memory > > * To what extent is the above calling convention standardized? I found > similar things > in coreboot[4] and in OpenSBI[5] Good question. I don't think it's specified in a spec, but it is very common Alistair > > > [1] https://github.com/SimonSapin/riscv-qemu-demo > > [2] > https://www.qemu.org/docs/master/system/arm/virt.html#hardware-configuration-information-for-bare-metal-programming > > [3] > https://gitlab.com/qemu-project/qemu/-/blob/v7.0.0/hw/riscv/boot.c#L297-317 > > [4] https://doc.coreboot.org/arch/riscv/index.html#stage-handoff-protocol > > [5] > https://github.com/riscv-software-src/opensbi/blob/v1.1/platform/generic/platform.c#L59-L75 > > > Thanks! > -- > Simon Sapin >
Re: [PATCH v3 0/2] hw/nvme: Add shadow doorbell buffer support
On Jun 16 20:34, Jinhao Fan wrote: > This patch adds shadow doorbell buffer support in NVMe 1.3 to QEMU > NVMe. The Doorbell Buffer Config admin command is implemented for the > guest to enable shadow doobell buffer. When this feature is enabled, each > SQ/CQ is associated with two buffers, i.e., Shadow Doorbell buffer and > EventIdx buffer. According to the Spec, each queue's doorbell register > is only updated when the Shadow Doorbell buffer value changes from being > less than or equal to the value of the corresponding EventIdx buffer > entry to being greater than that value. Therefore, the number of MMIO's > on the doorbell registers is greatly reduced. > > This patch is adapted from Huaicheng Li's patch[1] in 2018. > > [1] > https://patchwork.kernel.org/project/qemu-devel/patch/20180305194906.ga3...@gmail.com/ > > IOPS comparison with FIO: > > iodepth1 2 4 8 > QEMU 25.1k 25.9k 24.5k 24.0k > +dbbuf 29.1k 60.1k 99.8k 82.5k > > MMIO's per IO measured by perf-kvm: > > iodepth1 2 4 8 > QEMU 2.01 1.99 1.99 1.99 > +dbbuf 1.00 0.52 0.27 0.46 > > The tests are done on Ubuntu 22.04 with 5.15.0-33 kernel with Intel(R) > Xeon(R) Gold 6248R CPU @ 3.00GHz. > > QEMU set up: > > bin/x86_64-softmmu/qemu-system-x86_64 \ > -name "nvme-test" \ > -machine accel=kvm \ > -cpu host \ > -smp 4 \ > -m 8G \ > -daemonize \ > -device virtio-scsi-pci,id=scsi0 \ > -device scsi-hd,drive=hd0 \ > -drive > file=$OSIMGF,if=none,aio=native,cache=none,format=qcow2,id=hd0,snapshot=on \ > -drive "id=nvm,if=none,file=null-co://,file.read-zeroes=on,format=raw" \ > -device nvme,serial=deadbeef,drive=nvm \ > -net user,hostfwd=tcp::8080-:22 \ > -net nic,model=virtio > > FIO configuration: > > [global] > ioengine=libaio > filename=/dev/nvme0n1 > thread=1 > group_reporting=1 > direct=1 > verify=0 > time_based=1 > ramp_time=0 > runtime=30 > ;size=1G > ;iodepth=1 > rw=randread > bs=4k > > [test] > numjobs=1 > > Changes since v2: > - Do not ignore admin queue updates in nvme_process_db and nvme_post_cqes > - Calculate db_addr and ei_addr in hard-coded way > > Changes since v1: > - Add compatibility with hosts that do not use admin queue shadow doorbell > > Jinhao Fan (2): > hw/nvme: Implement shadow doorbell buffer support > hw/nvme: Add trace events for shadow doorbell buffer > > hw/nvme/ctrl.c | 118 ++- > hw/nvme/nvme.h | 8 +++ > hw/nvme/trace-events | 5 ++ > include/block/nvme.h | 2 + > 4 files changed, 132 insertions(+), 1 deletion(-) > > -- > 2.25.1 > > Jinhao, Thanks, applied to nvme-next! signature.asc Description: PGP signature
Re: [PULL 00/55] qemu-sparc queue 20220626
On 6/26/22 23:14, Mark Cave-Ayland wrote: The following changes since commit 40d522490714b65e0856444277db6c14c5cc3796: Merge tag 'for-upstream' of git://repo.or.cz/qemu/kevin into staging (2022-06-24 10:52:46 -0700) are available in the Git repository at: https://github.com/mcayland/qemu.git tags/qemu-sparc-20220626 for you to fetch changes up to 39fbaeca096a9bf6cbe2af88572c1cb2aa62aa8c: artist: set memory region owners for buffers to the artist device (2022-06-26 18:40:28 +0100) qemu-sparc queue - This is the PS2 QOM part 1 series, along with the trivial artist patch Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate. r~ Mark Cave-Ayland (55): ps2: checkpatch fixes ps2: QOMify PS2State ps2: QOMify PS2KbdState ps2: QOMify PS2MouseState ps2: move QOM type definitions from ps2.c to ps2.h ps2: improve function prototypes in ps2.c and ps2.h ps2: introduce PS2DeviceClass ps2: implement ps2_reset() for the PS2_DEVICE QOM type based upon ps2_common_reset() ps2: remove duplicate setting of scancode_set in ps2_kbd_init() ps2: implement ps2_kbd_realize() and use it to register ps2_keyboard_handler ps2: implement ps2_mouse_realize() and use it to register ps2_mouse_handler ps2: don't use vmstate_register() in ps2_kbd_init() ps2: don't use vmstate_register() in ps2_mouse_init() pl050: checkpatch fixes pl050: split pl050_update_irq() into separate pl050_set_irq() and pl050_update_irq() functions lasips2: spacing fixes lasips2: rename ps2dev_update_irq() to lasips2_port_set_irq() pckbd: checkpatch fixes pckbd: move KBDState from pckbd.c to i8042.h pckbd: move ISAKBDState from pckbd.c to i8042.h pckbd: introduce new I8042_MMIO QOM type pckbd: implement i8042_mmio_reset() for I8042_MMIO device pckbd: add mask qdev property to I8042_MMIO device pckbd: add size qdev property to I8042_MMIO device pckbd: implement i8042_mmio_realize() function pckbd: implement i8042_mmio_init() function pckbd: alter i8042_mm_init() to return a I8042_MMIO device pckbd: move mapping of I8042_MMIO registers to MIPS magnum machine pckbd: more vmstate_register() from i8042_mm_init() to i8042_mmio_realize() pckbd: move ps2_kbd_init() and ps2_mouse_init() to i8042_mmio_realize() ps2: make ps2_raise_irq() function static ps2: use ps2_raise_irq() instead of calling update_irq() directly ps2: introduce ps2_lower_irq() instead of calling update_irq() directly ps2: add gpio for output IRQ and optionally use it in ps2_raise_irq() and ps2_lower_irq() pckbd: replace irq_kbd and irq_mouse with qemu_irq array in KBDState pl050: switch over from update_irq() function to PS2 device gpio pl050: add QEMU interface comment lasips2: QOMify LASIPS2State lasips2: move lasips2 QOM types from lasips2.c to lasips2.h lasips2: rename lasips2_init() to lasips2_initfn() and update it to return the LASIPS2 device lasips2: implement lasips2_init() function lasips2: move mapping of LASIPS2 registers to HPPA machine lasips2: move initialisation of PS2 ports from lasi_initfn() to lasi_init() lasips2: add base property lasips2: implement lasips2_realize() lasips2: use sysbus IRQ for output IRQ lasips2: switch over from update_irq() function to PS2 device gpio lasips2: add QEMU interface comment pckbd: switch I8042_MMIO device from update_irq() function to PS2 device gpio pckbd: add QEMU interface comment for I8042_MMIO device pckbd: add i8042_reset() function to I8042 device pckbd: switch I8042 device from update_irq() function to PS2 device gpio pckbd: add QEMU interface comment for I8042 device ps2: remove update_irq() function and update_arg parameter artist: set memory region owners for buffers to the artist device hw/display/artist.c| 2 +- hw/hppa/machine.c | 11 +- hw/input/lasips2.c | 123 +++ hw/input/pckbd.c | 338 -- hw/input/pl050.c | 56 +++-- hw/input/ps2.c | 501 ++--- hw/mips/jazz.c | 11 +- include/hw/input/i8042.h | 75 ++- include/hw/input/lasips2.h | 39 +++- include/hw/input/ps2.h | 79 ++- 10 files changed, 846 insertions(+), 389 deletions(-)
Re: Booting bare-metal RISC-V virt (Was: [PATCH] Add some documentation for "dtb" devices tree blobs)
On 27/06/2022 07:40, Alistair Francis wrote: We have previously kept the addresses backwards compatible. So that software for an older virt machine will work on a newer one. There is currently talks about changing the virt machine memory layout in a breaking way and versioning in the current one though. So I don't really have a good answer for you. I would recommend reading as much as possible from the device tree dynamically at boot. In general though we don't want to break people, we just might have to make changes in the future to allow for new functionality. I agree that reading from the device tree as much as possible is good. We there’s still a need to get code running at all, and finding the device tree. So it would be good to decide to make stable what’s needed to get there (like was apparently decided for ARM) and document it. On principle maybe a firmware/bootloader could be entirely position-independent? But in what I’ve done/seen so far https://docs.rs/riscv-rt/latest/riscv_rt/ has address ranges hard-coded in a linker script for different regions, and when passing an ELF file to -kernel, QEMU maps it to those addresses but boots at 0x8000_ regardless. * With `qemu-system-riscv32 -machine virt -bios none -kernel something.elf -s -S`, GDB shows that execution starts at the lowest address of RAM, not of flash like I expected. Then what is emulated flash for? If you supply a flash image we will start executing from flash automatically. Passing with -drive? Should I use that instead of -kernel? * To what extent is the above calling convention standardized? I found similar things in coreboot[4] and in OpenSBI[5] Good question. I don't think it's specified in a spec, but it is very common Should we document this convention as something guest code can rely on? -- Simon Sapin
[PATCH v2 1/1] i386/monitor: Fix page table walking issue for LA57 enabled guest
Inverse the condition checking to PG_PRESENT_MASK when walk LA57
guest's pdpe/pde for "info mem" command.
The current condition checking:
if (PG_PRESENT_MASK is set)
Skip low level page table.
else
Try to walk low level page table.
This is wrong because PG_PRESENT_MASK is set means the pdpe/pde is
present so we should continue walking the low level page table it
points to. This issue leads to no mapping information is collected for
LA57 guest when run the command.
v2:
1. Fix Typo (Zhang Chen and Markus Armbruster
).
2. Rewrite commit message (Markus Armbruster ).
3. Add Fixes tag (Markus Armbruster ).
Fixes: 6c7c3c21f9 ("x86: implement la57 paging mode")
Signed-off-by: Yuan Yao
Reviewed-by: Zhang Chen
---
target/i386/monitor.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 8e4b4d600c..3339550bbe 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -489,7 +489,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
pdpe = le64_to_cpu(pdpe);
end = (l0 << 48) + (l1 << 39) + (l2 << 30);
-if (pdpe & PG_PRESENT_MASK) {
+if (!(pdpe & PG_PRESENT_MASK)) {
prot = 0;
mem_print(mon, env, &start, &last_prot, end, prot);
continue;
@@ -508,7 +508,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
pde = le64_to_cpu(pde);
end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21);
-if (pde & PG_PRESENT_MASK) {
+if (!(pde & PG_PRESENT_MASK)) {
prot = 0;
mem_print(mon, env, &start, &last_prot, end, prot);
continue;
--
2.27.0
Re: QEMU Disassembler
Actually, I have gotten the QEMU disassembler to run with some short customization. But I am having trouble understanding the output. I see lots of lines like this: | OBJD-H: 06040102a83507000cd8027620272573004c04cd20c100782244038c On Sun, Jun 26, 2022 at 11:00 PM Kenneth Adam Miller < kennethadammil...@gmail.com> wrote: > Hello all, > > How can I call the QEMU disassembler to run on an argument set of bytes? >
[PATCH 01/12] qtest: meson.build changes required to integrate python based qtests
These are some basic changes required in meson.build file in order to
incorporate python based qtests later on. No new qtests have been added in this
change.
Signed-off-by: Ani Sinha
---
tests/qtest/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 31287a9173..ad52f1c81b 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -310,6 +310,8 @@ qtests += {'dbus-display-test': [dbus_display1, gio]}
endif
qtest_executables = {}
+other_deps = []
+
foreach dir : target_dirs
if not dir.endswith('-softmmu')
continue
@@ -327,6 +329,7 @@ foreach dir : target_dirs
endif
qtest_env.set('G_TEST_DBUS_DAEMON', meson.project_source_root() /
'tests/dbus-vmstate-daemon.sh')
qtest_env.set('QTEST_QEMU_BINARY', './qemu-system-' + target_base)
+ qtest_env.set('QTEST_SOURCE_ROOT', meson.project_source_root())
if have_tools and have_vhost_user_blk_server
qtest_env.set('QTEST_QEMU_STORAGE_DAEMON_BINARY',
'./storage-daemon/qemu-storage-daemon')
test_deps += [qsd]
@@ -351,7 +354,7 @@ foreach dir : target_dirs
endif
test('qtest-@0@/@1@'.format(target_base, test),
qtest_executables[test],
- depends: [test_deps, qtest_emulator, emulator_modules],
+ depends: [test_deps, qtest_emulator, emulator_modules, other_deps],
env: qtest_env,
args: ['--tap', '-k'],
protocol: 'tap',
--
2.25.1
Re: [PATCH 00/12] Introduce new acpi/smbios qtests using biosbits
On Mon, Jun 27, 2022 at 12:14 PM Ani Sinha wrote: > > Biosbits is a software written by Josh Triplett that can be downloaded by > visiting https://biosbits.org/. The github codebase can be found here: > https://github.com/biosbits/bits/tree/master. It is a software that exercizes > the bios components such as acpi and smbios tables directly through acpica > bios interpreter (a freely available C based library written by Intel, > downloadable from https://acpica.org/ and is included with biosbits) without > an > operating system getting involved in between. > There are several advantages to directly testing the bios in a real physical > machine or VM as opposed to indirectly discovering bios issues through the > operating system. For one thing, the OSes tend to hide bios problems from the > end user. The other is that we have more control of what we wanted to test > and how by directly using acpica interpreter on top of the bios on a running > system. More details on the inspiration for developing biosbits and its real > life uses can be found in (a) and (b). > This patchset contains QEMU qtests written in python that exercizes the QEMU > bios components using biosbits and reports test failures. > > Details of each of the files added by this patchset are provided in the README > file which is part of Patch 11. Every effort to contact Josh, through various > means including email, twitter, linkedIn etc has failed. Hence, the changes to > build biosbits with the newer compiler, upgrade acpica and other changes are > currently maintained in a forked project in my personal github. We may want to > maintain bits in a separate fork in a stable repository that is accessible by > QEMU developers. > > The newly introduced qtest currently only run for x86_64 platform. They pass > both when running make check on a baremetal box as well as from inside a vm. > > Thanks to Igor M for pointing me to this work. > > (a) > https://blog.linuxplumbersconf.org/2011/ocw/system/presentations/867/original/bits.pdf > (b) https://www.youtube.com/watch?v=36QIepyUuhg Doh, sending the patch series failed since google won't allow file sizes larger than 25 MB. The bits prebuilt binaries have sizes 30 MB and 40 MB in two separate patches :( > > Ani Sinha (12): > qtest: meson.build changes required to integrate python based qtests > acpi/tests/bits: add prebuilt bios bits zip archive > acpi/tests/bits: add prebuilt bits generated grub modules and scripts > acpi/tests/bits: initial commit of test scripts that are run by > biosbits > acpi/tests/bits: disable acpi PSS tests that are failing in biosbits > acpi/tests/bits: add smilatency test suite from bits in order to > disable it > acpi/tests/bits: disable smilatency test since it does not pass > everytime > acpi/tests/bits: add biosbits config file for running bios tests > acpi/tests/bits: add acpi and smbios python tests that uses biosbits > acpi/tests/bits: add acpi bits qtest directory in meson for running > tests > acpi/tests/bits: add README file for bits qtests > MAINTAINERS: add myself as the maintainer for acpi biosbits qtests > > MAINTAINERS |5 + > tests/qtest/acpi-bits/README | 168 ++ > tests/qtest/acpi-bits/acpi-bits-test-venv.sh | 59 + > tests/qtest/acpi-bits/acpi-bits-test.py | 327 +++ > .../qtest/acpi-bits/bits-config/bits-cfg.txt | 18 + > tests/qtest/acpi-bits/bits-config/meson.build | 11 + > tests/qtest/acpi-bits/bits-tests/meson.build | 11 + > tests/qtest/acpi-bits/bits-tests/smbios.py| 2430 + > .../qtest/acpi-bits/bits-tests/smilatency.py | 103 + > tests/qtest/acpi-bits/bits-tests/testacpi.py | 283 ++ > tests/qtest/acpi-bits/bits-tests/testcpuid.py | 83 + > tests/qtest/acpi-bits/meson.build | 39 + > .../acpi-bits/prebuilt/bits-2095-grub.tar.gz | Bin 0 -> 41416278 bytes > tests/qtest/acpi-bits/prebuilt/bits-2095.zip | Bin 0 -> 31922898 bytes > tests/qtest/acpi-bits/prebuilt/meson.build| 11 + > tests/qtest/acpi-bits/requirements.txt|1 + > tests/qtest/meson.build |7 +- > 17 files changed, 3555 insertions(+), 1 deletion(-) > create mode 100644 tests/qtest/acpi-bits/README > create mode 100644 tests/qtest/acpi-bits/acpi-bits-test-venv.sh > create mode 100644 tests/qtest/acpi-bits/acpi-bits-test.py > create mode 100644 tests/qtest/acpi-bits/bits-config/bits-cfg.txt > create mode 100644 tests/qtest/acpi-bits/bits-config/meson.build > create mode 100644 tests/qtest/acpi-bits/bits-tests/meson.build > create mode 100644 tests/qtest/acpi-bits/bits-tests/smbios.py > create mode 100644 tests/qtest/acpi-bits/bits-tests/smilatency.py > create mode 100644 tests/qtest/acpi-bits/bits-tests/testacpi.py > create mode 100644 tests/qtest/acpi-bits/bits-tests/testcpuid.py > create mode 100644 tests/qtest/acpi-bits/meson.build > create mode 100644 tests/qtest/acpi
[PATCH 00/12] Introduce new acpi/smbios qtests using biosbits
Biosbits is a software written by Josh Triplett that can be downloaded by visiting https://biosbits.org/. The github codebase can be found here: https://github.com/biosbits/bits/tree/master. It is a software that exercizes the bios components such as acpi and smbios tables directly through acpica bios interpreter (a freely available C based library written by Intel, downloadable from https://acpica.org/ and is included with biosbits) without an operating system getting involved in between. There are several advantages to directly testing the bios in a real physical machine or VM as opposed to indirectly discovering bios issues through the operating system. For one thing, the OSes tend to hide bios problems from the end user. The other is that we have more control of what we wanted to test and how by directly using acpica interpreter on top of the bios on a running system. More details on the inspiration for developing biosbits and its real life uses can be found in (a) and (b). This patchset contains QEMU qtests written in python that exercizes the QEMU bios components using biosbits and reports test failures. Details of each of the files added by this patchset are provided in the README file which is part of Patch 11. Every effort to contact Josh, through various means including email, twitter, linkedIn etc has failed. Hence, the changes to build biosbits with the newer compiler, upgrade acpica and other changes are currently maintained in a forked project in my personal github. We may want to maintain bits in a separate fork in a stable repository that is accessible by QEMU developers. The newly introduced qtest currently only run for x86_64 platform. They pass both when running make check on a baremetal box as well as from inside a vm. Thanks to Igor M for pointing me to this work. (a) https://blog.linuxplumbersconf.org/2011/ocw/system/presentations/867/original/bits.pdf (b) https://www.youtube.com/watch?v=36QIepyUuhg Ani Sinha (12): qtest: meson.build changes required to integrate python based qtests acpi/tests/bits: add prebuilt bios bits zip archive acpi/tests/bits: add prebuilt bits generated grub modules and scripts acpi/tests/bits: initial commit of test scripts that are run by biosbits acpi/tests/bits: disable acpi PSS tests that are failing in biosbits acpi/tests/bits: add smilatency test suite from bits in order to disable it acpi/tests/bits: disable smilatency test since it does not pass everytime acpi/tests/bits: add biosbits config file for running bios tests acpi/tests/bits: add acpi and smbios python tests that uses biosbits acpi/tests/bits: add acpi bits qtest directory in meson for running tests acpi/tests/bits: add README file for bits qtests MAINTAINERS: add myself as the maintainer for acpi biosbits qtests MAINTAINERS |5 + tests/qtest/acpi-bits/README | 168 ++ tests/qtest/acpi-bits/acpi-bits-test-venv.sh | 59 + tests/qtest/acpi-bits/acpi-bits-test.py | 327 +++ .../qtest/acpi-bits/bits-config/bits-cfg.txt | 18 + tests/qtest/acpi-bits/bits-config/meson.build | 11 + tests/qtest/acpi-bits/bits-tests/meson.build | 11 + tests/qtest/acpi-bits/bits-tests/smbios.py| 2430 + .../qtest/acpi-bits/bits-tests/smilatency.py | 103 + tests/qtest/acpi-bits/bits-tests/testacpi.py | 283 ++ tests/qtest/acpi-bits/bits-tests/testcpuid.py | 83 + tests/qtest/acpi-bits/meson.build | 39 + .../acpi-bits/prebuilt/bits-2095-grub.tar.gz | Bin 0 -> 41416278 bytes tests/qtest/acpi-bits/prebuilt/bits-2095.zip | Bin 0 -> 31922898 bytes tests/qtest/acpi-bits/prebuilt/meson.build| 11 + tests/qtest/acpi-bits/requirements.txt|1 + tests/qtest/meson.build |7 +- 17 files changed, 3555 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/acpi-bits/README create mode 100644 tests/qtest/acpi-bits/acpi-bits-test-venv.sh create mode 100644 tests/qtest/acpi-bits/acpi-bits-test.py create mode 100644 tests/qtest/acpi-bits/bits-config/bits-cfg.txt create mode 100644 tests/qtest/acpi-bits/bits-config/meson.build create mode 100644 tests/qtest/acpi-bits/bits-tests/meson.build create mode 100644 tests/qtest/acpi-bits/bits-tests/smbios.py create mode 100644 tests/qtest/acpi-bits/bits-tests/smilatency.py create mode 100644 tests/qtest/acpi-bits/bits-tests/testacpi.py create mode 100644 tests/qtest/acpi-bits/bits-tests/testcpuid.py create mode 100644 tests/qtest/acpi-bits/meson.build create mode 100644 tests/qtest/acpi-bits/prebuilt/bits-2095-grub.tar.gz create mode 100644 tests/qtest/acpi-bits/prebuilt/bits-2095.zip create mode 100644 tests/qtest/acpi-bits/prebuilt/meson.build create mode 100644 tests/qtest/acpi-bits/requirements.txt -- 2.25.1
Re: [PATCH 00/12] Introduce new acpi/smbios qtests using biosbits
On Mon, Jun 27, 2022 at 12:22 PM Ani Sinha wrote: > > On Mon, Jun 27, 2022 at 12:14 PM Ani Sinha wrote: > > > > Biosbits is a software written by Josh Triplett that can be downloaded by > > visiting https://biosbits.org/. The github codebase can be found here: > > https://github.com/biosbits/bits/tree/master. It is a software that > > exercizes > > the bios components such as acpi and smbios tables directly through acpica > > bios interpreter (a freely available C based library written by Intel, > > downloadable from https://acpica.org/ and is included with biosbits) > > without an > > operating system getting involved in between. > > There are several advantages to directly testing the bios in a real physical > > machine or VM as opposed to indirectly discovering bios issues through the > > operating system. For one thing, the OSes tend to hide bios problems from > > the > > end user. The other is that we have more control of what we wanted to test > > and how by directly using acpica interpreter on top of the bios on a running > > system. More details on the inspiration for developing biosbits and its real > > life uses can be found in (a) and (b). > > This patchset contains QEMU qtests written in python that exercizes the QEMU > > bios components using biosbits and reports test failures. > > > > Details of each of the files added by this patchset are provided in the > > README > > file which is part of Patch 11. Every effort to contact Josh, through > > various > > means including email, twitter, linkedIn etc has failed. Hence, the changes > > to > > build biosbits with the newer compiler, upgrade acpica and other changes are > > currently maintained in a forked project in my personal github. We may want > > to > > maintain bits in a separate fork in a stable repository that is accessible > > by > > QEMU developers. > > > > The newly introduced qtest currently only run for x86_64 platform. They pass > > both when running make check on a baremetal box as well as from inside a vm. > > > > Thanks to Igor M for pointing me to this work. > > > > (a) > > https://blog.linuxplumbersconf.org/2011/ocw/system/presentations/867/original/bits.pdf > > (b) https://www.youtube.com/watch?v=36QIepyUuhg > > Doh, sending the patch series failed since google won't allow file > sizes larger than 25 MB. The bits prebuilt binaries have sizes 30 MB > and 40 MB in two separate patches :( I have pushed the patchset here: https://gitlab.com/anisinha/qemu/-/commits/acpi-bits . > > > > > Ani Sinha (12): > > qtest: meson.build changes required to integrate python based qtests > > acpi/tests/bits: add prebuilt bios bits zip archive > > acpi/tests/bits: add prebuilt bits generated grub modules and scripts > > acpi/tests/bits: initial commit of test scripts that are run by > > biosbits > > acpi/tests/bits: disable acpi PSS tests that are failing in biosbits > > acpi/tests/bits: add smilatency test suite from bits in order to > > disable it > > acpi/tests/bits: disable smilatency test since it does not pass > > everytime > > acpi/tests/bits: add biosbits config file for running bios tests > > acpi/tests/bits: add acpi and smbios python tests that uses biosbits > > acpi/tests/bits: add acpi bits qtest directory in meson for running > > tests > > acpi/tests/bits: add README file for bits qtests > > MAINTAINERS: add myself as the maintainer for acpi biosbits qtests > > > > MAINTAINERS |5 + > > tests/qtest/acpi-bits/README | 168 ++ > > tests/qtest/acpi-bits/acpi-bits-test-venv.sh | 59 + > > tests/qtest/acpi-bits/acpi-bits-test.py | 327 +++ > > .../qtest/acpi-bits/bits-config/bits-cfg.txt | 18 + > > tests/qtest/acpi-bits/bits-config/meson.build | 11 + > > tests/qtest/acpi-bits/bits-tests/meson.build | 11 + > > tests/qtest/acpi-bits/bits-tests/smbios.py| 2430 + > > .../qtest/acpi-bits/bits-tests/smilatency.py | 103 + > > tests/qtest/acpi-bits/bits-tests/testacpi.py | 283 ++ > > tests/qtest/acpi-bits/bits-tests/testcpuid.py | 83 + > > tests/qtest/acpi-bits/meson.build | 39 + > > .../acpi-bits/prebuilt/bits-2095-grub.tar.gz | Bin 0 -> 41416278 bytes > > tests/qtest/acpi-bits/prebuilt/bits-2095.zip | Bin 0 -> 31922898 bytes > > tests/qtest/acpi-bits/prebuilt/meson.build| 11 + > > tests/qtest/acpi-bits/requirements.txt|1 + > > tests/qtest/meson.build |7 +- > > 17 files changed, 3555 insertions(+), 1 deletion(-) > > create mode 100644 tests/qtest/acpi-bits/README > > create mode 100644 tests/qtest/acpi-bits/acpi-bits-test-venv.sh > > create mode 100644 tests/qtest/acpi-bits/acpi-bits-test.py > > create mode 100644 tests/qtest/acpi-bits/bits-config/bits-cfg.txt > > create mode 100644 tests/qtest/acpi-bits/bits-config/meson.build > > create mode 100644 tests/qtest/acpi-bits/bits-tests/meson.build > > create mode 10
