[Qemu-devel] [PATCH 0/1 v2] Fix do_rt_sigreturn on m68k linux userspace emulation
Changelog: v2: Avoid unneeded copy, use correct endianness. Michael Karcher (1): Fix do_rt_sigreturn on m68k linux userspace emulation linux-user/signal.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.1.4
[Qemu-devel] [PATCH 1/1 v2] Fix do_rt_sigreturn on m68k linux userspace emulation
do_rt_sigreturn uses an uninitialised local variable instead of fetching
the old signal mask directly from the signal frame when restoring the mask,
so the signal mask is undefined after do_rt_sigreturn. As the signal
frame data is in target-endian order, target_to_host_sigset instead of
target_to_host_sigset_internal is required.
do_sigreturn is correct in using target_to_host_sigset_internal, because
get_user already did the endianness conversion.
Signed-off-by: Michael Karcher
---
linux-user/signal.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index e03ed60..13f9142 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -5258,14 +5258,13 @@ long do_rt_sigreturn(CPUM68KState *env)
{
struct target_rt_sigframe *frame;
abi_ulong frame_addr = env->aregs[7] - 4;
-target_sigset_t target_set;
sigset_t set;
int d0;
if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
goto badframe;
-target_to_host_sigset_internal(&set, &target_set);
+target_to_host_sigset(&set, &frame->uc.tuc_sigmask);
do_sigprocmask(SIG_SETMASK, &set, NULL);
/* restore registers */
--
2.1.4
Re: [Qemu-devel] [RFC PATCH 0/8] Towards an Heterogeneous QEMU
Hello Peter, Apologies for the highly delayed response. On Nov 13, 2015 08:02, "Peter Crosthwaite" wrote: > > Hi Christian, > > Sorry about the delayed response. > > On Tue, Oct 27, 2015 at 3:30 AM, Christian Pinto < c.pi...@virtualopensystems.com> wrote: >> >> >> >> On 25/10/2015 22:38, Peter Crosthwaite wrote: >>> >>> On Thu, Oct 22, 2015 at 2:21 AM, Christian Pinto >>> wrote: Hello Peter, On 07/10/2015 17:48, Peter Crosthwaite wrote: > > On Mon, Oct 5, 2015 at 8:50 AM, Christian Pinto > wrote: >> >> Hello Peter, >> >> thanks for your comments >> >> On 01/10/2015 18:26, Peter Crosthwaite wrote: >>> >>> On Tue, Sep 29, 2015 at 6:57 AM, Christian Pinto >>> wrote: Hi all, This RFC patch-series introduces the set of changes enabling the architectural elements to model the architecture presented in a previous RFC letter: "[Qemu-devel][RFC] Towards an Heterogeneous QEMU". and the OS binary image needs to be placed in memory at model startup. >>> I don't see what this limitation is exactly. Can you explain more? I >>> do see a need to work on the ARM bootloader for AMP flows, it is a >>> pure SMP bootloader than assumes total control. >> >> the problem here was to me that when we launch QEMU a binary needs to be >> provided and put in memory >> in order to be executed. In this patch series the slave doesn't have a >> proper memory allocated when first launched. > > But it could though couldn't it? Can't the slave guest just have full > access to it's own address space (probably very similar to the masters > address space) from machine init time? This seems more realistic than > setting up the hardware based on guest level information. Actually the address space for a slave is built at init time, the thing that is not completely configured is the memory region modeling the RAM. Such region is configured in terms of size, but there is no pointer to the actual memory. The pointer is mmap-ed later before the slave boots. >>> based on what information? Is the master guest controlling this? If so >>> what is the real-hardware analogue for this concept where the address >>> map of the slave can change (i.e. be configured) at runtime? >> >> Hello Peter, >> >> The memory map of a slave is not controlled by the master guest, since it is >> dependent from the machine model used for the slave. The only thing the master >> controls is the subset of the main memory that is assigned to a slave. By >> saying that the memory pointer is sent to the slave later, before the boot, it is like setting the >> boot address for that specific slave within the whole platform memory. So >> essentially the offset passed for the mmap is from beginning of master memory up to the >> beginning of the memory carved out for the specific slave. I see this as a way to >> protect the master memory from malicious accesses from the slave side, so this >> way the slave will only "see" the part of the memory that it got assigned. >> > > That does sound like memory map control though. Is it simpler to just give the slave full access and implement such protections as a specific feature (probably some sort of IOMMU)? > Yes it is a kind of memory map control. An IOMMU like component would do the job, but as said already most of the focus of this project was on the IDM and the inter-QEMU communication. We could consider the implementation of an IOMMU like component in future extensions. >> >> The information about memory (fd + offset for mmap) is sent only later >> when >> the boot is triggered. This is also >> safe since the slave will be waiting in the incoming state, and thus no >> corruption or errors can happen before the >> boot is triggered. > > I was thinking more about your comment about slave-to-slave > interrupts. This would just trivially be a local software-generated > interrupts of some form within the slave cluster. Sorry, I did not catch your comment at first time. You are right, if cores are in the same cluster a software generated interrupt is going to be enough. Of course the eventfd based interrupts make sense for a remote QEMU. >>> Is eventfd a better implementation of remote-port GPIOs as in the Xilinx work? >> >> >> Functionally I think they provide the same behavior. We went for eventfd since >> when designing the code of the IDM we based it on what available on upstream QEMU >> to signal events between processes (e.g., eventfd). >> >>> Re the terminology, I don't like the idea of thinking of inter-qemu >>> "interrupts" as whatever system we decide on should be able to support >>> arbitrary signals going from one QEMU to another. I think the Xilinx >>> work already has reset
Re: [Qemu-devel] [PATCH 1/1] Fix do_rt_sigreturn on m68k linux userspace emulation
Le 12/12/2015 10:55, Michael Karcher a écrit : > On 09.12.2015 23:03, Laurent Vivier wrote: >> >> Le 09/12/2015 21:54, Michael Karcher a écrit : >>> do_rt_sigreturn forgets to initialize the signal mask variable before >>> trying to use it to restore the mask, so the signal mask is undefined >>> after do_rt_sigreturn. This bug has been in all the time since >>> 7181155d when do_rt_sigreturn was implemented for m68k. >>> [...] > BTW: documentation of the stack frame / signature for non-SA_SIGINFO > signal handlers seems to be quite lacking. There is a remark in the > sigaction manpage, but that one obviously only applies to i386... The best documentation is the kernel source: if you have a look at it you will see that these functions (setup_frame(), do_sigreturn(), ...) are just QEMU "translated" copy&paste. Laurent
[Qemu-devel] [PATCH 06/11] ppc: cleanup logging
Avoid "naked" qemu_log, bring documentation for DEBUG #defines
up to date.
Cc: David Gibson
Signed-off-by: Paolo Bonzini
---
target-ppc/excp_helper.c | 1 +
target-ppc/mmu-hash32.c | 12 ++--
target-ppc/mmu-hash64.c | 9 +
target-ppc/mmu_helper.c | 15 +++
target-ppc/timebase_helper.c | 10 ++
target-ppc/translate.c | 22 +-
6 files changed, 26 insertions(+), 43 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 102d789..dbc070c 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -23,6 +23,7 @@
#include "helper_regs.h"
//#define DEBUG_OP
+//#define DEBUG_SOFTWARE_TLB
//#define DEBUG_EXCEPTIONS
#ifdef DEBUG_EXCEPTIONS
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index dfee358..49bf120 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -24,17 +24,10 @@
#include "kvm_ppc.h"
#include "mmu-hash32.h"
-//#define DEBUG_MMU
//#define DEBUG_BAT
-#ifdef DEBUG_MMU
-# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
-#else
-# define LOG_MMU_STATE(cpu) do { } while (0)
-#endif
-
#ifdef DEBUG_BATS
-# define LOG_BATS(...) qemu_log(__VA_ARGS__)
+# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
#else
# define LOG_BATS(...) do { } while (0)
#endif
@@ -281,9 +274,8 @@ static int ppc_hash32_direct_store(CPUPPCState *env,
target_ulong sr,
}
return 1;
default:
-qemu_log("ERROR: instruction should not need "
+cpu_abort(cs, "ERROR: instruction should not need "
"address translation\n");
-abort();
}
if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
*raddr = eaddr;
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 7df6ede..34e20fa 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -23,17 +23,10 @@
#include "kvm_ppc.h"
#include "mmu-hash64.h"
-//#define DEBUG_MMU
//#define DEBUG_SLB
-#ifdef DEBUG_MMU
-# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
-#else
-# define LOG_MMU_STATE(cpu) do { } while (0)
-#endif
-
#ifdef DEBUG_SLB
-# define LOG_SLB(...) qemu_log(__VA_ARGS__)
+# define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
#else
# define LOG_SLB(...) do { } while (0)
#endif
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 30298d8..5217691 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -28,23 +28,22 @@
//#define DEBUG_BATS
//#define DEBUG_SOFTWARE_TLB
//#define DUMP_PAGE_TABLES
-//#define DEBUG_SOFTWARE_TLB
//#define FLUSH_ALL_TLBS
#ifdef DEBUG_MMU
-# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
+# define LOG_MMU_STATE(cpu) log_cpu_state_mask(CPU_LOG_MMU, (cpu), 0)
#else
# define LOG_MMU_STATE(cpu) do { } while (0)
#endif
#ifdef DEBUG_SOFTWARE_TLB
-# define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
+# define LOG_SWTLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
#else
# define LOG_SWTLB(...) do { } while (0)
#endif
#ifdef DEBUG_BATS
-# define LOG_BATS(...) qemu_log(__VA_ARGS__)
+# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
#else
# define LOG_BATS(...) do { } while (0)
#endif
@@ -162,7 +161,7 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx,
target_ulong pte0,
if (ctx->raddr != (hwaddr)-1ULL) {
/* all matches should have equal RPN, WIMG & PP */
if ((ctx->raddr & mmask) != (pte1 & mmask)) {
-qemu_log("Bad RPN/WIMG/PP\n");
+qemu_log_mask(CPU_LOG_MMU, "Bad RPN/WIMG/PP\n");
return -3;
}
}
@@ -508,7 +507,7 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env,
mmu_ctx_t *ctx,
/* Software TLB search */
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
#if defined(DUMP_PAGE_TABLES)
-if (qemu_log_enabled()) {
+if (qemu_log_mask(CPU_LOG_MMU)) {
hwaddr curaddr;
uint32_t a0, a1, a2, a3;
@@ -575,8 +574,8 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env,
mmu_ctx_t *ctx,
/* eciwx or ecowx */
return -4;
default:
-qemu_log("ERROR: instruction should not need "
-"address translation\n");
+qemu_log_mask(CPU_LOG_MMU, "ERROR: instruction should not need "
+ "address translation\n");
return -4;
}
if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
diff --git a/target-ppc/timebase_helper.c b/target-ppc/timebase_helper.c
index 865dcbe..cafa283 100644
--- a/target-ppc/timebase_helper.c
+++ b/target-ppc/timebase_helper.c
@@ -130,13 +130,14 @@ target_ulong helper_load_dcr(CPUPPCState *env,
target_ulong dcrn)
uint32_t val = 0;
if (unlikely(env->dcr_env == NULL)) {
-qemu_log("No DCR environ
[Qemu-devel] [PATCH 02/11] alpha: convert "naked" qemu_log to tracepoint
Cc: Richard Henderson
Signed-off-by: Paolo Bonzini
---
hw/alpha/pci.c | 3 ++-
trace-events | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/alpha/pci.c b/hw/alpha/pci.c
index d839dd5..5226e43 100644
--- a/hw/alpha/pci.c
+++ b/hw/alpha/pci.c
@@ -10,6 +10,7 @@
#include "alpha_sys.h"
#include "qemu/log.h"
#include "sysemu/sysemu.h"
+#include "trace.h"
/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */
@@ -73,7 +74,7 @@ static uint64_t iack_read(void *opaque, hwaddr addr, unsigned
size)
static void special_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
-qemu_log("pci: special write cycle");
+trace_alpha_pci_iack_write();
}
const MemoryRegionOps alpha_pci_iack_ops = {
diff --git a/trace-events b/trace-events
index 2fce98e..ee890c1 100644
--- a/trace-events
+++ b/trace-events
@@ -1756,6 +1756,9 @@ cpu_unhalt(int cpu_index) "unhalting cpu %d"
# hw/arm/virt-acpi-build.c
virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."
+# hw/alpha/pci.c
+alpha_pci_iack_write(void) ""
+
# audio/alsaaudio.c
alsa_revents(int revents) "revents = %d"
alsa_pollout(int i, int fd) "i = %d fd = %d"
--
2.5.0
[Qemu-devel] [PATCH 03/11] cris: avoid "naked" qemu_log
Cc: Edgar E. Iglesias
Signed-off-by: Paolo Bonzini
---
hw/char/etraxfs_ser.c | 2 +-
target-cris/helper.h| 1 -
target-cris/op_helper.c | 5 -
target-cris/translate.c | 2 +-
target-cris/translate_v10.c | 2 +-
5 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c
index 562021e..d4d875e 100644
--- a/hw/char/etraxfs_ser.c
+++ b/hw/char/etraxfs_ser.c
@@ -165,7 +165,7 @@ static void serial_receive(void *opaque, const uint8_t
*buf, int size)
/* Got a byte. */
if (s->rx_fifo_len >= 16) {
-qemu_log("WARNING: UART dropped char.\n");
+D(qemu_log("WARNING: UART dropped char.\n"));
return;
}
diff --git a/target-cris/helper.h b/target-cris/helper.h
index 0b383b2..ff35956 100644
--- a/target-cris/helper.h
+++ b/target-cris/helper.h
@@ -1,7 +1,6 @@
DEF_HELPER_2(raise_exception, void, env, i32)
DEF_HELPER_2(tlb_flush_pid, void, env, i32)
DEF_HELPER_2(spc_write, void, env, i32)
-DEF_HELPER_3(dump, void, i32, i32, i32)
DEF_HELPER_1(rfe, void, env)
DEF_HELPER_1(rfn, void, env)
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 5c0c14d..2296677 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -91,11 +91,6 @@ void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
#endif
}
-void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
-{
- qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
-}
-
/* Used by the tlb decoder. */
#define EXTRACT_FIELD(src, start, end) \
(((src) >> start) & ((1 << (end - start + 1)) - 1))
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 354c86d..2429931 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -779,7 +779,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
t_gen_subx_carry(dc, dst);
break;
default:
-qemu_log("illegal ALU op.\n");
+qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n");
BUG();
break;
}
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 3ab1c39..df20bdc 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -58,7 +58,7 @@ static inline int dec10_size(unsigned int size)
static inline void cris_illegal_insn(DisasContext *dc)
{
-qemu_log("illegal insn at pc=%x\n", dc->pc);
+qemu_log_mask(LOG_GUEST_ERROR, "illegal insn at pc=%x\n", dc->pc);
t_gen_raise_exception(EXCP_BREAK);
}
--
2.5.0
[Qemu-devel] [PATCH 10/11] linux-user: avoid "naked" qemu_log
Ensure that all log writes are protected by qemu_loglevel_mask or,
in serious cases, go to both the log and stderr.
Signed-off-by: Paolo Bonzini
---
linux-user/main.c | 71 ---
1 file changed, 31 insertions(+), 40 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 6783722..ee12035 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -45,6 +45,18 @@ static const char *cpu_model;
unsigned long mmap_min_addr;
unsigned long guest_base;
int have_guest_base;
+
+#define EXCP_DUMP(env, fmt, ...)\
+do {\
+CPUState *cs = ENV_GET_CPU(env);\
+fprintf(stderr, fmt , ## __VA_ARGS__); \
+cpu_dump_state(cs, stderr, fprintf, 0); \
+if (qemu_log_separate()) { \
+qemu_log(fmt, ## __VA_ARGS__); \
+log_cpu_state(cs, 0); \
+} \
+} while (0)
+
#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
/*
* When running 32-on-64 we should make sure we can fit all of the possible
@@ -416,8 +428,8 @@ void cpu_loop(CPUX86State *env)
break;
default:
pc = env->segs[R_CS].base + env->eip;
-fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x -
aborting\n",
-(long)pc, trapnr);
+EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x -
aborting\n",
+ (long)pc, trapnr);
abort();
}
process_pending_signals(env);
@@ -865,9 +877,7 @@ void cpu_loop(CPUARMState *env)
break;
default:
error:
-fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
-trapnr);
-cpu_dump_state(cs, stderr, fprintf, 0);
+EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n",
trapnr);
abort();
}
process_pending_signals(env);
@@ -1056,9 +1066,7 @@ void cpu_loop(CPUARMState *env)
env->xregs[0] = do_arm_semihosting(env);
break;
default:
-fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
-trapnr);
-cpu_dump_state(cs, stderr, fprintf, 0);
+EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n",
trapnr);
abort();
}
process_pending_signals(env);
@@ -1148,8 +1156,7 @@ void cpu_loop(CPUUniCore32State *env)
}
error:
-fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
-cpu_dump_state(cs, stderr, fprintf, 0);
+EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
abort();
}
#endif
@@ -1467,17 +1474,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn,
uint32_t val)
return -1;
}
-#define EXCP_DUMP(env, fmt, ...)\
-do {\
-CPUState *cs = ENV_GET_CPU(env);\
-fprintf(stderr, fmt , ## __VA_ARGS__); \
-cpu_dump_state(cs, stderr, fprintf, 0); \
-if (qemu_log_separate()) { \
-qemu_log(fmt, ## __VA_ARGS__); \
-log_cpu_state(cs, 0); \
-} \
-} while (0)
-
static int do_store_exclusive(CPUPPCState *env)
{
target_ulong addr;
@@ -2636,9 +2632,7 @@ done_syscall:
break;
default:
error:
-fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
-trapnr);
-cpu_dump_state(cs, stderr, fprintf, 0);
+EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n",
trapnr);
abort();
}
process_pending_signals(env);
@@ -2661,11 +2655,11 @@ void cpu_loop(CPUOpenRISCState *env)
switch (trapnr) {
case EXCP_RESET:
-qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
+qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n",
env->pc);
exit(EXIT_FAILURE);
break;
case EXCP_BUSERR:
-qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
+qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n",
env->pc);
gdbsig = TARGET_SIGBUS;
break;
case EXCP_DPF:
@@ -2674,25 +2668,25 @@ void cpu_loop(CPUOpenRISCState *env)
gdbsig
[Qemu-devel] [PATCH 00/11] Avoid always-active qemu_log calls
qemu_log calls should generally be wrapped by DEBUG_* preprocessor symbols or (preferred) qemu_log_mask should be used instead. This avoids that the upcoming integration of logging and tracing prints some log messages to stderr unconditionally. Similarly, most occurrences of qemu_log_enabled() should be changed to qemu_log_mask(). One exception is when these always-active qemu_log calls are coupled with printfs to stdout or stderr. These should be skipped if stderr is _already_ the logging destination, and the series thus introduces a new predicate qemu_log_separate() to replace qemu_log_enabled() in some cases. This series removes all the instances that I could find of these problems. Paolo Paolo Bonzini (11): qemu-log: introduce qemu_log_separate alpha: convert "naked" qemu_log to tracepoint cris: avoid "naked" qemu_log microblaze: avoid "naked" qemu_log s390x: avoid "naked" qemu_log ppc: cleanup logging tricore: avoid "naked" qemu_log xtensa: avoid "naked" qemu_log user: introduce "-d page" linux-user: avoid "naked" qemu_log linux-user: convert DEBUG_SIGNAL logging to tracepoints bsd-user/main.c | 4 +- bsd-user/signal.c | 2 - exec.c| 2 +- hw/alpha/pci.c| 3 +- hw/char/etraxfs_ser.c | 2 +- include/qemu/log.h| 8 +++ linux-user/elfload.c | 8 +-- linux-user/main.c | 75 --- linux-user/signal.c | 118 +- qemu-log.c| 2 + target-cris/helper.h | 1 - target-cris/op_helper.c | 5 -- target-cris/translate.c | 8 +-- target-cris/translate_v10.c | 2 +- target-microblaze/helper.c| 2 +- target-microblaze/mmu.c | 20 +++ target-microblaze/op_helper.c | 8 +-- target-microblaze/translate.c | 2 +- target-ppc/excp_helper.c | 8 +-- target-ppc/mmu-hash32.c | 12 + target-ppc/mmu-hash64.c | 9 +--- target-ppc/mmu_helper.c | 15 +++--- target-ppc/timebase_helper.c | 10 ++-- target-ppc/translate.c| 62 +++--- target-s390x/cc_helper.c | 2 +- target-s390x/helper.c | 2 +- target-s390x/misc_helper.c| 2 +- target-s390x/mmu_helper.c | 2 +- target-tricore/helper.c | 4 +- target-xtensa/gdbstub.c | 8 +-- target-xtensa/helper.c| 4 +- target-xtensa/op_helper.c | 20 +++ target-xtensa/translate.c | 28 +- target-xtensa/xtensa-semi.c | 2 +- trace-events | 14 + 35 files changed, 237 insertions(+), 239 deletions(-) -- 2.5.0
[Qemu-devel] [PATCH 07/11] tricore: avoid "naked" qemu_log
Cc: Bastian Koppelmann
Signed-off-by: Paolo Bonzini
---
target-tricore/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-tricore/helper.c b/target-tricore/helper.c
index 1808b28..1b70429 100644
--- a/target-tricore/helper.c
+++ b/target-tricore/helper.c
@@ -65,8 +65,8 @@ int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong
address,
access_type = ACCESS_INT;
ret = get_physical_address(env, &physical, &prot,
address, rw, access_type);
-qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx
- " prot %d\n", __func__, address, ret, physical, prot);
+qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical "
TARGET_FMT_plx
+ " prot %d\n", __func__, address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
tlb_set_page(cs, address & TARGET_PAGE_MASK,
--
2.5.0
[Qemu-devel] [PATCH 08/11] xtensa: avoid "naked" qemu_log
Cc: Max Filippov
Signed-off-by: Paolo Bonzini
---
target-xtensa/gdbstub.c | 8
target-xtensa/helper.c | 4 ++--
target-xtensa/op_helper.c | 20 ++--
target-xtensa/translate.c | 28 ++--
target-xtensa/xtensa-semi.c | 2 +-
5 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/target-xtensa/gdbstub.c b/target-xtensa/gdbstub.c
index bc2e1b5..dcf05ad 100644
--- a/target-xtensa/gdbstub.c
+++ b/target-xtensa/gdbstub.c
@@ -63,8 +63,8 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t
*mem_buf, int n)
return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
default:
-qemu_log("%s from reg %d of unsupported type %d\n",
- __func__, n, reg->type);
+qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported type %d\n",
+ __func__, n, reg->type);
return 0;
}
}
@@ -117,8 +117,8 @@ int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
break;
default:
-qemu_log("%s to reg %d of unsupported type %d\n",
- __func__, n, reg->type);
+qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported type %d\n",
+ __func__, n, reg->type);
return 0;
}
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index 2c3447b..cf25bf8 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -254,8 +254,8 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
env->config->exception_vector[cs->exception_index]);
env->exception_taken = 1;
} else {
-qemu_log("%s(pc = %08x) bad exception_index: %d\n",
-__func__, env->pc, cs->exception_index);
+qemu_log_mask(CPU_LOG_INT, "%s(pc = %08x) bad exception_index:
%d\n",
+ __func__, env->pc, cs->exception_index);
}
break;
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 718e54e..02100af 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -245,8 +245,8 @@ void HELPER(entry)(CPUXtensaState *env, uint32_t pc,
uint32_t s, uint32_t imm)
{
int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
-qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
-pc, env->sregs[PS]);
+qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x),
PS = %08x\n",
+ pc, env->sregs[PS]);
HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
} else {
uint32_t windowstart = xtensa_replicate_windowstart(env) >>
@@ -307,9 +307,9 @@ uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
if (n == 0 || (m != 0 && m != n) ||
((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
-qemu_log("Illegal retw instruction(pc = %08x), "
-"PS = %08x, m = %d, n = %d\n",
-pc, env->sregs[PS], m, n);
+qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc = %08x), "
+ "PS = %08x, m = %d, n = %d\n",
+ pc, env->sregs[PS], m, n);
HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
} else {
int owb = windowbase;
@@ -743,8 +743,8 @@ void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
tlb_flush_page(cs, entry->vaddr);
} else {
-qemu_log("%s %d, %d, %d trying to set immutable entry\n",
-__func__, dtlb, wi, ei);
+qemu_log_mask(LOG_GUEST_ERROR, "%s %d, %d, %d trying to set
immutable entry\n",
+ __func__, dtlb, wi, ei);
}
} else {
tlb_flush_page(cs, entry->vaddr);
@@ -806,15 +806,15 @@ static void set_dbreak(CPUXtensaState *env, unsigned i,
uint32_t dbreaka,
}
/* contiguous mask after inversion is one less than some power of 2 */
if ((~mask + 1) & ~mask) {
-qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
+qemu_log_mask(LOG_GUEST_ERROR, "DBREAKC mask is not contiguous:
0x%08x\n", dbreakc);
/* cut mask after the first zero bit */
mask = 0x << (32 - clo32(mask));
}
if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
flags, &env->cpu_watchpoint[i])) {
env->cpu_watchpoint[i] = NULL;
-qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
-dbreaka & mask, ~mask + 1);
+qemu_log_mask(LOG_GUEST_ERROR, "Failed to set data breakpoint at
0x%08x/%d\n",
+ dbreaka & mask, ~mask + 1);
}
}
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 06b0163..fbcec94 100644
--- a/target-xtensa/translate.c
+++ b/target-xt
[Qemu-devel] [PATCH 05/11] s390x: avoid "naked" qemu_log
Convert to debug-only qemu_log.
Cc: Alexander Graf
Signed-off-by: Paolo Bonzini
---
target-s390x/cc_helper.c | 2 +-
target-s390x/misc_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c
index bfce3f1..c4ee002 100644
--- a/target-s390x/cc_helper.c
+++ b/target-s390x/cc_helper.c
@@ -560,7 +560,7 @@ void HELPER(sacf)(CPUS390XState *env, uint64_t a1)
env->psw.mask |= PSW_ASC_HOME;
break;
default:
-qemu_log("unknown sacf mode: %" PRIx64 "\n", a1);
+HELPER_LOG("unknown sacf mode: %" PRIx64 "\n", a1);
program_interrupt(env, PGM_SPECIFICATION, 2);
break;
}
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index b601a33..dab02d3 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s390x/misc_helper.c
@@ -299,7 +299,7 @@ void HELPER(spx)(CPUS390XState *env, uint64_t a1)
uint32_t prefix = a1 & 0x7fffe000;
env->psa = prefix;
-qemu_log("prefix: %#x\n", prefix);
+HELPER_LOG("prefix: %#x\n", prefix);
tlb_flush_page(cs, 0);
tlb_flush_page(cs, TARGET_PAGE_SIZE);
}
--
2.5.0
[Qemu-devel] [PATCH 01/11] qemu-log: introduce qemu_log_separate
In some cases, the same message is printed both on stderr and in the log.
Avoid duplicate output in the default case where stderr _is_ the log,
and standardize this to stderr+log where it used to use stdio+log.
Signed-off-by: Paolo Bonzini
---
exec.c| 2 +-
include/qemu/log.h| 7 +++
linux-user/main.c | 4 ++--
target-cris/translate.c | 6 --
target-ppc/excp_helper.c | 7 +++
target-ppc/translate.c| 40
target-s390x/helper.c | 2 +-
target-s390x/mmu_helper.c | 2 +-
8 files changed, 43 insertions(+), 27 deletions(-)
diff --git a/exec.c b/exec.c
index 53a4b8c..dd11ef9 100644
--- a/exec.c
+++ b/exec.c
@@ -870,7 +870,7 @@ void cpu_abort(CPUState *cpu, const char *fmt, ...)
vfprintf(stderr, fmt, ap);
fprintf(stderr, "\n");
cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
-if (qemu_log_enabled()) {
+if (qemu_log_separate()) {
qemu_log("qemu: fatal: ");
qemu_log_vprintf(fmt, ap2);
qemu_log("\n");
diff --git a/include/qemu/log.h b/include/qemu/log.h
index 362cbc4..964ab9d 100644
--- a/include/qemu/log.h
+++ b/include/qemu/log.h
@@ -28,6 +28,13 @@ static inline bool qemu_log_enabled(void)
return qemu_logfile != NULL;
}
+/* Returns true if qemu_log() will write somewhere else than stderr
+ */
+static inline bool qemu_log_separate(void)
+{
+return qemu_logfile != NULL && qemu_logfile != stderr;
+}
+
#define CPU_LOG_TB_OUT_ASM (1 << 0)
#define CPU_LOG_TB_IN_ASM (1 << 1)
#define CPU_LOG_TB_OP (1 << 2)
diff --git a/linux-user/main.c b/linux-user/main.c
index 8acfe0f..a04e91e 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1472,8 +1472,8 @@ do {
\
CPUState *cs = ENV_GET_CPU(env);\
fprintf(stderr, fmt , ## __VA_ARGS__); \
cpu_dump_state(cs, stderr, fprintf, 0); \
-qemu_log(fmt, ## __VA_ARGS__); \
-if (qemu_log_enabled()) { \
+if (qemu_log_separate()) { \
+qemu_log(fmt, ## __VA_ARGS__); \
log_cpu_state(cs, 0); \
} \
} while (0)
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 2d710cc..354c86d 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -130,8 +130,10 @@ typedef struct DisasContext {
static void gen_BUG(DisasContext *dc, const char *file, int line)
{
-printf("BUG: pc=%x %s %d\n", dc->pc, file, line);
-qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
+fprintf(stderr, "BUG: pc=%x %s %d\n", dc->pc, file, line);
+if (qemu_log_separate()) {
+qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
+}
cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
}
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 4250106..102d789 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -131,12 +131,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
/* Machine check exception is not enabled.
* Enter checkstop state.
*/
-if (qemu_log_enabled()) {
+fprintf(stderr, "Machine check while not allowed. "
+"Entering checkstop state\n");
+if (qemu_log_separate()) {
qemu_log("Machine check while not allowed. "
"Entering checkstop state\n");
-} else {
-fprintf(stderr, "Machine check while not allowed. "
-"Entering checkstop state\n");
}
cs->halted = 1;
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 41a7258..cdf46dd 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4285,19 +4285,23 @@ static inline void gen_op_mfspr(DisasContext *ctx)
* allowing userland application to read the PVR
*/
if (sprn != SPR_PVR) {
-qemu_log("Trying to read privileged spr %d (0x%03x) at "
- TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
-printf("Trying to read privileged spr %d (0x%03x) at "
- TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
+fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
+TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
+if (qemu_log_separate()) {
+qemu_log("Trying to read privileged spr %d (0x%03x) at "
+
[Qemu-devel] [PATCH 09/11] user: introduce "-d page"
Signed-off-by: Paolo Bonzini
---
bsd-user/main.c | 4 ++--
include/qemu/log.h | 1 +
linux-user/elfload.c | 8
linux-user/main.c| 4 ++--
qemu-log.c | 2 ++
5 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index adf2de0..1ecaeb5 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -938,7 +938,7 @@ int main(int argc, char **argv)
unsigned long tmp;
if (fscanf(fp, "%lu", &tmp) == 1) {
mmap_min_addr = tmp;
-qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
+qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n",
mmap_min_addr);
}
fclose(fp);
}
@@ -955,7 +955,7 @@ int main(int argc, char **argv)
free(target_environ);
-if (qemu_log_enabled()) {
+if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
qemu_log("guest_base 0x%lx\n", guest_base);
log_page_dump();
diff --git a/include/qemu/log.h b/include/qemu/log.h
index 964ab9d..d837d90 100644
--- a/include/qemu/log.h
+++ b/include/qemu/log.h
@@ -48,6 +48,7 @@ static inline bool qemu_log_separate(void)
#define LOG_GUEST_ERROR(1 << 11)
#define CPU_LOG_MMU(1 << 12)
#define CPU_LOG_TB_NOCHAIN (1 << 13)
+#define CPU_LOG_PAGE (1 << 14)
/* Returns true if a bit is set in the current loglevel mask
*/
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 8b17c0e..b90be12 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1743,7 +1743,7 @@ unsigned long init_guest_space(unsigned long host_start,
}
}
-qemu_log("Reserved 0x%lx bytes of guest address space\n", host_size);
+qemu_log_mask(CPU_LOG_PAGE, "Reserved 0x%lx bytes of guest address
space\n", host_size);
return real_start;
}
@@ -1784,9 +1784,9 @@ static void probe_guest_base(const char *image_name,
}
guest_base = real_start - loaddr;
-qemu_log("Relocating guest address space from 0x"
- TARGET_ABI_FMT_lx " to 0x%lx\n",
- loaddr, real_start);
+qemu_log_mask(CPU_LOG_PAGE, "Relocating guest address space from 0x"
+ TARGET_ABI_FMT_lx " to 0x%lx\n",
+ loaddr, real_start);
}
return;
diff --git a/linux-user/main.c b/linux-user/main.c
index a04e91e..6783722 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -4241,7 +4241,7 @@ int main(int argc, char **argv, char **envp)
unsigned long tmp;
if (fscanf(fp, "%lu", &tmp) == 1) {
mmap_min_addr = tmp;
-qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
+qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n",
mmap_min_addr);
}
fclose(fp);
}
@@ -4300,7 +4300,7 @@ int main(int argc, char **argv, char **envp)
free(target_environ);
-if (qemu_log_enabled()) {
+if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
qemu_log("guest_base 0x%lx\n", guest_base);
log_page_dump();
diff --git a/qemu-log.c b/qemu-log.c
index 7cb01a8..901b930 100644
--- a/qemu-log.c
+++ b/qemu-log.c
@@ -117,6 +117,8 @@ const QEMULogItem qemu_log_items[] = {
{ LOG_GUEST_ERROR, "guest_errors",
"log when the guest OS does something invalid (eg accessing a\n"
"non-existent register)" },
+{ CPU_LOG_PAGE, "page",
+ "dump pages at beginning of user mode emulation" },
{ CPU_LOG_TB_NOCHAIN, "nochain",
"do not chain compiled TBs so that \"exec\" and \"cpu\" show\n"
"complete traces" },
--
2.5.0
[Qemu-devel] [PATCH 04/11] microblaze: avoid "naked" qemu_log
Cc: Edgar E. Iglesias
Signed-off-by: Paolo Bonzini
---
target-microblaze/helper.c| 2 +-
target-microblaze/mmu.c | 20 ++--
target-microblaze/op_helper.c | 8
target-microblaze/translate.c | 2 +-
4 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 8257b0e..a482e47 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -128,7 +128,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_HW_EXCP:
if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
-qemu_log("Exception raised on system without exceptions!\n");
+qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system
without exceptions!\n");
return;
}
diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
index 2ef1dc2..ee95a04 100644
--- a/target-microblaze/mmu.c
+++ b/target-microblaze/mmu.c
@@ -60,7 +60,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int
newpid)
uint32_t t;
if (newpid & ~0xff)
-qemu_log("Illegal rpid=%x\n", newpid);
+qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid);
for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
/* Lookup and decode. */
@@ -121,7 +121,7 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
t0 &= 0x3;
if (tlb_zsel > mmu->c_mmu_zones) {
-qemu_log("tlb zone select out of range! %d\n", tlb_zsel);
+qemu_log_mask(LOG_GUEST_ERROR, "tlb zone select out of range!
%d\n", tlb_zsel);
t0 = 1; /* Ignore. */
}
@@ -183,7 +183,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
uint32_t r;
if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
-qemu_log("MMU access on MMU-less system\n");
+qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
return 0;
}
@@ -192,7 +192,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
case MMU_R_TLBLO:
case MMU_R_TLBHI:
if (!(env->mmu.c_mmu_tlb_access & 1)) {
-qemu_log("Invalid access to MMU reg %d\n", rn);
+qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg
%d\n", rn);
return 0;
}
@@ -204,7 +204,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
case MMU_R_PID:
case MMU_R_ZPR:
if (!(env->mmu.c_mmu_tlb_access & 1)) {
-qemu_log("Invalid access to MMU reg %d\n", rn);
+qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg
%d\n", rn);
return 0;
}
r = env->mmu.regs[rn];
@@ -224,7 +224,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
-qemu_log("MMU access on MMU-less system\n");
+qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
return;
}
@@ -235,7 +235,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
i = env->mmu.regs[MMU_R_TLBX] & 0xff;
if (rn == MMU_R_TLBHI) {
if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
-qemu_log("invalidating index %x at pc=%x\n",
+qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at
pc=%x\n",
i, env->sregs[SR_PC]);
env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
mmu_flush_idx(env, i);
@@ -246,7 +246,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
break;
case MMU_R_ZPR:
if (env->mmu.c_mmu_tlb_access <= 1) {
-qemu_log("Invalid access to MMU reg %d\n", rn);
+qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg
%d\n", rn);
return;
}
@@ -259,7 +259,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
break;
case MMU_R_PID:
if (env->mmu.c_mmu_tlb_access <= 1) {
-qemu_log("Invalid access to MMU reg %d\n", rn);
+qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg
%d\n", rn);
return;
}
@@ -274,7 +274,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
int hit;
if (env->mmu.c_mmu_tlb_access <= 1) {
-qemu_log("Invalid access to MMU reg %d\n", rn);
+qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg
%d\n", rn);
return;
}
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index d324347..5637462 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_h
Re: [Qemu-devel] [PATCH 1/1 v2] Fix do_rt_sigreturn on m68k linux userspace emulation
Le 12/12/2015 11:13, Michael Karcher a écrit :
> do_rt_sigreturn uses an uninitialised local variable instead of fetching
> the old signal mask directly from the signal frame when restoring the mask,
> so the signal mask is undefined after do_rt_sigreturn. As the signal
> frame data is in target-endian order, target_to_host_sigset instead of
> target_to_host_sigset_internal is required.
>
> do_sigreturn is correct in using target_to_host_sigset_internal, because
> get_user already did the endianness conversion.
>
> Signed-off-by: Michael Karcher
> ---
> linux-user/signal.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/linux-user/signal.c b/linux-user/signal.c
> index e03ed60..13f9142 100644
> --- a/linux-user/signal.c
> +++ b/linux-user/signal.c
> @@ -5258,14 +5258,13 @@ long do_rt_sigreturn(CPUM68KState *env)
> {
> struct target_rt_sigframe *frame;
> abi_ulong frame_addr = env->aregs[7] - 4;
> -target_sigset_t target_set;
> sigset_t set;
> int d0;
>
> if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
> goto badframe;
>
> -target_to_host_sigset_internal(&set, &target_set);
> +target_to_host_sigset(&set, &frame->uc.tuc_sigmask);
> do_sigprocmask(SIG_SETMASK, &set, NULL);
>
> /* restore registers */
>
Reviewed-by: Laurent Vivier
Tested-by: Laurent Vivier
[Qemu-devel] [PATCH 11/11] linux-user: convert DEBUG_SIGNAL logging to tracepoints
"Unimplemented" messages go to stderr, everything else goes to tracepoints
Signed-off-by: Paolo Bonzini
---
bsd-user/signal.c | 2 -
linux-user/signal.c | 118 ++--
trace-events| 11 +
3 files changed, 69 insertions(+), 62 deletions(-)
diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index e4ee2d0..4887ecc 100644
--- a/bsd-user/signal.c
+++ b/bsd-user/signal.c
@@ -26,8 +26,6 @@
#include "qemu.h"
#include "target_signal.h"
-//#define DEBUG_SIGNAL
-
void signal_init(void)
{
}
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 9d62e02..919aa83 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -28,8 +28,7 @@
#include "qemu.h"
#include "qemu-common.h"
#include "target_signal.h"
-
-//#define DEBUG_SIGNAL
+#include "trace.h"
static struct target_sigaltstack target_sigaltstack_used = {
.ss_sp = 0,
@@ -444,7 +443,9 @@ static void QEMU_NORETURN force_sig(int target_sig)
TaskState *ts = (TaskState *)cpu->opaque;
int host_sig, core_dumped = 0;
struct sigaction act;
+
host_sig = target_to_host_signal(target_sig);
+trace_user_force_sig(env, target_sig, host_sig);
gdb_signalled(env, target_sig);
/* dump core if supported by target binary format */
@@ -499,10 +500,7 @@ int queue_signal(CPUArchState *env, int sig,
target_siginfo_t *info)
abi_ulong handler;
int queue;
-#if defined(DEBUG_SIGNAL)
-fprintf(stderr, "queue_signal: sig=%d\n",
-sig);
-#endif
+trace_user_queue_signal(env, sig);
k = &ts->sigtab[sig - 1];
queue = gdb_queuesig ();
handler = sigact_table[sig - 1]._sa_handler;
@@ -587,9 +585,7 @@ static void host_signal_handler(int host_signum, siginfo_t
*info,
sig = host_to_target_signal(host_signum);
if (sig < 1 || sig > TARGET_NSIG)
return;
-#if defined(DEBUG_SIGNAL)
-fprintf(stderr, "qemu: got signal %d\n", sig);
-#endif
+trace_user_host_signal(env, host_signum, sig);
host_to_target_siginfo_noswap(&tinfo, info);
if (queue_signal(env, sig, &tinfo) == 1) {
/* interrupt the virtual CPU as soon as possible */
@@ -682,10 +678,6 @@ int do_sigaction(int sig, const struct target_sigaction
*act,
if (sig < 1 || sig > TARGET_NSIG || sig == TARGET_SIGKILL || sig ==
TARGET_SIGSTOP)
return -EINVAL;
k = &sigact_table[sig - 1];
-#if defined(DEBUG_SIGNAL)
-fprintf(stderr, "sigaction sig=%d act=0x%p, oact=0x%p\n",
-sig, act, oact);
-#endif
if (oact) {
__put_user(k->_sa_handler, &oact->_sa_handler);
__put_user(k->sa_flags, &oact->sa_flags);
@@ -909,6 +901,7 @@ static void setup_frame(int sig, struct target_sigaction
*ka,
int i;
frame_addr = get_sigframe(ka, env, sizeof(*frame));
+trace_user_setup_frame(env, frame_addr);
if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0))
goto give_sigsegv;
@@ -970,6 +963,7 @@ static void setup_rt_frame(int sig, struct target_sigaction
*ka,
int i;
frame_addr = get_sigframe(ka, env, sizeof(*frame));
+trace_user_setup_rt_frame(env, frame_addr);
if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0))
goto give_sigsegv;
@@ -1081,9 +1075,7 @@ long do_sigreturn(CPUX86State *env)
sigset_t set;
int eax, i;
-#if defined(DEBUG_SIGNAL)
-fprintf(stderr, "do_sigreturn\n");
-#endif
+trace_user_do_sigreturn(env, frame_addr);
if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
goto badframe;
/* set blocked signals */
@@ -1115,6 +1107,7 @@ long do_rt_sigreturn(CPUX86State *env)
int eax;
frame_addr = env->regs[R_ESP] - 4;
+trace_user_do_rt_sigreturn(env, frame_addr);
if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
goto badframe;
target_to_host_sigset(&set, &frame->uc.tuc_sigmask);
@@ -1318,6 +1311,7 @@ static void target_setup_frame(int usig, struct
target_sigaction *ka,
abi_ulong frame_addr, return_addr;
frame_addr = get_sigframe(ka, env);
+trace_user_setup_frame(env, frame_addr);
if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
goto give_sigsegv;
}
@@ -1377,6 +1371,7 @@ long do_rt_sigreturn(CPUARMState *env)
struct target_rt_sigframe *frame = NULL;
abi_ulong frame_addr = env->xregs[31];
+trace_user_do_rt_sigreturn(env, frame_addr);
if (frame_addr & 15) {
goto badframe;
}
@@ -1703,6 +1698,7 @@ static void setup_frame_v1(int usig, struct
target_sigaction *ka,
abi_ulong frame_addr = get_sigframe(ka, regs, sizeof(*frame));
int i;
+trace_user_setup_frame(regs, frame_addr);
if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0))
return;
@@ -1724,6 +1720,7 @@ static void setup_frame_v2(int usig, struct
target_sigaction *ka,
struct sigframe_v2 *frame;
[Qemu-devel] [PATCH v3 2/7] vmxnet3: Change the offset of the MSIX PBA table
Place the PBA table at 0x1000, as placed by VMware virtual hardware.
Signed-off-by: Shmulik Ladkani
---
hw/net/vmxnet3.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index d323895..97f0aea 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -51,7 +51,8 @@
#define VMXNET3_MSIX_BAR_IDX (2)
#define VMXNET3_OFF_MSIX_TABLE (0x000)
-#define VMXNET3_OFF_MSIX_PBA (0x800)
+#define VMXNET3_OFF_MSIX_PBA(s) \
+((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
/* Link speed in Mbps should be shifted by 16 */
#define VMXNET3_LINK_SPEED (1000 << 16)
@@ -2114,7 +2115,7 @@ vmxnet3_init_msix(VMXNET3State *s)
&s->msix_bar,
VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
&s->msix_bar,
-VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA,
+VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s),
VMXNET3_MSIX_OFFSET(s));
if (0 > res) {
--
1.9.1
[Qemu-devel] [PATCH v3 1/7] vmxnet3: Change offsets of msi/msix pci capabilities
Place device reported PCI capabilities at the same offsets as placed by
the VMware virtual hardware: MSI at [84], MSI-X at [9c].
Signed-off-by: Shmulik Ladkani
---
hw/net/vmxnet3.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 37373e5..d323895 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -36,6 +36,16 @@
#define VMXNET3_MSIX_BAR_SIZE 0x2000
#define MIN_BUF_SIZE 60
+/* Compatability flags for migration */
+#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
+#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
+(1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
+
+#define VMXNET3_MSI_OFFSET(s) \
+((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
+#define VMXNET3_MSIX_OFFSET(s) \
+((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
+
#define VMXNET3_BAR0_IDX (0)
#define VMXNET3_BAR1_IDX (1)
#define VMXNET3_MSIX_BAR_IDX (2)
@@ -313,6 +323,9 @@ typedef struct {
MACAddr *mcast_list;
uint32_t mcast_list_len;
uint32_t mcast_list_buff_size; /* needed for live migration. */
+
+/* Compatability flags for migration */
+uint32_t compat_flags;
} VMXNET3State;
/* Interrupt management */
@@ -2102,7 +2115,7 @@ vmxnet3_init_msix(VMXNET3State *s)
VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
&s->msix_bar,
VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA,
-0);
+VMXNET3_MSIX_OFFSET(s));
if (0 > res) {
VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
@@ -2130,7 +2143,6 @@ vmxnet3_cleanup_msix(VMXNET3State *s)
}
}
-#define VMXNET3_MSI_OFFSET(0x50)
#define VMXNET3_USE_64BIT (true)
#define VMXNET3_PER_VECTOR_MASK (false)
@@ -2140,7 +2152,7 @@ vmxnet3_init_msi(VMXNET3State *s)
PCIDevice *d = PCI_DEVICE(s);
int res;
-res = msi_init(d, VMXNET3_MSI_OFFSET, VMXNET3_MAX_NMSIX_INTRS,
+res = msi_init(d, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS,
VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK);
if (0 > res) {
VMW_WRPRN("Failed to initialize MSI, error %d", res);
--
1.9.1
[Qemu-devel] [PATCH v3 0/7] vmxnet3: Fine-tune device capabilities
Various fixes to what the vmxnet3 device reports in its PCI configuration space, in order to be aligned with VMware virtual hardware exposed by ESXi/Workstation. Since v2: Introduce the compatability properties in separate patches, per Jason Wang's comment Since v1: Added migration compatability, per Jason Wang's comment Shmulik Ladkani (7): vmxnet3: Change offsets of msi/msix pci capabilities vmxnet3: Change the offset of the MSIX PBA table vmxnet3: Introduce 'x-old-msi-offsets' backword compatability property vmxnet3: coding: Introduce VMXNET3Class vmxnet3: The vmxnet3 device is a PCIE endpoint vmxnet3: Introduce 'x-disable-pcie' backword compatability property vmxnet3: Report the Device Serial Number capability hw/net/vmxnet3.c| 114 +--- include/hw/compat.h | 8 2 files changed, 116 insertions(+), 6 deletions(-) -- 1.9.1
[Qemu-devel] [PATCH v3 4/7] vmxnet3: coding: Introduce VMXNET3Class
Introduce a class type for vmxnet3, and the usual
DEVICE_CLASS/DEVICE_GET_CLASS macros.
No semantic change.
Signed-off-by: Shmulik Ladkani
---
hw/net/vmxnet3.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index d1fe888..14d4dcb 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -119,9 +119,18 @@
#define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
+typedef struct VMXNET3Class {
+PCIDeviceClass parent_class;
+} VMXNET3Class;
+
#define TYPE_VMXNET3 "vmxnet3"
#define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
+#define VMXNET3_DEVICE_CLASS(klass) \
+OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3)
+#define VMXNET3_DEVICE_GET_CLASS(obj) \
+OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3)
+
/* Cyclic ring abstraction */
typedef struct {
hwaddr pa;
@@ -2592,6 +2601,7 @@ static void vmxnet3_class_init(ObjectClass *class, void
*data)
static const TypeInfo vmxnet3_info = {
.name = TYPE_VMXNET3,
.parent= TYPE_PCI_DEVICE,
+.class_size= sizeof(VMXNET3Class),
.instance_size = sizeof(VMXNET3State),
.class_init= vmxnet3_class_init,
.instance_init = vmxnet3_instance_init,
--
1.9.1
[Qemu-devel] [PATCH v3 3/7] vmxnet3: Introduce 'x-old-msi-offsets' backword compatability property
Following the previous patches, where vmxnet3's pci's msi/msix
capability offsets and msix's PBA table offsets have been changed, this
patch introduces a boolean property 'x-old-msi-offsets' to vmxnet3,
whose default is false.
Setting 'x-old-msi-offsets' to 'on' preserves the old offsets behavior,
which allows migration to older versions.
Signed-off-by: Shmulik Ladkani
---
hw/net/vmxnet3.c| 2 ++
include/hw/compat.h | 4
2 files changed, 6 insertions(+)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 97f0aea..d1fe888 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -2564,6 +2564,8 @@ static const VMStateDescription vmstate_vmxnet3 = {
static Property vmxnet3_properties[] = {
DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
+DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags,
+VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/compat.h b/include/hw/compat.h
index d0b1c4f..01e326d 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -18,6 +18,10 @@
.driver = "virtio-pci",\
.property = "migrate-extra",\
.value= "off",\
+},{\
+.driver = "vmxnet3",\
+.property = "x-old-msi-offsets",\
+.value= "on",\
},
#define HW_COMPAT_2_3 \
--
1.9.1
[Qemu-devel] [PATCH v3 5/7] vmxnet3: The vmxnet3 device is a PCIE endpoint
Report the 'express endpoint' capability if on a PCIE bus.
Signed-off-by: Shmulik Ladkani
---
hw/net/vmxnet3.c | 53 -
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 14d4dcb..7ded287 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -40,7 +40,11 @@
#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
(1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
+#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
+#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
+(1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
+#define VMXNET3_EXP_EP_OFFSET (0x48)
#define VMXNET3_MSI_OFFSET(s) \
((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
#define VMXNET3_MSIX_OFFSET(s) \
@@ -121,6 +125,7 @@
typedef struct VMXNET3Class {
PCIDeviceClass parent_class;
+DeviceRealize parent_dc_realize;
} VMXNET3Class;
#define TYPE_VMXNET3 "vmxnet3"
@@ -2256,6 +2261,10 @@ static void vmxnet3_pci_realize(PCIDevice *pci_dev,
Error **errp)
vmxnet3_net_init(s);
+if (pci_is_express(pci_dev) && pci_bus_is_express(pci_dev->bus)) {
+pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
+}
+
register_savevm(dev, "vmxnet3-msix", -1, 1,
vmxnet3_msix_save, vmxnet3_msix_load, s);
}
@@ -2525,6 +2534,29 @@ static const VMStateInfo int_state_info = {
.put = vmxnet3_put_int_state
};
+static bool vmxnet3_vmstate_need_pcie_device(void *opaque)
+{
+VMXNET3State *s = VMXNET3(opaque);
+
+return !(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE);
+}
+
+static bool vmxnet3_vmstate_test_pci_device(void *opaque, int version_id)
+{
+return !vmxnet3_vmstate_need_pcie_device(opaque);
+}
+
+static const VMStateDescription vmstate_vmxnet3_pcie_device = {
+.name = "vmxnet3/pcie",
+.version_id = 1,
+.minimum_version_id = 1,
+.needed = vmxnet3_vmstate_need_pcie_device,
+.fields = (VMStateField[]) {
+VMSTATE_PCIE_DEVICE(parent_obj, VMXNET3State),
+VMSTATE_END_OF_LIST()
+}
+};
+
static const VMStateDescription vmstate_vmxnet3 = {
.name = "vmxnet3",
.version_id = 1,
@@ -2532,7 +2564,9 @@ static const VMStateDescription vmstate_vmxnet3 = {
.pre_save = vmxnet3_pre_save,
.post_load = vmxnet3_post_load,
.fields = (VMStateField[]) {
-VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
+VMSTATE_STRUCT_TEST(parent_obj, VMXNET3State,
+vmxnet3_vmstate_test_pci_device, 0,
+vmstate_pci_device, PCIDevice),
VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
VMSTATE_BOOL(lro_supported, VMXNET3State),
@@ -2567,6 +2601,7 @@ static const VMStateDescription vmstate_vmxnet3 = {
},
.subsections = (const VMStateDescription*[]) {
&vmxstate_vmxnet3_mcast_list,
+&vmstate_vmxnet3_pcie_device,
NULL
}
};
@@ -2578,10 +2613,24 @@ static Property vmxnet3_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static void vmxnet3_realize(DeviceState *qdev, Error **errp)
+{
+VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev);
+PCIDevice *pci_dev = PCI_DEVICE(qdev);
+VMXNET3State *s = VMXNET3(qdev);
+
+if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) {
+pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
+}
+
+vc->parent_dc_realize(qdev, errp);
+}
+
static void vmxnet3_class_init(ObjectClass *class, void *data)
{
DeviceClass *dc = DEVICE_CLASS(class);
PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
+VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class);
c->realize = vmxnet3_pci_realize;
c->exit = vmxnet3_pci_uninit;
@@ -2591,6 +2640,8 @@ static void vmxnet3_class_init(ObjectClass *class, void
*data)
c->class_id = PCI_CLASS_NETWORK_ETHERNET;
c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
+vc->parent_dc_realize = dc->realize;
+dc->realize = vmxnet3_realize;
dc->desc = "VMWare Paravirtualized Ethernet v3";
dc->reset = vmxnet3_qdev_reset;
dc->vmsd = &vmstate_vmxnet3;
--
1.9.1
[Qemu-devel] [PATCH v3 7/7] vmxnet3: Report the Device Serial Number capability
Report the DSN extended PCI capability at 0x100.
DSN value is a transformation of device MAC address, as calculated
by VMware virtual hardware.
DSN is reported only if device is pcie.
Signed-off-by: Shmulik Ladkani
---
hw/net/vmxnet3.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index f9cd02b..2e4a5a5 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -49,6 +49,7 @@
((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
#define VMXNET3_MSIX_OFFSET(s) \
((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
+#define VMXNET3_DSN_OFFSET (0x100)
#define VMXNET3_BAR0_IDX (0)
#define VMXNET3_BAR1_IDX (1)
@@ -2224,6 +2225,22 @@ static const MemoryRegionOps b1_ops = {
},
};
+static uint8_t *vmxnet3_device_serial_num(VMXNET3State *s)
+{
+static uint64_t dsn_payload;
+uint8_t *dsnp = (uint8_t *)&dsn_payload;
+
+dsnp[0] = 0xfe;
+dsnp[1] = s->conf.macaddr.a[3];
+dsnp[2] = s->conf.macaddr.a[4];
+dsnp[3] = s->conf.macaddr.a[5];
+dsnp[4] = s->conf.macaddr.a[0];
+dsnp[5] = s->conf.macaddr.a[1];
+dsnp[6] = s->conf.macaddr.a[2];
+dsnp[7] = 0xff;
+return dsnp;
+}
+
static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
{
DeviceState *dev = DEVICE(pci_dev);
@@ -2261,8 +2278,15 @@ static void vmxnet3_pci_realize(PCIDevice *pci_dev,
Error **errp)
vmxnet3_net_init(s);
-if (pci_is_express(pci_dev) && pci_bus_is_express(pci_dev->bus)) {
-pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
+if (pci_is_express(pci_dev)) {
+if (pci_bus_is_express(pci_dev->bus)) {
+pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
+}
+
+pcie_add_capability(pci_dev, PCI_EXT_CAP_ID_DSN, 0x1,
+VMXNET3_DSN_OFFSET, PCI_EXT_CAP_DSN_SIZEOF);
+memcpy(pci_dev->config + VMXNET3_DSN_OFFSET + 4,
+ vmxnet3_device_serial_num(s), sizeof(uint64_t));
}
register_savevm(dev, "vmxnet3-msix", -1, 1,
--
1.9.1
[Qemu-devel] [PATCH v3 6/7] vmxnet3: Introduce 'x-disable-pcie' backword compatability property
Following the previous patch which changed vmxnet3 to be a pci express
device, this patch introduces a boolean property 'x-disable-pcie' whose
default is false.
Setting 'x-disable-pcie' to 'on' preserves the old 'pci device' (non
express) behavior. This allows migration to older versions.
Signed-off-by: Shmulik Ladkani
---
hw/net/vmxnet3.c| 2 ++
include/hw/compat.h | 4
2 files changed, 6 insertions(+)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 7ded287..f9cd02b 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -2610,6 +2610,8 @@ static Property vmxnet3_properties[] = {
DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags,
VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false),
+DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags,
+VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/compat.h b/include/hw/compat.h
index 01e326d..642b082 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -22,6 +22,10 @@
.driver = "vmxnet3",\
.property = "x-old-msi-offsets",\
.value= "on",\
+},{\
+.driver = "vmxnet3",\
+.property = "x-disable-pcie",\
+.value= "on",\
},
#define HW_COMPAT_2_3 \
--
1.9.1
[Qemu-devel] [PATCH] rtc: introduce nmi disable bit handler for cmos
The Non-Maskable Interrupt (NMI) Enable bit is 0x80 bit of
Port 0x70 (and its aliases). This bit must be 0b to enable
the hardware chipset to send a Non-Maskable Interrupt. When
set to a 1b, NMI's are disabled. This bit is commonly accessed
by applications, BIOS, and even the operating system since it is
used to block NMI assertions when sensitive code is executing.
Currently, QEMU do no not handle the bit, means Qemu cannot
block NMI occur, sometimes maybe cause a race between the CMOS
read/write and the NMI handler. If you are setting the CMOS clock
or reading CMOS RAM and an NMI occurs, Bad values could be written
to or read from the CMOS RAM, or the NMI operation might not
occur correctly.
This patch introduce nmi disable bit handler to fix the problem
and make the emulated CMOS like the real hardware.
Signed-off-by: Gonglei
---
Please refer to:
https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg00616.html
Note: We can't reproduce the problem, what a pity :(
I holp the patch can fix it. Please review, thanks!
---
hw/i386/kvm/apic.c | 4 +++-
hw/timer/mc146818rtc.c | 11 +++
include/hw/timer/mc146818rtc_regs.h | 3 +++
include/sysemu/sysemu.h | 1 +
target-i386/kvm.c | 4 ++--
vl.c| 1 +
6 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c
index 5b47056..deea49f 100644
--- a/hw/i386/kvm/apic.c
+++ b/hw/i386/kvm/apic.c
@@ -12,6 +12,7 @@
#include "hw/i386/apic_internal.h"
#include "hw/pci/msi.h"
#include "sysemu/kvm.h"
+#include "sysemu/sysemu.h"
static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
int reg_id, uint32_t val)
@@ -132,7 +133,8 @@ static void do_inject_external_nmi(void *data)
cpu_synchronize_state(cpu);
lvt = s->lvt[APIC_LVT_LINT1];
-if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) {
+if (!nmi_disabled && (lvt & APIC_LVT_MASKED)
+&& ((lvt >> 8) & 7) == APIC_DM_NMI) {
ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
if (ret < 0) {
fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index a9f0efd..aaa8b4e 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -389,6 +389,17 @@ static void cmos_ioport_write(void *opaque, hwaddr addr,
RTCState *s = opaque;
if ((addr & 1) == 0) {
+/*
+ * The Non-Maskable Interrupt (NMI) Enable bit is 0x80 bit of
+ * Port 0x70 (and its aliases). This bit must be 0b to enable
+ * the hardware chipset to send a Non-Maskable Interrupt. When
+ * set to a 1b, NMI's are disabled. This bit is commonly accessed
+ * by applications, BIOS, and even the operating system since it is
+ * used to block NMI assertions when sensitive code is executing.
+ */
+nmi_disabled = !!(data & NMI_DISABLE_BIT);
+CMOS_DPRINTF("cmos: nmi_disabled=%s\n",
+ nmi_disabled ? "true" : "false");
s->cmos_index = data & 0x7f;
} else {
CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n",
diff --git a/include/hw/timer/mc146818rtc_regs.h
b/include/hw/timer/mc146818rtc_regs.h
index ccdee42..175249f 100644
--- a/include/hw/timer/mc146818rtc_regs.h
+++ b/include/hw/timer/mc146818rtc_regs.h
@@ -64,4 +64,7 @@
#define REG_C_AF 0x20
#define REG_C_MASK 0x70
+/* PORT_CMOS_INDEX nmi disable bit */
+#define NMI_DISABLE_BIT 0x80
+
#endif
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 3bb8897..a5b2342 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -177,6 +177,7 @@ extern uint8_t qemu_extra_params_fw[2];
extern QEMUClockType rtc_clock;
extern const char *mem_path;
extern int mem_prealloc;
+extern bool nmi_disabled;
#define MAX_NODES 128
#define NUMA_NODE_UNASSIGNED MAX_NODES
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 6dc9846..abbd65b 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -2456,9 +2456,9 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
CPUX86State *env = &x86_cpu->env;
int ret;
-/* Inject NMI */
+/* Inject NMI Or SMI */
if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
-if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
+if (!nmi_disabled && (cpu->interrupt_request & CPU_INTERRUPT_NMI)) {
qemu_mutex_lock_iothread();
cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
qemu_mutex_unlock_iothread();
diff --git a/vl.c b/vl.c
index 4211ff1..ff5b06f 100644
--- a/vl.c
+++ b/vl.c
@@ -185,6 +185,7 @@ bool boot_strict;
uint8_t *boot_splash_filedata;
size_t boot_splash_filedata_size;
uint8_t qemu_extra_params_fw[2];
+bool nmi_disabled;
int icount_align_option;
--
1.7.12.4
Re: [Qemu-devel] [PATCH 0/3] vmw_pvscsi: Fine-tune device capabilities
Hi, On Thu, 19 Nov 2015 16:25:47 +0100 Paolo Bonzini wrote: > On 19/11/2015 15:21, Shmulik Ladkani wrote: > > Various fixes to what the vmw_pvscsi device reports in its PCI > > configuration space, to better align with VMware virtual hardware > > as exposed by ESXi/Workstation. > > > > Shmulik Ladkani (3): > > vmw_pvscsi: Set device subsystem and revision > > vmw_pvscsi: The pvscsi device is a PCIE endpoint > > vmw_pvscsi: Change offsets of PCI capabilities > > Looks good, thanks! I'll queue these patches for 2.5. Thanks Paolo, Since these are not yet pulled, I'm submitting a v2 of the series. The above changes are guest visible, thus I've added compatability properties for these changes - to allow migrating from old versions, as suggested by Jason Wang for similar changes done to the vmxnet3 device (see [1]). Regards, Shmulik [1] https://lists.nongnu.org/archive/html/qemu-devel/2015-11/msg05515.html
Re: [Qemu-devel] [PATCH 10/11] linux-user: avoid "naked" qemu_log
Le 12/12/2015 11:36, Paolo Bonzini a écrit :
> Ensure that all log writes are protected by qemu_loglevel_mask or,
> in serious cases, go to both the log and stderr.
>
> Signed-off-by: Paolo Bonzini
> ---
> linux-user/main.c | 71
> ---
> 1 file changed, 31 insertions(+), 40 deletions(-)
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 6783722..ee12035 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -45,6 +45,18 @@ static const char *cpu_model;
> unsigned long mmap_min_addr;
> unsigned long guest_base;
> int have_guest_base;
> +
> +#define EXCP_DUMP(env, fmt, ...)\
> +do {\
> +CPUState *cs = ENV_GET_CPU(env);\
> +fprintf(stderr, fmt , ## __VA_ARGS__); \
> +cpu_dump_state(cs, stderr, fprintf, 0); \
> +if (qemu_log_separate()) { \
> +qemu_log(fmt, ## __VA_ARGS__); \
> +log_cpu_state(cs, 0); \
> +} \
> +} while (0)
> +
> #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
> /*
> * When running 32-on-64 we should make sure we can fit all of the possible
> @@ -416,8 +428,8 @@ void cpu_loop(CPUX86State *env)
> break;
> default:
> pc = env->segs[R_CS].base + env->eip;
> -fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x -
> aborting\n",
> -(long)pc, trapnr);
> +EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x -
> aborting\n",
> + (long)pc, trapnr);
> abort();
> }
> process_pending_signals(env);
> @@ -865,9 +877,7 @@ void cpu_loop(CPUARMState *env)
> break;
> default:
> error:
> -fprintf(stderr, "qemu: unhandled CPU exception 0x%x -
> aborting\n",
> -trapnr);
> -cpu_dump_state(cs, stderr, fprintf, 0);
> +EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x -
> aborting\n", trapnr);
> abort();
> }
> process_pending_signals(env);
> @@ -1056,9 +1066,7 @@ void cpu_loop(CPUARMState *env)
> env->xregs[0] = do_arm_semihosting(env);
> break;
> default:
> -fprintf(stderr, "qemu: unhandled CPU exception 0x%x -
> aborting\n",
> -trapnr);
> -cpu_dump_state(cs, stderr, fprintf, 0);
> +EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x -
> aborting\n", trapnr);
> abort();
> }
> process_pending_signals(env);
> @@ -1148,8 +1156,7 @@ void cpu_loop(CPUUniCore32State *env)
> }
>
> error:
> -fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
> trapnr);
> -cpu_dump_state(cs, stderr, fprintf, 0);
> +EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n",
> trapnr);
> abort();
> }
> #endif
> @@ -1467,17 +1474,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn,
> uint32_t val)
> return -1;
> }
>
> -#define EXCP_DUMP(env, fmt, ...)\
> -do {\
> -CPUState *cs = ENV_GET_CPU(env);\
> -fprintf(stderr, fmt , ## __VA_ARGS__); \
> -cpu_dump_state(cs, stderr, fprintf, 0); \
> -if (qemu_log_separate()) { \
> -qemu_log(fmt, ## __VA_ARGS__); \
> -log_cpu_state(cs, 0); \
> -} \
> -} while (0)
> -
> static int do_store_exclusive(CPUPPCState *env)
> {
> target_ulong addr;
> @@ -2636,9 +2632,7 @@ done_syscall:
> break;
> default:
> error:
> -fprintf(stderr, "qemu: unhandled CPU exception 0x%x -
> aborting\n",
> -trapnr);
> -cpu_dump_state(cs, stderr, fprintf, 0);
> +EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x -
> aborting\n", trapnr);
> abort();
> }
> process_pending_signals(env);
> @@ -2661,11 +2655,11 @@ void cpu_loop(CPUOpenRISCState *env)
>
> switch (trapnr) {
> case EXCP_RESET:
> -qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
> +qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n",
> env->pc);
> exit(EXIT_FAILURE);
> break;
> case EXCP_BUSERR:
> -
Re: [Qemu-devel] [PATCH 11/11] linux-user: convert DEBUG_SIGNAL logging to tracepoints
Le 12/12/2015 11:39, Paolo Bonzini a écrit :
> "Unimplemented" messages go to stderr, everything else goes to tracepoints
>
> Signed-off-by: Paolo Bonzini
> ---
> bsd-user/signal.c | 2 -
> linux-user/signal.c | 118
> ++--
> trace-events| 11 +
> 3 files changed, 69 insertions(+), 62 deletions(-)
>
> diff --git a/bsd-user/signal.c b/bsd-user/signal.c
> index e4ee2d0..4887ecc 100644
> --- a/bsd-user/signal.c
> +++ b/bsd-user/signal.c
> @@ -26,8 +26,6 @@
> #include "qemu.h"
> #include "target_signal.h"
>
> -//#define DEBUG_SIGNAL
> -
> void signal_init(void)
> {
> }
> diff --git a/linux-user/signal.c b/linux-user/signal.c
> index 9d62e02..919aa83 100644
> --- a/linux-user/signal.c
> +++ b/linux-user/signal.c
> @@ -28,8 +28,7 @@
> #include "qemu.h"
> #include "qemu-common.h"
> #include "target_signal.h"
> -
> -//#define DEBUG_SIGNAL
> +#include "trace.h"
>
> static struct target_sigaltstack target_sigaltstack_used = {
> .ss_sp = 0,
> @@ -444,7 +443,9 @@ static void QEMU_NORETURN force_sig(int target_sig)
> TaskState *ts = (TaskState *)cpu->opaque;
> int host_sig, core_dumped = 0;
> struct sigaction act;
> +
> host_sig = target_to_host_signal(target_sig);
> +trace_user_force_sig(env, target_sig, host_sig);
> gdb_signalled(env, target_sig);
>
> /* dump core if supported by target binary format */
> @@ -499,10 +500,7 @@ int queue_signal(CPUArchState *env, int sig,
> target_siginfo_t *info)
> abi_ulong handler;
> int queue;
>
> -#if defined(DEBUG_SIGNAL)
> -fprintf(stderr, "queue_signal: sig=%d\n",
> -sig);
> -#endif
> +trace_user_queue_signal(env, sig);
> k = &ts->sigtab[sig - 1];
> queue = gdb_queuesig ();
> handler = sigact_table[sig - 1]._sa_handler;
> @@ -587,9 +585,7 @@ static void host_signal_handler(int host_signum,
> siginfo_t *info,
> sig = host_to_target_signal(host_signum);
> if (sig < 1 || sig > TARGET_NSIG)
> return;
> -#if defined(DEBUG_SIGNAL)
> -fprintf(stderr, "qemu: got signal %d\n", sig);
> -#endif
> +trace_user_host_signal(env, host_signum, sig);
> host_to_target_siginfo_noswap(&tinfo, info);
> if (queue_signal(env, sig, &tinfo) == 1) {
> /* interrupt the virtual CPU as soon as possible */
> @@ -682,10 +678,6 @@ int do_sigaction(int sig, const struct target_sigaction
> *act,
> if (sig < 1 || sig > TARGET_NSIG || sig == TARGET_SIGKILL || sig ==
> TARGET_SIGSTOP)
> return -EINVAL;
> k = &sigact_table[sig - 1];
> -#if defined(DEBUG_SIGNAL)
> -fprintf(stderr, "sigaction sig=%d act=0x%p, oact=0x%p\n",
> -sig, act, oact);
> -#endif
> if (oact) {
> __put_user(k->_sa_handler, &oact->_sa_handler);
> __put_user(k->sa_flags, &oact->sa_flags);
> @@ -909,6 +901,7 @@ static void setup_frame(int sig, struct target_sigaction
> *ka,
> int i;
>
> frame_addr = get_sigframe(ka, env, sizeof(*frame));
> +trace_user_setup_frame(env, frame_addr);
>
> if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0))
> goto give_sigsegv;
> @@ -970,6 +963,7 @@ static void setup_rt_frame(int sig, struct
> target_sigaction *ka,
> int i;
>
> frame_addr = get_sigframe(ka, env, sizeof(*frame));
> +trace_user_setup_rt_frame(env, frame_addr);
>
> if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0))
> goto give_sigsegv;
> @@ -1081,9 +1075,7 @@ long do_sigreturn(CPUX86State *env)
> sigset_t set;
> int eax, i;
>
> -#if defined(DEBUG_SIGNAL)
> -fprintf(stderr, "do_sigreturn\n");
> -#endif
> +trace_user_do_sigreturn(env, frame_addr);
> if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
> goto badframe;
> /* set blocked signals */
> @@ -1115,6 +1107,7 @@ long do_rt_sigreturn(CPUX86State *env)
> int eax;
>
> frame_addr = env->regs[R_ESP] - 4;
> +trace_user_do_rt_sigreturn(env, frame_addr);
> if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
> goto badframe;
> target_to_host_sigset(&set, &frame->uc.tuc_sigmask);
> @@ -1318,6 +1311,7 @@ static void target_setup_frame(int usig, struct
> target_sigaction *ka,
> abi_ulong frame_addr, return_addr;
>
> frame_addr = get_sigframe(ka, env);
> +trace_user_setup_frame(env, frame_addr);
> if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
> goto give_sigsegv;
> }
> @@ -1377,6 +1371,7 @@ long do_rt_sigreturn(CPUARMState *env)
> struct target_rt_sigframe *frame = NULL;
> abi_ulong frame_addr = env->xregs[31];
>
> +trace_user_do_rt_sigreturn(env, frame_addr);
> if (frame_addr & 15) {
> goto badframe;
> }
> @@ -1703,6 +1698,7 @@ static void setup_frame_v1(int usig, struct
> target_sigaction *ka,
> abi_ulong frame_addr = get_sigframe(ka,
Re: [Qemu-devel] [PATCH 1/1] Fix do_rt_sigreturn on m68k linux userspace emulation
On 09.12.2015 23:03, Laurent Vivier wrote:
>
> Le 09/12/2015 21:54, Michael Karcher a écrit :
>> do_rt_sigreturn forgets to initialize the signal mask variable before
>> trying to use it to restore the mask, so the signal mask is undefined
>> after do_rt_sigreturn. This bug has been in all the time since
>> 7181155d when do_rt_sigreturn was implemented for m68k.
>>
>> Signed-off-by: Michael Karcher
>> ---
>> linux-user/signal.c | 5 -
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/linux-user/signal.c b/linux-user/signal.c
>> index e03ed60..ae1014b 100644
>> --- a/linux-user/signal.c
>> +++ b/linux-user/signal.c
>> @@ -5260,11 +5260,14 @@ long do_rt_sigreturn(CPUM68KState *env)
>> abi_ulong frame_addr = env->aregs[7] - 4;
>> target_sigset_t target_set;
>> sigset_t set;
>> -int d0;
>> +int d0, i;
>>
>> if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1))
>> goto badframe;
>>
>> +for(i = 0; i < TARGET_NSIG_WORDS; i++) {
>> +target_set.sig[i] = frame->uc.tuc_sigmask.sig[i];
>> +}
>> target_to_host_sigset_internal(&set, &target_set);
>> do_sigprocmask(SIG_SETMASK, &set, NULL);
>>
>>
> Nice catch.
>
> I agree with you that the current code is completely broken, but on the
> other architectures, this operation seems to be done directly by
>
> target_to_host_sigset(&set, &frame->uc.tuc_sigmask);
>
> Could you have try with that ?
target_to_host_sigset does endianness swapping, while my loop does not
do it. I made a test program (attached to this mail) that tests mask
behaviour with "classic" and "siginfo" handlers, and shows that this
patch still doesn't fix the issue completely (output should be four
times 1). Instead of re-masking the SIGCHLD (bit 16) in that example, it
tries to mask SIGKILL (bit 8) which is due to the endian mismatch. I
will send a fixed patch shortly.
Feel free to extend the program to other architectures to test it there,
too.
BTW: documentation of the stack frame / signature for non-SA_SIGINFO
signal handlers seems to be quite lacking. There is a remark in the
sigaction manpage, but that one obviously only applies to i386...
Thanks for your comments,
Michael Karcher
//#include
#include
#include
#include
#include
//#include
volatile int child_blocked;
volatile sig_atomic_t got_it;
#if defined(__i386)
#define HAVE_LEGACY
void handle(int signal, struct sigcontext sc)
{
child_blocked = sc.oldmask == (1 << (SIGCHLD-1));
got_it = 1;
}
#elif defined(__amd64)
#define HAVE_LEGACY
void handle(int signal, struct ucontext uc)
{
child_blocked = ((struct sigcontext*)&uc.uc_mcontext)->oldmask == (1 << (SIGCHLD-1));
got_it = 1;
}
#elif defined(__mc68000)
#define HAVE_LEGACY
void handle(int signal, int code, struct sigcontext *sc)
{
child_blocked = sc->sc_mask == (1 << (SIGCHLD-1));
got_it = 1;
}
#endif
void handle_siginfo(int signal, siginfo_t * info, void *ctx)
{
child_blocked = sigismember(&((ucontext_t*)ctx)->uc_sigmask, SIGCHLD);
got_it = 1;
}
int main(void)
{
struct sigaction sa;
sigset_t set;
#ifdef HAVE_LEGACY
sa.sa_flags = 0;
sa.sa_handler = handle;
sigemptyset(&sa.sa_mask);
sigaction(SIGUSR1, &sa, NULL);
sigemptyset(&set);
sigaddset(&set, SIGCHLD);
sigprocmask(SIG_SETMASK, &set, NULL);
got_it = 0;
kill(getpid(), SIGUSR1);
while(got_it == 0);
sigprocmask(SIG_SETMASK, NULL, &set);
printf("%d %d\n", child_blocked, sigismember(&set, SIGCHLD));
#endif
got_it = 0;
sa.sa_flags = SA_SIGINFO;
sa.sa_sigaction = handle_siginfo;
sigaction(SIGUSR1, &sa, NULL);
sigemptyset(&set);
sigaddset(&set, SIGCHLD);
sigprocmask(SIG_SETMASK, &set, NULL);
got_it = 0;
kill(getpid(), SIGUSR1);
while(got_it == 0);
sigprocmask(SIG_SETMASK, NULL, &set);
printf("%d %d\n", child_blocked, sigismember(&set, SIGCHLD));
}
[Qemu-devel] Monitoring memory writes
In my QEMU-based project I would like to perform "extensive" tracing of basic blocks (translation blocks). I.e. in addition to what the existing tracing mechanism does, I'd like to log registers modified by TB and memory (RAM) written by TB. As for registers, it seems to be trivial. My main problem is how to know what memory addresses/sizes were written by a TB. During the research of this subject I found the following thread: https://lists.gnu.org/archive/html/qemu-devel/2015-04/msg00944.html The bottom line, IUUC, is that the only way to get what I need is to disable the "fast path" of the memory accesses. However, I still can't realize how to modify the back-end correctly. Besides, I would like to be able to enable/disable the fast path at run-time - to minimize impact on the performance when the tracing is not enabled. Would it be possible? I'd appreciate any pointer! Thanks.
Re: [Qemu-devel] [PATCH 07/11] tricore: avoid "naked" qemu_log
On 12/12/2015 11:36 AM, Paolo Bonzini wrote: > Cc: Bastian Koppelmann > Signed-off-by: Paolo Bonzini > --- > target-tricore/helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > This doesn't look like something which should go into 2.5, so I'll add this into my queue for 2.6. Cheers, Bastian
Re: [Qemu-devel] [PATCH] target-*: Get rid of "PC advancement" trick
On 12/12/15 02:39, Richard Henderson wrote: On 12/10/2015 10:47 AM, Sergey Fedorov wrote: The "PC advancement" trick was used just after recognizing that a breakpoint exception was going to be generated. This trick has had two points: 1. Guarantee that tb->size isn't zero: there are many places where it's expected to be non-zero. In fact, that is even stated in the comment for this field. 2. Try to satisfy disassembler's check for instruction length. To this end, PC advancement was done for estimated instruction length, but actually, didn't work properly in variable-instruction-length cases. Substitute this trick with checking for TB size at the end of translation. If we get an empty TB then just set tb->size to 1 and skip disassembling. Setting tb->size to 1 is enough to get correct behaviour, whereas an empty TB doesn't obviously need to be disassembled. This doesn't help when the TB already has instructions, the TB would ordinarily cross a page boundary, and the breakpoint is at the page boundary. I see your point. But I am wondering why most architectures stop translating on a page boundary whereas i386 and m86k don't. There are some comments which say that's to ensure instruction fetch aborts occur at the right place. Isn't it necessary for all architectures? At least for those architectures which do stop translating on a page boundary, I think this patch is applicable. Certainly, it would be better to have a single solution for all architectures. Thanks, Sergey
Re: [Qemu-devel] [PATCH 07/11] tricore: avoid "naked" qemu_log
On 12 December 2015 at 19:47, Bastian Koppelmann wrote: > On 12/12/2015 11:36 AM, Paolo Bonzini wrote: >> Cc: Bastian Koppelmann >> Signed-off-by: Paolo Bonzini >> --- >> target-tricore/helper.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> > > This doesn't look like something which should go into 2.5, so I'll add > this into my queue for 2.6. Nothing not already in master is going into 2.5 unless somebody finds a "make install runs rm -rf /" level bug at the last minute :-) thanks -- PMM
