Re: [Qemu-devel] [PATCH v7 2/7] stm32f2xx_USART: Add the stm32f2xx USART Controller

[Alistair Francis]

On Tue, Dec 16, 2014 at 3:47 PM, Peter Crosthwaite
 wrote:
> On Wed, Dec 10, 2014 at 12:46 AM, Alistair Francis  
> wrote:
>> This patch adds the stm32f2xx USART controller
>> (UART also uses the same controller).
>>
>> Signed-off-by: Alistair Francis 
>> ---
>> V6:
>>  - Rename to STM32F2XX
>>  - Fix up unimplemented printing
>>  - Add a qemu_chr_accept()
>> V3:
>>  - Update debug printing
>> V2:
>>  - Drop charecters if the device is not enabled
>> - Thanks to Peter C
>>
>>  default-configs/arm-softmmu.mak   |   1 +
>>  hw/char/Makefile.objs |   1 +
>>  hw/char/stm32f2xx_usart.c | 219 
>> ++
>>  include/hw/char/stm32f2xx_usart.h |  69 
>>  4 files changed, 290 insertions(+)
>>  create mode 100644 hw/char/stm32f2xx_usart.c
>>  create mode 100644 include/hw/char/stm32f2xx_usart.h
>>
>> diff --git a/default-configs/arm-softmmu.mak 
>> b/default-configs/arm-softmmu.mak
>> index faea100..1348104 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -79,6 +79,7 @@ CONFIG_REALVIEW=y
>>  CONFIG_ZAURUS=y
>>  CONFIG_ZYNQ=y
>>  CONFIG_STM32F2XX_TIMER=y
>> +CONFIG_STM32F2XX_USART=y
>>
>>  CONFIG_VERSATILE_PCI=y
>>  CONFIG_VERSATILE_I2C=y
>> diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
>> index 317385d..5931cc8 100644
>> --- a/hw/char/Makefile.objs
>> +++ b/hw/char/Makefile.objs
>> @@ -15,6 +15,7 @@ obj-$(CONFIG_OMAP) += omap_uart.o
>>  obj-$(CONFIG_SH4) += sh_serial.o
>>  obj-$(CONFIG_PSERIES) += spapr_vty.o
>>  obj-$(CONFIG_DIGIC) += digic-uart.o
>> +obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
>>
>>  common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
>>  common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
>> diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
>> new file mode 100644
>> index 000..843ff4a
>> --- /dev/null
>> +++ b/hw/char/stm32f2xx_usart.c
>> @@ -0,0 +1,219 @@
>> +/*
>> + * STM32F2XX USART
>> + *
>> + * Copyright (c) 2014 Alistair Francis 
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a 
>> copy
>> + * of this software and associated documentation files (the "Software"), to 
>> deal
>> + * in the Software without restriction, including without limitation the 
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included 
>> in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
>> FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "hw/char/stm32f2xx_usart.h"
>> +
>> +#ifndef STM_USART_ERR_DEBUG
>> +#define STM_USART_ERR_DEBUG 0
>> +#endif
>> +
>> +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> +if (STM_USART_ERR_DEBUG >= lvl) { \
>> +qemu_log("%s: " fmt, __func__, ## args); \
>> +} \
>> +} while (0);
>> +
>> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>> +
>> +static int stm32f2xx_usart_can_receive(void *opaque)
>> +{
>> +STM32F2XXUsartState *s = opaque;
>> +
>> +if (!(s->usart_sr & USART_SR_RXNE)) {
>> +return 1;
>> +}
>> +
>> +return 0;
>> +}
>> +
>> +static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int 
>> size)
>> +{
>> +STM32F2XXUsartState *s = opaque;
>> +
>> +s->usart_dr = *buf;
>> +
>> +if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
>> +/* USART not enabled - drop the chars */
>> +DB_PRINT("Dropping the chars\n");
>> +return;
>> +}
>> +
>> +s->usart_sr |= USART_SR_RXNE;
>> +
>> +if (s->usart_cr1 & USART_CR1_RXNEIE) {
>> +qemu_set_irq(s->irq, 1);
>> +}
>> +
>> +DB_PRINT("Receiving: %c\n", s->usart_dr);
>> +}
>> +
>> +static void stm32f2xx_usart_reset(DeviceState *dev)
>> +{
>> +STM32F2XXUsartState *s = STM32F2XX_USART(dev);
>> +
>> +s->usart_sr = USART_SR_RESET;
>> +s->usart_dr = 0x;
>> +s->usart_brr = 0x;
>> +s->usart_cr1 = 0x;
>> +s->usart_cr2 = 0x;
>> +s->usart_cr3 = 0x;
>> +s->usart_gtpr = 0x;
>
> Does the interrupt lower on a reset?

It doesn't specify that it does, but I assume it will

>
>> +}
>> +
>> +static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
>> +   unsigned int s

Re: [Qemu-devel] [question] block: do we have any consideration about adding retry support in error handling?

[Bin Wu]

On 2014/12/25 15:19, Fam Zheng wrote:
> On Thu, 12/25 11:46, Bin Wu wrote:
>> On 2014/12/25 10:42, Fam Zheng wrote:
>>> On Thu, 12/25 09:57, Bin Wu wrote:
 Hi,

 When IO error happens in physical device, qemu block layer supports error
 reporting, error ignoring and error stoping(for example, virtio-blk). Can 
 we
 have any way to resend the error IO?
>>>
>>> With error stop, the request is retried after resume.
>>>
>>> Fam
>>>
>>>
>>
>> Thank you very much, Fam, I see. Another question: I think error stop is not 
>> the
>> default error handling strategy, how can we configure error stop in the VM 
>> XML
>> file? Can you just show me some example? Thanks again:>
> 
> This is a question for libvirt, look for "error_policy":
> 
> https://libvirt.org/formatdomain.html
> 
> Fam
> 
> 

yes,
...

...

-- 
Bin Wu

[Qemu-devel] [PATCH 0/2] PoC: Block replication for continuous checkpointing

[Yang Hongyang]

Hi all,

We are implementing COLO feature for QEMU.
For what COLO is and steps to setup and runing COLO, refer to:
http://wiki.qemu.org/Features/COLO
  * you can get almost everything about COLO from that Wiki page.
Previously posted RFC proposal:
http://lists.nongnu.org/archive/html/qemu-devel/2014-06/msg05567.html
Latest COLO code:
https://github.com/macrosheep/qemu (checkout the latest COLO branch)

Our current work is implementing COLO Disk manager, we are planning to
implement it as a block driver which called 'blkcolo'. But we need the
feedbacks from commiunity.

This patchset is a Proof of Concept of our Block replication design,
including:
  1. A document 'docs/blkcolo.txt' which describes the drift design
 specification.
  2. Some DEMO/POC code that will help you to understand how we are
 going to implement it.

Please feel free to comment.
We want comments/feedbacks as many as possiable please, thanks in advance.

Thanks,
Yang.

Wen Congyang (1):
  PoC: Block replication for COLO

Yang Hongyang (1):
  Block: Block replication design for COLO

 block.c   |  48 +++
 block/blkcolo.c   | 338 ++
 docs/blkcolo.txt  |  80 +++
 include/block/block.h |   6 +
 include/block/block_int.h |  21 +++
 5 files changed, 493 insertions(+)
 create mode 100644 block/blkcolo.c
 create mode 100644 docs/blkcolo.txt

-- 
1.9.1

[Qemu-devel] [PATCH 1/2] Block: Block replication design for COLO

[Yang Hongyang]

This is the initial design of block replication.
The blkcolo block driver enables disk replication for continuous
checkpoints. It is designed for COLO that Secondary VM is running.
It can also be applied for FT/HA scene that Secondary VM is not
running.

Signed-off-by: Wen Congyang 
Signed-off-by: Lai Jiangshan 
Signed-off-by: Yang Hongyang 
---
 docs/blkcolo.txt | 80 
 1 file changed, 80 insertions(+)
 create mode 100644 docs/blkcolo.txt

diff --git a/docs/blkcolo.txt b/docs/blkcolo.txt
new file mode 100644
index 000..af70fc8
--- /dev/null
+++ b/docs/blkcolo.txt
@@ -0,0 +1,80 @@
+Disk replication using blkcolo
+
+Copyright Fujitsu, Corp. 2014
+
+This work is licensed under the terms of the GNU GPL, version 2 or later.
+See the COPYING file in the top-level directory.
+
+The blkcolo block driver enables disk replication for continuous checkpoints.
+It is designed for COLO that Secondary VM is running. It can also be applied
+for FT/HA scene that Secondary VM is not running.
+
+This document gives an overview of blkcolo's design.
+
+== Background ==
+High availability solutions such as micro checkpoint and COLO will do
+consecutive checkpoint. The VM state of Primary VM and Secondary VM is
+identical right after a VM checkpoint, but becomes different as the VM
+executes till the next checkpoint. To support disk contents checkpoint,
+the modified disk contents in the Secondary VM must be buffered, and are
+only dropped at next checkpoint time. To reduce the network transportation
+effort at the time of checkpoint, the disk modification operations of
+Primary disk are asynchronously forwarded to the Secondary node.
+
+== Disk Buffer ==
+The following is the image of Disk buffer:
+
++--+++
+|Primary Write Requests||Secondary Write Requests|
++--+++
+  |   |
+  |  (4)
+  |   V
+  |  /-\
+  |  Copy and Forward| |
+  |-(1)--+   | Disk Buffer |
+  |  |   | |
+  | (3)  \-/
+  | speculative  ^
+  |write through(2)
+  |  |   |
+  V  V   |
+   +--+   ++
+   | Primary Disk |   | Secondary Disk |
+   +--+   ++
+1) Primary write requests will be copied and forwarded to Secondary
+   QEMU.
+2) Before Primary write requests are written to Secondary disk, the
+   original sector content will be read from Secondary disk and
+   buffered in the Disk buffer, but it will not overwrite the existing
+   sector content in the Disk buffer.
+3) Primary write requests will be written to Secondary disk.
+4) Secondary write requests will be bufferd in the Disk buffer and it
+   will overwrite the existing sector content in the buffer.
+
+== Capture I/O request ==
+The blkcolo is a new block driver protocol, so all I/O requests can be
+captured in the driver interface bdrv_co_readv()/bdrv_co_writev().
+
+== Checkpoint & failover ==
+The blkcolo buffers the write requests in Secondary QEMU. And the buffer
+should be dropped at a checkpoint, or be flushed to Secondary disk when
+failover. We add three block driver interfaces to do this:
+a. bdrv_wait_recv_completed()
+   This interface may block, and return when all Primary write
+   requests are forwarded to Secondary QEMU.
+b. bdrv_handle_checkpoint()
+   This interface is called after all VM state is transfered to
+   Secondary QEMU. The Disk buffer will be dropped in this interface.
+c. bdrv_cancel_checkpoint()
+   It is called when doing failover. We will flush the Disk buffer into
+   Secondary Disk and stop disk replication.
+
+== Usage ==
+On both Primary/Secondary host, invoke QEMU with the following parameters:
+"-drive file=blkcolo:host:port:/path/to/image"
+a. host
+   Hostname or IP of the Secondary host.
+b. port
+   The Secondary QEMU will listen on this port, and the Primary QEMU
+   will connect to this port.
-- 
1.9.1

[Qemu-devel] [PATCH 2/2] PoC: Block replication for COLO

[Yang Hongyang]

From: Wen Congyang 

It is not finished, but only show how it will be implemented.

Signed-off-by: Wen Congyang 
Signed-off-by: Yang Hongyang 
---
 block.c   |  48 +++
 block/blkcolo.c   | 338 ++
 include/block/block.h |   6 +
 include/block/block_int.h |  21 +++
 4 files changed, 413 insertions(+)
 create mode 100644 block/blkcolo.c

diff --git a/block.c b/block.c
index 4165d42..bff46c1 100644
--- a/block.c
+++ b/block.c
@@ -6086,3 +6086,51 @@ BlockAcctStats *bdrv_get_stats(BlockDriverState *bs)
 {
 return &bs->stats;
 }
+
+int bdrv_prepare_checkpoint(BlockDriverState *bs)
+{
+BlockDriver *drv = bs->drv;
+if (drv && drv->bdrv_prepare_checkpoint) {
+return drv->bdrv_prepare_checkpoint(bs);
+} else if (bs->file) {
+return bdrv_prepare_checkpoint(bs->file);
+}
+
+return -1;
+}
+
+int bdrv_do_checkpoint(BlockDriverState *bs)
+{
+BlockDriver *drv = bs->drv;
+if (drv && drv->bdrv_do_checkpoint) {
+return drv->bdrv_do_checkpoint(bs);
+} else if (bs->file) {
+return bdrv_do_checkpoint(bs->file);
+}
+
+return -1;
+}
+
+int bdrv_get_sent_data_size(BlockDriverState *bs)
+{
+BlockDriver *drv = bs->drv;
+if (drv && drv->bdrv_get_sent_data_size) {
+return drv->bdrv_get_sent_data_size(bs);
+} else if (bs->file) {
+return bdrv_get_sent_data_size(bs->file);
+}
+
+return -1;
+}
+
+int bdrv_stop_replication(BlockDriverState *bs)
+{
+BlockDriver *drv = bs->drv;
+if (drv && drv->bdrv_stop_replication) {
+return drv->bdrv_stop_replication(bs);
+} else if (bs->file) {
+return bdrv_stop_replication(bs->file);
+}
+
+return -1;
+}
diff --git a/block/blkcolo.c b/block/blkcolo.c
new file mode 100644
index 000..c75
--- /dev/null
+++ b/block/blkcolo.c
@@ -0,0 +1,338 @@
+/*
+ * Primary mode functions
+ */
+
+static void coroutine_fn colo_pvm_forward_co(void *opaque)
+{
+/*
+ * If the list is empty:
+ *   the status is COLO_PVM_CHECKPOINT_NONE, set the
+ *   state to idle and yield.
+ *   the status is COLO_PVM_CHECKPOINT_START, send
+ *   COLO_BLOCK_CHECKPOINT_SEC to the secondary QEMU.
+ * Otherwise, send the write requests to the secondary
+ * QEMU.
+ */
+}
+
+static colo_forward_state *colo_pvm_forward_request(BDRVBlkcoloState *s,
+int64_t sector_num,
+int nb_sectors,
+QEMUIOVector *qiov)
+{
+/*
+ * Add the write requests to the tail of the list.
+ * Wakeup the coroutine colo_pvm_forward_co() if
+ * it is in idle state.
+ */
+}
+
+static int coroutine_fn colo_pvm_handle_write_request(BlockDriverState *bs,
+  int64_t sector_num,
+  int nb_sectors,
+  QEMUIOVector *qiov)
+{
+int ret;
+
+/*
+ * call colo_pvm_forward_request to forward the primary
+ * write requests to the secondary QEMU.
+ */
+
+ret = bdrv_co_writev(bs->file, sector_num, nb_sectors, qiov);
+
+/* wait until the write request is forwarded to the secondary QEMU */
+
+return ret;
+}
+
+static int coroutine_fn colo_pvm_handle_read_request(BlockDriverState *bs,
+ int64_t sector_num,
+ int nb_sectors,
+ QEMUIOVector *qiov)
+{
+return bdrv_co_readv(bs->file, sector_num, nb_sectors, qiov);
+}
+
+/* It should be called in the migration/checkpoint thread */
+static int colo_pvm_hanlde_checkpoint(BDRVBlkcoloState *s)
+{
+/*
+ * wait until COLO_BLOCK_CHECKPOINT_SEC is sent to the
+ * secondary QEMU
+ */
+}
+
+/* It should be called in the migration/checkpoint thread */
+static void cancel_pvm_forward(BDRVBlkcoloState *s)
+{
+/*
+ * Set the state to cancelled, and wait all coroutines
+ * exit.
+ */
+
+/* switch to unprotected mode */
+}
+
+/*
+ * Secondary mode functions
+ *
+ * All write requests are forwarded to secondary QEMU from primary QEMU.
+ * The secondary QEMU should do the following things:
+ * 1. Receive and handle the forwarded write requests
+ * 2. Buffer the secondary write requests
+ */
+
+static void coroutine_fn colo_svm_handle_pvm_write_req_co(void *opaque)
+{
+/*
+ * Do the following things:
+ * 1. read the original sector content
+ * 2. write the original sector content into disk buffer
+ *if the sector content is not buffered
+ * 3. write the request to disk buffer
+ */
+}
+
+static void coroutine_fn colo_svm_handle_pvm_write_reqs_co(void *opaque)
+{
+/*
+ * If the list is empty, set the state to idle, and yie

Re: [Qemu-devel] [PATCH] linux-user: Fix broken m68k signal handling on 64 bit hosts

[Peter Maydell]

On 25 December 2014 at 05:10, Michael Tokarev  wrote:
> 22.12.2014 20:47, Peter Maydell wrote:
>> The m68k signal frame setup code which writes the signal return
>> trampoline code to the stack was assuming that a 'long' was 32 bits;
>> on 64 bit systems this meant we would end up writing the 32 bit
>> (2 insn) trampoline sequence to retaddr+4,retaddr+6 instead of
>> the intended retaddr+0,retaddr+2, resulting in a guest crash when
>> it tried to execute the invalid zero-bytes at retaddr+0.
>> Fix by using uint32_t instead; also use uint16_t rather than short
>> for consistency. This fixes bug LP:1404690.
>
> Cc: qemu-stable@ ?

Yeah, seems reasonable (though this has been busted for five
years, so I deduce that nobody's actually trying to use it...)

-- PMM

Re: [Qemu-devel] qemu-img:the sheepdog snapshot vdi's lock will not be released when use qemu-img to create a snapshot vdi

[long]

ok,thank you for your reply, but now the openstack cinder use both qemu-img and 
dog command,so  the recreate vdi from snapshot futrue has some problem.

https://github.com/openstack/cinder/blob/98706a9804d5896546cac0c565f74ec6cf0f24b9/cinder/volume/drivers/sheepdog.py
 



Thanks,
Xiaolong Xu

> 在 2014年12月24日，下午10:47，Hitoshi Mitake  写道：
> 
> At Mon, 22 Dec 2014 17:41:33 +0800,
> 徐小龙 wrote:
>> 
>> [1  ]
>> hi,all,
>> when i use `qemu-img snapshot -c test-s sheepdog:test` to create a
>> snapshot of sheepdog vdi,the snapshot's lock not be released.
>> 
>> root@hty-compute1:~/qemu# ./qemu-img create sheepdog:test 1G
>> Formatting 'sheepdog:test', fmt=raw size=1073741824
>> 
>> root@hty-compute1:~/qemu# dog vdi list
>>  NameIdSizeUsed  SharedCreation time   VDI id  Copies
>> Tag
>>  test 0  1.0 GB  0.0 MB  0.0 MB 2014-12-22 17:10   7c2b25  3
>> 
>> root@hty-compute1:~/qemu# ./qemu-img snapshot -c test-s sheepdog:test
>> WARNING: Image format was not specified for 'sheepdog:test' and probing
>> guessed raw.
>> Automatically detecting the format is dangerous for raw images,
>> write operations on block 0 will be restricted.
>> Specify the 'raw' format explicitly to remove the restrictions.
>> 
>> root@hty-compute1:~/qemu# dog vdi lock list
>> VDI | Owner node | Tag
>> s test | IPv4 ip:172.16.17.200 port:7000 test-s
>> 
>> when i create a snapshot ,the src vdi will be open and locked,in the
>> function `sd_open` read the vdi inode info saved in the struct
>> BDRVSheepdogState ,and in the function `sd_snapshot_create` the vdi inode
>> information in the struct BDRVSheepdogState will point to an new vdi ,so
>> when the function `sd_close` be called,the `sd_close` will try to released
>> the lock of new vdi.In conclusion,the snapshot vdi will lock forever , so
>> it's will be failed when i try to create a new vdi base on the snapshot.
>> 
>> root@hty-compute1:~/qemu# ./qemu-img create -b sheepdog:test:test-s
>> sheepdog:new-vdi
>> qemu-img: sheepdog:new-vdi: cannot get vdi info, VDI is already locked,
>> test 0 test-s
>> 
>> There may be some wrong in the function`sd_snapshot_create`.but I'm not
>> sure the root cause.
>> 
>> Thanks,
>> Xiaolong Xu
> 
> Xiaolong, thanks for your report. I'll fix it ASAP.
> 
> Could you use the dog command as a walkaround?
> 
> Thanks,
> Hitoshi
> 

Re: [Qemu-devel] [PATCH V2 0/4] *virtio-blk: add multiread support

[Peter Lieven]

Am 18.12.2014 um 11:34 schrieb Kevin Wolf:
> Am 16.12.2014 um 17:00 hat Peter Lieven geschrieben:
>> On 16.12.2014 16:48, Kevin Wolf wrote:
>>> Am 16.12.2014 um 16:21 hat Peter Lieven geschrieben:
 this series adds the long missing multiread support to virtio-blk.

 some remarks:
  - i introduced rd_merged and wr_merged block accounting stats to
blockstats as a generic interface which can be set from any
driver that will introduce multirequest merging in the future.
  - the knob to disable request merging is not yet there. I would
add it to the device properties also as a generic interface
to have the same switch for any driver that might introduce
request merging in the future. As there has been no knob in
the past I would post this as a seperate series as it needs
some mangling in parameter parsing which might lead to further
discussions.
  - the old multiwrite interface is still there and might be removed.

 v1->v2:
  - add overflow checking for nb_sectors [Kevin]
  - do not change the name of the macro of max mergable requests. [Fam]
>>> Diff to v1 looks good. Now I just need to check what it does to the
>>> performance. Did you run any benchmarks yourself?
>> I ran several installs of Debian/Ubuntu, Booting of Windows and Linux
>> systems. I looked at rd_total_time_ns and wr_total_time_ns and saw
>> no increase. Ofter I even saw even a decrease.
>>
>> {rd,wr}_total_time_ns measures the time from virtio_blk_handle_request
>> to virtio_blk_rw_complete. So it seems to be a good indicator for the time
>> spent with I/O.
>>
>> What you could to is post it on the top of your fio testing stack and
>> look at the throughput. Sequential Reads should be faster. The rest
>> not worse.
> So I finally ran some fio benchmark on the series. The result for small
> sequential reads (4k) is quite noisy, but it seems to be improved a bit.
> Larger sequenial reads (64k) and random reads seem to be mostly
> unaffected.
>
> For writes, however, I can see a degradation. Perhaps running multiple
> jobs in parallel means that we don't detect and merge sequential
> requests any more when they are interleaved with another sequential job.
> Or do you have an idea what else could have changed for writes?

I tried to digged a little more into this topic and maybe found whats
going on. If I a right you are using Kernel >= 3.17 in the guest for
your tests?

Here are my test results of 4k sequential writes under a Linux 3.13 guest.

Master:
virtio-fio: rd_bytes=856064 wr_bytes=34359738368 rd_operations=209 
wr_operations=8388608 flush_operations=0 wr_total_time_ns=980610962941 
rd_total_time_ns=5656675 flush_total_time_ns=0 rd_merged=0 wr_merged=658

Multiread_v2:
virtio-fio: rd_bytes=856064 wr_bytes=34359738368 rd_operations=209 
wr_operations=8388608 flush_operations=0 wr_total_time_ns=558830918737 
rd_total_time_ns=6159151 flush_total_time_ns=0 rd_merged=0 wr_merged=6266824

As you can see the number of merged requests is in the same order, but the 
wr_total_time_ns is heavily improved!

What happened between Linux 3.13 and 3.17 is that Ming introduced the Multiqeue 
feature into
the virtio-blk kernel code. The blk-mq developers intentionally set the number 
of hw_queues to 4
in Kernel 3.13 for virtio-blk. With the introduction of the Multiqeue feature 
in 3.17 the number of
hw_queues is set the the number of virtqueues. If multique is unsupported the 
number is 1 and
thus the number of hw_queues is also 1. So all the requests from all fio 
processes go into the same
hw_queue and this seems to break the performance. The requests are heavily 
interleaved this
way and as I only merge strictly sequential requests the old implementation 
which sorts requests
wins. But it uses twice the computation time for this.

I think this needs to be fixed in the virtio-blk kernel code and if we 
introduce multiqueue for virtio-blk into
qemu, we should set the number of virtqueues to at least 4. Maybe the number of 
cpus would also be a
good choice?!

Peter

Re: [Qemu-devel] [PATCH] gdbstub: Support AUXV packet for debugging PIE executables.

[Wei-cheng Wang]

Ping :)

Thanks,
Wei-cheng

On 11/28/2014 12:57 AM, Paolo Bonzini wrote:

CCing Riku Voipio for a review.

Paolo

On 23/11/2014 14:28, Wei-cheng, Wang wrote:

Hi,

This patch adds support for sending AUXV packet.
This is required for debugging Linux position independent executables.
Otherwise, gdb client cannot find out where the executable is loaded.

Signed-off-by: Wei-cheng, Wang 
---
  gdbstub.c | 41 +
  1 file changed, 41 insertions(+)

diff --git a/gdbstub.c b/gdbstub.c
index d1b5afd..30f3bbc 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1127,6 +1127,7 @@ static int gdb_handle_packet(GDBState *s, const
char *line_buf)
  if (cc->gdb_core_xml_file != NULL) {
  pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
  }
+pstrcat(buf, sizeof(buf), ";qXfer:auxv:read+");
  put_packet(s, buf);
  break;
  }
@@ -1173,6 +1174,46 @@ static int gdb_handle_packet(GDBState *s, const
char *line_buf)
  put_packet_binary(s, buf, len + 1);
  break;
  }
+#ifdef CONFIG_USER_ONLY
+if (strncmp(p, "Xfer:auxv:read:", 15) == 0) {
+TaskState *ts = s->c_cpu->opaque;
+target_ulong auxv = ts->info->saved_auxv;
+target_ulong auxv_len = ts->info->auxv_len;
+char *ptr;
+
+p += 15;
+while (*p && *p != ':')
+p++;
+p++;
+
+addr = strtoul(p, (char **)&p, 16);
+if (*p == ',')
+p++;
+len = strtoul(p, (char **)&p, 16);
+
+ptr = lock_user(VERIFY_READ, auxv, auxv_len, 0);
+if (ptr == NULL) {
+break;
+}
+
+if (addr > len) {
+snprintf(buf, sizeof(buf), "E00");
+put_packet(s, buf);
+break;
+}
+if (len > (MAX_PACKET_LENGTH - 5) / 2)
+len = (MAX_PACKET_LENGTH - 5) / 2;
+if (len < auxv_len - addr) {
+buf[0] = 'm';
+len = memtox(buf + 1, ptr + addr, len);
+} else {
+buf[0] = 'l';
+len = memtox(buf + 1, ptr + addr, auxv_len - addr);
+}
+put_packet_binary(s, buf, len + 1);
+unlock_user(ptr, auxv, len);
+}
+#endif /* !CONFIG_USER_ONLY */
  /* Unrecognised 'q' command.  */
  goto unknown_command;

Re: [Qemu-devel] [PATCH v7 1/7] stm32f2xx_timer: Add the stm32f2xx Timer

[Alistair Francis]

On Tue, Dec 16, 2014 at 3:39 PM, Peter Crosthwaite
 wrote:
> On Wed, Dec 10, 2014 at 12:46 AM, Alistair Francis  
> wrote:
>> This patch adds the stm32f2xx timers: TIM2, TIM3, TIM4 and TIM5
>> to QEMU.
>>
>> Signed-off-by: Alistair Francis 
>> ---
>> V6:
>>  - Rename to STM32F2XX
>>  - Change the timer calculations to use ns
>>  - Update the value to timer_mod to ensure it is in ns
>>  - Account for reloadable/resetable timer
>> - Thanks to Peter C for pointing this out
>> V4:
>>  - Update timer units again
>> - Thanks to Peter C
>> V3:
>>  - Update debug statements
>>  - Correct the units for timer_mod
>>  - Correctly set timer_offset from resets
>> V2:
>>  - Reorder the Makefile config
>>  - Fix up the debug printing
>>  - Correct the timer event trigger
>>
>>  default-configs/arm-softmmu.mak|   1 +
>>  hw/timer/Makefile.objs |   2 +
>>  hw/timer/stm32f2xx_timer.c | 331 
>> +
>>  include/hw/timer/stm32f2xx_timer.h | 101 +++
>>  4 files changed, 435 insertions(+)
>>  create mode 100644 hw/timer/stm32f2xx_timer.c
>>  create mode 100644 include/hw/timer/stm32f2xx_timer.h
>>
>> diff --git a/default-configs/arm-softmmu.mak 
>> b/default-configs/arm-softmmu.mak
>> index f3513fa..faea100 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -78,6 +78,7 @@ CONFIG_NSERIES=y
>>  CONFIG_REALVIEW=y
>>  CONFIG_ZAURUS=y
>>  CONFIG_ZYNQ=y
>> +CONFIG_STM32F2XX_TIMER=y
>>
>>  CONFIG_VERSATILE_PCI=y
>>  CONFIG_VERSATILE_I2C=y
>> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
>> index 2c86c3d..133bd0d 100644
>> --- a/hw/timer/Makefile.objs
>> +++ b/hw/timer/Makefile.objs
>> @@ -31,3 +31,5 @@ obj-$(CONFIG_DIGIC) += digic-timer.o
>>  obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
>>
>>  obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
>> +
>> +common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
>> diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
>> new file mode 100644
>> index 000..df27540
>> --- /dev/null
>> +++ b/hw/timer/stm32f2xx_timer.c
>> @@ -0,0 +1,331 @@
>> +/*
>> + * STM32F2XX Timer
>> + *
>> + * Copyright (c) 2014 Alistair Francis 
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a 
>> copy
>> + * of this software and associated documentation files (the "Software"), to 
>> deal
>> + * in the Software without restriction, including without limitation the 
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included 
>> in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
>> FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "hw/timer/stm32f2xx_timer.h"
>> +
>> +#ifndef STM_TIMER_ERR_DEBUG
>> +#define STM_TIMER_ERR_DEBUG 0
>> +#endif
>> +
>> +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> +if (STM_TIMER_ERR_DEBUG >= lvl) { \
>> +qemu_log("%s: " fmt, __func__, ## args); \
>> +} \
>> +} while (0);
>> +
>> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>> +
>> +static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s);
>> +
>> +static void stm32f2xx_timer_interrupt(void *opaque)
>> +{
>> +STM32F2XXTimerState *s = opaque;
>> +
>> +DB_PRINT("Interrupt\n");
>> +
>> +if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) {
>> +s->tim_sr |= 1;
>> +qemu_irq_pulse(s->irq);
>> +stm32f2xx_timer_set_alarm(s);
>> +}
>> +}
>> +
>> +static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s)
>> +{
>> +uint32_t ticks;
>> +int64_t now;
>> +
>> +DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1);
>> +
>> +now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
>> +ticks = s->tim_arr -
>> +((muldiv64(s->freq_hz, now, 10ULL) - s->tick_offset) /
>> +(s->tim_psc + 1));
>
> ticks seems to be the auto-reload register minus the total number of
> ticks elapsed since reset (now - tick_offset). For subsequent reloads
> in periodic timing this will always be -ve. Does tick_offset need to
> be warped every time the timer hits and autoreloads?
>

That's a good point, I'll fix that up.

>> +
>> +DB_PRINT("Alarm set in %d ticks\n", ticks);
>> +
>> +if (ticks == 0) {
>> +tim

[Qemu-devel] [PATCH RESEND 0/2] PoC: Block replication for continuous checkpointing

[Yang Hongyang]

Hi all,

Please ignore the previous one, this is the updated patch.

We are implementing COLO feature for QEMU.
For what COLO is and steps to setup and runing COLO, refer to:
http://wiki.qemu.org/Features/COLO
  * you can get almost everything about COLO from that Wiki page.
Previously posted RFC proposal:
http://lists.nongnu.org/archive/html/qemu-devel/2014-06/msg05567.html
Latest COLO code:
https://github.com/macrosheep/qemu (checkout the latest COLO branch)

Our current work is implementing COLO Disk manager, we are planning to
implement it as a block driver which called 'blkcolo'. But we need the
feedbacks from commiunity.

This patchset is a Proof of Concept of our Block replication design,
including:
  1. A document 'docs/blkcolo.txt' which describes the drift design
 specification.
  2. Some DEMO/POC code that will help you to understand how we are
 going to implement it.

Please feel free to comment.
We want comments/feedbacks as many as possiable please, thanks in advance.

Thanks,
Yang.

Wen Congyang (1):
  PoC: Block replication for COLO

Yang Hongyang (1):
  Block: Block replication design for COLO

 block.c   |  48 +++
 block/blkcolo.c   | 338 ++
 docs/blkcolo.txt  |  85 
 include/block/block.h |   6 +
 include/block/block_int.h |  21 +++
 5 files changed, 498 insertions(+)
 create mode 100644 block/blkcolo.c
 create mode 100644 docs/blkcolo.txt

-- 
1.9.1

[Qemu-devel] [PATCH RESEND 2/2] PoC: Block replication for COLO

[Yang Hongyang]

From: Wen Congyang 

It is not finished, but only show how it will be implemented.

Signed-off-by: Wen Congyang 
Signed-off-by: Yang Hongyang 
---
 block.c   |  48 +++
 block/blkcolo.c   | 338 ++
 include/block/block.h |   6 +
 include/block/block_int.h |  21 +++
 4 files changed, 413 insertions(+)
 create mode 100644 block/blkcolo.c

diff --git a/block.c b/block.c
index 4165d42..82a5283 100644
--- a/block.c
+++ b/block.c
@@ -6086,3 +6086,51 @@ BlockAcctStats *bdrv_get_stats(BlockDriverState *bs)
 {
 return &bs->stats;
 }
+
+int bdrv_prepare_checkpoint(BlockDriverState *bs)
+{
+BlockDriver *drv = bs->drv;
+if (drv && drv->bdrv_prepare_checkpoint) {
+return drv->bdrv_prepare_checkpoint(bs);
+} else if (bs->file) {
+return bdrv_prepare_checkpoint(bs->file);
+}
+
+return -1;
+}
+
+int bdrv_do_checkpoint(BlockDriverState *bs)
+{
+BlockDriver *drv = bs->drv;
+if (drv && drv->bdrv_do_checkpoint) {
+return drv->bdrv_do_checkpoint(bs);
+} else if (bs->file) {
+return bdrv_do_checkpoint(bs->file);
+}
+
+return -1;
+}
+
+int64_t bdrv_get_sent_data_size(BlockDriverState *bs)
+{
+BlockDriver *drv = bs->drv;
+if (drv && drv->bdrv_get_sent_data_size) {
+return drv->bdrv_get_sent_data_size(bs);
+} else if (bs->file) {
+return bdrv_get_sent_data_size(bs->file);
+}
+
+return -1;
+}
+
+int bdrv_stop_replication(BlockDriverState *bs)
+{
+BlockDriver *drv = bs->drv;
+if (drv && drv->bdrv_stop_replication) {
+return drv->bdrv_stop_replication(bs);
+} else if (bs->file) {
+return bdrv_stop_replication(bs->file);
+}
+
+return -1;
+}
diff --git a/block/blkcolo.c b/block/blkcolo.c
new file mode 100644
index 000..57ed4df
--- /dev/null
+++ b/block/blkcolo.c
@@ -0,0 +1,338 @@
+/*
+ * Primary mode functions
+ */
+
+static void coroutine_fn colo_pvm_forward_co(void *opaque)
+{
+/*
+ * If the list is empty:
+ *   the status is COLO_PVM_CHECKPOINT_NONE, set the
+ *   state to idle and yield.
+ *   the status is COLO_PVM_CHECKPOINT_START, send
+ *   COLO_BLOCK_CHECKPOINT_SEC to the secondary QEMU.
+ * Otherwise, send the write requests to the secondary
+ * QEMU.
+ */
+}
+
+static colo_forward_state *colo_pvm_forward_request(BDRVBlkcoloState *s,
+int64_t sector_num,
+int nb_sectors,
+QEMUIOVector *qiov)
+{
+/*
+ * Add the write requests to the tail of the list.
+ * Wakeup the coroutine colo_pvm_forward_co() if
+ * it is in idle state.
+ */
+}
+
+static int coroutine_fn colo_pvm_handle_write_request(BlockDriverState *bs,
+  int64_t sector_num,
+  int nb_sectors,
+  QEMUIOVector *qiov)
+{
+int ret;
+
+/*
+ * call colo_pvm_forward_request to forward the primary
+ * write requests to the secondary QEMU.
+ */
+
+ret = bdrv_co_writev(bs->file, sector_num, nb_sectors, qiov);
+
+/* wait until the write request is forwarded to the secondary QEMU */
+
+return ret;
+}
+
+static int coroutine_fn colo_pvm_handle_read_request(BlockDriverState *bs,
+ int64_t sector_num,
+ int nb_sectors,
+ QEMUIOVector *qiov)
+{
+return bdrv_co_readv(bs->file, sector_num, nb_sectors, qiov);
+}
+
+/* It should be called in the migration/checkpoint thread */
+static int colo_pvm_hanlde_checkpoint(BDRVBlkcoloState *s)
+{
+/*
+ * wait until COLO_BLOCK_CHECKPOINT_SEC is sent to the
+ * secondary QEMU
+ */
+}
+
+/* It should be called in the migration/checkpoint thread */
+static void cancel_pvm_forward(BDRVBlkcoloState *s)
+{
+/*
+ * Set the state to cancelled, and wait all coroutines
+ * exit.
+ */
+
+/* switch to unprotected mode */
+}
+
+/*
+ * Secondary mode functions
+ *
+ * All write requests are forwarded to secondary QEMU from primary QEMU.
+ * The secondary QEMU should do the following things:
+ * 1. Receive and handle the forwarded write requests
+ * 2. Buffer the secondary write requests
+ */
+
+static void coroutine_fn colo_svm_handle_pvm_write_req_co(void *opaque)
+{
+/*
+ * Do the following things:
+ * 1. read the original sector content
+ * 2. write the original sector content into disk buffer
+ *if the sector content is not buffered
+ * 3. write the request to disk buffer
+ */
+}
+
+static void coroutine_fn colo_svm_handle_pvm_write_reqs_co(void *opaque)
+{
+/*
+ * If the list is empty, set the state to idle, and

[Qemu-devel] [PATCH RESEND 1/2] Block: Block replication design for COLO

[Yang Hongyang]

This is the initial design of block replication.
The blkcolo block driver enables disk replication for continuous
checkpoints. It is designed for COLO that Secondary VM is running.
It can also be applied for FT/HA scene that Secondary VM is not
running.

Signed-off-by: Wen Congyang 
Signed-off-by: Lai Jiangshan 
Signed-off-by: Yang Hongyang 
---
 docs/blkcolo.txt | 85 
 1 file changed, 85 insertions(+)
 create mode 100644 docs/blkcolo.txt

diff --git a/docs/blkcolo.txt b/docs/blkcolo.txt
new file mode 100644
index 000..41c2a05
--- /dev/null
+++ b/docs/blkcolo.txt
@@ -0,0 +1,85 @@
+Disk replication using blkcolo
+
+Copyright Fujitsu, Corp. 2014
+
+This work is licensed under the terms of the GNU GPL, version 2 or later.
+See the COPYING file in the top-level directory.
+
+The blkcolo block driver enables disk replication for continuous checkpoints.
+It is designed for COLO that Secondary VM is running. It can also be applied
+for FT/HA scene that Secondary VM is not running.
+
+This document gives an overview of blkcolo's design.
+
+== Background ==
+High availability solutions such as micro checkpoint and COLO will do
+consecutive checkpoint. The VM state of Primary VM and Secondary VM is
+identical right after a VM checkpoint, but becomes different as the VM
+executes till the next checkpoint. To support disk contents checkpoint,
+the modified disk contents in the Secondary VM must be buffered, and are
+only dropped at next checkpoint time. To reduce the network transportation
+effort at the time of checkpoint, the disk modification operations of
+Primary disk are asynchronously forwarded to the Secondary node.
+
+== Disk Buffer ==
+The following is the image of Disk buffer:
+
++--+++
+|Primary Write Requests||Secondary Write Requests|
++--+++
+  |   |
+  |  (4)
+  |   V
+  |  /-\
+  |  Copy and Forward| |
+  |-(1)--+   | Disk Buffer |
+  |  |   | |
+  | (3)  \-/
+  | speculative  ^
+  |write through(2)
+  |  |   |
+  V  V   |
+   +--+   ++
+   | Primary Disk |   | Secondary Disk |
+   +--+   ++
+1) Primary write requests will be copied and forwarded to Secondary
+   QEMU.
+2) Before Primary write requests are written to Secondary disk, the
+   original sector content will be read from Secondary disk and
+   buffered in the Disk buffer, but it will not overwrite the existing
+   sector content in the Disk buffer.
+3) Primary write requests will be written to Secondary disk.
+4) Secondary write requests will be bufferd in the Disk buffer and it
+   will overwrite the existing sector content in the buffer.
+
+== Capture I/O request ==
+The blkcolo is a new block driver protocol, so all I/O requests can be
+captured in the driver interface bdrv_co_readv()/bdrv_co_writev().
+
+== Checkpoint & failover ==
+The blkcolo buffers the write requests in Secondary QEMU. And the buffer
+should be dropped at a checkpoint, or be flushed to Secondary disk when
+failover. We add four block driver interfaces to do this:
+a. bdrv_prepare_checkpoint()
+   This interface may block, and return when all Primary write
+   requests are forwarded to Secondary QEMU.
+b. bdrv_do_checkpoint()
+   This interface is called after all VM state is transfered to
+   Secondary QEMU. The Disk buffer will be dropped in this interface.
+c. bdrv_get_sent_data_size()
+   This is used on Primary node.
+   It should be called by migration/checkpoint thread in order
+   to decide whether to start a new checkpoint or not. If the data
+   amount being sent is too large, we should start a new checkpoint.
+d. bdrv_stop_replication()
+   It is called when failover. We will flush the Disk buffer into
+   Secondary Disk and stop disk replication.
+
+== Usage ==
+On both Primary/Secondary host, invoke QEMU with the following parameters:
+"-drive file=blkcolo:host:port:/path/to/image"
+a. host
+   Hostname or IP of the Secondary host.
+b. port
+   The Secondary QEMU will listen on this port, and the Primary QEMU
+   will connect to this port.
-- 
1.9.1

[Qemu-devel] [PATCH v8 0/7] Netduino 2 Machine Model

[Alistair Francis]

This patch series adds the Netduino 2 Machine to QEMU

Information on the board is avalible at:
http://www.netduino.com/netduino2/specs.htm

The git tree can be found at:
https://github.com/alistair23/qemu/tree/netduino2.8

This patch series makes some changes to the armv7m_init function
that allows the code to be reused with the Netduino 2 and the
Stellaris machines.

Some example code that runs on QEMU is avaliable at:
at: https://github.com/alistair23/CSSE3010-QEMU-Examples

There are more devices in the works, I figured I would just start
with these three

V8:
 - Update the timer device based on Peter C's comments
 - Update the USART device based on Peter C's comments
V7:
 - Rebase to QEMU 2.2
V6:
 - Rename the three devices to STM32FXX*
 - Correct the timer to use ns
 - Correct the number of devices that are inited
 - Rename memory regions
V5:
 - Remove the reset changes based on the ELF entry
V4:
 - Rebase
 - Correct timer units
V3:
 - Correct the timer interrupts
 - Update debug printing
 - Remove the sram_size argument from armv7m_init


Alistair Francis (7):
  stm32f2xx_timer: Add the stm32f2xx Timer
  stm32f2xx_USART: Add the stm32f2xx USART Controller
  stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG
  target_arm: Remove memory region init from armv7m_init
  target_arm: Parameterise the irq lines for armv7m_init
  stm32f205: Add the stm32f205 SoC
  netduino2: Add the Netduino 2 Machine

 default-configs/arm-softmmu.mak|   4 +
 hw/arm/Makefile.objs   |   2 +
 hw/arm/armv7m.c|  38 +
 hw/arm/netduino2.c |  54 ++
 hw/arm/stellaris.c |  27 ++-
 hw/arm/stm32f205_soc.c | 157 +
 hw/char/Makefile.objs  |   1 +
 hw/char/stm32f2xx_usart.c  | 229 +
 hw/misc/Makefile.objs  |   1 +
 hw/misc/stm32f2xx_syscfg.c | 160 ++
 hw/timer/Makefile.objs |   2 +
 hw/timer/stm32f2xx_timer.c | 337 +
 include/hw/arm/arm.h   |   3 +-
 include/hw/arm/stm32f205_soc.h |  69 
 include/hw/char/stm32f2xx_usart.h  |  69 
 include/hw/misc/stm32f2xx_syscfg.h |  61 +++
 include/hw/timer/stm32f2xx_timer.h | 103 
 17 files changed, 1279 insertions(+), 38 deletions(-)
 create mode 100644 hw/arm/netduino2.c
 create mode 100644 hw/arm/stm32f205_soc.c
 create mode 100644 hw/char/stm32f2xx_usart.c
 create mode 100644 hw/misc/stm32f2xx_syscfg.c
 create mode 100644 hw/timer/stm32f2xx_timer.c
 create mode 100644 include/hw/arm/stm32f205_soc.h
 create mode 100644 include/hw/char/stm32f2xx_usart.h
 create mode 100644 include/hw/misc/stm32f2xx_syscfg.h
 create mode 100644 include/hw/timer/stm32f2xx_timer.h

-- 
2.1.0

[Qemu-devel] [PATCH v8 3/7] stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG

[Alistair Francis]

This patch adds the stm32f2xx System Configuration
Controller. This is used to configure what memory is mapped
at address 0 (although that is not supported) as well
as configure how the EXTI interrupts work (also not
supported at the moment).

This device is not required for basic examples, but more
complex systems will require it (as well as the EXTI device)

Signed-off-by: Alistair Francis 
Reviewed-by: Peter Crosthwaite 
---
V6:
 - Rename to STM32F2XX
 - Remove all casts from debug printing
V5:
 - Correct the masks used for writing
V3:
 - Update debug printing

 default-configs/arm-softmmu.mak|   1 +
 hw/misc/Makefile.objs  |   1 +
 hw/misc/stm32f2xx_syscfg.c | 160 +
 include/hw/misc/stm32f2xx_syscfg.h |  61 ++
 4 files changed, 223 insertions(+)
 create mode 100644 hw/misc/stm32f2xx_syscfg.c
 create mode 100644 include/hw/misc/stm32f2xx_syscfg.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 1348104..a5aab7f 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -80,6 +80,7 @@ CONFIG_ZAURUS=y
 CONFIG_ZYNQ=y
 CONFIG_STM32F2XX_TIMER=y
 CONFIG_STM32F2XX_USART=y
+CONFIG_STM32F2XX_SYSCFG=y
 
 CONFIG_VERSATILE_PCI=y
 CONFIG_VERSATILE_I2C=y
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index e47fea8..ea5abb6 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -38,5 +38,6 @@ obj-$(CONFIG_OMAP) += omap_sdrc.o
 obj-$(CONFIG_OMAP) += omap_tap.o
 obj-$(CONFIG_SLAVIO) += slavio_misc.o
 obj-$(CONFIG_ZYNQ) += zynq_slcr.o
+obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
 
 obj-$(CONFIG_PVPANIC) += pvpanic.o
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
new file mode 100644
index 000..4ae4042
--- /dev/null
+++ b/hw/misc/stm32f2xx_syscfg.c
@@ -0,0 +1,160 @@
+/*
+ * STM32F2XX SYSCFG
+ *
+ * Copyright (c) 2014 Alistair Francis 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/misc/stm32f2xx_syscfg.h"
+
+#ifndef STM_SYSCFG_ERR_DEBUG
+#define STM_SYSCFG_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+if (STM_SYSCFG_ERR_DEBUG >= lvl) { \
+qemu_log("%s: " fmt, __func__, ## args); \
+} \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f2xx_syscfg_reset(DeviceState *dev)
+{
+STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(dev);
+
+s->syscfg_memrmp = 0x;
+s->syscfg_pmc = 0x;
+s->syscfg_exticr1 = 0x;
+s->syscfg_exticr2 = 0x;
+s->syscfg_exticr3 = 0x;
+s->syscfg_exticr4 = 0x;
+s->syscfg_cmpcr = 0x;
+}
+
+static uint64_t stm32f2xx_syscfg_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+STM32F2XXSyscfgState *s = opaque;
+
+DB_PRINT("0x%"HWADDR_PRIx"\n", addr);
+
+switch (addr) {
+case SYSCFG_MEMRMP:
+return s->syscfg_memrmp;
+case SYSCFG_PMC:
+return s->syscfg_pmc;
+case SYSCFG_EXTICR1:
+return s->syscfg_exticr1;
+case SYSCFG_EXTICR2:
+return s->syscfg_exticr2;
+case SYSCFG_EXTICR3:
+return s->syscfg_exticr3;
+case SYSCFG_EXTICR4:
+return s->syscfg_exticr4;
+case SYSCFG_CMPCR:
+return s->syscfg_cmpcr;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+return 0;
+}
+
+return 0;
+}
+
+static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
+   uint64_t val64, unsigned int size)
+{
+STM32F2XXSyscfgState *s = opaque;
+uint32_t value = val64;
+
+DB_PRINT("0x%x, 0x%"HWADDR_PRIx"\n", value, addr);
+
+switch (addr) {
+case SYSCFG_MEMRMP:
+qemu_log_mask(LOG_UNIMP,
+  "%s: Changeing the memory mapping isn't supported " \
+

[Qemu-devel] [PATCH v8 2/7] stm32f2xx_USART: Add the stm32f2xx USART Controller

[Alistair Francis]

This patch adds the stm32f2xx USART controller
(UART also uses the same controller).

Signed-off-by: Alistair Francis 
---
V8:
 - Clear IRQ on reset
 - Lower IRQ on data read/status clear
 - Set IRQ if enabled while data is avaliable
V6:
 - Rename to STM32F2XX
 - Fix up unimplemented printing
 - Add a qemu_chr_accept()
V3:
 - Update debug printing
V2:
 - Drop charecters if the device is not enabled
- Thanks to Peter C

 default-configs/arm-softmmu.mak   |   1 +
 hw/char/Makefile.objs |   1 +
 hw/char/stm32f2xx_usart.c | 229 ++
 include/hw/char/stm32f2xx_usart.h |  69 
 4 files changed, 300 insertions(+)
 create mode 100644 hw/char/stm32f2xx_usart.c
 create mode 100644 include/hw/char/stm32f2xx_usart.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index faea100..1348104 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -79,6 +79,7 @@ CONFIG_REALVIEW=y
 CONFIG_ZAURUS=y
 CONFIG_ZYNQ=y
 CONFIG_STM32F2XX_TIMER=y
+CONFIG_STM32F2XX_USART=y
 
 CONFIG_VERSATILE_PCI=y
 CONFIG_VERSATILE_I2C=y
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index 317385d..5931cc8 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -15,6 +15,7 @@ obj-$(CONFIG_OMAP) += omap_uart.o
 obj-$(CONFIG_SH4) += sh_serial.o
 obj-$(CONFIG_PSERIES) += spapr_vty.o
 obj-$(CONFIG_DIGIC) += digic-uart.o
+obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
 
 common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
 common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
new file mode 100644
index 000..260b053
--- /dev/null
+++ b/hw/char/stm32f2xx_usart.c
@@ -0,0 +1,229 @@
+/*
+ * STM32F2XX USART
+ *
+ * Copyright (c) 2014 Alistair Francis 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/char/stm32f2xx_usart.h"
+
+#ifndef STM_USART_ERR_DEBUG
+#define STM_USART_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+if (STM_USART_ERR_DEBUG >= lvl) { \
+qemu_log("%s: " fmt, __func__, ## args); \
+} \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static int stm32f2xx_usart_can_receive(void *opaque)
+{
+STM32F2XXUsartState *s = opaque;
+
+if (!(s->usart_sr & USART_SR_RXNE)) {
+return 1;
+}
+
+return 0;
+}
+
+static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
+{
+STM32F2XXUsartState *s = opaque;
+
+s->usart_dr = *buf;
+
+if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
+/* USART not enabled - drop the chars */
+DB_PRINT("Dropping the chars\n");
+return;
+}
+
+s->usart_sr |= USART_SR_RXNE;
+
+if (s->usart_cr1 & USART_CR1_RXNEIE) {
+qemu_set_irq(s->irq, 1);
+}
+
+DB_PRINT("Receiving: %c\n", s->usart_dr);
+}
+
+static void stm32f2xx_usart_reset(DeviceState *dev)
+{
+STM32F2XXUsartState *s = STM32F2XX_USART(dev);
+
+s->usart_sr = USART_SR_RESET;
+s->usart_dr = 0x;
+s->usart_brr = 0x;
+s->usart_cr1 = 0x;
+s->usart_cr2 = 0x;
+s->usart_cr3 = 0x;
+s->usart_gtpr = 0x;
+
+qemu_set_irq(s->irq, 0);
+}
+
+static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
+   unsigned int size)
+{
+STM32F2XXUsartState *s = opaque;
+uint64_t retvalue;
+
+DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
+
+switch (addr) {
+case USART_SR:
+retvalue = s->usart_sr;
+s->usart_sr &= ~USART_SR_TC;
+if (s->chr) {
+qemu_chr_accept_input(s->chr);
+}
+return retvalue;
+case USART_DR:
+DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) 
s->usart_dr);
+s->usart_sr |= USART_SR_TXE;
+s->usart_sr &= ~USART_SR_RXNE;
+

[Qemu-devel] [PATCH v8 4/7] target_arm: Remove memory region init from armv7m_init

[Alistair Francis]

This patch moves the memory region init code from the
armv7m_init function to the stellaris_init function

Signed-off-by: Alistair Francis 
Reviewed-by: Peter Crosthwaite 
---
V3:
 - Rename the flash_size argument to mem_size
 - Remove the sram_size and related code
- Thanks to Peter C
V2:
 - Change the memory region names to match the machine

 hw/arm/armv7m.c  | 33 +++--
 hw/arm/stellaris.c   | 24 
 include/hw/arm/arm.h |  3 +--
 3 files changed, 24 insertions(+), 36 deletions(-)

diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index ef24ca4..50281f7 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -163,11 +163,10 @@ static void armv7m_reset(void *opaque)
 }
 
 /* Init CPU and memory for a v7-M based board.
-   flash_size and sram_size are in kb.
+   mem_size is in bytes.
Returns the NVIC array.  */
 
-qemu_irq *armv7m_init(MemoryRegion *system_memory,
-  int flash_size, int sram_size,
+qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size,
   const char *kernel_filename, const char *cpu_model)
 {
 ARMCPU *cpu;
@@ -180,13 +179,8 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory,
 uint64_t lowaddr;
 int i;
 int big_endian;
-MemoryRegion *sram = g_new(MemoryRegion, 1);
-MemoryRegion *flash = g_new(MemoryRegion, 1);
 MemoryRegion *hack = g_new(MemoryRegion, 1);
 
-flash_size *= 1024;
-sram_size *= 1024;
-
 if (cpu_model == NULL) {
cpu_model = "cortex-m3";
 }
@@ -197,27 +191,6 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory,
 }
 env = &cpu->env;
 
-#if 0
-/* > 32Mb SRAM gets complicated because it overlaps the bitband area.
-   We don't have proper commandline options, so allocate half of memory
-   as SRAM, up to a maximum of 32Mb, and the rest as code.  */
-if (ram_size > (512 + 32) * 1024 * 1024)
-ram_size = (512 + 32) * 1024 * 1024;
-sram_size = (ram_size / 2) & TARGET_PAGE_MASK;
-if (sram_size > 32 * 1024 * 1024)
-sram_size = 32 * 1024 * 1024;
-code_size = ram_size - sram_size;
-#endif
-
-/* Flash programming is done via the SCU, so pretend it is ROM.  */
-memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size,
-   &error_abort);
-vmstate_register_ram_global(flash);
-memory_region_set_readonly(flash, true);
-memory_region_add_subregion(system_memory, 0, flash);
-memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size, &error_abort);
-vmstate_register_ram_global(sram);
-memory_region_add_subregion(system_memory, 0x2000, sram);
 armv7m_bitband_init();
 
 nvic = qdev_create(NULL, "armv7m_nvic");
@@ -244,7 +217,7 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory,
 image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,
   NULL, big_endian, ELF_MACHINE, 1);
 if (image_size < 0) {
-image_size = load_image_targphys(kernel_filename, 0, flash_size);
+image_size = load_image_targphys(kernel_filename, 0, mem_size);
 lowaddr = 0;
 }
 if (image_size < 0) {
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 64bd4b4..d0c61c5 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1220,10 +1220,26 @@ static void stellaris_init(const char *kernel_filename, 
const char *cpu_model,
 int i;
 int j;
 
-flash_size = ((board->dc0 & 0x) + 1) << 1;
-sram_size = (board->dc0 >> 18) + 1;
-pic = armv7m_init(get_system_memory(),
-  flash_size, sram_size, kernel_filename, cpu_model);
+MemoryRegion *sram = g_new(MemoryRegion, 1);
+MemoryRegion *flash = g_new(MemoryRegion, 1);
+MemoryRegion *system_memory = get_system_memory();
+
+flash_size = (((board->dc0 & 0x) + 1) << 1) * 1024;
+sram_size = ((board->dc0 >> 18) + 1) * 1024;
+
+/* Flash programming is done via the SCU, so pretend it is ROM.  */
+memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size,
+   &error_abort);
+vmstate_register_ram_global(flash);
+memory_region_set_readonly(flash, true);
+memory_region_add_subregion(system_memory, 0, flash);
+
+memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
+   &error_abort);
+vmstate_register_ram_global(sram);
+memory_region_add_subregion(system_memory, 0x2000, sram);
+
+pic = armv7m_init(system_memory, flash_size, kernel_filename, cpu_model);
 
 if (board->dc1 & (1 << 16)) {
 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
index c4bf56d..f8b329b 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/arm.h
@@ -15,8 +15,7 @@
 #include "hw/irq.h"
 
 /* armv7m.c */
-qemu_irq *armv7m_init(MemoryRegion *system_memory,
-  int flash_size, in

[Qemu-devel] [PATCH v8 1/7] stm32f2xx_timer: Add the stm32f2xx Timer

[Alistair Francis]

This patch adds the stm32f2xx timers: TIM2, TIM3, TIM4 and TIM5
to QEMU.

Signed-off-by: Alistair Francis 
---
V8:
 - Fix tick_offset to allow now to wrap around
 - Remove the calls to get_ticks_per_sec()
 - Pre-scale the guest visable time
V6:
 - Rename to STM32F2XX
 - Change the timer calculations to use ns
 - Update the value to timer_mod to ensure it is in ns
 - Account for reloadable/resetable timer
- Thanks to Peter C for pointing this out
V4:
 - Update timer units again
- Thanks to Peter C
V3:
 - Update debug statements
 - Correct the units for timer_mod
 - Correctly set timer_offset from resets
V2:
 - Reorder the Makefile config
 - Fix up the debug printing
 - Correct the timer event trigger

 default-configs/arm-softmmu.mak|   1 +
 hw/timer/Makefile.objs |   2 +
 hw/timer/stm32f2xx_timer.c | 337 +
 include/hw/timer/stm32f2xx_timer.h | 103 
 4 files changed, 443 insertions(+)
 create mode 100644 hw/timer/stm32f2xx_timer.c
 create mode 100644 include/hw/timer/stm32f2xx_timer.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index f3513fa..faea100 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -78,6 +78,7 @@ CONFIG_NSERIES=y
 CONFIG_REALVIEW=y
 CONFIG_ZAURUS=y
 CONFIG_ZYNQ=y
+CONFIG_STM32F2XX_TIMER=y
 
 CONFIG_VERSATILE_PCI=y
 CONFIG_VERSATILE_I2C=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 2c86c3d..133bd0d 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -31,3 +31,5 @@ obj-$(CONFIG_DIGIC) += digic-timer.o
 obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
 
 obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
+
+common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
new file mode 100644
index 000..b16789e
--- /dev/null
+++ b/hw/timer/stm32f2xx_timer.c
@@ -0,0 +1,337 @@
+/*
+ * STM32F2XX Timer
+ *
+ * Copyright (c) 2014 Alistair Francis 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/timer/stm32f2xx_timer.h"
+
+#ifndef STM_TIMER_ERR_DEBUG
+#define STM_TIMER_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+if (STM_TIMER_ERR_DEBUG >= lvl) { \
+qemu_log("%s: " fmt, __func__, ## args); \
+} \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s);
+
+static void stm32f2xx_timer_interrupt(void *opaque)
+{
+STM32F2XXTimerState *s = opaque;
+
+DB_PRINT("Interrupt\n");
+
+if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) {
+s->tim_sr |= 1;
+qemu_irq_pulse(s->irq);
+stm32f2xx_timer_set_alarm(s);
+}
+}
+
+static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s)
+{
+uint32_t ticks;
+int64_t now, wait_time;
+
+DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1);
+
+now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+/* When now wraps around, update the tick_offset to represent
+ * the last time the clock was reset
+ */
+if (now < s->tick_offset) {
+s->tick_offset = s->tick_offset - TIMER_MAX_TICKS;
+}
+ticks = s->tim_arr -
+((muldiv64(s->freq_hz, now, 10ULL) - s->tick_offset) /
+(s->tim_psc + 1));
+
+DB_PRINT("Alarm set in %d ticks\n", ticks);
+
+if (ticks == 0) {
+timer_del(s->timer);
+stm32f2xx_timer_interrupt(s);
+} else {
+wait_time = now + muldiv64(ticks, 10ULL, s->freq_hz);
+
+timer_mod(s->timer, wait_time);
+DB_PRINT("Wait Time: %" PRId64 " ticks\n", wait_time);
+}
+}
+
+static void stm32f2xx_timer_reset(DeviceState *dev)
+{
+STM32F2XXTimerState *s = STM32F2XXTIMER(dev);
+
+s->tim_cr1 = 0;
+s->tim_cr2 = 0;
+s->tim_smcr = 0;
+s->tim_dier = 0;
+s->tim_sr = 0;
+s->ti

[Qemu-devel] [PATCH v8 5/7] target_arm: Parameterise the irq lines for armv7m_init

[Alistair Francis]

This patch allows the board to specifiy the number of NVIC interrupt
lines when using armv7m_init.

Signed-off-by: Alistair Francis 
Reviewed-by: Peter Crosthwaite 
---

 hw/arm/armv7m.c  | 7 ---
 hw/arm/stellaris.c   | 5 -
 include/hw/arm/arm.h | 2 +-
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 50281f7..7169027 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -166,14 +166,14 @@ static void armv7m_reset(void *opaque)
mem_size is in bytes.
Returns the NVIC array.  */
 
-qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size,
+qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
   const char *kernel_filename, const char *cpu_model)
 {
 ARMCPU *cpu;
 CPUARMState *env;
 DeviceState *nvic;
 /* FIXME: make this local state.  */
-static qemu_irq pic[64];
+qemu_irq *pic = g_new(qemu_irq, num_irq);
 int image_size;
 uint64_t entry;
 uint64_t lowaddr;
@@ -194,11 +194,12 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, int 
mem_size,
 armv7m_bitband_init();
 
 nvic = qdev_create(NULL, "armv7m_nvic");
+qdev_prop_set_uint32(nvic, "num-irq", num_irq);
 env->nvic = nvic;
 qdev_init_nofail(nvic);
 sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
-for (i = 0; i < 64; i++) {
+for (i = 0; i < num_irq; i++) {
 pic[i] = qdev_get_gpio_in(nvic, i);
 }
 
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index d0c61c5..6fad10f 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -29,6 +29,8 @@
 #define BP_OLED_SSI  0x02
 #define BP_GAMEPAD   0x04
 
+#define NUM_IRQ_LINES 64
+
 typedef const struct {
 const char *name;
 uint32_t did0;
@@ -1239,7 +1241,8 @@ static void stellaris_init(const char *kernel_filename, 
const char *cpu_model,
 vmstate_register_ram_global(sram);
 memory_region_add_subregion(system_memory, 0x2000, sram);
 
-pic = armv7m_init(system_memory, flash_size, kernel_filename, cpu_model);
+pic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,
+  kernel_filename, cpu_model);
 
 if (board->dc1 & (1 << 16)) {
 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
index f8b329b..5c940eb 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/arm.h
@@ -15,7 +15,7 @@
 #include "hw/irq.h"
 
 /* armv7m.c */
-qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size,
+qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
   const char *kernel_filename, const char *cpu_model);
 
 /* arm_boot.c */
-- 
2.1.0

[Qemu-devel] [PATCH v8 6/7] stm32f205: Add the stm32f205 SoC

[Alistair Francis]

This patch adds the stm32f205 SoC. This will be used by the
Netduino 2 to create a machine.

Signed-off-by: Alistair Francis 
---
V6:
 - Correct the number of USART/UART devices
 - Use macros to define how many devices are inited
 - Update the memory regions name from netduino.* to
   STM32F205.*

 default-configs/arm-softmmu.mak |   1 +
 hw/arm/Makefile.objs|   1 +
 hw/arm/stm32f205_soc.c  | 157 
 include/hw/arm/stm32f205_soc.h  |  69 ++
 4 files changed, 228 insertions(+)
 create mode 100644 hw/arm/stm32f205_soc.c
 create mode 100644 include/hw/arm/stm32f205_soc.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a5aab7f..9ac755e 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,6 +81,7 @@ CONFIG_ZYNQ=y
 CONFIG_STM32F2XX_TIMER=y
 CONFIG_STM32F2XX_USART=y
 CONFIG_STM32F2XX_SYSCFG=y
+CONFIG_STM32F205_SOC=y
 
 CONFIG_VERSATILE_PCI=y
 CONFIG_VERSATILE_I2C=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 6088e53..9769317 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -8,3 +8,4 @@ obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o 
pxa2xx_pic.o
 obj-$(CONFIG_DIGIC) += digic.o
 obj-y += omap1.o omap2.o strongarm.o
 obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
+obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
new file mode 100644
index 000..186e15d
--- /dev/null
+++ b/hw/arm/stm32f205_soc.c
@@ -0,0 +1,157 @@
+/*
+ * STM32F205 SoC
+ *
+ * Copyright (c) 2014 Alistair Francis 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/arm/stm32f205_soc.h"
+
+/* At the moment only Timer 2 to 5 are modelled */
+static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x4000, 0x4400,
+0x4800, 0x4C00 };
+static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
+0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
+
+static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
+static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
+
+static void stm32f205_soc_initfn(Object *obj)
+{
+STM32F205State *s = STM32F205_SOC(obj);
+int i;
+
+object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
+qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
+
+for (i = 0; i < STM_NUM_USARTS; i++) {
+object_initialize(&s->usart[i], sizeof(s->usart[i]),
+  TYPE_STM32F2XX_USART);
+qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
+}
+
+for (i = 0; i < STM_NUM_TIMERS; i++) {
+object_initialize(&s->timer[i], sizeof(s->timer[i]),
+  TYPE_STM32F2XX_TIMER);
+qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
+}
+}
+
+static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+STM32F205State *s = STM32F205_SOC(dev_soc);
+DeviceState *syscfgdev, *usartdev, *timerdev;
+SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
+qemu_irq *pic;
+Error *err = NULL;
+int i;
+
+MemoryRegion *system_memory = get_system_memory();
+MemoryRegion *sram = g_new(MemoryRegion, 1);
+MemoryRegion *flash = g_new(MemoryRegion, 1);
+MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
+
+memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
+   &error_abort);
+memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
+ flash, 0, FLASH_SIZE);
+
+vmstate_register_ram_global(flash);
+
+memory_region_set_readonly(flash, true);
+memory_region_set_readonly(flash_alias, true);
+
+memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
+memory_region_add_subregion(system_memory, 0, flash_al

[Qemu-devel] [PATCH v8 7/7] netduino2: Add the Netduino 2 Machine

[Alistair Francis]

This patch adds the Netduino 2 Machine.

This is a Cortex-M3 based machine. Information can be found at:
http://www.netduino.com/netduino2/specs.htm

Signed-off-by: Alistair Francis 
---

 hw/arm/Makefile.objs |  1 +
 hw/arm/netduino2.c   | 54 
 2 files changed, 55 insertions(+)
 create mode 100644 hw/arm/netduino2.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 9769317..2577f68 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -3,6 +3,7 @@ obj-$(CONFIG_DIGIC) += digic_boards.o
 obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
 obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
 obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
+obj-y += netduino2.o
 
 obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
 obj-$(CONFIG_DIGIC) += digic.o
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
new file mode 100644
index 000..305983f
--- /dev/null
+++ b/hw/arm/netduino2.c
@@ -0,0 +1,54 @@
+/*
+ * Netduino 2 Machine Model
+ *
+ * Copyright (c) 2014 Alistair Francis 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/arm/stm32f205_soc.h"
+
+static void netduino2_init(MachineState *machine)
+{
+DeviceState *dev;
+Error *err = NULL;
+
+dev = qdev_create(NULL, TYPE_STM32F205_SOC);
+if (machine->kernel_filename) {
+qdev_prop_set_string(dev, "kernel-filename", machine->kernel_filename);
+}
+object_property_set_bool(OBJECT(dev), true, "realized", &err);
+if (err != NULL) {
+error_report("%s", error_get_pretty(err));
+exit(1);
+}
+}
+
+static QEMUMachine netduino2_machine = {
+.name = "netduino2",
+.desc = "Netduino 2 Machine",
+.init = netduino2_init,
+};
+
+static void netduino2_machine_init(void)
+{
+qemu_register_machine(&netduino2_machine);
+}
+
+machine_init(netduino2_machine_init);
-- 
2.1.0