Re: [Qemu-devel] [PATCH v2] Fix X86 CPU topology in KVM mode

[Jan Kiszka]

On 2011-09-10 16:37, Bharata B Rao wrote:
> On Fri, Sep 9, 2011 at 10:44 PM, Anthony Liguori  
> wrote:
>>
>> This breaks the build:
>>
>>  CCi386-linux-user/helper.o
>> /home/anthony/git/qemu/target-i386/helper.c: In function ‘cpu_x86_init’:
>> /home/anthony/git/qemu/target-i386/helper.c:1260:47: error: ‘smp_cpus’
>> undeclared (first use in this function)
>> /home/anthony/git/qemu/target-i386/helper.c:1260:47: note: each undeclared
>> identifier is reported only once for each function it appears in
>> make[1]: *** [helper.o] Error 1
>> make: *** [subdir-i386-linux-user] Error 2
>>
>> Please do a full build before submitting patches.
> 
> Sorry about this, the complexity of qemu and its capability to
> support/emulate such wide range of targets is slowly sinking in :)
> 
> smp_cpus is defined in vl.c which doesn't even get compiled for
> targets like i386-linux-user and hence we end up in above undefined
> reference error.
> 
> I wouldn't attempt another fix until I spend some time understanding
> the code organization for various targets. Meanwhile since the root
> cause of the probem and the solution are known, if anyone more well
> versed with qemu code organization can fix this, please go ahead.

Just assign cpuid_apic_id unconditionally in cpu_x86_init. Will have no
side effects.

Jan



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Re: [Qemu-devel] About hotplug multifunction

[Michael S. Tsirkin]

On Sat, Sep 10, 2011 at 02:43:11AM +0900, Isaku Yamahata wrote:
> pci/pcie hot plug needs clean up for multifunction hotplug in long term.
> Only single function device case works. Multifunction case is broken somwehat.
> Especially the current acpi based hotplug should be replaced by
> the standardized hot plug controller in long term.

We'll need to keep supporting windows XP, which IIUC only
supports hotplug through ACPI. So it looks like we'll
need both.

-- 
MST

Re: [Qemu-devel] About hotplug multifunction

[Michael S. Tsirkin]

On Fri, Sep 09, 2011 at 03:34:26PM -0300, Marcelo Tosatti wrote:
> > > something I noted when readin our acpi code:
> > > we currently pass eject request for function 0 only:
> > >Name (_ADR, nr##)
> > > We either need a device per function there (acpi 1.0),
> > > send eject request for them all, or use 
> > > as function number (newer acpi, not sure which version).
> > > Need to see which guests (windows,linux) can handle which form.
> > 
> > I'd guess we need to change that to .
> 
> No need, only make sure function 0 is there and all other functions
> should be removed automatically by the guest on eject notification.

Hmm, the ACPI spec explicitly says:

High word = Device #, Low word = Function #.
(e.g., device 3, function 2 is 0x00030002). To refer
to all the functions on a device #, use a function
number of ).


> ACPI PCI hotplug is based on slots, not on functions. It does not
> support addition/removal of individual functions.

Interesting. Is this just based on general logic,
reading of the linux driver or the ACPI spec?

The ACPI spec itself seems pretty vague. All tables
list devices, where each device has an _ADR entry,
which is built up of PCI device # and function #.

-- 
MST

Re: [Qemu-devel] unable to access the serial port on the Vm

[Stefan Hajnoczi]

On Thu, Sep 08, 2011 at 10:12:06AM -0700, bala suru wrote:
> Hi,
> I'm running one VM on the Qemu hypervisor.
> I'm tried too access the /dev/ttyS0 from the VM, but I cant access that ,.
> it shows input out error .
> 
> i.e when I do $cat /dev/ttyS0 -> it gives  input output  error .
> what may be the problem .. pls help

Please send your QEMU command-line.

Stefan

Re: [Qemu-devel] [PATCH] PPC: Fix via-cuda memory registration

[Avi Kivity]

On 09/08/2011 07:54 PM, Alexander Graf wrote:

PS: Please test your patches. This one could have been found with an invocation
 as simple as "qemu-system-ppc". We boot into the OpenBIOS prompt by 
default,
 so you wouldn't even have required a guest image or kernel.




Sorry about that.

Note that it's pretty hard to test these patches.  I often don't even 
know which binary as the device->target relationship is not immediately 
visible, and I don't really know what to expect from the guest.


It would be best if we had a kvm-autotest testset for tcg, it would 
probably run in just a few minutes and increase confidence in these patches.


--
error compiling committee.c: too many arguments to function

Re: [Qemu-devel] [PATCH] PPC: Fix via-cuda memory registration

[Alexander Graf]

Am 11.09.2011 um 12:41 schrieb Avi Kivity :

> On 09/08/2011 07:54 PM, Alexander Graf wrote:
>> PS: Please test your patches. This one could have been found with an 
>> invocation
>> as simple as "qemu-system-ppc". We boot into the OpenBIOS prompt by 
>> default,
>> so you wouldn't even have required a guest image or kernel.
>> 
> 
> 
> Sorry about that.
> 
> Note that it's pretty hard to test these patches.  I often don't even know 
> which binary as the device->target relationship is not immediately visible, 

The patch was explicitly to convert ppc ;).

> and I don't really know what to expect from the guest.

The very easy check-fundamentals thing to do for ppc is to execute 
qemu-system-ppc without arguments. It should drop you into an OF prompt. Both 
memory api bugs on ppc I've seen now would have been exposed with that.

I agree that we should have something slightly more sophisticated, but doing 
such a bare minimum test is almost for free to the tester and covers at least 
basic functionality :). I don't mind people introducibg subtle bugs in corner 
cases - these things happen. But an abort() when you execute the binary? That 
really shouldn't happen ever. This one is almost as bad.

> It would be best if we had a kvm-autotest testset for tcg, it would probably 
> run in just a few minutes and increase confidence in these patches.

Yeah, I am using kvm-autotest today for regression testing, but it's very hard 
to tell it to run multiple different binaries. The target program variable can 
only be set for an execution job, making it impossible to run multiple targets 
in one autotest run.

Also, not all targets implement enough functionality for autotest. The e500 
machine for example doesn't support power off - real hw doesn't either. So we 
always have to kill the vm exposing potential data loss. But that's probably 
gone by now with cache=unsafe fixed with your previous patches :). However that 
means that a simple test run takes quite a while already thanks to timeouts.


Alex

[Qemu-devel] [PATCH 00/15] Sparc AREG0 conversion

[Blue Swirl]

After this patch set, only load and store op helpers remain in
op_helper.c. I have some patches for those but they need more thought.

I was too lazy to attach the patches. Instead, the patch set can be found in:
git://repo.or.cz/qemu/blueswirl.git
http://repo.or.cz/r/qemu/blueswirl.git

Blue Swirl (15):
  Sparc: fix coding style
  Sparc: split helper.c
  Sparc: move trivial functions from op_helper.c
  Sparc: avoid AREG0 for raise_exception and helper_debug
  Sparc: fix coding style
  Sparc: split FPU and VIS op helpers
  Sparc: avoid AREG0 for float and VIS ops
  Sparc: split lazy condition code handling op helpers
  Sparc: avoid AREG0 for lazy condition code helpers
  Sparc: split CWP and PSTATE op helpers
  Sparc: avoid AREG0 for CWP and PSTATE helpers
  Sparc: avoid AREG0 for softint op helpers and Leon cache control
  Sparc: avoid AREG0 for division op helpers
  Sparc: fix coding style in helper.c
  Sparc: split MMU helpers

 Makefile.target   |5 +
 target-sparc/cc_helper.c  |  485 
 target-sparc/cpu.h|   36 +-
 target-sparc/cpu_init.c   |  848 ++
 target-sparc/fop_helper.c |  394 +++
 target-sparc/helper.c | 1929 ++--
 target-sparc/helper.h |  226 ++--
 target-sparc/int_helper.c |  356 ++
 target-sparc/mmu_helper.c |  877 +++
 target-sparc/op_helper.c  | 2748 +++--
 target-sparc/translate.c  |  366 +++---
 target-sparc/vis_helper.c |  406 +++
 target-sparc/win_helper.c |  407 +++
 13 files changed, 4612 insertions(+), 4471 deletions(-)
 create mode 100644 target-sparc/cc_helper.c
 create mode 100644 target-sparc/cpu_init.c
 create mode 100644 target-sparc/fop_helper.c
 create mode 100644 target-sparc/int_helper.c
 create mode 100644 target-sparc/mmu_helper.c
 create mode 100644 target-sparc/vis_helper.c
 create mode 100644 target-sparc/win_helper.c

[Qemu-devel] [PATCH 01/15] Sparc: fix coding style

[Blue Swirl]

Before the next patch, fix coding style of the areas affected.

Signed-off-by: Blue Swirl 
---
 target-sparc/helper.c |   73 +++-
 1 files changed, 41 insertions(+), 32 deletions(-)

diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index c80531a..955d180 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -1144,7 +1144,7 @@ void cpu_reset(CPUSPARCState *env)
 env->cleanwin = env->nwindows - 2;
 env->cansave = env->nwindows - 2;
 env->pstate = PS_RMO | PS_PEF | PS_IE;
-env->asi = 0x82; // Primary no-fault
+env->asi = 0x82; /* Primary no-fault */
 #endif
 #else
 #if !defined(TARGET_SPARC64)
@@ -1172,14 +1172,16 @@ static int cpu_sparc_register(CPUSPARCState
*env, const char *cpu_model)
 {
 sparc_def_t def1, *def = &def1;

-if (cpu_sparc_find_by_name(def, cpu_model) < 0)
+if (cpu_sparc_find_by_name(def, cpu_model) < 0) {
 return -1;
+}

 env->def = g_malloc0(sizeof(*def));
 memcpy(env->def, def, sizeof(*def));
 #if defined(CONFIG_USER_ONLY)
-if ((env->def->features & CPU_FEATURE_FLOAT))
+if ((env->def->features & CPU_FEATURE_FLOAT)) {
 env->def->features |= CPU_FEATURE_FLOAT128;
+}
 #endif
 env->cpu_model_str = cpu_model;
 env->version = def->iu_version;
@@ -1359,7 +1361,7 @@ static const sparc_def_t sparc_defs[] = {
 },
 {
 .name = "Sun UltraSparc T1",
-// defined in sparc_ifu_fdp.v and ctu.h
+/* defined in sparc_ifu_fdp.v and ctu.h */
 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
 .fpu_version = 0x,
 .mmu_version = mmu_sun4v,
@@ -1370,7 +1372,7 @@ static const sparc_def_t sparc_defs[] = {
 },
 {
 .name = "Sun UltraSparc T2",
-// defined in tlu_asi_ctl.v and n2_revid_cust.v
+/* defined in tlu_asi_ctl.v and n2_revid_cust.v */
 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
 .fpu_version = 0x,
 .mmu_version = mmu_sun4v,
@@ -1512,10 +1514,10 @@ static const sparc_def_t sparc_defs[] = {
 .features = CPU_DEFAULT_FEATURES,
 },
 {
-.name = "TI SuperSparc 40", // STP1020NPGA
-.iu_version = 0x4100, // SuperSPARC 2.x
+.name = "TI SuperSparc 40", /* STP1020NPGA */
+.iu_version = 0x4100, /* SuperSPARC 2.x */
 .fpu_version = 0 << 17,
-.mmu_version = 0x0800, // SuperSPARC 2.x, no MXCC
+.mmu_version = 0x0800, /* SuperSPARC 2.x, no MXCC */
 .mmu_bm = 0x2000,
 .mmu_ctpr_mask = 0xffc0,
 .mmu_cxr_mask = 0x,
@@ -1525,10 +1527,10 @@ static const sparc_def_t sparc_defs[] = {
 .features = CPU_DEFAULT_FEATURES,
 },
 {
-.name = "TI SuperSparc 50", // STP1020PGA
-.iu_version = 0x4000, // SuperSPARC 3.x
+.name = "TI SuperSparc 50", /* STP1020PGA */
+.iu_version = 0x4000, /* SuperSPARC 3.x */
 .fpu_version = 0 << 17,
-.mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
+.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
 .mmu_bm = 0x2000,
 .mmu_ctpr_mask = 0xffc0,
 .mmu_cxr_mask = 0x,
@@ -1539,9 +1541,9 @@ static const sparc_def_t sparc_defs[] = {
 },
 {
 .name = "TI SuperSparc 51",
-.iu_version = 0x4000, // SuperSPARC 3.x
+.iu_version = 0x4000, /* SuperSPARC 3.x */
 .fpu_version = 0 << 17,
-.mmu_version = 0x0100, // SuperSPARC 3.x, MXCC
+.mmu_version = 0x0100, /* SuperSPARC 3.x, MXCC */
 .mmu_bm = 0x2000,
 .mmu_ctpr_mask = 0xffc0,
 .mmu_cxr_mask = 0x,
@@ -1552,10 +1554,10 @@ static const sparc_def_t sparc_defs[] = {
 .features = CPU_DEFAULT_FEATURES,
 },
 {
-.name = "TI SuperSparc 60", // STP1020APGA
-.iu_version = 0x4000, // SuperSPARC 3.x
+.name = "TI SuperSparc 60", /* STP1020APGA */
+.iu_version = 0x4000, /* SuperSPARC 3.x */
 .fpu_version = 0 << 17,
-.mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
+.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
 .mmu_bm = 0x2000,
 .mmu_ctpr_mask = 0xffc0,
 .mmu_cxr_mask = 0x,
@@ -1566,9 +1568,9 @@ static const sparc_def_t sparc_defs[] = {
 },
 {
 .name = "TI SuperSparc 61",
-.iu_version = 0x4400, // SuperSPARC 3.x
+.iu_version = 0x4400, /* SuperSPARC 3.x */
 .fpu_version = 0 << 17,
-.mmu_version = 0x0100, // SuperSPARC 3.x, MXCC
+.mmu_version = 0x0100, /* SuperSPARC 3.x, MXCC */
 .mmu_bm = 0x2000,
 .mmu_ctpr_mask = 0xffc0,
 .mmu_cxr_mask = 0x,
@@ -1580,9 +1582,9 @@ static const sparc_def_t sparc_defs[] = {
 },
 {
 .name = "TI SuperSparc II",
-.iu_versio

[Qemu-devel] [PATCH 04/15] Sparc: avoid AREG0 for raise_exception and helper_debug

[Blue Swirl]

Make raise_exception() and helper_debug() take a parameter for
CPUState instead of relying on global env. Move the functions
to helper.c.

Signed-off-by: Blue Swirl 
---
 target-sparc/helper.c|   12 ++
 target-sparc/helper.h|4 +-
 target-sparc/op_helper.c |  100 --
 target-sparc/translate.c |   26 ++--
 4 files changed, 70 insertions(+), 72 deletions(-)

diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index e9182ac..7a25605 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -871,6 +871,18 @@ target_phys_addr_t
cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 #endif

 /* misc op helpers */
+void helper_raise_exception(CPUState *env, int tt)
+{
+env->exception_index = tt;
+cpu_loop_exit(env);
+}
+
+void helper_debug(CPUState *env)
+{
+env->exception_index = EXCP_DEBUG;
+cpu_loop_exit(env);
+}
+
 void helper_shutdown(void)
 {
 #if !defined(CONFIG_USER_ONLY)
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index 2d36af3..a452666 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -32,7 +32,7 @@ DEF_HELPER_1(tick_get_count, i64, ptr)
 DEF_HELPER_2(tick_set_limit, void, ptr, i64)
 #endif
 DEF_HELPER_2(check_align, void, tl, i32)
-DEF_HELPER_0(debug, void)
+DEF_HELPER_1(debug, void, env)
 DEF_HELPER_0(save, void)
 DEF_HELPER_0(restore, void)
 DEF_HELPER_2(udiv, tl, tl, tl)
@@ -83,7 +83,7 @@ DEF_HELPER_0(fcmpeq_fcc1, void)
 DEF_HELPER_0(fcmpeq_fcc2, void)
 DEF_HELPER_0(fcmpeq_fcc3, void)
 #endif
-DEF_HELPER_1(raise_exception, void, int)
+DEF_HELPER_2(raise_exception, void, env, int)
 DEF_HELPER_0(shutdown, void)
 #define F_HELPER_0_0(name) DEF_HELPER_0(f ## name, void)
 #define F_HELPER_DQ_0_0(name)   \
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index dbdccea..6a333c1 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -321,17 +321,6 @@ static inline target_ulong asi_address_mask(CPUState *env1,
 }
 }

-static void raise_exception(int tt)
-{
-env->exception_index = tt;
-cpu_loop_exit(env);
-}
-
-void HELPER(raise_exception)(int tt)
-{
-raise_exception(tt);
-}
-
 void helper_check_align(target_ulong addr, uint32_t align)
 {
 if (addr & align) {
@@ -339,7 +328,7 @@ void helper_check_align(target_ulong addr, uint32_t align)
 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
"\n", addr, env->pc);
 #endif
-raise_exception(TT_UNALIGNED);
+helper_raise_exception(env, TT_UNALIGNED);
 }
 }

@@ -853,7 +842,7 @@ void helper_check_ieee_exceptions(void)
 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
 /* Unmasked exception, generate a trap */
 env->fsr |= FSR_FTT_IEEE_EXCP;
-raise_exception(TT_FP_EXCP);
+helper_raise_exception(env, TT_FP_EXCP);
 } else {
 /* Accumulate exceptions */
 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
@@ -907,14 +896,14 @@ void helper_fsqrtq(void)
 (env->fsr & FSR_NVM)) { \
 env->fsr |= FSR_NVC;\
 env->fsr |= FSR_FTT_IEEE_EXCP;  \
-raise_exception(TT_FP_EXCP);\
+helper_raise_exception(env, TT_FP_EXCP);\
 }   \
 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
 case float_relation_unordered:  \
 if ((env->fsr & FSR_NVM)) { \
 env->fsr |= FSR_NVC;\
 env->fsr |= FSR_FTT_IEEE_EXCP;  \
-raise_exception(TT_FP_EXCP);\
+helper_raise_exception(env, TT_FP_EXCP);\
 } else {\
 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS;\
@@ -943,14 +932,14 @@ void helper_fsqrtq(void)
 (env->fsr & FSR_NVM)) { \
 env->fsr |= FSR_NVC;\
 env->fsr |= FSR_FTT_IEEE_EXCP;  \
-raise_exception(TT_FP_EXCP);\
+helper_raise_exception(env, TT_FP_EXCP);\
 }   \
 switch (glue(size, _compare) (src1, src2, &env->fp_status)) {   \
 case float_relation_unordered:  \
 if ((env->fsr & FSR_NVM)) {

[Qemu-devel] [PATCH 14/15] Sparc: fix coding style in helper.c

[Blue Swirl]

Before the next patch, fix coding style of the areas affected.

Signed-off-by: Blue Swirl 
---
 target-sparc/helper.c |   95 +++--
 1 files changed, 52 insertions(+), 43 deletions(-)

diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 5f8cf31..1b21782 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -25,7 +25,7 @@
 //#define DEBUG_MMU

 #ifdef DEBUG_MMU
-#define DPRINTF_MMU(fmt, ...) \
+#define DPRINTF_MMU(fmt, ...)   \
 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
 #else
 #define DPRINTF_MMU(fmt, ...) do {} while (0)
@@ -38,10 +38,11 @@
 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
int mmu_idx)
 {
-if (rw & 2)
+if (rw & 2) {
 env1->exception_index = TT_TFAULT;
-else
+} else {
 env1->exception_index = TT_DFAULT;
+}
 return 1;
 }

@@ -100,7 +101,7 @@ static int get_physical_address(CPUState *env,
target_phys_addr_t *physical,

 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
 *page_size = TARGET_PAGE_SIZE;
-// Boot mode: instruction fetches are taken from PROM
+/* Boot mode: instruction fetches are taken from PROM */
 if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
 *physical = env->prom_addr | (address & 0x7ULL);
 *prot = PAGE_READ | PAGE_EXEC;
@@ -111,7 +112,7 @@ static int get_physical_address(CPUState *env,
target_phys_addr_t *physical,
 return 0;
 }

-*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
+*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1);
 *physical = 0xULL;

 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
@@ -178,15 +179,17 @@ static int get_physical_address(CPUState *env,
target_phys_addr_t *physical,
 /* check access */
 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
 error_code = access_table[*access_index][access_perms];
-if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
+if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) {
 return error_code;
+}

 /* update page modified and dirty bits */
 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
 pde |= PG_ACCESSED_MASK;
-if (is_dirty)
+if (is_dirty) {
 pde |= PG_MODIFIED_MASK;
+}
 stl_phys_notdirty(pde_ptr, pde);
 }

@@ -205,8 +208,8 @@ static int get_physical_address(CPUState *env,
target_phys_addr_t *physical,
 }

 /* Perform address translation */
-int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
-  int mmu_idx)
+int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+   int mmu_idx)
 {
 target_phys_addr_t paddr;
 target_ulong vaddr;
@@ -226,25 +229,27 @@ int cpu_sparc_handle_mmu_fault (CPUState *env,
target_ulong address, int rw,
 return 0;
 }

-if (env->mmuregs[3]) /* Fault status register */
+if (env->mmuregs[3]) { /* Fault status register */
 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
+}
 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
 env->mmuregs[4] = address; /* Fault address register */

 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
-// No fault mode: if a mapping is available, just override
-// permissions. If no mapping is available, redirect accesses to
-// neverland. Fake/overridden mappings will be flushed when
-// switching to normal mode.
+/* No fault mode: if a mapping is available, just override
+   permissions. If no mapping is available, redirect accesses to
+   neverland. Fake/overridden mappings will be flushed when
+   switching to normal mode. */
 vaddr = address & TARGET_PAGE_MASK;
 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
 return 0;
 } else {
-if (rw & 2)
+if (rw & 2) {
 env->exception_index = TT_TFAULT;
-else
+} else {
 env->exception_index = TT_DFAULT;
+}
 return 1;
 }
 }
@@ -266,8 +271,9 @@ target_ulong mmu_probe(CPUState *env, target_ulong
address, int mmulev)
 case 3: /* Reserved */
 return 0;
 case 1: /* L1 PDE */
-if (mmulev == 3)
+if (mmulev == 3) {
 return pde;
+}
 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
 pde = ldl_phys(pde_ptr);

@@ -279,8 +285,9 @@ target_ulong mmu_probe(CPUState *env, target_ulong
address, int mmulev)
 case 2: /* L1 PTE */
 return pde;
 case 1: /* L2 PDE */
-if (mmul

Re: [Qemu-devel] Why qemu write/rw speed is so low?

[Christoph Hellwig]

On Fri, Sep 09, 2011 at 04:04:07PM +0200, Kevin Wolf wrote:
> > need to read in the existing 4 KB, modify the 512 bytes in place, and
> > write out the 4 KB block again.  This is read-modify-write.  In this
> > worst-case scenario a 512 byte write turns into a 4 KB read followed
> > by a 4 KB write.
> 
> But that should only happen with a 4k sector size, otherwise there's no
> reason for RMW.

The might not be a need for RMW, but if you're doing 512 byte writes to a
sparse file on 4k filesystem that filesystem will have to serialize the
I/O to prevent races from happening during block allocation.

Re: [Qemu-devel] qemu virtIO blocking operation - question

[Stefan Hajnoczi]

On Fri, Sep 09, 2011 at 07:45:17PM -0500, Sinha, Ani wrote:
> So I am writing a virtIO driver for a device that supports blocking calls 
> like poll() etc. Now the front end paravirtualized driver mirrors the request 
> to the backend "host" qemu process that then does the actual call on the host 
> kernel on behalf of the guest. Now my question is, when I do a blocking call 
> from within the callback that I have registered when I created the virtqueue, 
> does it block the entire vcpu? If it does, do I have to create an async 
> context for it? Looking at virtio-net and virtio-block, I can see the concept 
> of bottom halves but I am not sure if this helps me in any way.

What device are you adding?  It would help to share what you are trying
to accomplish.

QEMU has an event loop where you can register non-blocking file
descriptors.  Callback functions that are invoked when the file
descriptor becomes readable/writable.  This is how block I/O,
networking, VNC UI, monitor, etc work and probably what you should do
too.

You may find these posts I wrote helpful, they explain vcpu threads and
the I/O thread:
http://blog.vmsplice.net/2011/03/qemu-internals-big-picture-overview.html
http://blog.vmsplice.net/2011/03/qemu-internals-overall-architecture-and.html

Stefan

[Qemu-devel] [PATCH 03/15] Sparc: move trivial functions from op_helper.c

[Blue Swirl]

These functions don't need access to CPUState or already pass it,
so relocating them from op_helper.c to helper.c and int_helper.c
is trivial.

Signed-off-by: Blue Swirl 
---
 target-sparc/helper.c |   41 +++
 target-sparc/int_helper.c |7 ++
 target-sparc/op_helper.c  |   47 -
 3 files changed, 48 insertions(+), 47 deletions(-)

diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 1866f63..e9182ac 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -18,6 +18,9 @@
  */

 #include "cpu.h"
+#include "host-utils.h"
+#include "helper.h"
+#include "sysemu.h"

 //#define DEBUG_MMU

@@ -866,3 +869,41 @@ target_phys_addr_t
cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 return phys_addr;
 }
 #endif
+
+/* misc op helpers */
+void helper_shutdown(void)
+{
+#if !defined(CONFIG_USER_ONLY)
+qemu_system_shutdown_request();
+#endif
+}
+
+#ifdef TARGET_SPARC64
+target_ulong helper_popc(target_ulong val)
+{
+return ctpop64(val);
+}
+
+void helper_tick_set_count(void *opaque, uint64_t count)
+{
+#if !defined(CONFIG_USER_ONLY)
+cpu_tick_set_count(opaque, count);
+#endif
+}
+
+uint64_t helper_tick_get_count(void *opaque)
+{
+#if !defined(CONFIG_USER_ONLY)
+return cpu_tick_get_count(opaque);
+#else
+return 0;
+#endif
+}
+
+void helper_tick_set_limit(void *opaque, uint64_t limit)
+{
+#if !defined(CONFIG_USER_ONLY)
+cpu_tick_set_limit(opaque, limit);
+#endif
+}
+#endif
diff --git a/target-sparc/int_helper.c b/target-sparc/int_helper.c
index 31dc192..f88ddac 100644
--- a/target-sparc/int_helper.c
+++ b/target-sparc/int_helper.c
@@ -262,3 +262,10 @@ void do_interrupt(CPUState *env)
 #endif
 }
 #endif
+
+#ifdef TARGET_SPARC64
+trap_state *cpu_tsptr(CPUState* env)
+{
+return &env->ts[env->tl & MAXTL_MASK];
+}
+#endif
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 2e56177..dbdccea 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1,8 +1,6 @@
 #include "cpu.h"
 #include "dyngen-exec.h"
-#include "host-utils.h"
 #include "helper.h"
-#include "sysemu.h"

 #if !defined(CONFIG_USER_ONLY)
 #include "softmmu_exec.h"
@@ -334,13 +332,6 @@ void HELPER(raise_exception)(int tt)
 raise_exception(tt);
 }

-void helper_shutdown(void)
-{
-#if !defined(CONFIG_USER_ONLY)
-qemu_system_shutdown_request();
-#endif
-}
-
 void helper_check_align(target_ulong addr, uint32_t align)
 {
 if (addr & align) {
@@ -4003,11 +3994,6 @@ target_ulong helper_alignaddr(target_ulong
addr, target_ulong offset)
 return tmp & ~7ULL;
 }

-target_ulong helper_popc(target_ulong val)
-{
-return ctpop64(val);
-}
-
 static inline uint64_t *get_gregset(uint32_t pstate)
 {
 switch (pstate) {
@@ -4164,13 +4150,6 @@ void helper_write_softint(uint64_t value)
 }
 #endif

-#ifdef TARGET_SPARC64
-trap_state* cpu_tsptr(CPUState* env)
-{
-return &env->ts[env->tl & MAXTL_MASK];
-}
-#endif
-
 #if !defined(CONFIG_USER_ONLY)

 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
@@ -4321,32 +4300,6 @@ static void
do_unassigned_access(target_phys_addr_t addr, int is_write,
 }
 #endif

-
-#ifdef TARGET_SPARC64
-void helper_tick_set_count(void *opaque, uint64_t count)
-{
-#if !defined(CONFIG_USER_ONLY)
-cpu_tick_set_count(opaque, count);
-#endif
-}
-
-uint64_t helper_tick_get_count(void *opaque)
-{
-#if !defined(CONFIG_USER_ONLY)
-return cpu_tick_get_count(opaque);
-#else
-return 0;
-#endif
-}
-
-void helper_tick_set_limit(void *opaque, uint64_t limit)
-{
-#if !defined(CONFIG_USER_ONLY)
-cpu_tick_set_limit(opaque, limit);
-#endif
-}
-#endif
-
 #if !defined(CONFIG_USER_ONLY)
 void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size)
-- 
1.6.2.4

[Qemu-devel] [PATCH 09/15] Sparc: avoid AREG0 for lazy condition code helpers

[Blue Swirl]

Make lazy condition code helpers take a parameter for CPUState instead
of relying on global env.

Signed-off-by: Blue Swirl 
---
 Makefile.target  |2 +-
 target-sparc/cc_helper.c |   73 ++---
 target-sparc/helper.h|4 +-
 target-sparc/op_helper.c |2 +-
 target-sparc/translate.c |   18 ++--
 5 files changed, 49 insertions(+), 50 deletions(-)

diff --git a/Makefile.target b/Makefile.target
index 552be5b..3d6d112 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -95,7 +95,7 @@ tcg/tcg.o: cpu.h

 # HELPER_CFLAGS is used for all the code compiled with static register
 # variables
-op_helper.o cc_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
+op_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)

 # Note: this is a workaround. The real fix is to avoid compiling
 # cpu_signal_handler() in user-exec.c.
diff --git a/target-sparc/cc_helper.c b/target-sparc/cc_helper.c
index a067397..04bd2cf 100644
--- a/target-sparc/cc_helper.c
+++ b/target-sparc/cc_helper.c
@@ -18,15 +18,14 @@
  */

 #include "cpu.h"
-#include "dyngen-exec.h"
 #include "helper.h"

-static uint32_t compute_all_flags(void)
+static uint32_t compute_all_flags(CPUState *env)
 {
 return env->psr & PSR_ICC;
 }

-static uint32_t compute_C_flags(void)
+static uint32_t compute_C_flags(CPUState *env)
 {
 return env->psr & PSR_CARRY;
 }
@@ -44,12 +43,12 @@ static inline uint32_t get_NZ_icc(int32_t dst)
 }

 #ifdef TARGET_SPARC64
-static uint32_t compute_all_flags_xcc(void)
+static uint32_t compute_all_flags_xcc(CPUState *env)
 {
 return env->xcc & PSR_ICC;
 }

-static uint32_t compute_C_flags_xcc(void)
+static uint32_t compute_C_flags_xcc(CPUState *env)
 {
 return env->xcc & PSR_CARRY;
 }
@@ -77,7 +76,7 @@ static inline uint32_t get_V_div_icc(target_ulong src2)
 return ret;
 }

-static uint32_t compute_all_div(void)
+static uint32_t compute_all_div(CPUState *env)
 {
 uint32_t ret;

@@ -86,7 +85,7 @@ static uint32_t compute_all_div(void)
 return ret;
 }

-static uint32_t compute_C_div(void)
+static uint32_t compute_C_div(CPUState *env)
 {
 return 0;
 }
@@ -156,7 +155,7 @@ static inline uint32_t get_V_add_xcc(target_ulong
dst, target_ulong src1,
 return ret;
 }

-static uint32_t compute_all_add_xcc(void)
+static uint32_t compute_all_add_xcc(CPUState *env)
 {
 uint32_t ret;

@@ -166,13 +165,13 @@ static uint32_t compute_all_add_xcc(void)
 return ret;
 }

-static uint32_t compute_C_add_xcc(void)
+static uint32_t compute_C_add_xcc(CPUState *env)
 {
 return get_C_add_xcc(CC_DST, CC_SRC);
 }
 #endif

-static uint32_t compute_all_add(void)
+static uint32_t compute_all_add(CPUState *env)
 {
 uint32_t ret;

@@ -182,13 +181,13 @@ static uint32_t compute_all_add(void)
 return ret;
 }

-static uint32_t compute_C_add(void)
+static uint32_t compute_C_add(CPUState *env)
 {
 return get_C_add_icc(CC_DST, CC_SRC);
 }

 #ifdef TARGET_SPARC64
-static uint32_t compute_all_addx_xcc(void)
+static uint32_t compute_all_addx_xcc(CPUState *env)
 {
 uint32_t ret;

@@ -198,7 +197,7 @@ static uint32_t compute_all_addx_xcc(void)
 return ret;
 }

-static uint32_t compute_C_addx_xcc(void)
+static uint32_t compute_C_addx_xcc(CPUState *env)
 {
 uint32_t ret;

@@ -207,7 +206,7 @@ static uint32_t compute_C_addx_xcc(void)
 }
 #endif

-static uint32_t compute_all_addx(void)
+static uint32_t compute_all_addx(CPUState *env)
 {
 uint32_t ret;

@@ -217,7 +216,7 @@ static uint32_t compute_all_addx(void)
 return ret;
 }

-static uint32_t compute_C_addx(void)
+static uint32_t compute_C_addx(CPUState *env)
 {
 uint32_t ret;

@@ -235,7 +234,7 @@ static inline uint32_t get_V_tag_icc(target_ulong
src1, target_ulong src2)
 return ret;
 }

-static uint32_t compute_all_tadd(void)
+static uint32_t compute_all_tadd(CPUState *env)
 {
 uint32_t ret;

@@ -246,7 +245,7 @@ static uint32_t compute_all_tadd(void)
 return ret;
 }

-static uint32_t compute_all_taddtv(void)
+static uint32_t compute_all_taddtv(CPUState *env)
 {
 uint32_t ret;

@@ -321,7 +320,7 @@ static inline uint32_t get_V_sub_xcc(target_ulong
dst, target_ulong src1,
 return ret;
 }

-static uint32_t compute_all_sub_xcc(void)
+static uint32_t compute_all_sub_xcc(CPUState *env)
 {
 uint32_t ret;

@@ -331,13 +330,13 @@ static uint32_t compute_all_sub_xcc(void)
 return ret;
 }

-static uint32_t compute_C_sub_xcc(void)
+static uint32_t compute_C_sub_xcc(CPUState *env)
 {
 return get_C_sub_xcc(CC_SRC, CC_SRC2);
 }
 #endif

-static uint32_t compute_all_sub(void)
+static uint32_t compute_all_sub(CPUState *env)
 {
 uint32_t ret;

@@ -347,13 +346,13 @@ static uint32_t compute_all_sub(void)
 return ret;
 }

-static uint32_t compute_C_sub(void)
+static uint32_t compute_C_sub(CPUState *env)
 {
 return get_C_sub_icc(CC_SRC, CC_SRC2);
 }

 #ifdef TARGET_SPARC64
-static uint32_t compute_all_subx_xcc(void)
+static uint32_t compute_all_subx_xcc(CPUState *env)
 {
 

[Qemu-devel] [PATCH 10/15] Sparc: split CWP and PSTATE op helpers

[Blue Swirl]

Move CWP and PSTATE op helpers to win_helper.c.

Signed-off-by: Blue Swirl 
---
 Makefile.target   |4 +-
 target-sparc/cpu.h|4 +-
 target-sparc/op_helper.c  |  489 +--
 target-sparc/win_helper.c |  518 +
 4 files changed, 524 insertions(+), 491 deletions(-)
 create mode 100644 target-sparc/win_helper.c

diff --git a/Makefile.target b/Makefile.target
index 3d6d112..01062ad 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -78,7 +78,7 @@ libobj-$(TARGET_SPARC64) += vis_helper.o
 libobj-$(CONFIG_NEED_MMU) += mmu.o
 libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
 ifeq ($(TARGET_BASE_ARCH), sparc)
-libobj-y += int_helper.o fop_helper.o cc_helper.o cpu_init.o
+libobj-y += int_helper.o fop_helper.o cc_helper.o win_helper.o cpu_init.o
 endif

 libobj-y += disas.o
@@ -95,7 +95,7 @@ tcg/tcg.o: cpu.h

 # HELPER_CFLAGS is used for all the code compiled with static register
 # variables
-op_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
+op_helper.o win_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)

 # Note: this is a workaround. The real fix is to avoid compiling
 # cpu_signal_handler() in user-exec.c.
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index c9ab7e4..6bf9275 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -509,7 +509,7 @@ void gen_intermediate_code_init(CPUSPARCState *env);
 /* cpu-exec.c */
 int cpu_sparc_exec(CPUSPARCState *s);

-/* op_helper.c */
+/* win_helper.c */
 target_ulong cpu_get_psr(CPUState *env1);
 void cpu_put_psr(CPUState *env1, target_ulong val);
 #ifdef TARGET_SPARC64
@@ -522,6 +522,8 @@ void cpu_change_pstate(CPUState *env1, uint32_t new_pstate);
 int cpu_cwp_inc(CPUState *env1, int cwp);
 int cpu_cwp_dec(CPUState *env1, int cwp);
 void cpu_set_cwp(CPUState *env1, int new_cwp);
+
+/* op_helper.c */
 void leon3_irq_manager(void *irq_manager, int intno);

 /* sun4m.c, sun4u.c */
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 70978e0..23ccce5 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -333,140 +333,6 @@ void helper_check_align(target_ulong addr, uint32_t align)
 }
 }

-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
-{
-dst[0] = src[0];
-dst[1] = src[1];
-dst[2] = src[2];
-dst[3] = src[3];
-dst[4] = src[4];
-dst[5] = src[5];
-dst[6] = src[6];
-dst[7] = src[7];
-}
-
-static void set_cwp(int new_cwp)
-{
-/* put the modified wrap registers at their proper location */
-if (env->cwp == env->nwindows - 1) {
-memcpy32(env->regbase, env->regbase + env->nwindows * 16);
-}
-env->cwp = new_cwp;
-
-/* put the wrap registers at their temporary location */
-if (new_cwp == env->nwindows - 1) {
-memcpy32(env->regbase + env->nwindows * 16, env->regbase);
-}
-env->regwptr = env->regbase + (new_cwp * 16);
-}
-
-void cpu_set_cwp(CPUState *env1, int new_cwp)
-{
-CPUState *saved_env;
-
-saved_env = env;
-env = env1;
-set_cwp(new_cwp);
-env = saved_env;
-}
-
-static target_ulong get_psr(void)
-{
-helper_compute_psr(env);
-
-#if !defined (TARGET_SPARC64)
-return env->version | (env->psr & PSR_ICC) |
-(env->psref ? PSR_EF : 0) |
-(env->psrpil << 8) |
-(env->psrs ? PSR_S : 0) |
-(env->psrps ? PSR_PS : 0) |
-(env->psret ? PSR_ET : 0) | env->cwp;
-#else
-return env->psr & PSR_ICC;
-#endif
-}
-
-target_ulong cpu_get_psr(CPUState *env1)
-{
-CPUState *saved_env;
-target_ulong ret;
-
-saved_env = env;
-env = env1;
-ret = get_psr();
-env = saved_env;
-return ret;
-}
-
-static void put_psr(target_ulong val)
-{
-env->psr = val & PSR_ICC;
-#if !defined (TARGET_SPARC64)
-env->psref = (val & PSR_EF) ? 1 : 0;
-env->psrpil = (val & PSR_PIL) >> 8;
-#endif
-#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
-cpu_check_irqs(env);
-#endif
-#if !defined (TARGET_SPARC64)
-env->psrs = (val & PSR_S) ? 1 : 0;
-env->psrps = (val & PSR_PS) ? 1 : 0;
-env->psret = (val & PSR_ET) ? 1 : 0;
-set_cwp(val & PSR_CWP);
-#endif
-env->cc_op = CC_OP_FLAGS;
-}
-
-void cpu_put_psr(CPUState *env1, target_ulong val)
-{
-CPUState *saved_env;
-
-saved_env = env;
-env = env1;
-put_psr(val);
-env = saved_env;
-}
-
-static int cwp_inc(int cwp)
-{
-if (unlikely(cwp >= env->nwindows)) {
-cwp -= env->nwindows;
-}
-return cwp;
-}
-
-int cpu_cwp_inc(CPUState *env1, int cwp)
-{
-CPUState *saved_env;
-target_ulong ret;
-
-saved_env = env;
-env = env1;
-ret = cwp_inc(cwp);
-env = saved_env;
-return ret;
-}
-
-static int cwp_dec(int cwp)
-{
-if (unlikely(cwp < 0)) {
-cwp += env->nwindows;
-}
-return cwp;
-}
-
-int cpu_cwp_dec(CPUState *env1, int cwp)
-{
-CPUState *saved_env;
-target_ulong ret;
-
-saved_env = env;
-   

[Qemu-devel] [PATCH 12/15] Sparc: avoid AREG0 for softint op helpers and Leon cache control

[Blue Swirl]

Make softint op helpers and Leon cache irq manager take a parameter
for CPUState instead of relying on global env. Move the functions
to int_helper.c.

Signed-off-by: Blue Swirl 
---
 target-sparc/cpu.h|   31 ---
 target-sparc/helper.h |6 +-
 target-sparc/int_helper.c |   87 +-
 target-sparc/op_helper.c  |   94 -
 target-sparc/translate.c  |6 +-
 5 files changed, 117 insertions(+), 107 deletions(-)

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 6bf9275..ce1e668 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -335,6 +335,27 @@ enum {
 #define SFSR_CT_NOTRANS (3ULL <<  4)
 #define SFSR_CT_MASK(3ULL <<  4)

+/* Leon3 cache control */
+
+/* Cache control: emulate the behavior of cache control registers but without
+   any effect on the emulated */
+
+#define CACHE_STATE_MASK 0x3
+#define CACHE_DISABLED   0x0
+#define CACHE_FROZEN 0x1
+#define CACHE_ENABLED0x3
+
+/* Cache Control register fields */
+
+#define CACHE_CTRL_IF (1 <<  4)  /* Instruction Cache Freeze on Interrupt */
+#define CACHE_CTRL_DF (1 <<  5)  /* Data Cache Freeze on Interrupt */
+#define CACHE_CTRL_DP (1 << 14)  /* Data cache flush pending */
+#define CACHE_CTRL_IP (1 << 15)  /* Instruction cache flush pending */
+#define CACHE_CTRL_IB (1 << 16)  /* Instruction burst fetch */
+#define CACHE_CTRL_FI (1 << 21)  /* Flush Instruction cache (Write only) */
+#define CACHE_CTRL_FD (1 << 22)  /* Flush Data cache (Write only) */
+#define CACHE_CTRL_DS (1 << 23)  /* Data cache snoop enable */
+
 typedef struct SparcTLBEntry {
 uint64_t tag;
 uint64_t tte;
@@ -478,7 +499,7 @@ typedef struct CPUSPARCState {
 sparc_def_t *def;

 void *irq_manager;
-void (*qemu_irq_ack) (void *irq_manager, int intno);
+void (*qemu_irq_ack)(CPUState *env, void *irq_manager, int intno);

 /* Leon3 cache control */
 uint32_t cache_control;
@@ -523,8 +544,9 @@ int cpu_cwp_inc(CPUState *env1, int cwp);
 int cpu_cwp_dec(CPUState *env1, int cwp);
 void cpu_set_cwp(CPUState *env1, int new_cwp);

-/* op_helper.c */
-void leon3_irq_manager(void *irq_manager, int intno);
+/* int_helper.c */
+void do_interrupt(CPUState *env);
+void leon3_irq_manager(CPUState *env, void *irq_manager, int intno);

 /* sun4m.c, sun4u.c */
 void cpu_check_irqs(CPUSPARCState *env);
@@ -721,9 +743,6 @@ static inline bool tb_am_enabled(int tb_flags)
 #endif
 }

-/* helper.c */
-void do_interrupt(CPUState *env);
-
 static inline bool cpu_has_work(CPUState *env1)
 {
 return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index b18cbc6..943b4ba 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -24,9 +24,9 @@ DEF_HELPER_4(ldf_asi, void, tl, int, int, int)
 DEF_HELPER_4(stf_asi, void, tl, int, int, int)
 DEF_HELPER_4(cas_asi, tl, tl, tl, tl, i32)
 DEF_HELPER_4(casx_asi, tl, tl, tl, tl, i32)
-DEF_HELPER_1(set_softint, void, i64)
-DEF_HELPER_1(clear_softint, void, i64)
-DEF_HELPER_1(write_softint, void, i64)
+DEF_HELPER_2(set_softint, void, env, i64)
+DEF_HELPER_2(clear_softint, void, env, i64)
+DEF_HELPER_2(write_softint, void, env, i64)
 DEF_HELPER_2(tick_set_count, void, ptr, i64)
 DEF_HELPER_1(tick_get_count, i64, ptr)
 DEF_HELPER_2(tick_set_limit, void, ptr, i64)
diff --git a/target-sparc/int_helper.c b/target-sparc/int_helper.c
index f88ddac..3361eed 100644
--- a/target-sparc/int_helper.c
+++ b/target-sparc/int_helper.c
@@ -18,8 +18,25 @@
  */

 #include "cpu.h"
+#include "helper.h"

 //#define DEBUG_PCALL
+//#define DEBUG_PSTATE
+//#define DEBUG_CACHE_CONTROL
+
+#ifdef DEBUG_PSTATE
+#define DPRINTF_PSTATE(fmt, ...)\
+do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
+#endif
+
+#ifdef DEBUG_CACHE_CONTROL
+#define DPRINTF_CACHE_CONTROL(fmt, ...) \
+do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
+#endif

 #ifdef TARGET_SPARC64
 #ifdef DEBUG_PCALL
@@ -257,7 +274,7 @@ void do_interrupt(CPUState *env)
 #if !defined(CONFIG_USER_ONLY)
 /* IRQ acknowledgment */
 if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
-env->qemu_irq_ack(env->irq_manager, intno);
+env->qemu_irq_ack(env, env->irq_manager, intno);
 }
 #endif
 }
@@ -268,4 +285,72 @@ trap_state *cpu_tsptr(CPUState* env)
 {
 return &env->ts[env->tl & MAXTL_MASK];
 }
+
+static void do_modify_softint(CPUState *env, const char *operation,
+  uint32_t value)
+{
+if (env->softint != value) {
+env->softint = value;
+DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
+#if !defined(CONFIG_USER_ONLY)
+if (cpu_interrupts_enabled(env)) {
+cpu_check_irqs(env);
+}
+

[Qemu-devel] [PATCH 08/15] Sparc: split lazy condition code handling op helpers

[Blue Swirl]

Move lazy condition code handling op helpers to cc_helper.c.

Signed-off-by: Blue Swirl 
---
 Makefile.target  |4 +-
 target-sparc/cc_helper.c |  486 ++
 target-sparc/op_helper.c |  464 ---
 3 files changed, 488 insertions(+), 466 deletions(-)
 create mode 100644 target-sparc/cc_helper.c

diff --git a/Makefile.target b/Makefile.target
index 5bb59ee..552be5b 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -78,7 +78,7 @@ libobj-$(TARGET_SPARC64) += vis_helper.o
 libobj-$(CONFIG_NEED_MMU) += mmu.o
 libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
 ifeq ($(TARGET_BASE_ARCH), sparc)
-libobj-y += int_helper.o fop_helper.o cpu_init.o
+libobj-y += int_helper.o fop_helper.o cc_helper.o cpu_init.o
 endif

 libobj-y += disas.o
@@ -95,7 +95,7 @@ tcg/tcg.o: cpu.h

 # HELPER_CFLAGS is used for all the code compiled with static register
 # variables
-op_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
+op_helper.o cc_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)

 # Note: this is a workaround. The real fix is to avoid compiling
 # cpu_signal_handler() in user-exec.c.
diff --git a/target-sparc/cc_helper.c b/target-sparc/cc_helper.c
new file mode 100644
index 000..a067397
--- /dev/null
+++ b/target-sparc/cc_helper.c
@@ -0,0 +1,486 @@
+/*
+ * Helpers for lazy condition code handling
+ *
+ *  Copyright (c) 2003-2005 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "cpu.h"
+#include "dyngen-exec.h"
+#include "helper.h"
+
+static uint32_t compute_all_flags(void)
+{
+return env->psr & PSR_ICC;
+}
+
+static uint32_t compute_C_flags(void)
+{
+return env->psr & PSR_CARRY;
+}
+
+static inline uint32_t get_NZ_icc(int32_t dst)
+{
+uint32_t ret = 0;
+
+if (dst == 0) {
+ret = PSR_ZERO;
+} else if (dst < 0) {
+ret = PSR_NEG;
+}
+return ret;
+}
+
+#ifdef TARGET_SPARC64
+static uint32_t compute_all_flags_xcc(void)
+{
+return env->xcc & PSR_ICC;
+}
+
+static uint32_t compute_C_flags_xcc(void)
+{
+return env->xcc & PSR_CARRY;
+}
+
+static inline uint32_t get_NZ_xcc(target_long dst)
+{
+uint32_t ret = 0;
+
+if (!dst) {
+ret = PSR_ZERO;
+} else if (dst < 0) {
+ret = PSR_NEG;
+}
+return ret;
+}
+#endif
+
+static inline uint32_t get_V_div_icc(target_ulong src2)
+{
+uint32_t ret = 0;
+
+if (src2 != 0) {
+ret = PSR_OVF;
+}
+return ret;
+}
+
+static uint32_t compute_all_div(void)
+{
+uint32_t ret;
+
+ret = get_NZ_icc(CC_DST);
+ret |= get_V_div_icc(CC_SRC2);
+return ret;
+}
+
+static uint32_t compute_C_div(void)
+{
+return 0;
+}
+
+static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1)
+{
+uint32_t ret = 0;
+
+if (dst < src1) {
+ret = PSR_CARRY;
+}
+return ret;
+}
+
+static inline uint32_t get_C_addx_icc(uint32_t dst, uint32_t src1,
+  uint32_t src2)
+{
+uint32_t ret = 0;
+
+if (((src1 & src2) | (~dst & (src1 | src2))) & (1U << 31)) {
+ret = PSR_CARRY;
+}
+return ret;
+}
+
+static inline uint32_t get_V_add_icc(uint32_t dst, uint32_t src1,
+ uint32_t src2)
+{
+uint32_t ret = 0;
+
+if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1U << 31)) {
+ret = PSR_OVF;
+}
+return ret;
+}
+
+#ifdef TARGET_SPARC64
+static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1)
+{
+uint32_t ret = 0;
+
+if (dst < src1) {
+ret = PSR_CARRY;
+}
+return ret;
+}
+
+static inline uint32_t get_C_addx_xcc(target_ulong dst, target_ulong src1,
+  target_ulong src2)
+{
+uint32_t ret = 0;
+
+if (((src1 & src2) | (~dst & (src1 | src2))) & (1ULL << 63)) {
+ret = PSR_CARRY;
+}
+return ret;
+}
+
+static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1,
+ target_ulong src2)
+{
+uint32_t ret = 0;
+
+if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63)) {
+ret = PSR_OVF;
+}
+return ret;
+}
+
+static uint32_t compute_all_add_xcc(void)
+{
+uint32_t ret;
+
+ret = get_NZ_xcc(CC_DST);
+ret |= get_C_add_xcc(CC_DST, CC_SRC);
+ret |= get_V_add_xcc(CC_DST,

[Qemu-devel] [PATCH 06/15] Sparc: split FPU and VIS op helpers

[Blue Swirl]

Move FPU op helpers to fop_helper.c. Move VIS op helpers to vis_helper.c,
compile it only for Sparc64.

Signed-off-by: Blue Swirl 
---
 Makefile.target   |5 +-
 target-sparc/fop_helper.c |  394 
 target-sparc/op_helper.c  |  743 -
 target-sparc/vis_helper.c |  403 
 4 files changed, 800 insertions(+), 745 deletions(-)
 create mode 100644 target-sparc/fop_helper.c
 create mode 100644 target-sparc/vis_helper.c

diff --git a/Makefile.target b/Makefile.target
index c3074f4..8f7bdab 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -74,10 +74,11 @@ libobj-y += op_helper.o helper.o
 ifeq ($(TARGET_BASE_ARCH), i386)
 libobj-y += cpuid.o
 endif
+libobj-$(TARGET_SPARC64) += vis_helper.o
 libobj-$(CONFIG_NEED_MMU) += mmu.o
 libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
 ifeq ($(TARGET_BASE_ARCH), sparc)
-libobj-y += int_helper.o cpu_init.o
+libobj-y += int_helper.o fop_helper.o cpu_init.o
 endif

 libobj-y += disas.o
@@ -94,7 +95,7 @@ tcg/tcg.o: cpu.h

 # HELPER_CFLAGS is used for all the code compiled with static register
 # variables
-op_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
+op_helper.o fop_helper.o vis_helper.o user-exec.o: QEMU_CFLAGS +=
$(HELPER_CFLAGS)

 # Note: this is a workaround. The real fix is to avoid compiling
 # cpu_signal_handler() in user-exec.c.
diff --git a/target-sparc/fop_helper.c b/target-sparc/fop_helper.c
new file mode 100644
index 000..ddd0af9
--- /dev/null
+++ b/target-sparc/fop_helper.c
@@ -0,0 +1,394 @@
+/*
+ * FPU op helpers
+ *
+ *  Copyright (c) 2003-2005 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "cpu.h"
+#include "dyngen-exec.h"
+#include "helper.h"
+
+#define DT0 (env->dt0)
+#define DT1 (env->dt1)
+#define QT0 (env->qt0)
+#define QT1 (env->qt1)
+
+#define F_HELPER(name, p) void helper_f##name##p(void)
+
+#define F_BINOP(name)   \
+float32 helper_f ## name ## s (float32 src1, float32 src2)  \
+{   \
+return float32_ ## name (src1, src2, &env->fp_status);  \
+}   \
+F_HELPER(name, d)   \
+{   \
+DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
+}   \
+F_HELPER(name, q)   \
+{   \
+QT0 = float128_ ## name (QT0, QT1, &env->fp_status);\
+}
+
+F_BINOP(add);
+F_BINOP(sub);
+F_BINOP(mul);
+F_BINOP(div);
+#undef F_BINOP
+
+void helper_fsmuld(float32 src1, float32 src2)
+{
+DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
+  float32_to_float64(src2, &env->fp_status),
+  &env->fp_status);
+}
+
+void helper_fdmulq(void)
+{
+QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
+   float64_to_float128(DT1, &env->fp_status),
+   &env->fp_status);
+}
+
+float32 helper_fnegs(float32 src)
+{
+return float32_chs(src);
+}
+
+#ifdef TARGET_SPARC64
+F_HELPER(neg, d)
+{
+DT0 = float64_chs(DT1);
+}
+
+F_HELPER(neg, q)
+{
+QT0 = float128_chs(QT1);
+}
+#endif
+
+/* Integer to float conversion.  */
+float32 helper_fitos(int32_t src)
+{
+return int32_to_float32(src, &env->fp_status);
+}
+
+void helper_fitod(int32_t src)
+{
+DT0 = int32_to_float64(src, &env->fp_status);
+}
+
+void helper_fitoq(int32_t src)
+{
+QT0 = int32_to_float128(src, &env->fp_status);
+}
+
+#ifdef TARGET_SPARC64
+float32 helper_fxtos(void)
+{
+return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
+}
+
+F_HELPER(xto, d)
+{
+DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
+}
+
+F_HELPER(xto, q)
+{
+QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
+}
+#endif
+#undef F_HELPER
+
+/* floating point conversion */
+float32 helper_fdtos(void)
+{
+return float64_to_float32(DT1, &env->fp_status);
+}
+
+void helper_fstod(float32 src)
+{
+DT0 = float32_to_float64(src, &env->fp_status);
+}
+
+float32 helper_fqtos

[Qemu-devel] [PATCH 13/15] Sparc: avoid AREG0 for division op helpers

[Blue Swirl]

Make [su]div{,cc} helpers take a parameter for CPUState instead
of relying on global env. Move the functions to helper.c.

Signed-off-by: Blue Swirl 
---
 target-sparc/helper.c|   76 ++
 target-sparc/helper.h|8 ++--
 target-sparc/op_helper.c |   74 
 target-sparc/translate.c |   12 +--
 4 files changed, 88 insertions(+), 82 deletions(-)

diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 7a25605..5f8cf31 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -919,3 +919,79 @@ void helper_tick_set_limit(void *opaque, uint64_t limit)
 #endif
 }
 #endif
+
+static target_ulong helper_udiv_common(CPUState *env, target_ulong a,
+   target_ulong b, int cc)
+{
+int overflow = 0;
+uint64_t x0;
+uint32_t x1;
+
+x0 = (a & 0x) | ((int64_t) (env->y) << 32);
+x1 = (b & 0x);
+
+if (x1 == 0) {
+helper_raise_exception(env, TT_DIV_ZERO);
+}
+
+x0 = x0 / x1;
+if (x0 > 0x) {
+x0 = 0x;
+overflow = 1;
+}
+
+if (cc) {
+env->cc_dst = x0;
+env->cc_src2 = overflow;
+env->cc_op = CC_OP_DIV;
+}
+return x0;
+}
+
+target_ulong helper_udiv(CPUState *env, target_ulong a, target_ulong b)
+{
+return helper_udiv_common(env, a, b, 0);
+}
+
+target_ulong helper_udiv_cc(CPUState *env, target_ulong a, target_ulong b)
+{
+return helper_udiv_common(env, a, b, 1);
+}
+
+static target_ulong helper_sdiv_common(CPUState *env, target_ulong a,
+   target_ulong b, int cc)
+{
+int overflow = 0;
+int64_t x0;
+int32_t x1;
+
+x0 = (a & 0x) | ((int64_t) (env->y) << 32);
+x1 = (b & 0x);
+
+if (x1 == 0) {
+helper_raise_exception(env, TT_DIV_ZERO);
+}
+
+x0 = x0 / x1;
+if ((int32_t) x0 != x0) {
+x0 = x0 < 0 ? 0x8000 : 0x7fff;
+overflow = 1;
+}
+
+if (cc) {
+env->cc_dst = x0;
+env->cc_src2 = overflow;
+env->cc_op = CC_OP_DIV;
+}
+return x0;
+}
+
+target_ulong helper_sdiv(CPUState *env, target_ulong a, target_ulong b)
+{
+return helper_sdiv_common(env, a, b, 0);
+}
+
+target_ulong helper_sdiv_cc(CPUState *env, target_ulong a, target_ulong b)
+{
+return helper_sdiv_common(env, a, b, 1);
+}
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index 943b4ba..615ddef 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -35,10 +35,10 @@ DEF_HELPER_2(check_align, void, tl, i32)
 DEF_HELPER_1(debug, void, env)
 DEF_HELPER_1(save, void, env)
 DEF_HELPER_1(restore, void, env)
-DEF_HELPER_2(udiv, tl, tl, tl)
-DEF_HELPER_2(udiv_cc, tl, tl, tl)
-DEF_HELPER_2(sdiv, tl, tl, tl)
-DEF_HELPER_2(sdiv_cc, tl, tl, tl)
+DEF_HELPER_3(udiv, tl, env, tl, tl)
+DEF_HELPER_3(udiv_cc, tl, env, tl, tl)
+DEF_HELPER_3(sdiv, tl, env, tl, tl)
+DEF_HELPER_3(sdiv_cc, tl, env, tl, tl)
 DEF_HELPER_2(stdf, void, tl, int)
 DEF_HELPER_2(lddf, void, tl, int)
 DEF_HELPER_2(ldqf, void, tl, int)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 0aec548..e54b71f 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -2195,80 +2195,6 @@ target_ulong helper_casx_asi(target_ulong addr,
target_ulong val1,
 }
 #endif /* TARGET_SPARC64 */

-static target_ulong helper_udiv_common(target_ulong a, target_ulong b, int cc)
-{
-int overflow = 0;
-uint64_t x0;
-uint32_t x1;
-
-x0 = (a & 0x) | ((int64_t) (env->y) << 32);
-x1 = (b & 0x);
-
-if (x1 == 0) {
-helper_raise_exception(env, TT_DIV_ZERO);
-}
-
-x0 = x0 / x1;
-if (x0 > 0x) {
-x0 = 0x;
-overflow = 1;
-}
-
-if (cc) {
-env->cc_dst = x0;
-env->cc_src2 = overflow;
-env->cc_op = CC_OP_DIV;
-}
-return x0;
-}
-
-target_ulong helper_udiv(target_ulong a, target_ulong b)
-{
-return helper_udiv_common(a, b, 0);
-}
-
-target_ulong helper_udiv_cc(target_ulong a, target_ulong b)
-{
-return helper_udiv_common(a, b, 1);
-}
-
-static target_ulong helper_sdiv_common(target_ulong a, target_ulong b, int cc)
-{
-int overflow = 0;
-int64_t x0;
-int32_t x1;
-
-x0 = (a & 0x) | ((int64_t) (env->y) << 32);
-x1 = (b & 0x);
-
-if (x1 == 0) {
-helper_raise_exception(env, TT_DIV_ZERO);
-}
-
-x0 = x0 / x1;
-if ((int32_t) x0 != x0) {
-x0 = x0 < 0 ? 0x8000 : 0x7fff;
-overflow = 1;
-}
-
-if (cc) {
-env->cc_dst = x0;
-env->cc_src2 = overflow;
-env->cc_op = CC_OP_DIV;
-}
-return x0;
-}
-
-target_ulong helper_sdiv(target_ulong a, target_ulong b)
-{
-return helper_sdiv_common(a, b, 0);
-}
-
-target_ulong helper_sdiv_cc(target_ulong a, target_ulong b)
-{
-return helper_sdiv_common(a, b, 1);
-}
-
 void helper_stdf(tar

[Qemu-devel] [PATCH 11/15] Sparc: avoid AREG0 for CWP and PSTATE helpers

[Blue Swirl]

Make CWP and PSTATE helpers take a parameter for CPUState instead
of relying on global env. Move the functions to helper.c, remove
wrapper functions.

Signed-off-by: Blue Swirl 
---
 Makefile.target   |2 +-
 target-sparc/helper.h |   32 +++---
 target-sparc/translate.c  |   34 
 target-sparc/win_helper.c |  223 +++-
 4 files changed, 90 insertions(+), 201 deletions(-)

diff --git a/Makefile.target b/Makefile.target
index 01062ad..d8d5543 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -95,7 +95,7 @@ tcg/tcg.o: cpu.h

 # HELPER_CFLAGS is used for all the code compiled with static register
 # variables
-op_helper.o win_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
+op_helper.o user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)

 # Note: this is a workaround. The real fix is to avoid compiling
 # cpu_signal_handler() in user-exec.c.
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index 57d0073..b18cbc6 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -1,21 +1,21 @@
 #include "def-helper.h"

 #ifndef TARGET_SPARC64
-DEF_HELPER_0(rett, void)
-DEF_HELPER_1(wrpsr, void, tl)
-DEF_HELPER_0(rdpsr, tl)
+DEF_HELPER_1(rett, void, env)
+DEF_HELPER_2(wrpsr, void, env, tl)
+DEF_HELPER_1(rdpsr, tl, env)
 #else
-DEF_HELPER_1(wrpil, void, tl)
-DEF_HELPER_1(wrpstate, void, tl)
-DEF_HELPER_0(done, void)
-DEF_HELPER_0(retry, void)
-DEF_HELPER_0(flushw, void)
-DEF_HELPER_0(saved, void)
-DEF_HELPER_0(restored, void)
-DEF_HELPER_0(rdccr, tl)
-DEF_HELPER_1(wrccr, void, tl)
-DEF_HELPER_0(rdcwp, tl)
-DEF_HELPER_1(wrcwp, void, tl)
+DEF_HELPER_2(wrpil, void, env, tl)
+DEF_HELPER_2(wrpstate, void, env, tl)
+DEF_HELPER_1(done, void, env)
+DEF_HELPER_1(retry, void, env)
+DEF_HELPER_1(flushw, void, env)
+DEF_HELPER_1(saved, void, env)
+DEF_HELPER_1(restored, void, env)
+DEF_HELPER_1(rdccr, tl, env)
+DEF_HELPER_2(wrccr, void, env, tl)
+DEF_HELPER_1(rdcwp, tl, env)
+DEF_HELPER_2(wrcwp, void, env, tl)
 DEF_HELPER_3(array8, tl, env, tl, tl)
 DEF_HELPER_3(alignaddr, tl, env, tl, tl)
 DEF_HELPER_1(popc, tl, tl)
@@ -33,8 +33,8 @@ DEF_HELPER_2(tick_set_limit, void, ptr, i64)
 #endif
 DEF_HELPER_2(check_align, void, tl, i32)
 DEF_HELPER_1(debug, void, env)
-DEF_HELPER_0(save, void)
-DEF_HELPER_0(restore, void)
+DEF_HELPER_1(save, void, env)
+DEF_HELPER_1(restore, void, env)
 DEF_HELPER_2(udiv, tl, tl, tl)
 DEF_HELPER_2(udiv_cc, tl, tl, tl)
 DEF_HELPER_2(sdiv, tl, tl, tl)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 214252a..1f6d7fb 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2107,7 +2107,7 @@ static void disas_sparc_insn(DisasContext * dc)
 #ifdef TARGET_SPARC64
 case 0x2: /* V9 rdccr */
 gen_helper_compute_psr(cpu_env);
-gen_helper_rdccr(cpu_dst);
+gen_helper_rdccr(cpu_dst, cpu_env);
 gen_movl_TN_reg(rd, cpu_dst);
 break;
 case 0x3: /* V9 rdasi */
@@ -2184,7 +2184,7 @@ static void disas_sparc_insn(DisasContext * dc)
 goto priv_insn;
 gen_helper_compute_psr(cpu_env);
 dc->cc_op = CC_OP_FLAGS;
-gen_helper_rdpsr(cpu_dst);
+gen_helper_rdpsr(cpu_dst, cpu_env);
 #else
 CHECK_IU_FEATURE(dc, HYPV);
 if (!hypervisor(dc))
@@ -2297,7 +2297,7 @@ static void disas_sparc_insn(DisasContext * dc)
 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
 break;
 case 9: // cwp
-gen_helper_rdcwp(cpu_tmp0);
+gen_helper_rdcwp(cpu_tmp0, cpu_env);
 break;
 case 10: // cansave
 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
@@ -2351,7 +2351,7 @@ static void disas_sparc_insn(DisasContext * dc)
 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
 #ifdef TARGET_SPARC64
 save_state(dc, cpu_cond);
-gen_helper_flushw();
+gen_helper_flushw(cpu_env);
 #else
 if (!supervisor(dc))
 goto priv_insn;
@@ -3379,7 +3379,7 @@ static void disas_sparc_insn(DisasContext * dc)
 #else
 case 0x2: /* V9 wrccr */
 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
-gen_helper_wrccr(cpu_dst);
+gen_helper_wrccr(cpu_env, cpu_dst);
 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
 dc->cc_op = CC_OP_FLAGS;
 break;
@@ -3499,10 +3499,10 @@ static void disas_sparc_insn(DisasContext * dc)
 #ifdef TARGET_SPARC64
 switch (rd) {
 case 0:
-gen_helper_saved();
+gen_helper_sav

[Qemu-devel] AHCI Port Interrupt Enable register cleaning on soft reset

[Alexander Motin]

Hi.

I've found that FreeBSD AHCI driver doesn't work with AHCI hardware
emulation of QEMU 0.15.0. I believe the problem is on QEMU's side. As I
see, it clears port's Interrupt Enable register each time when reset of
any level happens. Is is reasonable for the global controller reset. It
is probably not good, but acceptable for FreeBSD driver for the port
hard reset. But it is IMO wrong for the device soft reset. None of real
hardware I know behaves that way.

This patch fixes the problem for me:
http://people.freebsd.org/~mav/qemu.ahci.patch

-- 
Alexander Motin

Re: [Qemu-devel] About hotplug multifunction

[Marcelo Tosatti]

On Sun, Sep 11, 2011 at 12:23:57PM +0300, Michael S. Tsirkin wrote:
> On Fri, Sep 09, 2011 at 03:34:26PM -0300, Marcelo Tosatti wrote:
> > > > something I noted when readin our acpi code:
> > > > we currently pass eject request for function 0 only:
> > > >Name (_ADR, nr##)
> > > > We either need a device per function there (acpi 1.0),
> > > > send eject request for them all, or use 
> > > > as function number (newer acpi, not sure which version).
> > > > Need to see which guests (windows,linux) can handle which form.
> > > 
> > > I'd guess we need to change that to .
> > 
> > No need, only make sure function 0 is there and all other functions
> > should be removed automatically by the guest on eject notification.
> 
> Hmm, the ACPI spec explicitly says:
> 
> High word = Device #, Low word = Function #.
> (e.g., device 3, function 2 is 0x00030002). To refer
> to all the functions on a device #, use a function
> number of ).

Right, but this is the _ADR of the device instance in ACPI. 
The communication between QEMU and the ACPI DSL code is all 
based in slots.

> > ACPI PCI hotplug is based on slots, not on functions. It does not
> > support addition/removal of individual functions.
> 
> Interesting. Is this just based on general logic,
> reading of the linux driver or the ACPI spec?

Its based on Seabios ACPI DST implementation and its relationship with
the QEMU implementation in acpi_piix4.c.

> The ACPI spec itself seems pretty vague. All tables
> list devices, where each device has an _ADR entry,
> which is built up of PCI device # and function #.

Yes, it is vague. Given the mandate from the PCI spec a device _must
contain_ function 0, usage (including hotplug/unplug) of individual
functions other than 0 as separate devices is a no-go.

Re: [Qemu-devel] unable to access the serial port on the Vm

[Stefan Hajnoczi]

On Sun, Sep 11, 2011 at 4:17 PM, bala suru  wrote:
> Hi,
> I'm not checking through the Qenu command line . I'm checking from the VM
> itself .
>
> How to check for the  Qemu Command ..?

Please keep qemu-devel@nongnu.org CCed so others can contribute to the
discussion.

With "QEMU command-line" I meant running "ps aux | grep qemu" on the
host to check what command-line the qemu or qemu-kvm program has been
invoked with.  This will include the -serial or -chardev options which
controls how the emulated serial port is made available on the host.

Normally the emulated serial port can be redirected to your current
terminal by launching qemu with "-serial stdio".

Stefan

[Qemu-devel] [PATCH] pkg-config: Add a pkg-config script for cross compilations

[Stefan Weil]

This script can be used for cross compilations.
I use it on Debian / Ubuntu to provide a cross pkg-config
for MinGW (32 and 64 bit), ARM, MIPS and PowerPC.

Signed-off-by: Stefan Weil 
---
 scripts/cross-pkg-config |   22 ++
 1 files changed, 22 insertions(+), 0 deletions(-)
 create mode 100755 scripts/cross-pkg-config

diff --git a/scripts/cross-pkg-config b/scripts/cross-pkg-config
new file mode 100755
index 000..a5f839b
--- /dev/null
+++ b/scripts/cross-pkg-config
@@ -0,0 +1,22 @@
+#!/bin/sh
+
+# This script provides a cross pkg-config for QEMU cross compilations.
+# It will use the standard pkg-config with special options for the
+# cross environment which is assumed to be in /usr/{cross-prefix}.
+
+# Installation (Debian and similar distributions):
+# Simply copy or link it to /usr/bin/{cross-prefix}-pkg-config.
+
+# Examples (Debian, Ubuntu):
+# /usr/bin/amd64-mingw32msvc-pkg-config
+# /usr/bin/i586-mingw32msvc-pkg-config
+# /usr/bin/arm-linux-gnueabi-pkg-config
+# /usr/bin/mipsel-linux-gnu-pkg-config
+
+basename=`basename $0`
+prefix=/usr/`echo $basename|sed s/-pkg-config//`
+PKG_CONFIG_LIBDIR=$prefix/lib/pkgconfig
+export PKG_CONFIG_LIBDIR
+exec pkg-config --define-variable=prefix=$prefix $@
+
+# end
-- 
1.7.2.5

[Qemu-devel] [PATCH 0/4] Trace conversion

[Blue Swirl]

This patch set depends on the previous Sparc set.

Now that some op helpers are regular code, the DPRINTFs can be
converted to traceponts.

Convert also ESP while in the mood.

Blue Swirl (4):
  Sparc: convert mmu_helper to trace framework
  Sparc: convert int_helper to trace framework
  Sparc: convert win_helper to trace framework
  ESP: convert to trace framework

 hw/esp.c  |   70 +++-
 target-sparc/int_helper.c |   41 +
 target-sparc/mmu_helper.c |   64 +
 target-sparc/win_helper.c |   30 +--
 trace-events  |   56 
 5 files changed, 129 insertions(+), 132 deletions(-)

[Qemu-devel] [PATCH 1/4] Sparc: convert mmu_helper to trace framework

[Blue Swirl]

Signed-off-by: Blue Swirl 
---
 target-sparc/mmu_helper.c |   64 ++---
 trace-events  |   10 +++
 2 files changed, 30 insertions(+), 44 deletions(-)

diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 5743081..8cdc224 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -18,15 +18,7 @@
  */

 #include "cpu.h"
-
-//#define DEBUG_MMU
-
-#ifdef DEBUG_MMU
-#define DPRINTF_MMU(fmt, ...)   \
-do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF_MMU(fmt, ...) do {} while (0)
-#endif
+#include "trace.h"

 /* Sparc MMU emulation */

@@ -538,10 +530,7 @@ static int get_physical_address_data(CPUState *env,
 if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
 do_fault = 1;
 sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
-
-DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64
-" mmu_idx=%d tl=%d\n",
-address, context, mmu_idx, env->tl);
+trace_mmu_helper_dfault(address, context, mmu_idx, env->tl);
 }
 if (rw == 4) {
 if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) {
@@ -562,9 +551,7 @@ static int get_physical_address_data(CPUState *env,
 do_fault = 1;
 env->exception_index = TT_DPROT;

-DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64
-" mmu_idx=%d tl=%d\n",
-address, context, mmu_idx, env->tl);
+trace_mmu_helper_dprot(address, context, mmu_idx, env->tl);
 }

 if (!do_fault) {
@@ -598,8 +585,7 @@ static int get_physical_address_data(CPUState *env,
 }
 }

-DPRINTF_MMU("DMISS at %" PRIx64 " context %" PRIx64 "\n",
-address, context);
+trace_mmu_helper_dmiss(address, context);

 /*
  * On MMU misses:
@@ -662,8 +648,7 @@ static int get_physical_address_code(CPUState *env,

 env->immu.tag_access = (address & ~0x1fffULL) | context;

-DPRINTF_MMU("TFAULT at %" PRIx64 " context %" PRIx64 "\n",
-address, context);
+trace_mmu_helper_tfault(address, context);

 return 1;
 }
@@ -673,8 +658,7 @@ static int get_physical_address_code(CPUState *env,
 }
 }

-DPRINTF_MMU("TMISS at %" PRIx64 " context %" PRIx64 "\n",
-address, context);
+trace_mmu_helper_tmiss(address, context);

 /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
 env->immu.tag_access = (address & ~0x1fffULL) | context;
@@ -691,21 +675,20 @@ static int get_physical_address(CPUState *env,
target_phys_addr_t *physical,
everything when an entry is evicted.  */
 *page_size = TARGET_PAGE_SIZE;

-#if defined(DEBUG_MMU)
 /* safety net to catch wrong softmmu index use from dynamic code */
 if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
-DPRINTF_MMU("get_physical_address %s tl=%d mmu_idx=%d"
-" primary context=%" PRIx64
-" secondary context=%" PRIx64
-" address=%" PRIx64
-"\n",
-(rw == 2 ? "CODE" : "DATA"),
-env->tl, mmu_idx,
-env->dmmu.mmu_primary_context,
-env->dmmu.mmu_secondary_context,
-address);
+if (rw == 2) {
+trace_mmu_helper_get_phys_addr_code(env->tl, mmu_idx,
+env->dmmu.mmu_primary_context,
+
env->dmmu.mmu_secondary_context,
+address);
+} else {
+trace_mmu_helper_get_phys_addr_data(env->tl, mmu_idx,
+env->dmmu.mmu_primary_context,
+
env->dmmu.mmu_secondary_context,
+address);
+}
 }
-#endif

 if (rw == 2) {
 return get_physical_address_code(env, physical, prot, address,
@@ -732,16 +715,9 @@ int cpu_sparc_handle_mmu_fault(CPUState *env,
target_ulong address, int rw,
 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
  (TARGET_PAGE_SIZE - 1));

-DPRINTF_MMU("Translate at %" PRIx64 " -> %" PRIx64 ","
-" vaddr %" PRIx64
-" mmu_idx=%d"
-" tl=%d"
-" primary context=%" PRIx64
-" secondary context=%" PRIx64
-"\n",
-address, paddr, vaddr, mmu_idx, env->tl,
-env->dmmu.mmu_primary_context,
-env->dmmu.mmu_secondary_context);
+trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl,
+   env->dmmu.mmu_primary_context,
+ 

[Qemu-devel] [PATCH 2/4] Sparc: convert int_helper to trace framework

[Blue Swirl]

Signed-off-by: Blue Swirl 
---
 target-sparc/int_helper.c |   41 +++--
 trace-events  |7 +++
 2 files changed, 22 insertions(+), 26 deletions(-)

diff --git a/target-sparc/int_helper.c b/target-sparc/int_helper.c
index 3361eed..76a3fdb 100644
--- a/target-sparc/int_helper.c
+++ b/target-sparc/int_helper.c
@@ -19,24 +19,9 @@

 #include "cpu.h"
 #include "helper.h"
+#include "trace.h"

 //#define DEBUG_PCALL
-//#define DEBUG_PSTATE
-//#define DEBUG_CACHE_CONTROL
-
-#ifdef DEBUG_PSTATE
-#define DPRINTF_PSTATE(fmt, ...)\
-do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
-#endif
-
-#ifdef DEBUG_CACHE_CONTROL
-#define DPRINTF_CACHE_CONTROL(fmt, ...) \
-do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
-#endif

 #ifdef TARGET_SPARC64
 #ifdef DEBUG_PCALL
@@ -286,35 +271,39 @@ trap_state *cpu_tsptr(CPUState* env)
 return &env->ts[env->tl & MAXTL_MASK];
 }

-static void do_modify_softint(CPUState *env, const char *operation,
-  uint32_t value)
+static bool do_modify_softint(CPUState *env, uint32_t value)
 {
 if (env->softint != value) {
 env->softint = value;
-DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
 #if !defined(CONFIG_USER_ONLY)
 if (cpu_interrupts_enabled(env)) {
 cpu_check_irqs(env);
 }
 #endif
+return true;
 }
+return false;
 }

 void helper_set_softint(CPUState *env, uint64_t value)
 {
-do_modify_softint(env, "helper_set_softint",
-  env->softint | (uint32_t)value);
+if (do_modify_softint(env, env->softint | (uint32_t)value)) {
+trace_int_helper_set_softint(env->softint);
+}
 }

 void helper_clear_softint(CPUState *env, uint64_t value)
 {
-do_modify_softint(env, "helper_clear_softint",
-  env->softint & (uint32_t)~value);
+if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
+trace_int_helper_clear_softint(env->softint);
+}
 }

 void helper_write_softint(CPUState *env, uint64_t value)
 {
-do_modify_softint(env, "helper_write_softint", (uint32_t)value);
+if (do_modify_softint(env, (uint32_t)value)) {
+trace_int_helper_write_softint(env->softint);
+}
 }
 #else
 #if !defined(CONFIG_USER_ONLY)
@@ -327,7 +316,7 @@ static void leon3_cache_control_int(CPUState *env)
 state = env->cache_control & CACHE_STATE_MASK;
 if (state == CACHE_ENABLED) {
 state = CACHE_FROZEN;
-DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
+trace_int_helper_icache_freeze();
 }

 env->cache_control &= ~CACHE_STATE_MASK;
@@ -339,7 +328,7 @@ static void leon3_cache_control_int(CPUState *env)
 state = (env->cache_control >> 2) & CACHE_STATE_MASK;
 if (state == CACHE_ENABLED) {
 state = CACHE_FROZEN;
-DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
+trace_int_helper_dcache_freeze();
 }

 env->cache_control &= ~(CACHE_STATE_MASK << 2);
diff --git a/trace-events b/trace-events
index 99a6c30..b360487 100644
--- a/trace-events
+++ b/trace-events
@@ -511,3 +511,10 @@ mmu_helper_tmiss(uint64_t address, uint64_t
context) "TMISS at %"PRIx64" context
 mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t
prim_context, uint64_t sec_context, uint64_t address) "tl=%d
mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64"
address=%"PRIx64
 mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t
prim_context, uint64_t sec_context, uint64_t address) "tl=%d
mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64"
address=%"PRIx64
 mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx,
uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate
at %"PRIx64" -> %"PRIx64", mmu_idx=%d tl=%d primary context=%"PRIx64"
secondary context=%"PRIx64
+
+# target-sparc/int_helper.c
+int_helper_set_softint(uint32_t softint) "new %08x"
+int_helper_clear_softint(uint32_t softint) "new %08x"
+int_helper_write_softint(uint32_t softint) "new %08x"
+int_helper_icache_freeze(void) "Instruction cache: freeze"
+int_helper_dcache_freeze(void) "Data cache: freeze"
-- 
1.6.2.4

[Qemu-devel] [PATCH 3/4] Sparc: convert win_helper to trace framework

[Blue Swirl]

Signed-off-by: Blue Swirl 
---
 target-sparc/win_helper.c |   30 --
 trace-events  |8 
 2 files changed, 16 insertions(+), 22 deletions(-)

diff --git a/target-sparc/win_helper.c b/target-sparc/win_helper.c
index f42d996..a68c649 100644
--- a/target-sparc/win_helper.c
+++ b/target-sparc/win_helper.c
@@ -19,15 +19,7 @@

 #include "cpu.h"
 #include "helper.h"
-
-//#define DEBUG_PSTATE
-
-#ifdef DEBUG_PSTATE
-#define DPRINTF_PSTATE(fmt, ...)\
-do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
-#endif
+#include "trace.h"

 static inline void memcpy32(target_ulong *dst, const target_ulong *src)
 {
@@ -293,11 +285,7 @@ static inline uint64_t *get_gregset(CPUState
*env, uint32_t pstate)
 {
 switch (pstate) {
 default:
-DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
-   pstate,
-   (pstate & PS_IG) ? " IG" : "",
-   (pstate & PS_MG) ? " MG" : "",
-   (pstate & PS_AG) ? " AG" : "");
+trace_win_helper_gregset_error(pstate);
 /* pass through to normal set of global registers */
 case 0:
 return env->bgregs;
@@ -324,16 +312,15 @@ void cpu_change_pstate(CPUState *env, uint32_t new_pstate)
 new_pstate_regs = new_pstate & 0xc01;

 if (new_pstate_regs != pstate_regs) {
-DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
-   pstate_regs, new_pstate_regs);
+trace_win_helper_switch_pstate(pstate_regs, new_pstate_regs);
+
 /* Switch global register bank */
 src = get_gregset(env, new_pstate_regs);
 dst = get_gregset(env, pstate_regs);
 memcpy32(dst, env->gregs);
 memcpy32(env->gregs, src);
 } else {
-DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
-   new_pstate_regs);
+trace_win_helper_no_switch_pstate(new_pstate_regs);
 }
 env->pstate = new_pstate;
 }
@@ -352,8 +339,7 @@ void helper_wrpstate(CPUState *env, target_ulong new_state)
 void helper_wrpil(CPUState *env, target_ulong new_pil)
 {
 #if !defined(CONFIG_USER_ONLY)
-DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
-   env->psrpil, (uint32_t)new_pil);
+trace_win_helper_wrpil(env->psrpil, (uint32_t)new_pil);

 env->psrpil = new_pil;

@@ -375,7 +361,7 @@ void helper_done(CPUState *env)
 cpu_put_cwp64(env, tsptr->tstate & 0xff);
 env->tl--;

-DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
+trace_win_helper_done(env->tl);

 #if !defined(CONFIG_USER_ONLY)
 if (cpu_interrupts_enabled(env)) {
@@ -396,7 +382,7 @@ void helper_retry(CPUState *env)
 cpu_put_cwp64(env, tsptr->tstate & 0xff);
 env->tl--;

-DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
+trace_win_helper_retry(env->tl);

 #if !defined(CONFIG_USER_ONLY)
 if (cpu_interrupts_enabled(env)) {
diff --git a/trace-events b/trace-events
index b360487..e89a30c 100644
--- a/trace-events
+++ b/trace-events
@@ -518,3 +518,11 @@ int_helper_clear_softint(uint32_t softint) "new %08x"
 int_helper_write_softint(uint32_t softint) "new %08x"
 int_helper_icache_freeze(void) "Instruction cache: freeze"
 int_helper_dcache_freeze(void) "Data cache: freeze"
+
+# target-sparc/win_helper.c
+win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset:
active pstate bits=%x"
+win_helper_switch_pstate(uint32_t pstate_regs, uint32_t
new_pstate_regs) "change_pstate: switching regs old=%x new=%x"
+win_helper_no_switch_pstate(uint32_t new_pstate_regs) "change_pstate:
regs new=%x (unchanged)"
+win_helper_wrpil(uint32_t psrpil, uint32_t new_pil) "old=%x new=%x"
+win_helper_done(uint32_t tl) "tl=%d"
+win_helper_retry(uint32_t tl) "tl=%d"
-- 
1.6.2.4

[Qemu-devel] [PATCH 4/4] ESP: convert to trace framework

[Blue Swirl]

Signed-off-by: Blue Swirl 
---
 hw/esp.c |   70 -
 trace-events |   31 +
 2 files changed, 61 insertions(+), 40 deletions(-)

diff --git a/hw/esp.c b/hw/esp.c
index ca41f80..697c2c5 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -25,9 +25,7 @@
 #include "sysbus.h"
 #include "scsi.h"
 #include "esp.h"
-
-/* debug ESP card */
-//#define DEBUG_ESP
+#include "trace.h"

 /*
  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
@@ -37,13 +35,6 @@
  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  */

-#ifdef DEBUG_ESP
-#define DPRINTF(fmt, ...)   \
-do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...) do {} while (0)
-#endif
-
 #define ESP_ERROR(fmt, ...) \
 do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)

@@ -158,7 +149,7 @@ static void esp_raise_irq(ESPState *s)
 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
 s->rregs[ESP_RSTAT] |= STAT_INT;
 qemu_irq_raise(s->irq);
-DPRINTF("Raise IRQ\n");
+trace_esp_raise_irq();
 }
 }

@@ -167,7 +158,7 @@ static void esp_lower_irq(ESPState *s)
 if (s->rregs[ESP_RSTAT] & STAT_INT) {
 s->rregs[ESP_RSTAT] &= ~STAT_INT;
 qemu_irq_lower(s->irq);
-DPRINTF("Lower IRQ\n");
+trace_esp_lower_irq();
 }
 }

@@ -178,13 +169,13 @@ static void esp_dma_enable(void *opaque, int
irq, int level)

 if (level) {
 s->dma_enabled = 1;
-DPRINTF("Raise enable\n");
+trace_esp_dma_enable();
 if (s->dma_cb) {
 s->dma_cb(s);
 s->dma_cb = NULL;
 }
 } else {
-DPRINTF("Lower enable\n");
+trace_esp_dma_disable();
 s->dma_enabled = 0;
 }
 }
@@ -214,7 +205,7 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf)
 memcpy(buf, s->ti_buf, dmalen);
 buf[0] = buf[2] >> 5;
 }
-DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
+trace_esp_get_cmd(dmalen, target);

 s->ti_size = 0;
 s->ti_rptr = 0;
@@ -243,7 +234,7 @@ static void do_busid_cmd(ESPState *s, uint8_t
*buf, uint8_t busid)
 int32_t datalen;
 int lun;

-DPRINTF("do_busid_cmd: busid 0x%x\n", busid);
+trace_esp_do_busid_cmd(busid);
 lun = busid & 7;
 s->current_req = scsi_req_new(s->current_dev, 0, lun, buf, NULL);
 datalen = scsi_req_enqueue(s->current_req);
@@ -308,7 +299,7 @@ static void handle_satn_stop(ESPState *s)
 }
 s->cmdlen = get_cmd(s, s->cmdbuf);
 if (s->cmdlen) {
-DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
+trace_esp_handle_satn_stop(s->cmdlen);
 s->do_cmd = 1;
 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
@@ -319,7 +310,7 @@ static void handle_satn_stop(ESPState *s)

 static void write_response(ESPState *s)
 {
-DPRINTF("Transfer status (status=%d)\n", s->status);
+trace_esp_write_response(s->status);
 s->ti_buf[0] = s->status;
 s->ti_buf[1] = 0;
 if (s->dma) {
@@ -355,7 +346,7 @@ static void esp_do_dma(ESPState *s)
 to_device = (s->ti_size < 0);
 len = s->dma_left;
 if (s->do_cmd) {
-DPRINTF("command len %d + %d\n", s->cmdlen, len);
+trace_esp_do_dma(s->cmdlen, len);
 s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
 s->ti_size = 0;
 s->cmdlen = 0;
@@ -400,15 +391,15 @@ static void esp_command_complete(SCSIRequest
*req, uint32_t status)
 {
 ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);

-DPRINTF("SCSI Command complete\n");
+trace_esp_command_complete();
 if (s->ti_size != 0) {
-DPRINTF("SCSI command completed unexpectedly\n");
+trace_esp_command_complete_unexpected();
 }
 s->ti_size = 0;
 s->dma_left = 0;
 s->async_len = 0;
 if (status) {
-DPRINTF("Command failed\n");
+trace_esp_command_complete_fail();
 }
 s->status = status;
 s->rregs[ESP_RSTAT] = STAT_ST;
@@ -424,7 +415,7 @@ static void esp_transfer_data(SCSIRequest *req,
uint32_t len)
 {
 ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);

-DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
+trace_esp_transfer_data(s->dma_left, s->ti_size);
 s->async_len = len;
 s->async_buf = scsi_req_get_buf(req);
 if (s->dma_left) {
@@ -452,13 +443,13 @@ static void handle_ti(ESPState *s)
 minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
 else
 minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
-DPRINTF("Transfer Information len %d\n", minlen);
+trace_esp_handle_ti(minlen);
 if (s->dma) {
 s->dma_left = minlen;
 s->rregs[ESP_RSTAT] &= ~STAT_TC;
 esp_do_dma(s);
 } else if (s->do_cmd) {
-

Re: [Qemu-devel] [PATCH V8 03/14] Add persistent state handling to TPM TIS frontend driver

[Stefan Berger]

On 09/09/2011 05:13 PM, Paul Moore wrote:

On Wednesday, August 31, 2011 10:35:54 AM Stefan Berger wrote:

Index: qemu-git/hw/tpm_tis.c
===
--- qemu-git.orig/hw/tpm_tis.c
+++ qemu-git/hw/tpm_tis.c
@@ -6,6 +6,8 @@
   * Author: Stefan Berger
   * David Safford
   *
+ * Xen 4 support: Andrease Niederl
+ *
   * This program is free software; you can redistribute it and/or
   * modify it under the terms of the GNU General Public License as
   * published by the Free Software Foundation, version 2 of the
@@ -839,3 +841,167 @@ static int tis_init(ISADevice *dev)
   err_exit:
  return -1;
  }
+
+/* persistent state handling */
+
+static void tis_pre_save(void *opaque)
+{
+TPMState *s = opaque;
+uint8_t locty = s->active_locty;

Is it safe to read s->active_locty without the state_lock?  I'm not sure at
this point but I saw it being protected by the lock elsewhere ...
It cannot change anymore since no vCPU is in the TPM TIS emulation layer 
anymore but all we're doing is wait for the last outstanding command to 
be returned to use from the TPM thread.
I don't mind putting this reading into the critical section, though, 
just to have it be consistent.



If the state_lock does not protect all of the structure, it might be nice to
add some comments in the structure declaration explaining what fields are
protected by the state_lock and which are not.


+qemu_mutex_lock(&s->state_lock);
+
+/* wait for outstanding requests to complete */
+if (IS_VALID_LOCTY(locty)&&  s->loc[locty].state == STATE_EXECUTION) {
+if (!s->be_driver->ops->job_for_main_thread) {
+qemu_cond_wait(&s->from_tpm_cond,&s->state_lock);
+} else {
+while (s->loc[locty].state == STATE_EXECUTION) {
+qemu_mutex_unlock(&s->state_lock);
+
+s->be_driver->ops->job_for_main_thread(NULL);
+usleep(1);
+
+qemu_mutex_lock(&s->state_lock);

Hmm, this may be right, but it looks dangerous to me; can the active_locty
change while the state_lock is dropped?  What about loc[locty].state?
This is correct since at this time the VM is not executing anymore, so 
no vCPU can be in the TPM TIS emulation code anymore, but we're waiting 
for the last outstanding TPM command finish processing in the TPM thread 
(to have it's response 'caught' and stored as part of the TPM TIS 
state). The locking is against the thread at this point that may change 
the .state variable, although I don't think it would be necessary to 
hold the lock there at all except for in the case where the condition is 
being waited for in the other else branch.

+}
+}
+}
+
+#ifdef DEBUG_TIS_SR
+fprintf(stderr,
+"tpm_tis: suspend: locty 0 : r_offset = %d, w_offset = %d\n",
+s->loc[0].r_offset, s->loc[0].w_offset);
+if (s->loc[0].r_offset) {
+tis_dump_state(opaque, 0);
+}
+#endif
+
+qemu_mutex_unlock(&s->state_lock);
+
+/* copy current active read or write buffer into the buffer
+   written to disk */
+if (IS_VALID_LOCTY(locty)) {
+switch (s->loc[locty].state) {

More concerns about loc[locty].state without the state_lock.

The section you are quoting here is further down in the same function 
that prepares the TPM TIS for state serialization before final 
migration/suspend. At this point we have caught the last outstanding 
response from the TPM thread and that thread will not process any more 
commands at this point (queuing of commands it not possible with TPM TIS 
but strictly sending a single request to  it, have it processed, getting 
that response -- so the thread will be idle). Also since no more vCPU is 
in the TPM TIS emulation layer the state cannot change anymore. Again, 
also here I can have the critical section extended over this area.

+case STATE_RECEPTION:
+memcpy(s->buf,
+   s->loc[locty].w_buffer.buffer,
+   MIN(sizeof(s->buf),
+   s->loc[locty].w_buffer.size));
+s->offset = s->loc[locty].w_offset;

Same thing, just different fields ...


+break;
+case STATE_COMPLETION:
+memcpy(s->buf,
+   s->loc[locty].r_buffer.buffer,
+   MIN(sizeof(s->buf),
+   s->loc[locty].r_buffer.size));
+s->offset = s->loc[locty].r_offset;

Again ...
Ok, I can move that single qemu_mutex_unlock(&s->state_lock) above to 
after the switch() though I don't think it is necessary in this case due 
the state the emulation is in. Though I agree that the code 'looks' more 
correct.

+break;
+default:
+/* leak nothing */
+memset(s->buf, 0x0, sizeof(s->buf));

Maybe?


What do you mean?
This command just makes sure that no previous response still stored in 
the TPM TIS buffer is being stored as part of the TPM TIS state 
se

[Qemu-devel] [PATCH] Add astyle option file for code formatting

[Stefan Weil]

For new C code (and maybe also for existing code), a code formatter
like Artistic Style is helpful because it can fix tabs, indentation
and other style issues.

This option file tries to set astyle options which match QEMU's
coding conventions.

The quality of astyle's code formatting depends on the astyle version
(I got best results with newer versions) and on the code which is going
to be formatted.

For some code, formatting of brackets and operators does not work well.
Fixing indentation and tabs always worked well for me.

Signed-off-by: Stefan Weil 
---
 scripts/astylerc |   16 
 1 files changed, 16 insertions(+), 0 deletions(-)
 create mode 100644 scripts/astylerc

diff --git a/scripts/astylerc b/scripts/astylerc
new file mode 100644
index 000..dcf9e3f
--- /dev/null
+++ b/scripts/astylerc
@@ -0,0 +1,16 @@
+# Artistic Style (astyle) options for qemu source code.
+
+# Usage:
+# astyle --options=scripts/astylerc {source files}
+
+# For best results, use latest astyle from http://astyle.sourceforge.net/.
+
+add-brackets
+align-pointer=name
+convert-tabs
+style=otbs
+brackets=linux
+indent=spaces=4
+pad-oper
+pad-header
+unpad-paren
-- 
1.7.2.5

Re: [Qemu-devel] [PATCH] pkg-config: Add a pkg-config script for cross compilations

[Peter Maydell]

On 11 September 2011 16:55, Stefan Weil  wrote:
> --- /dev/null
> +++ b/scripts/cross-pkg-config
> @@ -0,0 +1,22 @@
> +#!/bin/sh

Missing "-e"

> +
> +# This script provides a cross pkg-config for QEMU cross compilations.
> +# It will use the standard pkg-config with special options for the
> +# cross environment which is assumed to be in /usr/{cross-prefix}.

Missing copyright and license.

> +basename=`basename $0`

Insufficient quoting (gives wrong answer if the script is in a
path with a space in and is executed via $PATH or an absolute path).

> +prefix=/usr/`echo $basename|sed s/-pkg-config//`

You can do this with shell substring manipulation.

> +PKG_CONFIG_LIBDIR=$prefix/lib/pkgconfig

Missing quoting.

> +export PKG_CONFIG_LIBDIR

Posix allows export name=value so you can combine this with the above.

> +exec pkg-config --define-variable=prefix=$prefix $@

Missing quoting.

Try:
basename="$(basename "$0")"
prefix="/usr/${basename%-pkg-config}"
export PKG_CONFIG_LIBDIR="$prefix/lib/pkgconfig"
exec pkg-config --define-variable=prefix="$prefix" "$@"

-- PMM

Re: [Qemu-devel] [PATCH v5 00/32] target-xtensa: new target architecture

[Max Filippov]

> > This series adds support for Tensilica Xtensa target.
> > Port status: Linux for DC232B works in the qemu.
> >Not implemented xtensa options: MAC16,
> >floating point coprocessor, cache option, debug option.
> >
> > v4 ->  v5 changes:
> > - implement boolean option;
> > - fix v4 stylistical issues (underscores, comparison order, missing braces);
> > - turn WINDOWBASE_BOUND and WINDOWSTART_BIT macros into inline functions;
> > - convert sample boards to memory API.
> >
> > Git tree is available at git://jcmvbkbc.spb.ru/dumb/qemu-xtensa.git xtensa
> 
> What about adding some documentation to qemu-doc.texi?

Ok, will do it in the next round.

Thanks.
-- Max

Re: [Qemu-devel] [PATCH] pkg-config: Add a pkg-config script for cross compilations

[Paolo Bonzini]

On 09/11/2011 05:55 PM, Stefan Weil wrote:

This script can be used for cross compilations.
I use it on Debian / Ubuntu to provide a cross pkg-config
for MinGW (32 and 64 bit), ARM, MIPS and PowerPC.


I think the lack of such script is a bug in your distro.  Fedora 
provides /usr/bin/i686-pc-mingw32-pkg-config.  You should report a bug 
with Debian.


Paolo

[Qemu-devel] [PATCH v2] pkg-config: Add a pkg-config script for cross compilations

[Stefan Weil]

This script can be used for cross compilations.
I use it on Debian / Ubuntu to provide a cross pkg-config
for MinGW (32 and 64 bit), ARM, MIPS and PowerPC.

v2: Improvements as suggested by Peter Maydell.
Thanks for the review.

Signed-off-by: Stefan Weil 
---
 scripts/cross-pkg-config |   28 
 1 files changed, 28 insertions(+), 0 deletions(-)
 create mode 100755 scripts/cross-pkg-config

diff --git a/scripts/cross-pkg-config b/scripts/cross-pkg-config
new file mode 100755
index 000..8d7fe17
--- /dev/null
+++ b/scripts/cross-pkg-config
@@ -0,0 +1,28 @@
+#!/bin/sh -e
+
+# pkg-config for cross compilations
+
+# Copyright (C) 2011 Stefan Weil
+
+# This work is licensed under the terms of the GNU GPL, version 2 or later.
+# See the file COPYING in the top-level directory.
+
+# This script provides a cross pkg-config for QEMU cross compilations.
+# It will use the standard pkg-config with special options for the
+# cross environment which is assumed to be in /usr/{cross-prefix}.
+
+# Installation (Debian and similar distributions):
+# Simply copy or link it to /usr/bin/{cross-prefix}-pkg-config.
+
+# Examples (Debian, Ubuntu):
+# /usr/bin/amd64-mingw32msvc-pkg-config
+# /usr/bin/i586-mingw32msvc-pkg-config
+# /usr/bin/arm-linux-gnueabi-pkg-config
+# /usr/bin/mipsel-linux-gnu-pkg-config
+
+basename=`basename "$0"`
+prefix="/usr/${basename%-pkg-config}"
+export PKG_CONFIG_LIBDIR="$prefix/lib/pkgconfig"
+exec pkg-config --define-variable=prefix="$prefix" "$@"
+
+# end
-- 
1.7.2.5

Re: [Qemu-devel] [PATCH] pkg-config: Add a pkg-config script for cross compilations

[Stefan Weil]

Am 11.09.2011 20:25, schrieb Paolo Bonzini:

On 09/11/2011 05:55 PM, Stefan Weil wrote:

This script can be used for cross compilations.
I use it on Debian / Ubuntu to provide a cross pkg-config
for MinGW (32 and 64 bit), ARM, MIPS and PowerPC.


I think the lack of such script is a bug in your distro.  Fedora 
provides /usr/bin/i686-pc-mingw32-pkg-config.  You should report a bug 
with Debian.


Paolo


Well, Redhat has a large interest in QEMU, so I assume that Fedora
is better prepared for cross compilations than most other distributions.
Does it also provide cross glib-2.0, sdl, zlib, ...?
How does it implement cross pkg-config? As a binary compiled from source,
or as a script using native pkg-config?

Debian has only very limited cross development support.
Most cross packages I use come from Emdebian. I doubt that
they have the manpower to do more than they already do.
As far as I know, they don't provide any cross package which
needs a cross pkg-config, so the missing cross pkg-config is
not really a bug...

How about other distributions? Are there others beside Fedora
with good cross dev support? Some large embedded projects still build
their own cross toolchain instead of using precompiled binaries.
For all those which don't have a cross pkg-config, the script
saves the time and memory needed for building it.

Stefan

Re: [Qemu-devel] About hotplug multifunction

[Michael S. Tsirkin]

On Sun, Sep 11, 2011 at 12:01:49PM -0300, Marcelo Tosatti wrote:
> On Sun, Sep 11, 2011 at 12:23:57PM +0300, Michael S. Tsirkin wrote:
> > On Fri, Sep 09, 2011 at 03:34:26PM -0300, Marcelo Tosatti wrote:
> > > > > something I noted when readin our acpi code:
> > > > > we currently pass eject request for function 0 only:
> > > > >Name (_ADR, nr##)
> > > > > We either need a device per function there (acpi 1.0),
> > > > > send eject request for them all, or use 
> > > > > as function number (newer acpi, not sure which version).
> > > > > Need to see which guests (windows,linux) can handle which form.
> > > > 
> > > > I'd guess we need to change that to .
> > > 
> > > No need, only make sure function 0 is there and all other functions
> > > should be removed automatically by the guest on eject notification.
> > 
> > Hmm, the ACPI spec explicitly says:
> > 
> > High word = Device #, Low word = Function #.
> > (e.g., device 3, function 2 is 0x00030002). To refer
> > to all the functions on a device #, use a function
> > number of ).
> 
> Right, but this is the _ADR of the device instance in ACPI. 
> The communication between QEMU and the ACPI DSL code is all 
> based in slots.

It's easy to extend that if we like though.

> > > ACPI PCI hotplug is based on slots, not on functions. It does not
> > > support addition/removal of individual functions.
> > 
> > Interesting. Is this just based on general logic,
> > reading of the linux driver or the ACPI spec?
> 
> Its based on Seabios ACPI DST implementation and its relationship with
> the QEMU implementation in acpi_piix4.c.
> 
> > The ACPI spec itself seems pretty vague. All tables
> > list devices, where each device has an _ADR entry,
> > which is built up of PCI device # and function #.
> 
> Yes, it is vague. Given the mandate from the PCI spec a device _must
> contain_ function 0, usage (including hotplug/unplug) of individual
> functions other than 0 as separate devices is a no-go.

It doesn't seem to be a big issue.
We could, for example, keep a stub function 0 around.

-- 
MST

[Qemu-devel] [PATCH] memory: simple memory tree printer

[Blue Swirl]

Add a monitor command 'info mtree' to show the memory hierarchy.

Signed-off-by: Blue Swirl 
---
Example output:
qemu-system-i386 -monitor stdio
QEMU 0.15.50 monitor - type 'help' for more information
(qemu) info mtree
memory
system addr  off  size 7fff
-pam-ram addr 000ec000 off  size 4000
-pam-ram addr 000e8000 off  size 4000
-pam-ram addr 000e4000 off  size 4000
-pam-ram addr 000e off  size 4000
-pam-ram addr 000dc000 off  size 4000
-pam-ram addr 000d8000 off  size 4000
-pam-ram addr 000d4000 off  size 4000
-pam-ram addr 000d off  size 4000
-pam-ram addr 000cc000 off  size 4000
-pam-rom addr 000c8000 off  size 4000
-pam-rom addr 000c4000 off  size 4000
-pam-rom addr 000c off  size 4000
-pam-rom addr 000f off  size 1
-smram-region addr 000a off  size 2
-pci-hole64 addr 4000 off  size 4000
-pci-hole addr 0800 off  size f800
-ram-below-4g addr  off  size 800
-apic addr fee0 off  size 10
I/O
io addr  off  size 1
-e1000-io addr c000 off  size 40
-piix-bmdma-container addr c040 off  size 10
--bmdma addr 000c off  size 4
--piix-bmdma addr 0008 off  size 4
--bmdma addr 0004 off  size 4
--piix-bmdma addr  off  size 4
-pci-conf-data addr 0cfc off  size 4
-pci-conf-idx addr 0cf8 off  size 4

Sparc
memory
system addr  off  size 7fff
-escc addr 7110 off  size 8
-escc addr 7100 off  size 8
-lance-mmio addr 78c0 off  size 4
I/O
io addr  off  size 1

Sparc64
memory
system addr  off  size 7fff
-pci-mmio addr 01ff off  size 1
--vga.chain4 addr 000a off  size 1
--isa-mmio addr 0300 off  size 80
--isa-mmio addr 0200 off  size 100
--vga.rom addr 0100 off  size 1
--vga.vram addr 0080 off  size 80
--vga-lowmem addr 01fe020a off  size 2
-apb-pci-ioport addr 01fe0200 off  size 1
-apb-pci-config addr 01fe0100 off  size 100
-apb-config addr 01fe off  size 1
I/O
io addr  off  size 1
-cmd646-bmdma addr 0700 off  size 10
--cmd646-bmdma-ioport addr 000c off  size 4
--cmd646-bmdma-bus addr 0008 off  size 4
--cmd646-bmdma-ioport addr 0004 off  size 4
--cmd646-bmdma-bus addr  off  size 4
-cmd646-cmd addr 0680 off  size 4
-cmd646-data addr 0600 off  size 8
-cmd646-cmd addr 0580 off  size 4
-cmd646-data addr 0500 off  size 8
-ne2000 addr 0400 off  size 100

PPC
memory
system addr  off  size 7fff
-vga.chain4 addr 000a off  size 1
-macio addr 8088 off  size 8
--macio-nvram addr 0006 off  size 2
--pmac-ide addr 0002 off  size 1000
--(null) addr 00016000 off  size 0
--escc-bar addr 00013000 off  size 40
--dbdma addr 8000 off  size 1000
--heathrow-pic addr  off  size 1000
-vga.rom addr 8080 off  size 1
-vga.vram addr 8000 off  size 80
-vga-lowmem addr 800a off  size 2
-escc addr 80013000 off  size 40
-pci-data-idx addr fee0 off  size 1000
-pci-conf-idx addr fec0 off  size 1000
-isa-mmio addr fe00 off  size 20
I/O
io addr  off  size 1
-cmd646-bmdma addr 0700 off  size 10
--cmd646-bmdma-ioport addr 000c off  size 4
--cmd646-bmdma-bus addr 0008 off  size 4
--cmd646-bmdma-ioport addr 0004 off  size 4
--cmd646-bmdma-bus addr  off  size 4
-cmd646-cmd addr 0680 off  size 4
-cmd646-data addr 0600 off  

Re: [Qemu-devel] AHCI Port Interrupt Enable register cleaning on soft reset

[Alexander Graf]

Am 11.09.2011 um 16:43 schrieb Alexander Motin :

> Hi.
> 
> I've found that FreeBSD AHCI driver doesn't work with AHCI hardware
> emulation of QEMU 0.15.0. I believe the problem is on QEMU's side. As I
> see, it clears port's Interrupt Enable register each time when reset of
> any level happens. Is is reasonable for the global controller reset. It
> is probably not good, but acceptable for FreeBSD driver for the port
> hard reset. But it is IMO wrong for the device soft reset. None of real
> hardware I know behaves that way.
> 
> This patch fixes the problem for me:
> http://people.freebsd.org/~mav/qemu.ahci.patch

Ah, cool! So FreeBSD works with AHCI using this patch? Please send it again as 
an inline patch (if really really hard not 100% important) and add a 
signed-off-by line (very important) to the patch.


Alex

Re: [Qemu-devel] [PATCH] qemu-doc: Remove URL which is no longer available

[Alexander Graf]

Am 10.09.2011 um 23:09 schrieb Stefan Weil :

> http://perso.magic.fr/l_indien/ was removed several years ago.
> There is obviously no mirror or any other replacement for it.

I would prefer to see the sources in a public git repo and to have ppc_rom.bin 
rebuilt from that. IIUC Andreas is already working on this.

Alex

> 
> Signed-off-by: Stefan Weil 
> ---
> qemu-doc.texi |6 +-
> 1 files changed, 1 insertions(+), 5 deletions(-)
> 
> diff --git a/qemu-doc.texi b/qemu-doc.texi
> index 31199f6..a1e86c1 100644
> --- a/qemu-doc.texi
> +++ b/qemu-doc.texi
> @@ -1493,8 +1493,7 @@ PREP Non Volatile RAM
> PC compatible keyboard and mouse.
> @end itemize
> 
> -QEMU uses the Open Hack'Ware Open Firmware Compatible BIOS available at
> -@url{http://perso.magic.fr/l_indien/OpenHackWare/index.htm}.
> +QEMU uses the Open Hack'Ware Open Firmware Compatible BIOS.
> 
> Since version 0.9.1, QEMU uses OpenBIOS @url{http://www.openbios.org/}
> for the g3beige and mac99 PowerMac machines. OpenBIOS is a free (GPL
> @@ -1528,9 +1527,6 @@ These variables are not used by Open Hack'Ware.
> @c man end
> 
> 
> -More information is available at
> -@url{http://perso.magic.fr/l_indien/qemu-ppc/}.
> -
> @node Sparc32 System emulator
> @section Sparc32 System emulator
> @cindex system emulation (Sparc32)
> -- 
> 1.7.2.5
> 
> 

Re: [Qemu-devel] [PATCH] qemu-doc: Remove URL which is no longer available

[Andreas Färber]

Am 11.09.2011 um 22:39 schrieb Alexander Graf:


Am 10.09.2011 um 23:09 schrieb Stefan Weil :


http://perso.magic.fr/l_indien/ was removed several years ago.
There is obviously no mirror or any other replacement for it.


I would prefer to see the sources in a public git repo and to have  
ppc_rom.bin rebuilt from that. IIUC Andreas is already working on  
this.


Yes, I set up http://repo.or.cz/w/openhackware.git today.

We'll look into the build and the patches referenced by Blue over the  
next days.


@Stefan H.: Please disregard this patch, I intend to supply an  
alternative one. If we urgently need to apply a change, we should at  
least keep the URL where it was formerly accessible, so that the  
interested reader has a chance to look it up in the Internet Archive.


Andreas

[Qemu-devel] Re-playable trace!

[shbi shb]

Hi,

Is it possible to get a re-playable trace (memory snapshot) in Qemu? Do you
have any idea for adding this functionality to Qemu?
I need to get a trace of execution in the guest OS, do some modification on
the trace and run it again.

My problem is that two execution trace of a program may not be the same. So,
I would need one trace which I can run it in Qemu again. Do you have any
clue?


Thank you,

Re: [Qemu-devel] [PATCH 0/2] improve qemu-img conversion performance

[Sage Weil]

On Fri, 9 Sep 2011, Kevin Wolf wrote:
> Am 08.09.2011 18:36, schrieb Sage Weil:
> > On Thu, 8 Sep 2011, Kevin Wolf wrote:
> >> Am 08.09.2011 01:06, schrieb Yehuda Sadeh:
> >>> The following set of patches improve the qemu-img conversion process
> >>> performance. When using a higher latency backend, small writes have a
> >>> severe impact on the time it takes to do image conversion. 
> >>> We switch to using async writes, and we avoid splitting writes due to
> >>> holes when the holes are small enough.
> >>>
> >>> Yehuda Sadeh (2):
> >>>   qemu-img: async write to block device when converting image
> >>>   qemu-img: don't skip writing small holes
> >>>
> >>>  qemu-img.c |   34 +++---
> >>>  1 files changed, 27 insertions(+), 7 deletions(-)
> >>>
> >>
> >> This doesn't seem to be against git master or the block tree. Please 
> >> rebase.
> >>
> >> I think that commit a22f123c may obsolete your patch 2/2.
> > 
> > With git.kernel.org down, where should I be looking for the latest 
> > upstream?
> 
> qemu has never been on kernel.org. The interesting repositories for you are:
> 
> * Upstream: git://git.qemu.org/qemu.git master
> * Block development branch: git://repo.or.cz/qemu/kevin.git block

Oh right.  I've been working from qemu-kvm.git.  

I've done some (still minimal) testing, and it looks like the combination 
of a22f123c and the new writeback/flush stuff in librbd gets the same 
result as doing async io explicitly from qemu-img.c.  Want to take a look, 
Yehuda?  It still defaults to off, so you'll need to add 
rbd_writeback_window=800 or similar to the rbd device string.

Thanks!
sage

Re: [Qemu-devel] [PATCH 0/2] improve qemu-img conversion performance

[Yehuda Sadeh Weinraub]

On Sun, Sep 11, 2011 at 8:14 PM, Sage Weil  wrote:
> On Fri, 9 Sep 2011, Kevin Wolf wrote:
>> Am 08.09.2011 18:36, schrieb Sage Weil:
>> > On Thu, 8 Sep 2011, Kevin Wolf wrote:
>> >> Am 08.09.2011 01:06, schrieb Yehuda Sadeh:
>> >>> The following set of patches improve the qemu-img conversion process
>> >>> performance. When using a higher latency backend, small writes have a
>> >>> severe impact on the time it takes to do image conversion.
>> >>> We switch to using async writes, and we avoid splitting writes due to
>> >>> holes when the holes are small enough.
>> >>>
>> >>> Yehuda Sadeh (2):
>> >>>   qemu-img: async write to block device when converting image
>> >>>   qemu-img: don't skip writing small holes
>> >>>
>> >>>  qemu-img.c |   34 +++---
>> >>>  1 files changed, 27 insertions(+), 7 deletions(-)
>> >>>
>> >>
>> >> This doesn't seem to be against git master or the block tree. Please 
>> >> rebase.
>> >>
>> >> I think that commit a22f123c may obsolete your patch 2/2.
>> >
>> > With git.kernel.org down, where should I be looking for the latest
>> > upstream?
>>
>> qemu has never been on kernel.org. The interesting repositories for you are:
>>
>> * Upstream: git://git.qemu.org/qemu.git master
>> * Block development branch: git://repo.or.cz/qemu/kevin.git block
>
> Oh right.  I've been working from qemu-kvm.git.
>
> I've done some (still minimal) testing, and it looks like the combination
> of a22f123c and the new writeback/flush stuff in librbd gets the same
> result as doing async io explicitly from qemu-img.c.  Want to take a look,
> Yehuda?  It still defaults to off, so you'll need to add
> rbd_writeback_window=800 or similar to the rbd device string.
>

I'll take a look. I do have a rebased version for the qemu-img async
patch, and I think qemu can benefit from that anyway.

Yehuda

Re: [Qemu-devel] [PATCH] pkg-config: Add a pkg-config script for cross compilations

[Paolo Bonzini]

On 09/11/2011 08:47 PM, Stefan Weil wrote:

Well, Redhat has a large interest in QEMU, so I assume that Fedora
is better prepared for cross compilations than most other distributions.


Why are the two related? :)  Fedora's cross compilation machinery is 
indeed used by Red Hat for some virt-related stuff, but not for QEMU 
even though I used it successfully for it.  In fact, Fedora-mingw32 
started as a special interest group entirely outside Red Hat.



Does it also provide cross glib-2.0, sdl, zlib, ...?


Yes.


How does it implement cross pkg-config? As a binary compiled from source,
or as a script using native pkg-config?


It's a script doing basically

PKG_CONFIG_LIBDIR="/usr/i686-pc-mingw32/sys-root/mingw/lib/pkgconfig:/usr/i686-pc-mingw32/sys-root/mingw/share/pkgconfig" 
pkg-config "$@"



How about other distributions? Are there others beside Fedora
with good cross dev support? Some large embedded projects still build
their own cross toolchain instead of using precompiled binaries.
For all those which don't have a cross pkg-config, the script
saves the time and memory needed for building it.


Yes, I agree.  However, I still think it's better to prepare 
documentation about how to cross compile (including fetching 
dependencies etc.), and embed the script in the document.


Paolo

Re: [Qemu-devel] [PATCH 00/15] Sparc AREG0 conversion

[Paolo Bonzini]

On 09/11/2011 03:29 PM, Blue Swirl wrote:

After this patch set, only load and store op helpers remain in
op_helper.c. I have some patches for those but they need more thought.


Have you benchmarked it?

Paolo

Re: [Qemu-devel] [PATCH] memory: simple memory tree printer

[Richard Henderson]

On 09/11/2011 09:31 PM, Blue Swirl wrote:
> Field 'offset' is always zero, maybe that is not interesting. Will it
> become one day?

It's not always zero, but only used by certain devices.


r~