Re: [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values
Thiemo Seufer a écrit : > Aurelien Jarno wrote: >> Hi all, >> >> The patch below fixes the Status_rw_bitmask values for 64-bit CPUs: >> - Reverse endianess is currently not implemented, the RE bit should >> not be writable. > > OTOH, those CPUs support RE, that's why I left the bit writable. > I think you'll have to boot RiscOS to check the difference, I don't > know of any other user. :-) Ok, I see. The best would clearly to implement that. >> - 64-bit is implemented, the PX bit should be writable. > > The current version is correct, R4000 and 5K don't implement PX, the > 20Kc and later CPUs do. I don't know about R4000, but the 5K manual (from www.mips.com) clearly says that this bit is implemented. Also this bit is marked as "required" in the MIPS64 PRA manual (for both R1 and R2), and the 5K CPU is presented as a MIPS64R1 CPU. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' [EMAIL PROTECTED] | [EMAIL PROTECTED] `-people.debian.org/~aurel32 | www.aurel32.net
Re: [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values
Aurelien Jarno wrote: [snip] > >> - 64-bit is implemented, the PX bit should be writable. > > > > The current version is correct, R4000 and 5K don't implement PX, the > > 20Kc and later CPUs do. > > I don't know about R4000, but the 5K manual (from www.mips.com) clearly > says that this bit is implemented. Also this bit is marked as "required" > in the MIPS64 PRA manual (for both R1 and R2), and the 5K CPU is > presented as a MIPS64R1 CPU. Agreed for the 5K, I used too old Documentation to check this. Thiemo
[Qemu-devel] [PATCH] Fix TLS support on x86
Hi,
this patch is based on the NPTL/TLS patch, David Woodhouse sent to the
list some months ago, which unfortulately did not work for me, so these
are the fixes needed to get it working. After all there is a certain
chance, that I got something wrong but basically it does the following:
1. Implement the tg_kill syscall
2. Set the GS shadow register according to the information
set_thread_area receives. I'm not sure about that part, but using the
qemu internal functions (cpu_x86_load_seg) did not work for me.
3. Implement the "new" (2.5.xx) TID setting features of clone()
4. Use clone() for forking, since fork() did not always work for me
(especially when using TLS)
I'm open for suggestions. Using this patch all single-threaded and most
simple multi-threaded current applications (glibc 2.5) do work.
Everything bigger however does not. If anyone on this list is more into
these things, I would very much appreciate any help.
Regards,
Alexander Graf
Index: qemu-0.9.0/linux-user/i386/syscall_nr.h
===
--- qemu-0.9.0.orig/linux-user/i386/syscall_nr.h
+++ qemu-0.9.0/linux-user/i386/syscall_nr.h
@@ -271,5 +271,6 @@
#define TARGET_NR_clock_getres (TARGET_NR_timer_create+7)
#define TARGET_NR_clock_nanosleep (TARGET_NR_timer_create+8)
+#define TARGET_NR_tgkill 270
#define TARGET_NR_utimes 271
#define TARGET_NR_fadvise64_64 272
Index: qemu-0.9.0/linux-user/syscall.c
===
--- qemu-0.9.0.orig/linux-user/syscall.c
+++ qemu-0.9.0/linux-user/syscall.c
@@ -145,6 +145,8 @@ type name (type1 arg1,type2 arg2,type3 a
#define __NR_sys_rt_sigqueueinfo __NR_rt_sigqueueinfo
#define __NR_sys_syslog __NR_syslog
#define __NR_sys_fadvise64 __NR_fadvise64
+#define __NR_sys_tgkill __NR_tgkill
+#define __NR_sys_clone __NR_clone
#if defined(__alpha__) || defined (__ia64__) || defined(__x86_64__)
#define __NR__llseek __NR_lseek
@@ -166,6 +168,8 @@ _syscall5(int, _llseek, uint, fd, ulon
_syscall3(int,sys_rt_sigqueueinfo,int,pid,int,sig,siginfo_t *,uinfo)
_syscall3(int,sys_syslog,int,type,char*,bufp,int,len)
_syscall4(int,sys_fadvise64,int,fd,loff_t,offset,loff_t,len,int,advice)
+_syscall3(int,sys_tgkill,int,tgid,int,pid,int,sig)
+_syscall5(int,sys_clone, int, flags, void *, child_stack, int *, parent_tidptr, struct user_desc *, newtls, int *, child_tidptr)
#ifdef __NR_exit_group
_syscall1(int,exit_group,int,error_code)
#endif
@@ -1699,7 +1704,7 @@ int do_modify_ldt(CPUX86State *env, int
return ret;
}
-int do_set_thread_area(CPUX86State *env, target_ulong ptr)
+int do_set_thread_area(CPUX86State *env, target_ulong ptr, int set_shadow_registers)
{
uint64_t *gdt_table = g2h(env->gdt.base);
struct target_modify_ldt_ldt_s ldt_info;
@@ -1708,6 +1713,7 @@ int do_set_thread_area(CPUX86State *env,
int seg_not_present, useable;
uint32_t *lp, entry_1, entry_2;
int i;
+SegmentCache *sc = &env->segs[R_GS];
lock_user_struct(target_ldt_info, ptr, 1);
ldt_info.entry_number = tswap32(target_ldt_info->entry_number);
@@ -1767,6 +1767,12 @@ int do_set_thread_area(CPUX86State *env,
(useable << 20) |
0x7000;
+if(set_shadow_registers) {
+sc->selector = env->regs[R_GS];
+sc->base = ldt_info.base_addr;
+sc->limit = ldt_info.limit;
+sc->flags = entry_2;
+}
/* Install the new entry ... */
install:
lp = (uint32_t *)(gdt_table + ldt_info.entry_number);
@@ -1779,20 +1802,21 @@ install:
thread/process */
#define NEW_STACK_SIZE 8192
-static int clone_func(void *arg)
+static int clone_func(CPUState *cloneenv)
{
-CPUState *env = arg;
-cpu_loop(env);
+cpu_loop(cloneenv);
/* never exits */
return 0;
}
-int do_fork(CPUState *env, unsigned int flags, unsigned long newsp)
+int do_fork(CPUState *env, unsigned int flags, target_ulong newsp, target_ulong parent_tidptr, target_ulong newtls, target_ulong child_tidptr)
{
int ret;
+int cpu_index;
+unsigned long parent_tid=gettid();
TaskState *ts;
uint8_t *new_stack;
-CPUState *new_env;
+CPUState *new_env, *next_cpu;
#if defined(TARGET_I386)
uint64_t *new_gdt_table;
#endif
@@ -1807,9 +1835,14 @@ int do_fork(CPUState *env, unsigned int
/* add in task state list */
ts->next = first_task_state;
first_task_state = ts;
-/* we create a new CPU instance. */
-new_env = cpu_init();
-memcpy(new_env, env, sizeof(CPUState));
+/* we create a new CPU instance. (cpu_copy() in cvs) */
+ new_env = cpu_init();
+ /* preserve chaining and index */
+ next_cpu = new_env->next_cpu;
+ cpu_index = new_env->cpu_index;
+ memcpy(new_env,
[Qemu-devel] [PATCH] qemu-user mmap strange behavior on multi-threaded applications
Hi,
when using multi-threading, the page table gets modified (I did not find
the place where that happened though). Because of this the internal
mmap() calculation (a static counter) does not work reliably, because it
tries to map regions, which are already mapped onto (at least when
taking a look at page_dump()).
Additionally two memory syscalls should not have to be executed
simultaneously, so I added a spin_lock on everything that smelled like
it could break something.
While trying to get mplayer running I found a check in mprotect to only
support PROT_READ, PROT_WRITE and PROT_EXEC, but mplayer tries to load a
library with PROT_GROWSDOWN. To get it running I just ignored the flag
and had no problems with that. I'm not sure weather this is always the case.
This patch is not meant to be included. It is a hacky workaround for
bugs I found on my way getting NPTL applications to work.
If anyone more experienced in this could take a look at the main
problem, I would really very much appreciate it. As soon as I trigger a
syscall in a new thread, the internal page table gets modified. I sent a
test case that triggers this problem ca. 2 weeks ago. I suspect this has
something to do with copy-on-write?
Regards,
Alexander Graf
Index: qemu-0.9.0/linux-user/syscall.c
===
--- qemu-0.9.0.orig/linux-user/syscall.c
+++ qemu-0.9.0/linux-user/syscall.c
@@ -185,6 +185,9 @@ extern int getresgid(gid_t *, gid_t *, g
extern int setgroups(int, gid_t *);
extern int uselib(const char*);
+#include "exec-all.h"
+long mmap_lock;
+
static inline long get_errno(long ret)
{
if (ret == -1)
@@ -227,9 +235,11 @@ long do_brk(target_ulong new_brk)
/* We need to allocate more memory after the brk... */
new_alloc_size = HOST_PAGE_ALIGN(new_brk - brk_page + 1);
+spin_lock(&mmap_lock);
mapped_addr = get_errno(target_mmap(brk_page, new_alloc_size,
PROT_READ|PROT_WRITE,
MAP_ANON|MAP_FIXED|MAP_PRIVATE, 0, 0));
+spin_unlock(&mmap_lock);
if (is_error(mapped_addr)) {
return mapped_addr;
} else {
@@ -2133,6 +2133,7 @@ static long do_futex(target_ulong uaddr,
struct timespec host_utime;
unsigned long val2 = utime;
+ spin_lock(&mmap_lock);
if (utime && (op == FUTEX_WAIT || op == FUTEX_LOCK_PI)) {
target_to_host_timespec(&host_utime, utime);
val2 = (unsigned long)&host_utime;
@@ -2230,6 +2265,7 @@ static long do_futex(target_ulong uaddr,
}
#endif
#endif
+ spin_unlock(&mmap_lock);
return syscall(__NR_futex, g2h(uaddr), op, val, val2, g2h(uaddr2), val3);
}
@@ -2985,15 +3021,19 @@ long do_syscall(void *cpu_env, int num,
v5 = tswapl(v[4]);
v6 = tswapl(v[5]);
unlock_user(v, arg1, 0);
+ spin_lock(&mmap_lock);
ret = get_errno(target_mmap(v1, v2, v3,
target_to_host_bitmask(v4, mmap_flags_tbl),
v5, v6));
+ spin_unlock(&mmap_lock);
}
#else
+ spin_lock(&mmap_lock);
ret = get_errno(target_mmap(arg1, arg2, arg3,
target_to_host_bitmask(arg4, mmap_flags_tbl),
arg5,
arg6));
+ spin_unlock(&mmap_lock);
#endif
break;
#ifdef TARGET_NR_mmap2
@@ -3003,36 +3043,54 @@ long do_syscall(void *cpu_env, int num,
#else
#define MMAP_SHIFT TARGET_PAGE_BITS
#endif
+ spin_lock(&mmap_lock);
ret = get_errno(target_mmap(arg1, arg2, arg3,
target_to_host_bitmask(arg4, mmap_flags_tbl),
arg5,
arg6 << MMAP_SHIFT));
+ spin_unlock(&mmap_lock);
break;
#endif
case TARGET_NR_munmap:
+ spin_lock(&mmap_lock);
ret = get_errno(target_munmap(arg1, arg2));
+ spin_unlock(&mmap_lock);
break;
case TARGET_NR_mprotect:
+ spin_lock(&mmap_lock);
ret = get_errno(target_mprotect(arg1, arg2, arg3));
+ spin_unlock(&mmap_lock);
break;
case TARGET_NR_mremap:
+ spin_lock(&mmap_lock);
ret = get_errno(target_mremap(arg1, arg2, arg3, arg4, arg5));
+ spin_unlock(&mmap_lock);
break;
/* ??? msync/mlock/munlock are broken for softmmu. */
case TARGET_NR_msync:
+ spin_lock(&mmap_lock);
ret = get_errno(msync(g2h(arg1), arg2, arg3));
+ spin_unlock(&mmap_lock);
break;
case TARGET_NR_mlock:
+ spin_lock(&mmap_lock);
ret = get_errno(mlock(g2h(arg1), arg2));
+ spin_unlock(&mmap_lock);
break;
case TARGET_NR_munlock:
+ spin_lock(&mmap_lock);
ret = get_errno(munlock(g2h(arg1), arg2));
+ spin_unlock(&mmap_lock);
break;
case TARGET_NR_mlockall:
+ spin_lock(&mmap_lock);
ret = get_
Re: [Qemu-devel] Sparc32 network problems
On 6/8/07, Andreas Färber <[EMAIL PROTECTED]> wrote:
> Blue Swirl wrote:
>> On 6/6/07, Andreas Färber <[EMAIL PROTECTED]> wrote:
>>> I also made some local changes to tcx.c today to avoid having a
>>> blue-
>>> footed penguin on Intel. There's a TODO in that file saying the RGB
>>> functions should be merged with vga.c (where they are being patched
>>> by Q) - should I provide a qemu patch doing this and fixing the
>>> issue
>>> for both? Or is this for some reason restricted to Q?
>>
>> I made a patch to fix both vga and tcx while also unifying the pixel
>> operations, does it fix the blue foot disease on PPC?
>
> Hm, _with_ this patch I get (on PPC/Linux, emulating LE MIPS):
> - a blue-footed penguin when the cirrus FB is started
> - blue instead of red colour in console output
> - A general blue-to-red inversion for X11 in 16bit mode.
>
> Note that the colours for the last one were already not quite right
> (e.g. grey became a pale blue), but with your patch it looks even
> weirder.
I haven't been able to test the new patch yet.
Q's patch and my adaptation for tcx just reversed the order of the
colors, just like BlueSwirl's patch except that they used #if
__LITTLE_ENDIAN__ in place of #ifdef WORDS_BIGENDIAN, and this worked
for both i386 and sparc32 guests on i386 host (but is not applied for
ppc host).
http://www.kju-app.org/proj/browser/trunk/patches/q_vga.c_02.diff
I think this is not correct either, instead the DisplayState bgr
attribute should be used. This version should work like before, and on
BGR displays the colours should be correct. VGA needs a similar change
for 15 and 16 bit depths if I'm correct.
Index: qemu/hw/pixel_ops.h
===
--- /dev/null 1970-01-01 00:00:00.0 +
+++ qemu/hw/pixel_ops.h 2007-06-08 16:08:58.0 +
@@ -0,0 +1,41 @@
+static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
+}
+
+static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
+}
+
+static inline unsigned int rgb_to_pixel15bgr(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return ((b >> 3) << 10) | ((g >> 3) << 5) | (r >> 3);
+}
+
+static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
+}
+
+static inline unsigned int rgb_to_pixel16bgr(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return ((b >> 3) << 11) | ((g >> 2) << 5) | (r >> 3);
+}
+
+static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return (r << 16) | (g << 8) | b;
+}
+
+static inline unsigned int rgb_to_pixel32bgr(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return (b << 16) | (g << 8) | r;
+}
Index: qemu/hw/tcx.c
===
--- qemu.orig/hw/tcx.c 2007-06-07 19:35:27.0 +
+++ qemu/hw/tcx.c 2007-06-08 16:09:03.0 +
@@ -22,6 +22,7 @@
* THE SOFTWARE.
*/
#include "vl.h"
+#include "pixel_ops.h"
#define MAXX 1024
#define MAXY 768
@@ -47,27 +48,6 @@
static void tcx_invalidate_display(void *opaque);
static void tcx24_invalidate_display(void *opaque);
-/* XXX: unify with vga draw line functions */
-static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
-{
-return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
-}
-
-static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
-{
-return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
-}
-
-static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
-{
-return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
-}
-
-static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
-{
-return (r << 16) | (g << 8) | b;
-}
-
static void update_palette_entries(TCXState *s, int start, int end)
{
int i;
@@ -78,13 +58,22 @@
s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
break;
case 15:
-s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
+if (s->ds->bgr)
+s->palette[i] = rgb_to_pixel15bgr(s->r[i], s->g[i], s->b[i]);
+else
+s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
break;
case 16:
-s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
+if (s->ds->bgr)
+s->palette[i] =
[Qemu-devel] qemu vl.h hw/dma.c hw/ds1225y.c hw/pckbd.c hw/p...
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/06/08 16:45:24 Modified files: . : vl.h hw : dma.c ds1225y.c pckbd.c pflash_cfi02.c ppc405.h ppc405_boards.c ppc405_uc.c serial.c Log message: Fix incorrect target_ulong use in hw devices CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/vl.h?cvsroot=qemu&r1=1.250&r2=1.251 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/dma.c?cvsroot=qemu&r1=1.14&r2=1.15 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ds1225y.c?cvsroot=qemu&r1=1.1&r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/pckbd.c?cvsroot=qemu&r1=1.20&r2=1.21 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/pflash_cfi02.c?cvsroot=qemu&r1=1.5&r2=1.6 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc405.h?cvsroot=qemu&r1=1.3&r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc405_boards.c?cvsroot=qemu&r1=1.1&r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc405_uc.c?cvsroot=qemu&r1=1.3&r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/serial.c?cvsroot=qemu&r1=1.17&r2=1.18
Re: [Qemu-devel] Sparc32 network problems
Blue Swirl wrote: [snip] > >I haven't been able to test the new patch yet. > > > >Q's patch and my adaptation for tcx just reversed the order of the > >colors, just like BlueSwirl's patch except that they used #if > >__LITTLE_ENDIAN__ in place of #ifdef WORDS_BIGENDIAN, and this worked > >for both i386 and sparc32 guests on i386 host (but is not applied for > >ppc host). > > > >http://www.kju-app.org/proj/browser/trunk/patches/q_vga.c_02.diff > > I think this is not correct either, instead the DisplayState bgr > attribute should be used. This version should work like before, and on > BGR displays the colours should be correct. VGA needs a similar change > for 15 and 16 bit depths if I'm correct. This one doesn't change anything for my testcases, so I guess it is ok for me. Thiemo
Re: [Qemu-devel] Sparc32 network problems
On 6/8/07, Thiemo Seufer <[EMAIL PROTECTED]> wrote:
Blue Swirl wrote:
[snip]
> >I haven't been able to test the new patch yet.
> >
> >Q's patch and my adaptation for tcx just reversed the order of the
> >colors, just like BlueSwirl's patch except that they used #if
> >__LITTLE_ENDIAN__ in place of #ifdef WORDS_BIGENDIAN, and this worked
> >for both i386 and sparc32 guests on i386 host (but is not applied for
> >ppc host).
> >
> >http://www.kju-app.org/proj/browser/trunk/patches/q_vga.c_02.diff
>
> I think this is not correct either, instead the DisplayState bgr
> attribute should be used. This version should work like before, and on
> BGR displays the colours should be correct. VGA needs a similar change
> for 15 and 16 bit depths if I'm correct.
This one doesn't change anything for my testcases, so I guess it
is ok for me.
Could you test if this version fixes the 16/15 bit PPC host case?
Index: qemu/hw/pixel_ops.h
===
--- /dev/null 1970-01-01 00:00:00.0 +
+++ qemu/hw/pixel_ops.h 2007-06-08 17:09:59.0 +
@@ -0,0 +1,41 @@
+static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
+}
+
+static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
+}
+
+static inline unsigned int rgb_to_pixel15bgr(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return ((b >> 3) << 10) | ((g >> 3) << 5) | (r >> 3);
+}
+
+static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
+}
+
+static inline unsigned int rgb_to_pixel16bgr(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return ((b >> 3) << 11) | ((g >> 2) << 5) | (r >> 3);
+}
+
+static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return (r << 16) | (g << 8) | b;
+}
+
+static inline unsigned int rgb_to_pixel32bgr(unsigned int r, unsigned int g,
+ unsigned int b)
+{
+return (b << 16) | (g << 8) | r;
+}
Index: qemu/hw/tcx.c
===
--- qemu.orig/hw/tcx.c 2007-06-08 16:40:44.0 +
+++ qemu/hw/tcx.c 2007-06-08 17:09:59.0 +
@@ -22,6 +22,7 @@
* THE SOFTWARE.
*/
#include "vl.h"
+#include "pixel_ops.h"
#define MAXX 1024
#define MAXY 768
@@ -47,27 +48,6 @@
static void tcx_invalidate_display(void *opaque);
static void tcx24_invalidate_display(void *opaque);
-/* XXX: unify with vga draw line functions */
-static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
-{
-return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
-}
-
-static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
-{
-return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
-}
-
-static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
-{
-return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
-}
-
-static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
-{
-return (r << 16) | (g << 8) | b;
-}
-
static void update_palette_entries(TCXState *s, int start, int end)
{
int i;
@@ -78,13 +58,22 @@
s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
break;
case 15:
-s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
+if (s->ds->bgr)
+s->palette[i] = rgb_to_pixel15bgr(s->r[i], s->g[i], s->b[i]);
+else
+s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
break;
case 16:
-s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
+if (s->ds->bgr)
+s->palette[i] = rgb_to_pixel16bgr(s->r[i], s->g[i], s->b[i]);
+else
+s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
break;
case 32:
-s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
+if (s->ds->bgr)
+s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
+else
+s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
break;
}
}
Index: qemu/hw/vga.c
===
--- qemu.orig/hw/vga.c 2007-06-08 16:40:44.0 +
+++ qemu/hw/vga.c 2007-06-08 18:56:32.0 +
@@ -23,6 +23,7 @@
*/
#include "vl.h"
#include "vg
Re: [Qemu-devel] Sparc32 network problems
Q's patch and my adaptation for tcx just reversed the order of the colors, just like BlueSwirl's patch except that they used #if __LITTLE_ENDIAN__ in place of #ifdef WORDS_BIGENDIAN, and this worked for both i386 and sparc32 guests on i386 host (but is not applied for ppc host). http://www.kju-app.org/proj/browser/trunk/patches/q_vga.c_02.diff I think this is not correct either, instead the DisplayState bgr attribute should be used. This version should work like before, and on BGR displays the colours should be correct. VGA needs a similar change for 15 and 16 bit depths if I'm correct. This one doesn't change anything for my testcases, so I guess it is ok for me. It is not okay. It works on ppc but on Intel applied to 0.9.0 s->ds- >bgr does not evaluate to true so OpenBIOS and Tux are blue again... (tested i386 and sparc guests; my console output indicates rgb_to_pixel32 is called for tcx) Andreas
[Qemu-devel] Emulation Slower with Kqemu
I run Windows 98SE with qemu on a FreeBSD 6.2 i386 host. If I load the kqemu kernel module, the emulation runs significantly slower that without it. What am I doing wrong?
