Re: [Qemu-devel] Guest cannot see more than 1 cpu with -smp

[David Chow]

Hi all,

Does anyone have any success in SMP? because I saw many people talk 
about it in the list but personally no success on it. Any help will be 
appreciated. Thanks.


David

David Chow wrote:

Dear all,

With latest qemu 0.9.0, the -smp 2 doesn't work. guest os never sees 
more than one CPU. I am running suse 10 on host and redhat el4 on 
guest . Tried several attempts and seems doesn't work.


I lookup some pcbios code, it seems bios attempt to read address 
0xf000 for num cpus, but not find in hw/pc.c or vl.c that deal with 
this address . Is there are a problem on number of cpus not passing to 
the bios of vm correctly?


regards,
David Chow

[Qemu-devel] autoexpand images

[Christian Buhtz]

Is it possible to create hard-disk images that expand automaticly? 
Create a 10G image that is realy 2G big, because just 2G are in use but 
the guest-system see 10G.

[Qemu-devel] Re: autoexpand images

[Christian Buhtz]

Christian Buhtz schrieb:
Is it possible to create hard-disk images that expand automaticly? 


Ah, I found the qcow2 image format.

[Qemu-devel] mac os x on qemu?

[Christian Buhtz]

Did I understand the docs right that I am able to install MacOS X on 
qemu if qemu runs under WinXP on a IntelPC?

[Qemu-devel] [M68K] Full extension word format addressing mode

[Andreas Schwab]

This patch implements the full extension word format addressing mode in
the m68k emulation.  I have manually verified that it gets all cases
right.

Andreas.

Index: target-m68k/translate.c
===
RCS file: /sources/qemu/qemu/target-m68k/translate.c,v
retrieving revision 1.5
diff -u -a -p -a -u -p -r1.5 target-m68k/translate.c
--- target-m68k/translate.c 23 May 2007 19:58:11 -  1.5
+++ target-m68k/translate.c 26 May 2007 12:56:00 -
@@ -217,6 +217,18 @@ static int gen_ldst(DisasContext *s, int
 }
 }
 
+/* Read a 32-bit immediate constant.  */
+static inline uint32_t read_im32(DisasContext *s)
+{
+uint32_t im;
+im = ((uint32_t)lduw_code(s->pc)) << 16;
+s->pc += 2;
+im |= lduw_code(s->pc);
+s->pc += 2;
+return im;
+}
+
+
 /* Handle a base + index + displacement effective addresss.  A base of
-1 means pc-relative.  */
 static int gen_lea_indexed(DisasContext *s, int opsize, int base)
@@ -226,41 +238,105 @@ static int gen_lea_indexed(DisasContext 
 uint16_t ext;
 int add;
 int tmp;
+uint32_t bd, od;
 
 offset = s->pc;
 ext = lduw_code(s->pc);
 s->pc += 2;
-tmp = ((ext >> 12) & 7) + ((ext & 0x8000) ? QREG_A0 : QREG_D0);
-/* ??? Check W/L bit.  */
-scale = (ext >> 9) & 3;
-if (scale == 0) {
-add = tmp;
-} else {
-add = gen_new_qreg(QMODE_I32);
-gen_op_shl32(add, tmp, gen_im32(scale));
-}
-tmp = gen_new_qreg(QMODE_I32);
-if (base != -1) {
-gen_op_add32(tmp, base, gen_im32((int8_t)ext));
-gen_op_add32(tmp, tmp, add);
-} else {
-gen_op_add32(tmp, add, gen_im32(offset + (int8_t)ext));
+if (ext & 0x100) {
+   /* full extension word format */
+   if ((ext & 0x30) > 0x10)
+   /* base displacement */
+   if ((ext & 0x30) == 0x20) {
+   bd = (int16_t)lduw_code(s->pc);
+   s->pc += 2;
+   } else
+   bd = read_im32(s);
+   else
+   bd = 0;
+   if ((ext & 0x40) == 0) {
+   /* index not suppressed */
+   add = ((ext >> 12) & 7) + ((ext & 0x8000) ? QREG_A0 : QREG_D0);
+   if ((ext & 0x800) == 0) {
+   tmp = gen_new_qreg(QMODE_I32);
+   gen_op_ext16s32(tmp, add);
+   add = tmp;
+   }
+   scale = (ext >> 9) & 3;
+   if (scale != 0) {
+   if ((ext & 0x800) == 0)
+   tmp = add;
+   else
+   tmp = gen_new_qreg(QMODE_I32);
+   gen_op_shl32(tmp, add, gen_im32(scale));
+   add = tmp;
+   }
+   }
+   if ((ext & 0x80) == 0) {
+   /* base not suppressed */
+   if (base == -1)
+   tmp = gen_im32(offset + bd);
+   else if (bd != 0) {
+   tmp = gen_new_qreg(QMODE_I32);
+   gen_op_add32(tmp, base, gen_im32(bd));
+   } else
+   tmp = base;
+   if ((ext & 0x44) == 0)
+   gen_op_add32(tmp, tmp, add);
+   } else if (bd != 0) {
+   tmp = gen_im32(bd);
+   if ((ext & 0x44) == 0)
+   gen_op_add32(tmp, tmp, add);
+   } else if ((ext & 0x44) == 0)
+   tmp = add;
+   else
+   tmp = gen_im32(0);
+   if ((ext & 3) != 0) {
+   /* memory indirect */
+   tmp = gen_load(s, OS_LONG, tmp, 0);
+   if ((ext & 0x44) == 4)
+   gen_op_add32(tmp, tmp, add);
+   if ((ext & 3) > 1)
+   /* outer displacement */
+   if ((ext & 3) == 2) {
+   od = (int16_t)lduw_code(s->pc);
+   s->pc += 2;
+   } else
+   od = read_im32(s);
+   else
+   od = 0;
+   if (od != 0)
+   gen_op_add32(tmp, tmp, gen_im32(od));
+   }
+} else {
+   /* brief extension word format */
+   tmp = ((ext >> 12) & 7) + ((ext & 0x8000) ? QREG_A0 : QREG_D0);
+   if ((ext & 0x800) == 0) {
+   add = gen_new_qreg(QMODE_I32);
+   gen_op_ext16s32(add, tmp);
+   tmp = add;
+   }
+   scale = (ext >> 9) & 3;
+   if (scale == 0) {
+   add = tmp;
+   } else {
+   if ((ext & 0x800) == 0)
+   add = tmp;
+   else
+   add = gen_new_qreg(QMODE_I32);
+   gen_op_shl32(add, tmp, gen_im32(scale));
+   }
+   tmp = gen_new_qreg(QMODE_I32);
+   if (base != -1) {
+   gen_op_add32(tmp, base, gen_im32((int8_t)ext));
+   gen_op_add32(tmp, tmp, add);
+   } else {
+   gen_op_add32(tmp, add, gen_im32(offset + (int8_t)ext));
+   }
 }
 return tmp;
 }
 
-/* Read a 32-bit immediate constant.  */
-static inline uint32_t read_im32(DisasContext *s)
-{
-uint32_t im;
-im = ((uint32_t)lduw_code(s->pc)) << 16;
-s->pc += 2;
-im |= lduw_code(s->pc);
-s->pc +=

[Qemu-devel] cpu-speed

[Christian Buhtz]

Is it possible to manipulate the cpu-speed down?

Re: [Qemu-devel] cpu-speed

[Paul Brook]

On Saturday 26 May 2007, Christian Buhtz wrote:
> Is it possible to manipulate the cpu-speed down?

No. qemu is not cycle accurate, and has no useful way of measuring effective 
emulated CPU speed. A direct implication of this is that it is not meaningful 
to try and regulate the "speed" of the emulated cpu.

You can of course use the facilities provided by your host OS to regulate the 
amount of host CPU time qemu gets.

Paul

Re: [Qemu-devel] [win] front-end

[Ricardo Almeida]

On 5/26/07, Christian Buhtz <[EMAIL PROTECTED]> wrote:

I downloaded the 0.9.0 for Windows and the current snapshot. There is no
  front-end for qemu just a commandline.

Is there a ergonimic way to config and setup qemu on windows?



From the QEmu homepage: http://fabrice.bellard.free.fr/qemu/links.html


* Q (http://www.kju-app.org/kju/) is a Mac OS X port of QEMU with a nice GUI.
* QEMU Manager (http://www.davereyn.co.uk/about.htm) , a GUI for the
Windows port of QEMU.
* QEMU Launcher (http://emeitner.f2o.org/qemu_launcher), a GTK front
end for QEMU on Linux.
* QEMoon (http://qemoon.org/), a QEMU gui frontend for Linux and
Windows in Java using the Eclipse framework.
* qemudo (http://qemudo.sourceforge.net/), QEMU Web Interface.
* QtEmu (http://qtemu.org/), a graphical user interface for QEMU
written in Qt4 for Linux and Windows.

[Qemu-devel] qemu Makefile.target arm-semi.c gdbstub.c qemu-...

[Paul Brook]

CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook  07/05/26 15:09:38

Modified files:
.  : Makefile.target arm-semi.c gdbstub.c 
 qemu-doc.texi vl.c 
linux-user : main.c qemu.h 
target-m68k: cpu.h op.c op_helper.c translate.c 
Added files:
.  : m68k-semi.c 
Removed files:
linux-user : m68k-semi.c 

Log message:
M68k system mode semihosting.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/Makefile.target?cvsroot=qemu&r1=1.177&r2=1.178
http://cvs.savannah.gnu.org/viewcvs/qemu/arm-semi.c?cvsroot=qemu&r1=1.2&r2=1.3
http://cvs.savannah.gnu.org/viewcvs/qemu/gdbstub.c?cvsroot=qemu&r1=1.55&r2=1.56
http://cvs.savannah.gnu.org/viewcvs/qemu/qemu-doc.texi?cvsroot=qemu&r1=1.143&r2=1.144
http://cvs.savannah.gnu.org/viewcvs/qemu/vl.c?cvsroot=qemu&r1=1.300&r2=1.301
http://cvs.savannah.gnu.org/viewcvs/qemu/m68k-semi.c?cvsroot=qemu&rev=1.1
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemu&r1=1.110&r2=1.111
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/qemu.h?cvsroot=qemu&r1=1.31&r2=1.32
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/m68k-semi.c?cvsroot=qemu&r1=1.1&r2=0
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/cpu.h?cvsroot=qemu&r1=1.4&r2=1.5
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/op.c?cvsroot=qemu&r1=1.5&r2=1.6
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/op_helper.c?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/translate.c?cvsroot=qemu&r1=1.5&r2=1.6

[Qemu-devel] qemu/linux-user syscall_defs.h

[Paul Brook]

CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook  07/05/26 15:18:52

Modified files:
linux-user : syscall_defs.h 

Log message:
Suppress pointer from integer of different size warning.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/syscall_defs.h?cvsroot=qemu&r1=1.31&r2=1.32

[Qemu-devel] qemu configure

[Paul Brook]

CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook  07/05/26 16:38:53

Modified files:
.  : configure 

Log message:
Reject invalid targets.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/configure?cvsroot=qemu&r1=1.144&r2=1.145

[Qemu-devel] qemu softmmu-semi.h

[Paul Brook]

CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook  07/05/26 16:46:21

Added files:
.  : softmmu-semi.h 

Log message:
Add missing file.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/softmmu-semi.h?cvsroot=qemu&rev=1.1

[Qemu-devel] qemu linux-user/main.c target-m68k/cpu.h target...

[Paul Brook]

CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook  07/05/26 16:52:22

Modified files:
linux-user : main.c 
target-m68k: cpu.h helper.c translate.c 

Log message:
Rework m68k cpu feature flags.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemu&r1=1.111&r2=1.112
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/cpu.h?cvsroot=qemu&r1=1.5&r2=1.6
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/helper.c?cvsroot=qemu&r1=1.2&r2=1.3
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/translate.c?cvsroot=qemu&r1=1.6&r2=1.7

[Qemu-devel] qemu Changelog

[Paul Brook]

CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook  07/05/26 16:56:01

Modified files:
.  : Changelog 

Log message:
Update Changelog.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/Changelog?cvsroot=qemu&r1=1.135&r2=1.136

[Qemu-devel] qemu .cvsignore

[Paul Brook]

CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook  07/05/26 16:59:06

Modified files:
.  : .cvsignore 

Log message:
Ignore m68k-softmmu.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/.cvsignore?cvsroot=qemu&r1=1.19&r2=1.20

[Qemu-devel] qemu cpu-all.h exec.c

[Blue Swirl]

CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl   07/05/26 17:36:03

Modified files:
.  : cpu-all.h exec.c 

Log message:
Implement generic sub-page I/O based on earlier work by J. Mayer.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-all.h?cvsroot=qemu&r1=1.71&r2=1.72
http://cvs.savannah.gnu.org/viewcvs/qemu/exec.c?cvsroot=qemu&r1=1.96&r2=1.97

[Qemu-devel] qemu vl.h hw/cs4231.c hw/esp.c hw/pcnet.c hw/sl...

[Blue Swirl]

CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl   07/05/26 17:39:43

Modified files:
.  : vl.h 
hw : cs4231.c esp.c pcnet.c slavio_intctl.c 
 slavio_misc.c slavio_serial.c slavio_timer.c 
 sparc32_dma.c sun4m.c 

Log message:
Split DMA controller in two
Fix register size related bugs

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/vl.h?cvsroot=qemu&r1=1.239&r2=1.240
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/cs4231.c?cvsroot=qemu&r1=1.2&r2=1.3
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/esp.c?cvsroot=qemu&r1=1.20&r2=1.21
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/pcnet.c?cvsroot=qemu&r1=1.11&r2=1.12
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_intctl.c?cvsroot=qemu&r1=1.13&r2=1.14
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_misc.c?cvsroot=qemu&r1=1.7&r2=1.8
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_serial.c?cvsroot=qemu&r1=1.17&r2=1.18
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_timer.c?cvsroot=qemu&r1=1.11&r2=1.12
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sparc32_dma.c?cvsroot=qemu&r1=1.4&r2=1.5
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4m.c?cvsroot=qemu&r1=1.39&r2=1.40

Re: [Qemu-devel] autoexpand images

[Tony Nelson]

At 1:15 PM +0200 5/26/07, Christian Buhtz wrote:
>Is it possible to create hard-disk images that expand automaticly?
>Create a 10G image that is realy 2G big, because just 2G are in use but
>the guest-system see 10G.

A sparse file will do this for you, on Linux.  At least it did it for me. :)

If you use QCOW 2, be sure to use trunk rather than the formal release
version.  Someone will know the revision where QCOW 2's data loss bug got
fixed.
-- 

TonyN.:'   
  '  

Re: [Qemu-devel] Re: autoexpand images

[Jannes Faber]

On 5/26/07, Christian Buhtz <[EMAIL PROTECTED]> wrote:


Christian Buhtz schrieb:
> Is it possible to create hard-disk images that expand automaticly?

Ah, I found the qcow2 image format.





Search for sparse files. Might be more what you are looking for.

--
Jannes Faber

Re: [Qemu-devel] [PATCH, MIPS64] 64-bit addressing fixes

[Aurelien Jarno]

On Mon, May 21, 2007 at 04:52:05PM +0300, Blue Swirl wrote:
> I don't know MIPS, but perhaps you could try this trick used in Sparc:
> static inline void gen_jmp_im(target_ulong pc)
> {
> #ifdef TARGET_SPARC64
>if (pc == (uint32_t)pc) {
>gen_op_jmp_im(pc);
>} else {
>gen_op_jmp_im64(pc >> 32, pc);
>}
> #else
>gen_op_jmp_im(pc);
> #endif
> }
> 

Here is a new patch using the same trick as the one used in Sparc. It
renders the code clearer. Sorry for the delay.

Index: target-mips/op.c
===
RCS file: /sources/qemu/qemu/target-mips/op.c,v
retrieving revision 1.62
diff -u -d -p -r1.62 op.c
--- target-mips/op.c23 May 2007 08:24:25 -  1.62
+++ target-mips/op.c26 May 2007 21:12:05 -
@@ -976,6 +976,14 @@ void op_save_btarget (void)
 RETURN();
 }
 
+#ifdef TARGET_MIPS64
+void op_save_btarget64 (void)
+{
+env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
+RETURN();
+}
+#endif
+
 /* Conditional branch */
 void op_set_bcond (void)
 {
@@ -2409,6 +2417,14 @@ void op_save_pc (void)
 RETURN();
 }
 
+#ifdef TARGET_MIPS64
+void op_save_pc64 (void)
+{
+env->PC = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
+RETURN();
+}
+#endif
+
 void op_interrupt_restart (void)
 {
 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
Index: target-mips/op_template.c
===
RCS file: /sources/qemu/qemu/target-mips/op_template.c,v
retrieving revision 1.5
diff -u -d -p -r1.5 op_template.c
--- target-mips/op_template.c   29 Apr 2007 21:19:03 -  1.5
+++ target-mips/op_template.c   26 May 2007 21:12:05 -
@@ -68,4 +68,20 @@ SET_RESET(T1, _T1)
 SET_RESET(T2, _T2)
 
 #undef SET_RESET
+
+#ifdef TARGET_MIPS64
+#define SET64(treg, tregname)   \
+void glue(op_set64, tregname)(void) \
+{   \
+treg = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2; \
+RETURN();   \
+}
+
+SET64(T0, _T0)
+SET64(T1, _T1)
+SET64(T2, _T2)
+
+#undef SET64
+
+#endif
 #endif
Index: target-mips/translate.c
===
RCS file: /sources/qemu/qemu/target-mips/translate.c,v
retrieving revision 1.87
diff -u -d -p -r1.87 translate.c
--- target-mips/translate.c 23 May 2007 08:24:25 -  1.87
+++ target-mips/translate.c 26 May 2007 21:12:05 -
@@ -569,6 +569,18 @@ do {
 } \
 } while (0)
 
+#ifdef TARGET_MIPS64
+#define GEN_LOAD_IMM_TN(Tn, Imm)  \
+do {  \
+if (Imm == 0) {   \
+glue(gen_op_reset_, Tn)();\
+} else if ((int32_t)Imm == Imm) { \
+glue(gen_op_set_, Tn)(Imm);   \
+} else {  \
+glue(gen_op_set64_, Tn)(((uint64_t)Imm) >> 32, (uint32_t)Imm);\
+} \
+} while (0)
+#else
 #define GEN_LOAD_IMM_TN(Tn, Imm)  \
 do {  \
 if (Imm == 0) {   \
@@ -577,6 +589,7 @@ do {
 glue(gen_op_set_, Tn)(Imm);   \
 } \
 } while (0)
+#endif
 
 #define GEN_STORE_TN_REG(Rn, Tn)  \
 do {  \
@@ -595,6 +608,32 @@ do {
 glue(gen_op_store_fpr_, FTn)(Fn); \
 } while (0)
 
+static inline void gen_save_pc(target_ulong pc)
+{
+#ifdef TARGET_MIPS64
+if (pc == (int32_t)pc) {
+gen_op_save_pc(pc);
+} else {
+gen_op_save_pc64(pc >> 32, (uint32_t)pc);
+}
+#else
+gen_op_save_pc(pc);
+#endif
+}
+
+static inline void gen_save_btarget(target_ulong btarget)
+{
+#ifdef TARGET_MIPS64
+if (btarget == (int32_t)btarget) {
+gen_op_save_btarget(btarget);
+} else {
+gen_op_save_btarget64(btarget >> 32, (uint32_t)btarget);
+}
+#else
+gen_op_save_btarget(btarget);
+#endif
+}
+
 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
 {
 #if defined MIPS_DEBUG_DISAS
@@ -604,7 +643,7 @@ static inline void save_cp

[Qemu-devel] qemu/target-m68k cpu.h translate.c

[Paul Brook]

CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook  07/05/26 21:16:48

Modified files:
target-m68k: cpu.h translate.c 

Log message:
M68k extended addressing modes.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/cpu.h?cvsroot=qemu&r1=1.6&r2=1.7
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/translate.c?cvsroot=qemu&r1=1.7&r2=1.8

Re: [Qemu-devel] [M68K] Full extension word format addressing mode

[Paul Brook]

On Saturday 26 May 2007, Andreas Schwab wrote:
> This patch implements the full extension word format addressing mode in
> the m68k emulation.  I have manually verified that it gets all cases
> right.

> + if ((ext & 0x80) == 0) {
> + /* base not suppressed */
> + if (base == -1)
> + tmp = gen_im32(offset + bd);
> + else if (bd != 0) {
> + tmp = gen_new_qreg(QMODE_I32);
> + gen_op_add32(tmp, base, gen_im32(bd));
> + } else
> + tmp = base;
> + if ((ext & 0x44) == 0)
> + gen_op_add32(tmp, tmp, add);

This corrupts a2 in the following instruction:

move.l ([%a2,%a1.l],0),%a0

I've fixed that and tweaked how temporary variables are used.

Paul

Re: [Qemu-devel] MIPS64 problem with ethernet

[Aurelien Jarno]

On Mon, May 21, 2007 at 10:49:12AM -0500, Jason Wessel wrote:
> Aurelien Jarno wrote:
> >Jason Wessel a écrit :
> >  
> >>The ethernet device does not come up correctly on a 64 MIPS target with 
> >>a 64 bit kernel.
> >>
> >
> >Which Ethernet card are you using? The pcnet one is working correctly
> >here. I am using a 2.6.21.1 kernel.
> >
> >  
> It works perfectly fine if I boot a 32bit kernel on the 64bit mips qemu 
> with the pcnet32.  It is when I boot the 64bit kernel on the 64bit mips 
> qemu that I see the issue.  The only difference I can see is the math 
> operations in the kcalloc() inline because the sizes are different in 32 
> vs 64 of course.  I too was using a 2.6.21.1 kernel with mips.org 
> patches.  Likely that I am using a different compiler though.  Keeping 
> in mind that the same kernel 32bit and 64bit kernels works fine on real 
> hardware.
> 

As discussed on IRC, the problem is only present on 32-bit hosts. It is
due to the do_ddivu which is falsely implemented using lldiv and then by
casting the result. The patch below uses / and % as on the 64-bit host
code. It is maybe slower than lldiv, but at least it gives the correct
result. This probably involves some libgcc code, so it is better to keep
it in op_helper.c for 32-bit hosts.

Index: target-mips/op_helper.c
===
RCS file: /sources/qemu/qemu/target-mips/op_helper.c,v
retrieving revision 1.49
diff -u -d -p -r1.49 op_helper.c
--- target-mips/op_helper.c 20 May 2007 13:27:58 -  1.49
+++ target-mips/op_helper.c 25 May 2007 14:57:23 -
@@ -240,10 +240,8 @@ void do_ddiv (void)
 void do_ddivu (void)
 {
 if (T1 != 0) {
-/* XXX: lldivu? */
-lldiv_t res = lldiv(T0, T1);
-env->LO = (uint64_t)res.quot;
-env->HI = (uint64_t)res.rem;
+env->LO = T0 / T1;
+env->HI = T0 % T1;
 }
 }
 #endif

-- 
  .''`.  Aurelien Jarno | GPG: 1024D/F1BCDB73
 : :' :  Debian developer   | Electrical Engineer
 `. `'   [EMAIL PROTECTED] | [EMAIL PROTECTED]
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[Qemu-devel] qemu/target-m68k translate.c

[Paul Brook]

CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook  07/05/26 22:11:13

Modified files:
target-m68k: translate.c 

Log message:
Generate m68k address faults.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/translate.c?cvsroot=qemu&r1=1.8&r2=1.9

Re: [Qemu-devel] [M68K] Full extension word format addressing mode

[Andreas Schwab]

Paul Brook <[EMAIL PROTECTED]> writes:

> On Saturday 26 May 2007, Andreas Schwab wrote:
>> This patch implements the full extension word format addressing mode in
>> the m68k emulation.  I have manually verified that it gets all cases
>> right.
>
>> +if ((ext & 0x80) == 0) {
>> +/* base not suppressed */
>> +if (base == -1)
>> +tmp = gen_im32(offset + bd);
>> +else if (bd != 0) {
>> +tmp = gen_new_qreg(QMODE_I32);
>> +gen_op_add32(tmp, base, gen_im32(bd));
>> +} else
>> +tmp = base;
>> +if ((ext & 0x44) == 0)
>> +gen_op_add32(tmp, tmp, add);
>
> This corrupts a2 in the following instruction:
>
> move.l ([%a2,%a1.l],0),%a0
>
> I've fixed that and tweaked how temporary variables are used.

Thanks.  Here's a patch for a small typo:

Index: translate.c
===
RCS file: /sources/qemu/qemu/target-m68k/translate.c,v
retrieving revision 1.9
diff -u -a -p -u -p -a -r1.9 translate.c
--- translate.c 26 May 2007 22:11:13 -  1.9
+++ translate.c 26 May 2007 22:42:35 -
@@ -313,7 +313,7 @@ static int gen_lea_indexed(DisasContext 
 od = 0;
 }
 if (od != 0) {
-gen_op_add32(add, tmp, gen_im32(od));
+gen_op_add32(tmp, add, gen_im32(od));
 add = tmp;
 }
 }

Andreas.

-- 
Andreas Schwab, SuSE Labs, [EMAIL PROTECTED]
SuSE Linux Products GmbH, Maxfeldstraße 5, 90409 Nürnberg, Germany
PGP key fingerprint = 58CA 54C7 6D53 942B 1756  01D3 44D5 214B 8276 4ED5
"And now for something completely different."

[Qemu-devel] qemu/target-m68k translate.c

[Paul Brook]

CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook  07/05/26 23:48:38

Modified files:
target-m68k: translate.c 

Log message:
Fix typo in m68k outer displacement addressing (Andreas Schwab).

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/translate.c?cvsroot=qemu&r1=1.9&r2=1.10