[Qemu-devel] Emulating x86 DOS on ARM Linux
Hi all, I want to know if is possible to emulate a x86 running Microsoft DOS (or, at least, FreeDOS) on a ARM920T running Linux. In fact, I've seen from http://fabrice.bellard.free.fr/qemu/status.html that the Host ARM support is still in a testing phase. Moreover, I would need to know how to cross-compile the Qemu binary for the ARM on a x86 Linux host (I didn't find any webpage explaining how to do that...) Many thanks for any help and suggestion, Claudio
[Qemu-devel] two repeatable kqemu-related crashes
Hi all I've found two repeatable (possibly related) ways to crash kqemu with 0.9.0 and several earlier versions also I think. It's under linux 2.6.9 fully updated CentOS 4.4 (clone of RH enterprise linux 4.4) First, I cannot use kqemu 1.3.0pre11 (either prebuilt or compiled from source, they're bitwise identical) because as soon as qemu starts, the window reports guest stopped, and within 3 seconds the host machine freezes completely flashing caps lock and scroll lock lights. Hard reboot necessary. Second problem, so I am using a previous kqemu, pre9 I think. The following only occurs with kqemu loaded... I'm hosting win2k SP4: under administrative tools I run Computer Management, and select Disk Management. I either get a qemu crash immediately or after clicking the first disk. On crash gives output like this: EAX=00010282 EBX=00c22008 ECX=63010101 EDX=bf42584c ESI=00c22008 EDI=00c24610 EBP=0006f5d0 ESP=0006f5a8 EIP=77e149a7 EFL=00010246 [---Z-P-] CPL=3 II=0 A20=1 SMM=0 HLT=0 ES =0023 00cff300 CS =001b 00cffb00 SS =0023 00cff300 DS =0023 00cff300 FS =003b 7ffde000 0fff 7f40f3fd GS = LDT= 8000 TR =0028 803eb000 20ab 8000893e GDT= 80036000 03ff IDT= 80036400 07ff CR0=e001003b CR2=77f8dfd0 CR3=07a3f000 CR4=0690 Unsupported return value: 0x I hope this information allows for whatever bugs are causing this to be identified and fixed. Thanks
[Qemu-devel] Full instruction tracing
Hello! I was wondering if there is a way to get a full trace dump of the original (not translated) executed instructions using qemu. Can someone give me some pointers on how this might be implemented in qemu (if it doesn't already exist)? Thank you, Alexandros
[Qemu-devel]Debian for arm
Hi all, I would like to build Debian for an ARM target and simulate it with qemu. I tried the following command: qemu-system-arm -M versatilepb -cdrom debian-31r5-arm-netinst.iso -hda hda.img -boot d Obviously, it doesn't work (it always asked for a kernel image). I have already experienced a net-install through qemu for i386 target. Is this possible with an ARM target? regards, maxime.
Re: [Qemu-devel]Debian for arm
On Friday 13 April 2007 14:21, Maxime Tierrie wrote: > Hi all, > > I would like to build Debian for an ARM target and simulate it with qemu. > I tried the following command: > qemu-system-arm -M versatilepb -cdrom debian-31r5-arm-netinst.iso -hda > hda.img -boot d > Obviously, it doesn't work (it always asked for a kernel image). > I have already experienced a net-install through qemu for i386 target. > Is this possible with an ARM target? http://www.aurel32.net/info/debian_arm_qemu.php Paul
Re: [Qemu-devel]Debian for arm
Paul Brook a écrit : On Friday 13 April 2007 14:21, Maxime Tierrie wrote: Hi all, I would like to build Debian for an ARM target and simulate it with qemu. I tried the following command: qemu-system-arm -M versatilepb -cdrom debian-31r5-arm-netinst.iso -hda hda.img -boot d Obviously, it doesn't work (it always asked for a kernel image). I have already experienced a net-install through qemu for i386 target. Is this possible with an ARM target? http://www.aurel32.net/info/debian_arm_qemu.php Paul Thank you Paul. Unfortunately, I have already tried it few days ago and it didn't work. That's why I asked for a net-install. Maxime.
Re: [Qemu-devel]Debian for arm
On Fri, Apr 13, 2007 at 03:21:08PM +0200, Maxime Tierrie wrote: > Hi all, > > I would like to build Debian for an ARM target and simulate it with qemu. > I tried the following command: > qemu-system-arm -M versatilepb -cdrom debian-31r5-arm-netinst.iso -hda > hda.img > -boot d > Obviously, it doesn't work (it always asked for a kernel image). > I have already experienced a net-install through qemu for i386 target. Is > this > possible with an ARM target? See Aurelien's walkthrough for this: http://www.aurel32.net/info/debian_arm_qemu.php -- Daniel Jacobowitz CodeSourcery
Re: [Qemu-devel]Debian for arm
> > http://www.aurel32.net/info/debian_arm_qemu.php > > > > Paul > > Thank you Paul. Unfortunately, I have already tried it few days ago and > it didn't work. That's why I asked for a net-install. This is a network install. Paul
[Qemu-devel] qemu/target-sparc cpu.h op.c op_helper.c transl...
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/04/13 15:46:16 Modified files: target-sparc : cpu.h op.c op_helper.c translate.c Log message: Alignment check mechanism (not fully enabled yet) (Aurelien Jarno) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/cpu.h?cvsroot=qemu&r1=1.33&r2=1.34 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/op.c?cvsroot=qemu&r1=1.28&r2=1.29 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/op_helper.c?cvsroot=qemu&r1=1.24&r2=1.25 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/translate.c?cvsroot=qemu&r1=1.49&r2=1.50
[Qemu-devel] qemu/target-sparc op.c translate.c
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/04/13 15:49:56 Modified files: target-sparc : op.c translate.c Log message: Fix Sparc64 wrfprs, move VIS ops where they belong, more VIS ops CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/op.c?cvsroot=qemu&r1=1.29&r2=1.30 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/translate.c?cvsroot=qemu&r1=1.50&r2=1.51
[Qemu-devel] sparc64 gdb
I'm currently reqriting bits of the qemu gdb stub to take advantage of new GDB
target description mechanisms, and have come accross what looks like a bug in
the sparc64 code.
My understanding is that gdb considers sparc64 to have 48 "registers". The
first 32 are the same as sparc32, the last 16 (named f32, f34 ... f62) are
double precision registers. gdb then overlays this with d and q regs, but we
don't need to care about that.
The gdb remote protocol is defined to return register values in target byte
order. Currently we have the followingthe following:
for (i = 0; i < 64; i += 2) {
uint64_t tmp;
tmp = (uint64_t)tswap32(*((uint32_t *)&env->fpr[i])) << 32;
tmp |= tswap32(*((uint32_t *)&env->fpr[i + 1]));
registers[i/2 + 32] = tmp;
}
By my reading this get f0 and f1 the wrong way round on little-endian hosts.
Should this be(omitting uint32 *casts for clarity):
tmp = env->fpr[i];
tmp |= env->fpr[i + 1];
registers[i/2 + 32] = tswap64(tmp)
?
My sparc64 machine takes several hours to boot, so help from someone with
knowledge and/or toolchains to test this would be appreciated.
Paul
[Qemu-devel] Re: sparc64 gdb
> By my reading this get f0 and f1 the wrong way round on little-endian > hosts. Should this be(omitting uint32 *casts for clarity): > > tmp = env->fpr[i]; > tmp |= env->fpr[i + 1]; > registers[i/2 + 32] = tswap64(tmp) Argh. What I meant was: tmp = env->fpr[i] << 32; tmp |= env->fpr[i + 1]; registers[i/2 + 32] = tswap64(tmp) Paul
Re: [Qemu-devel] sparc64 gdb
My understanding is that gdb considers sparc64 to have 48 "registers". The
first 32 are the same as sparc32, the last 16 (named f32, f34 ... f62) are
double precision registers. gdb then overlays this with d and q regs, but
we
don't need to care about that.
Quoting the V9 manual:
The FPU contains:
- 32 single-precision (32-bit) floating-point registers, numbered f[0],
f[1], .. f[31].
- 32 double-precision (64-bit) floating-point registers, numbered f[0],
f[2], .. f[62]
- 16 quad-precision (128-bit) floating-point registers, numbered f[0], f[4],
.. f[60].
The gdb remote protocol is defined to return register values in target byte
order. Currently we have the followingthe following:
for (i = 0; i < 64; i += 2) {
uint64_t tmp;
tmp = (uint64_t)tswap32(*((uint32_t *)&env->fpr[i])) << 32;
tmp |= tswap32(*((uint32_t *)&env->fpr[i + 1]));
registers[i/2 + 32] = tmp;
}
By my reading this get f0 and f1 the wrong way round on little-endian
hosts.
Should this be(omitting uint32 *casts for clarity):
tmp = env->fpr[i];
tmp |= env->fpr[i + 1];
registers[i/2 + 32] = tswap64(tmp)
Yes, something like that would be more correct.
Re: [Qemu-devel] sparc64 gdb
I can confirm that native gdb64 talking to x86 Qemu gets incorrect double float registers values, 32-bit looks fine.
[Qemu-devel] Re: Full instruction tracing
Alexandros Frantzis <[EMAIL PROTECTED]> writes: > Can someone give me some pointers on how this might be implemented in > qemu (if it doesn't already exist)? There was recently a thread about this: http://thread.gmane.org/gmane.comp.emulators.qemu/16604 -- http://www.iki.fi/~ananaza/
[Qemu-devel] qemu/hw esp.c slavio_serial.c tcx.c
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/04/13 19:24:07 Modified files: hw : esp.c slavio_serial.c tcx.c Log message: Fix Sparc32 device save methods CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/esp.c?cvsroot=qemu&r1=1.18&r2=1.19 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_serial.c?cvsroot=qemu&r1=1.13&r2=1.14 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/tcx.c?cvsroot=qemu&r1=1.10&r2=1.11
[Qemu-devel] FDC and M48T59 save/reset methods
Hi,
I'd like to commit the attached FDC and M48T59 device save and reset
methods. After this change, all Sparc32 devices can be saved.
Any comments?
Index: qemu/hw/fdc.c
===
--- qemu.orig/hw/fdc.c 2007-04-13 19:22:56.0 +
+++ qemu/hw/fdc.c 2007-04-13 19:25:09.0 +
@@ -485,6 +485,64 @@
fdctrl_write_mem,
};
+static void fdc_save (QEMUFile *f, void *opaque)
+{
+fdctrl_t *s = opaque;
+
+qemu_put_8s(f, &s->state);
+qemu_put_8s(f, &s->dma_en);
+qemu_put_8s(f, &s->cur_drv);
+qemu_put_8s(f, &s->bootsel);
+qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
+qemu_put_be32s(f, &s->data_pos);
+qemu_put_be32s(f, &s->data_len);
+qemu_put_8s(f, &s->data_state);
+qemu_put_8s(f, &s->data_dir);
+qemu_put_8s(f, &s->int_status);
+qemu_put_8s(f, &s->eot);
+qemu_put_8s(f, &s->timer0);
+qemu_put_8s(f, &s->timer1);
+qemu_put_8s(f, &s->precomp_trk);
+qemu_put_8s(f, &s->config);
+qemu_put_8s(f, &s->lock);
+qemu_put_8s(f, &s->pwrd);
+}
+
+static int fdc_load (QEMUFile *f, void *opaque, int version_id)
+{
+fdctrl_t *s = opaque;
+
+if (version_id != 1)
+return -EINVAL;
+
+qemu_get_8s(f, &s->state);
+qemu_get_8s(f, &s->dma_en);
+qemu_get_8s(f, &s->cur_drv);
+qemu_get_8s(f, &s->bootsel);
+qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
+qemu_get_be32s(f, &s->data_pos);
+qemu_get_be32s(f, &s->data_len);
+qemu_get_8s(f, &s->data_state);
+qemu_get_8s(f, &s->data_dir);
+qemu_get_8s(f, &s->int_status);
+qemu_get_8s(f, &s->eot);
+qemu_get_8s(f, &s->timer0);
+qemu_get_8s(f, &s->timer1);
+qemu_get_8s(f, &s->precomp_trk);
+qemu_get_8s(f, &s->config);
+qemu_get_8s(f, &s->lock);
+qemu_get_8s(f, &s->pwrd);
+
+return 0;
+}
+
+static void fdctrl_external_reset(void *opaque)
+{
+fdctrl_t *s = opaque;
+
+fdctrl_reset(s, 0);
+}
+
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
uint32_t io_base,
BlockDriverState **fds)
@@ -525,6 +583,8 @@
register_ioport_write(io_base + 0x01, 5, 1, &fdctrl_write, fdctrl);
register_ioport_write(io_base + 0x07, 1, 1, &fdctrl_write, fdctrl);
}
+register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);
+qemu_register_reset(fdctrl_external_reset, fdctrl);
for (i = 0; i < 2; i++) {
fd_revalidate(&fdctrl->drives[i]);
}
Index: qemu/hw/m48t59.c
===
--- qemu.orig/hw/m48t59.c 2007-04-13 19:22:56.0 +
+++ qemu/hw/m48t59.c 2007-04-13 19:25:09.0 +
@@ -575,12 +575,50 @@
&nvram_readl,
};
+static void m48t59_save(QEMUFile *f, void *opaque)
+{
+m48t59_t *s = opaque;
+
+qemu_put_8s(f, &s->lock);
+qemu_put_be16s(f, &s->addr);
+qemu_put_buffer(f, s->buffer, s->size);
+}
+
+static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
+{
+m48t59_t *s = opaque;
+
+if (version_id != 1)
+return -EINVAL;
+
+qemu_get_8s(f, &s->lock);
+qemu_get_be16s(f, &s->addr);
+qemu_get_buffer(f, s->buffer, s->size);
+
+return 0;
+}
+
+static void m48t59_reset(void *opaque)
+{
+m48t59_t *NVRAM = opaque;
+
+if (NVRAM->alrm_timer != NULL) {
+qemu_del_timer(NVRAM->alrm_timer);
+ NVRAM->alrm_timer = NULL;
+}
+if (NVRAM->wd_timer != NULL) {
+qemu_del_timer(NVRAM->wd_timer);
+ NVRAM->wd_timer = NULL;
+}
+}
+
/* Initialisation routine */
m48t59_t *m48t59_init (qemu_irq IRQ, target_ulong mem_base,
uint32_t io_base, uint16_t size,
int type)
{
m48t59_t *s;
+target_ulong save_base;
s = qemu_mallocz(sizeof(m48t59_t));
if (!s)
@@ -610,5 +648,9 @@
}
s->lock = 0;
+qemu_register_reset(m48t59_reset, s);
+save_base = mem_base ? mem_base : io_base;
+register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);
+
return s;
}
[Qemu-devel] qemu/target-mips helper.c op.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer 07/04/13 20:17:54 Modified files: target-mips: helper.c op.c Log message: Another fix for CP0 Cause register handling. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemu&r1=1.33&r2=1.34 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemu&r1=1.39&r2=1.40
Re: [Qemu-devel] FDC and M48T59 save/reset methods
> I'd like to commit the attached FDC and M48T59 device save and reset > methods. After this change, all Sparc32 devices can be saved. > > Any comments? Do you also need to save the state of the attached drives? Paul
Re: [Qemu-devel] FDC and M48T59 save/reset methods
Blue Swirl <[EMAIL PROTECTED]> wrote: > Hi, > > I'd like to commit the attached FDC and M48T59 device save and reset > methods. After this change, all Sparc32 devices can be saved. > > Any comments? http://lists.gnu.org/archive/html/qemu-devel/2007-03/msg00435.html Other than the comments from this email makes absolutely no sense now. :-) I'll give it a whirl. Ben
[Qemu-devel] qemu/target-mips op_helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer 07/04/13 22:30:36 Modified files: target-mips: op_helper.c Log message: Nicer Log formatting. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemu&r1=1.38&r2=1.39
[Qemu-devel] PATCH: updated Solaris isinf support
This is an update to a previous patch to fix the missing macro isinf
(and isnan) for Solaris that is used in target-i386/helper.c. This
patch is against qemu/fpu/softfloat-native.h, which is a better place
for the macro, as opposed to putting it in target-i386/helper.c.
Attribution to Juergen Keil for extending the original idea, with
help from autoconf documentation.
Eventually, Solaris 10/11 will correctly support isinf, but until
the updates are made, this will work for now.
Ben--- qemu.ORIG/fpu/softfloat-native.h 2007-03-20 18:10:42.0 -0400
+++ qemu/fpu/softfloat-native.h 2007-04-13 17:58:22.643179000 -0400
@@ -33,6 +33,29 @@
#define isunordered(x,y)unordered(x, y)
#endif
+#if defined(__sun__) && !defined(NEED_LIBSUNMATH)
+
+#ifndef isnan
+# define isnan(x) \
+(sizeof (x) == sizeof (long double) ? isnan_ld (x) \
+ : sizeof (x) == sizeof (double) ? isnan_d (x) \
+ : isnan_f (x))
+static inline int isnan_f (float x) { return x != x; }
+static inline int isnan_d (double x) { return x != x; }
+static inline int isnan_ld (long double x) { return x != x; }
+#endif
+
+#ifndef isinf
+# define isinf(x) \
+(sizeof (x) == sizeof (long double) ? isinf_ld (x) \
+ : sizeof (x) == sizeof (double) ? isinf_d (x) \
+ : isinf_f (x))
+static inline int isinf_f (float x) { return isnan (x - x); }
+static inline int isinf_d (double x) { return isnan (x - x); }
+static inline int isinf_ld (long double x) { return isnan (x - x); }
+#endif
+#endif
+
typedef float float32;
typedef double float64;
#ifdef FLOATX80
Re: [Qemu-devel] Re: Full instruction tracing
Both the methods discussed in the past thread (which Antti pointed in the previous mail) worked well for me. -Shashi. On 4/13/07, Antti P Miettinen <[EMAIL PROTECTED]> wrote: Alexandros Frantzis <[EMAIL PROTECTED]> writes: > Can someone give me some pointers on how this might be implemented in > qemu (if it doesn't already exist)? There was recently a thread about this: http://thread.gmane.org/gmane.comp.emulators.qemu/16604 -- http://www.iki.fi/~ananaza/
Re: [Qemu-devel] FDC and M48T59 save/reset methods
On 4/13/07, Paul Brook <[EMAIL PROTECTED]> wrote: > I'd like to commit the attached FDC and M48T59 device save and reset > methods. After this change, all Sparc32 devices can be saved. > > Any comments? Do you also need to save the state of the attached drives? Yes, at least motor state, head position and last operation status. I'll update the patch.
Re: [Qemu-devel] FDC and M48T59 save/reset methods
On 4/14/07, Blue Swirl <[EMAIL PROTECTED]> wrote:
On 4/13/07, Paul Brook <[EMAIL PROTECTED]> wrote:
> > I'd like to commit the attached FDC and M48T59 device save and reset
> > methods. After this change, all Sparc32 devices can be saved.
> >
> > Any comments?
>
> Do you also need to save the state of the attached drives?
Yes, at least motor state, head position and last operation status.
I'll update the patch.
Is this version OK?
Index: qemu/hw/fdc.c
===
--- qemu.orig/hw/fdc.c 2007-04-13 19:22:56.0 +
+++ qemu/hw/fdc.c 2007-04-14 06:47:30.0 +
@@ -1,7 +1,7 @@
/*
* QEMU Floppy disk emulator (Intel 82078)
*
- * Copyright (c) 2003 Jocelyn Mayer
+ * Copyright (c) 2003, 2007 Jocelyn Mayer
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -485,6 +485,99 @@
fdctrl_write_mem,
};
+static void fd_save (QEMUFile *f, fdrive_t *fd)
+{
+uint8_t tmp;
+
+tmp = fd->drflags;
+qemu_put_8s(f, &tmp);
+qemu_put_8s(f, &fd->head);
+qemu_put_8s(f, &fd->track);
+qemu_put_8s(f, &fd->sect);
+qemu_put_8s(f, &fd->dir);
+qemu_put_8s(f, &fd->rw);
+}
+
+static void fdc_save (QEMUFile *f, void *opaque)
+{
+fdctrl_t *s = opaque;
+
+qemu_put_8s(f, &s->state);
+qemu_put_8s(f, &s->dma_en);
+qemu_put_8s(f, &s->cur_drv);
+qemu_put_8s(f, &s->bootsel);
+qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
+qemu_put_be32s(f, &s->data_pos);
+qemu_put_be32s(f, &s->data_len);
+qemu_put_8s(f, &s->data_state);
+qemu_put_8s(f, &s->data_dir);
+qemu_put_8s(f, &s->int_status);
+qemu_put_8s(f, &s->eot);
+qemu_put_8s(f, &s->timer0);
+qemu_put_8s(f, &s->timer1);
+qemu_put_8s(f, &s->precomp_trk);
+qemu_put_8s(f, &s->config);
+qemu_put_8s(f, &s->lock);
+qemu_put_8s(f, &s->pwrd);
+fd_save(f, s->drives[0]);
+fd_save(f, s->drives[1]);
+}
+
+static int fd_load (QEMUFile *f, fdrive_t *fd)
+{
+uint8_t tmp;
+
+qemu_get_8s(f, &tmp);
+fd->drflags = tmp;
+qemu_get_8s(f, &fd->head);
+qemu_get_8s(f, &fd->track);
+qemu_get_8s(f, &fd->sect);
+qemu_get_8s(f, &fd->dir);
+qemu_get_8s(f, &fd->rw);
+
+return 0;
+}
+
+static int fdc_load (QEMUFile *f, void *opaque, int version_id)
+{
+fdctrl_t *s = opaque;
+int ret;
+
+if (version_id != 1)
+return -EINVAL;
+
+qemu_get_8s(f, &s->state);
+qemu_get_8s(f, &s->dma_en);
+qemu_get_8s(f, &s->cur_drv);
+qemu_get_8s(f, &s->bootsel);
+qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
+qemu_get_be32s(f, &s->data_pos);
+qemu_get_be32s(f, &s->data_len);
+qemu_get_8s(f, &s->data_state);
+qemu_get_8s(f, &s->data_dir);
+qemu_get_8s(f, &s->int_status);
+qemu_get_8s(f, &s->eot);
+qemu_get_8s(f, &s->timer0);
+qemu_get_8s(f, &s->timer1);
+qemu_get_8s(f, &s->precomp_trk);
+qemu_get_8s(f, &s->config);
+qemu_get_8s(f, &s->lock);
+qemu_get_8s(f, &s->pwrd);
+
+ret = fd_load(f, s->drives[0]);
+if (ret == 0)
+ret = fd_load(f, s->drives[1]);
+
+return ret;
+}
+
+static void fdctrl_external_reset(void *opaque)
+{
+fdctrl_t *s = opaque;
+
+fdctrl_reset(s, 0);
+}
+
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
uint32_t io_base,
BlockDriverState **fds)
@@ -525,6 +618,8 @@
register_ioport_write(io_base + 0x01, 5, 1, &fdctrl_write, fdctrl);
register_ioport_write(io_base + 0x07, 1, 1, &fdctrl_write, fdctrl);
}
+register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);
+qemu_register_reset(fdctrl_external_reset, fdctrl);
for (i = 0; i < 2; i++) {
fd_revalidate(&fdctrl->drives[i]);
}
Index: qemu/hw/m48t59.c
===
--- qemu.orig/hw/m48t59.c 2007-04-13 19:22:56.0 +
+++ qemu/hw/m48t59.c 2007-04-14 06:51:03.0 +
@@ -1,7 +1,7 @@
/*
* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
*
- * Copyright (c) 2003-2005 Jocelyn Mayer
+ * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -575,12 +575,47 @@
&nvram_readl,
};
+static void m48t59_save(QEMUFile *f, void *opaque)
+{
+m48t59_t *s = opaque;
+
+qemu_put_8s(f, &s->lock);
+qemu_put_be16s(f, &s->addr);
+qemu_put_buffer(f, s->buffer, s->size);
+}
+
+static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
+{
+m48t59_t *s = opaque;
+
+if (version_id != 1)
+return -EINVAL;
+
+qemu_get_8s(f, &s->lock);
+qemu_get_be16s(f, &s->addr);
+qemu_get_buffer(f, s->buffer, s->size);
+
+return 0;
+}
+
+static void m
