[OpenWrt-Devel] [PATCH v3 1/5] ar71xx: add eth rx delay for qca955x platforms

2015-09-17 Thread Chris R Blake 
From: Chris R Blake 

This patch is to add support for qca955x_eth_rx_delay
to work with the qca955x SoC.

Signed-off-by: Chris R Blake 
---
 ...42-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch | 58 ++
 1 file changed, 58 insertions(+)
 create mode 100644 
target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch

diff --git 
a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch
 
b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch
new file mode 100644
index 000..75e216e
--- /dev/null
+++ 
b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch
@@ -0,0 +1,58 @@
+--- a/arch/mips/ath79/dev-eth.c
 b/arch/mips/ath79/dev-eth.c
+@@ -823,6 +825,32 @@
+   iounmap(base);
+ }
+
++void __init ath79_setup_qca955x_eth_rx_delay(unsigned int rxd,
++unsigned int rxdv)
++{
++  void __iomem *base;
++  u32 t;
++
++  rxd &= QCA955X_ETH_CFG_RXD_DELAY_MASK;
++  rxdv &= QCA955X_ETH_CFG_RDV_DELAY_MASK;
++
++  base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
++
++  t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
++
++  t &= ~(QCA955X_ETH_CFG_RXD_DELAY_MASK << 
QCA955X_ETH_CFG_RXD_DELAY_SHIFT |
++ QCA955X_ETH_CFG_RDV_DELAY_MASK << 
QCA955X_ETH_CFG_RDV_DELAY_SHIFT);
++
++  t |= (rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT |
++rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT);
++
++  __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
++  /* flush write */
++  __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
++
++  iounmap(base);
++}
++
+ static int ath79_eth_instance __initdata;
+ void __init ath79_register_eth(unsigned int id)
+ {
+--- a/arch/mips/ath79/dev-eth.h
 b/arch/mips/ath79/dev-eth.h
+@@ -49,5 +49,6 @@
+ void ath79_setup_ar934x_eth_cfg(u32 mask);
+ void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
+ void ath79_setup_qca955x_eth_cfg(u32 mask);
++void ath79_setup_qca955x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
+
+ #endif /* _ATH79_DEV_ETH_H */
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1098,5 +1098,11 @@
+
+ #define QCA955X_ETH_CFG_RGMII_EN  BIT(0)
+ #define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
++#define QCA955X_ETH_CFG_RXD_DELAY BIT(14)
++#define QCA955X_ETH_CFG_RXD_DELAY_MASK0x3
++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT   14
++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
++#define QCA955X_ETH_CFG_RDV_DELAY_MASK0x3
++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT   16
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
-- 
2.5.1
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[OpenWrt-Devel] [PATCH v3 2/5] ar71xx: add support for qca955x sgmii/serdes calibration

2015-09-17 Thread Chris R Blake 
From: Chris R Blake 

This patch is to add support for sgmii/serdes calibration from
within the OpenWRT environment. This is needed on boards that
do not use u-boot or do not have a pre-init process that runs
calibration.

Signed-off-by: Chris R Blake 
---
 ...S-ath79-add-qca955x-mac-sgmii-calibration.patch | 82 ++
 1 file changed, 82 insertions(+)
 create mode 100644 
target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch

diff --git 
a/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch
 
b/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch
new file mode 100644
index 000..eb7c5de
--- /dev/null
+++ 
b/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch
@@ -0,0 +1,82 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h   2015-08-05 
12:58:15.580496899 +0200
 b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h   2015-08-05 
13:52:32.590857293 +0200
+@@ -360,6 +360,7 @@
+ #define QCA955X_PLL_CLK_CTRL_REG  0x08
+ #define QCA955X_PLL_ETH_XMII_CONTROL_REG  0x28
+ #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
++#define QCA955X_PLL_ETH_SGMII_SERDES_REG  0x4c
+
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+@@ -392,6 +393,10 @@
+ #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL   BIT(21)
+ #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL   BIT(24)
+
++#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT  BIT(2)
++#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK   BIT(1)
++#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL   BIT(0)
++
+ #define QCA956X_PLL_CPU_CONFIG_REG0x00
+ #define QCA956X_PLL_CPU_CONFIG1_REG   0x04
+ #define QCA956X_PLL_DDR_CONFIG_REG0x08
+@@ -1104,5 +1109,11 @@
+ #define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
+ #define QCA955X_ETH_CFG_RDV_DELAY_MASK0x3
+ #define QCA955X_ETH_CFG_RDV_DELAY_SHIFT   16
++
++#define QCA955X_GMAC_REG_SGMII_SERDES 0x0018
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION  BIT(23)
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT23
++#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS   BIT(15)
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
+--- a/arch/mips/ath79/dev-eth.c2015-08-05 14:17:25.757504251 +0200
 b/arch/mips/ath79/dev-eth.c2015-08-05 14:09:54.716333554 +0200
+@@ -849,6 +849,37 @@ void __init ath79_setup_qca955x_eth_rx_d
+   iounmap(base);
+ }
+
++void __init ath79_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value)
++{
++  void __iomem *ethbase, *pllbase;
++  u32 t;
++
++  ethbase = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
++  pllbase = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
++
++  /* To Check the locking of the SGMII PLL */
++  t = __raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES);
++  t &= ~(QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK <<
++ QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT);
++  t |= (sgmii_value & QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK) <<
++   QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT;
++  __raw_writel(t, ethbase + QCA955X_GMAC_REG_SGMII_SERDES);
++
++  __raw_writel(QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT |
++   QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK |
++   QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL,
++   pllbase + QCA955X_PLL_ETH_SGMII_SERDES_REG);
++
++  ath79_device_reset_clear(QCA955X_RESET_SGMII_ANALOG);
++  ath79_device_reset_clear(QCA955X_RESET_SGMII);
++
++  while (!(__raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES) &
++  QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS));
++
++  iounmap(ethbase);
++  iounmap(pllbase);
++}
++
+ static int ath79_eth_instance __initdata;
+ void __init ath79_register_eth(unsigned int id)
+ {
+--- a/arch/mips/ath79/dev-eth.h2015-08-05 14:17:25.757504251 +0200
 b/arch/mips/ath79/dev-eth.h2015-08-05 13:58:20.292866210 +0200
+@@ -50,5 +50,6 @@ void ath79_setup_ar934x_eth_cfg(u32 mask
+ void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
+ void ath79_setup_qca955x_eth_cfg(u32 mask);
+ void ath79_setup_qca955x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
++void ath79_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value);
+
+ #endif /* _ATH79_DEV_ETH_H */
-- 
2.5.1
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[OpenWrt-Devel] [RFC 4/5] ar71xx: add LED driver NU801

2015-09-17 Thread Chris R Blake 
From: Chris R Blake 

The MR18 uses a 3-channel 16-bit PWM Constant Current Driver
for its status LED.

Signed-off-by: Chris R Blake 
---
 package/base-files/files/etc/init.d/led|   2 +-
 .../linux/ar71xx/files/drivers/leds/leds-nu801.c   | 396 +
 .../linux/ar71xx/files/include/linux/leds-nu801.h  |  38 ++
 target/linux/ar71xx/modules.mk |  16 +
 .../818-MIPS-ath79-add-nu801-led-driver.patch  |  26 ++
 5 files changed, 477 insertions(+), 1 deletion(-)
 create mode 100644 target/linux/ar71xx/files/drivers/leds/leds-nu801.c
 create mode 100644 target/linux/ar71xx/files/include/linux/leds-nu801.h
 create mode 100644 
target/linux/ar71xx/patches-4.1/818-MIPS-ath79-add-nu801-led-driver.patch

diff --git a/package/base-files/files/etc/init.d/led 
b/package/base-files/files/etc/init.d/led
index 3f45732..84cd028 100755
--- a/package/base-files/files/etc/init.d/led
+++ b/package/base-files/files/etc/init.d/led
@@ -44,7 +44,7 @@ load_led() {
ret="$?"
 
[ $default = 1 ] &&
-   echo 1 >/sys/class/leds/${sysfs}/brightness
+   cat /sys/class/leds/${sysfs}/max_brightness > 
/sys/class/leds/${sysfs}/brightness
 
[ $ret = 0 ] || {
echo >&2 "Skipping trigger '$trigger' for led '$name' 
due to missing kernel module"
diff --git a/target/linux/ar71xx/files/drivers/leds/leds-nu801.c 
b/target/linux/ar71xx/files/drivers/leds/leds-nu801.c
new file mode 100644
index 000..0dfc015
--- /dev/null
+++ b/target/linux/ar71xx/files/drivers/leds/leds-nu801.c
@@ -0,0 +1,396 @@
+/*
+ * LED driver for NU801
+ *
+ * Kevin Paul Herbert
+ * Copyright (c) 2012, Meraki, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#define MAX_NAME_LENGTH 24
+#define NUM_COLORS 3
+
+static const char * const led_nu801_colors[] = { "blue", "green", "red" };
+
+struct led_nu801_led_data {
+   struct led_classdev cdev;
+   struct led_nu801_data *controller;
+   enum led_brightness level;
+   char name[MAX_NAME_LENGTH];
+};
+
+struct led_nu801_data {
+   unsigned cki;
+   unsigned sdi;
+   int lei;
+   struct delayed_work work;
+   struct led_nu801_led_data *led_chain;
+   int num_leds;
+   const char *device_name;
+   const char *name;
+   u32 ndelay;
+   atomic_t pending;
+};
+
+static void led_nu801_work(struct work_struct *work)
+{
+   struct led_nu801_data   *controller =
+   container_of(work, struct led_nu801_data, work.work);
+   struct led_nu801_led_data *led;
+   u16 bit;
+   u16 brightness;
+   int index;
+
+   for (index = 0; index < controller->num_leds; index++) {
+   led = &controller->led_chain[index];
+   brightness = led->level << 8; /* To do: gamma correction */
+   for (bit = 0x8000; bit; bit = bit >> 1) {
+   gpio_set_value(controller->sdi,
+  (brightness & bit) != 0);
+   gpio_set_value(controller->cki, 1);
+   if (unlikely(((index == (controller->num_leds - 1)) &&
+ (bit == 1) &&
+ (controller->lei < 0 {
+   udelay(600);
+   } else {
+   ndelay(controller->ndelay);
+   }
+   gpio_set_value(controller->cki, 0);
+   ndelay(controller->ndelay);
+   }
+   }
+   if (controller->lei >= 0) {
+   gpio_set_value(controller->lei, 1);
+   ndelay(controller->ndelay);
+   gpio_set_value(controller->lei, 0);
+   }
+   atomic_set(&controller->pending, 1);
+}
+
+static void led_nu801_set(struct led_classdev *led_cdev,
+ enum led_brightness value)
+{
+   struct led_nu801_led_data *led_dat =
+   container_of(led_cdev, struct led_nu801_led_data, cdev);
+   struct led_nu801_data *controller = led_dat->controller;
+
+   if (led_dat->level != value) {
+   led_dat->level = value;
+   if (atomic_dec_and_test(&controller->pending))
+   schedule_delayed_work(&led_dat->controller->work,
+ (HZ/1000) + 1);
+   }
+}
+
+static int __init led_nu801_create(struct led_nu801_data *con

[OpenWrt-Devel] [RFC 5/5] ar71xx: add support for Cisco's MR18

2015-09-17 Thread Chris R Blake 
From: Chris R Blake 

This patch adds support for Cisco's MR18.
Detailed instructions for the flashing the device can
be found in the OpenWrt forum thread:
<https://forum.openwrt.org/viewtopic.php?id=59248>

Signed-off-by: Chris R Blake 
---
 package/base-files/files/lib/functions/system.sh   |  17 ++
 target/linux/ar71xx/base-files/etc/diag.sh |   3 +
 .../etc/hotplug.d/firmware/10-ath9k-eeprom |  39 +++-
 .../ar71xx/base-files/etc/uci-defaults/01_leds |   4 +
 .../ar71xx/base-files/etc/uci-defaults/02_network  |   1 +
 target/linux/ar71xx/base-files/lib/ar71xx.sh   |   3 +
 .../base-files/lib/preinit/05_set_iface_mac_ar71xx |   4 +
 .../ar71xx/base-files/lib/upgrade/merakinand.sh| 136 +++
 .../ar71xx/base-files/lib/upgrade/platform.sh  |   4 +
 target/linux/ar71xx/config-4.1 |   1 +
 .../linux/ar71xx/files/arch/mips/ath79/mach-mr18.c | 254 +
 target/linux/ar71xx/image/Makefile |  34 +++
 target/linux/ar71xx/nand/config-default|   1 +
 target/linux/ar71xx/nand/profiles/meraki.mk|  17 ++
 .../817-MIPS-ath79-add-meraki-mr18-support.patch   |  41 
 15 files changed, 558 insertions(+), 1 deletion(-)
 create mode 100644 target/linux/ar71xx/base-files/lib/upgrade/merakinand.sh
 create mode 100644 target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c
 create mode 100644 target/linux/ar71xx/nand/profiles/meraki.mk
 create mode 100644 
target/linux/ar71xx/patches-4.1/817-MIPS-ath79-add-meraki-mr18-support.patch

diff --git a/package/base-files/files/lib/functions/system.sh 
b/package/base-files/files/lib/functions/system.sh
index 8d75a5a..2f5d063 100644
--- a/package/base-files/files/lib/functions/system.sh
+++ b/package/base-files/files/lib/functions/system.sh
@@ -41,6 +41,23 @@ mtd_get_mac_binary() {
dd bs=1 skip=$offset count=6 if=$part 2>/dev/null | hexdump -v -n 6 -e 
'5/1 "%02x:" 1/1 "%02x"'
 }
 
+mtd_get_mac_binary_ubi() {
+   local mtdname="$1"
+   local offset="$2"
+
+   . /lib/upgrade/nand.sh
+
+   local ubidev=$(nand_find_ubi $CI_UBIPART)
+   local part="$(nand_find_volume $ubidev $mtdname)"
+
+   if [ -z "$part" ]; then
+   echo "mtd_get_mac_binary: ubi partition $mtdname not found!" >&2
+   return
+   fi
+
+   dd bs=1 skip=$offset count=6 if=/dev/$part 2>/dev/null | hexdump -v -n 
6 -e '5/1 "%02x:" 1/1 "%02x"'
+}
+
 mtd_get_part_size() {
local part_name=$1
local first dev size erasesize name
diff --git a/target/linux/ar71xx/base-files/etc/diag.sh 
b/target/linux/ar71xx/base-files/etc/diag.sh
index cfba6b4..d6cc23f 100644
--- a/target/linux/ar71xx/base-files/etc/diag.sh
+++ b/target/linux/ar71xx/base-files/etc/diag.sh
@@ -144,6 +144,9 @@ get_status_led() {
mr16)
status_led="mr16:green:power"
;;
+   mr18)
+   status_led="mr18:green:tricolor0"
+   ;;
mr600)
status_led="mr600:orange:power"
;;
diff --git 
a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom 
b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
index b5f0588..381ff55 100644
--- a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
+++ b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
@@ -9,11 +9,14 @@ ath9k_eeprom_extract() {
local part=$1
local offset=$2
local count=$3
+   local ubidev=$(nand_find_ubi $CI_UBIPART)
local mtd
 
mtd=$(find_mtd_chardev $part)
[ -n "$mtd" ] || \
-   ath9k_eeprom_die "no mtd device found for partition $part"
+   mtd="/dev/$(nand_find_volume $ubidev $part)"
+   [ -n "$mtd" ] || \
+   ath9k_eeprom_die "no mtd device found for partition 
$part"
 
dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 
2>/dev/null || \
ath9k_eeprom_die "failed to extract from $mtd"
@@ -29,15 +32,25 @@ ath9k_patch_firmware_mac() {
 
 [ -e /lib/firmware/$FIRMWARE ] && exit 0
 
+
 . /lib/ar71xx.sh
 . /lib/functions.sh
 . /lib/functions/system.sh
+. /lib/upgrade/nand.sh
 
 board=$(ar71xx_board_name)
 
 case "$FIRMWARE" in
 "soc_wmac.eeprom")
case $board in
+   mr18)
+   if [ -n "$(nand_find_volume ubi0 caldata)" ]; then
+   ath9k_eeprom_extract "caldata" 4096 2048
+   else
+   ath9k_eeprom_extract "odm-caldata" 4096 2048
+   fi
+   ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary_ubi 
board-config 102) +1)
+   ;;

[OpenWrt-Devel] [PATCH v4 5/5] ar71xx: add support for Cisco's MR18

2015-09-20 Thread Chris R Blake 
From: Chris R Blake 

This patch adds support for Cisco's MR18.
Detailed instructions for the flashing the device can
be found in the OpenWrt forum thread:
<https://forum.openwrt.org/viewtopic.php?id=59248>

Signed-off-by: Chris R Blake 
---
 package/base-files/files/etc/rc.button/reset   |   2 +-
 package/base-files/files/lib/functions/system.sh   |  17 ++
 target/linux/ar71xx/base-files/etc/diag.sh |   3 +
 .../etc/hotplug.d/firmware/10-ath9k-eeprom |  39 +++-
 .../ar71xx/base-files/etc/uci-defaults/01_leds |   4 +
 .../ar71xx/base-files/etc/uci-defaults/02_network  |   1 +
 target/linux/ar71xx/base-files/lib/ar71xx.sh   |   3 +
 .../base-files/lib/preinit/05_set_iface_mac_ar71xx |   4 +
 .../ar71xx/base-files/lib/upgrade/merakinand.sh| 137 +++
 .../ar71xx/base-files/lib/upgrade/platform.sh  |   7 +
 target/linux/ar71xx/config-4.1 |   1 +
 .../linux/ar71xx/files/arch/mips/ath79/mach-mr18.c | 254 +
 target/linux/ar71xx/image/Makefile |  34 +++
 target/linux/ar71xx/nand/config-default|   1 +
 target/linux/ar71xx/nand/profiles/meraki.mk|  17 ++
 .../817-MIPS-ath79-add-meraki-mr18-support.patch   |  41 
 16 files changed, 563 insertions(+), 2 deletions(-)
 create mode 100644 target/linux/ar71xx/base-files/lib/upgrade/merakinand.sh
 create mode 100644 target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c
 create mode 100644 target/linux/ar71xx/nand/profiles/meraki.mk
 create mode 100644 
target/linux/ar71xx/patches-4.1/817-MIPS-ath79-add-meraki-mr18-support.patch

diff --git a/package/base-files/files/etc/rc.button/reset 
b/package/base-files/files/etc/rc.button/reset
index c6dc7cf..f4fb9f0 100755
--- a/package/base-files/files/etc/rc.button/reset
+++ b/package/base-files/files/etc/rc.button/reset
@@ -19,7 +19,7 @@ released)
elif [ "$SEEN" -gt 5 ]
then
echo "FACTORY RESET" > /dev/console
-   jffs2reset -y && reboot &
+   jffs2reset -y && reboot -f &
fi
 ;;
 esac
diff --git a/package/base-files/files/lib/functions/system.sh 
b/package/base-files/files/lib/functions/system.sh
index 8d75a5a..928a429 100644
--- a/package/base-files/files/lib/functions/system.sh
+++ b/package/base-files/files/lib/functions/system.sh
@@ -41,6 +41,23 @@ mtd_get_mac_binary() {
dd bs=1 skip=$offset count=6 if=$part 2>/dev/null | hexdump -v -n 6 -e 
'5/1 "%02x:" 1/1 "%02x"'
 }
 
+mtd_get_mac_binary_ubi() {
+   local mtdname="$1"
+   local offset="$2"
+
+   . /lib/upgrade/nand.sh
+
+   local ubidev=$( nand_find_ubi $CI_UBIPART )
+   local part="$( nand_find_volume $ubidev $1 )"
+
+   if [ -z "$part" ]; then
+   echo "mtd_get_mac_binary: ubi partition $mtdname not found!" >&2
+   return
+   fi
+
+   dd bs=1 skip=$offset count=6 if=/dev/$part 2>/dev/null | hexdump -v -n 
6 -e '5/1 "%02x:" 1/1 "%02x"'
+}
+
 mtd_get_part_size() {
local part_name=$1
local first dev size erasesize name
diff --git a/target/linux/ar71xx/base-files/etc/diag.sh 
b/target/linux/ar71xx/base-files/etc/diag.sh
index cfba6b4..d6cc23f 100644
--- a/target/linux/ar71xx/base-files/etc/diag.sh
+++ b/target/linux/ar71xx/base-files/etc/diag.sh
@@ -144,6 +144,9 @@ get_status_led() {
mr16)
status_led="mr16:green:power"
;;
+   mr18)
+   status_led="mr18:green:tricolor0"
+   ;;
mr600)
status_led="mr600:orange:power"
;;
diff --git 
a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom 
b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
index b5f0588..e61bcfc 100644
--- a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
+++ b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
@@ -9,11 +9,14 @@ ath9k_eeprom_extract() {
local part=$1
local offset=$2
local count=$3
+   local ubidev=$( nand_find_ubi $CI_UBIPART )
local mtd
 
mtd=$(find_mtd_chardev $part)
[ -n "$mtd" ] || \
-   ath9k_eeprom_die "no mtd device found for partition $part"
+   mtd="/dev/$(nand_find_volume $ubidev $part)"
+   [ -n "$mtd" ] || \
+   ath9k_eeprom_die "no mtd device found for partition 
$part"
 
dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 
2>/dev/null || \
ath9k_eeprom_die "failed to extract from $mtd"
@@ -29,15 +32,25 @@ ath9k_patch_firmware_mac() {
 
 [ -e /lib/firmware/$FIRMWARE ] && exit 0
 
+
 . /lib/ar71xx.sh
 . /lib/func

[OpenWrt-Devel] [PATCH v4 4/5] ar71xx: add LED driver NU801

2015-09-20 Thread Chris R Blake 
From: Chris R Blake 

The MR18 uses a 3-channel 16-bit PWM Constant Current Driver
for its status LED.

Signed-off-by: Chris R Blake 
---
 package/base-files/files/etc/init.d/led|   2 +-
 .../linux/ar71xx/files/drivers/leds/leds-nu801.c   | 396 +
 .../linux/ar71xx/files/include/linux/leds-nu801.h  |  38 ++
 target/linux/ar71xx/modules.mk |  16 +
 .../818-MIPS-ath79-add-nu801-led-driver.patch  |  26 ++
 5 files changed, 477 insertions(+), 1 deletion(-)
 create mode 100644 target/linux/ar71xx/files/drivers/leds/leds-nu801.c
 create mode 100644 target/linux/ar71xx/files/include/linux/leds-nu801.h
 create mode 100644 
target/linux/ar71xx/patches-4.1/818-MIPS-ath79-add-nu801-led-driver.patch

diff --git a/package/base-files/files/etc/init.d/led 
b/package/base-files/files/etc/init.d/led
index 3f45732..84cd028 100755
--- a/package/base-files/files/etc/init.d/led
+++ b/package/base-files/files/etc/init.d/led
@@ -44,7 +44,7 @@ load_led() {
ret="$?"
 
[ $default = 1 ] &&
-   echo 1 >/sys/class/leds/${sysfs}/brightness
+   cat /sys/class/leds/${sysfs}/max_brightness > 
/sys/class/leds/${sysfs}/brightness
 
[ $ret = 0 ] || {
echo >&2 "Skipping trigger '$trigger' for led '$name' 
due to missing kernel module"
diff --git a/target/linux/ar71xx/files/drivers/leds/leds-nu801.c 
b/target/linux/ar71xx/files/drivers/leds/leds-nu801.c
new file mode 100644
index 000..0dfc015
--- /dev/null
+++ b/target/linux/ar71xx/files/drivers/leds/leds-nu801.c
@@ -0,0 +1,396 @@
+/*
+ * LED driver for NU801
+ *
+ * Kevin Paul Herbert
+ * Copyright (c) 2012, Meraki, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#define MAX_NAME_LENGTH 24
+#define NUM_COLORS 3
+
+static const char * const led_nu801_colors[] = { "blue", "green", "red" };
+
+struct led_nu801_led_data {
+   struct led_classdev cdev;
+   struct led_nu801_data *controller;
+   enum led_brightness level;
+   char name[MAX_NAME_LENGTH];
+};
+
+struct led_nu801_data {
+   unsigned cki;
+   unsigned sdi;
+   int lei;
+   struct delayed_work work;
+   struct led_nu801_led_data *led_chain;
+   int num_leds;
+   const char *device_name;
+   const char *name;
+   u32 ndelay;
+   atomic_t pending;
+};
+
+static void led_nu801_work(struct work_struct *work)
+{
+   struct led_nu801_data   *controller =
+   container_of(work, struct led_nu801_data, work.work);
+   struct led_nu801_led_data *led;
+   u16 bit;
+   u16 brightness;
+   int index;
+
+   for (index = 0; index < controller->num_leds; index++) {
+   led = &controller->led_chain[index];
+   brightness = led->level << 8; /* To do: gamma correction */
+   for (bit = 0x8000; bit; bit = bit >> 1) {
+   gpio_set_value(controller->sdi,
+  (brightness & bit) != 0);
+   gpio_set_value(controller->cki, 1);
+   if (unlikely(((index == (controller->num_leds - 1)) &&
+ (bit == 1) &&
+ (controller->lei < 0 {
+   udelay(600);
+   } else {
+   ndelay(controller->ndelay);
+   }
+   gpio_set_value(controller->cki, 0);
+   ndelay(controller->ndelay);
+   }
+   }
+   if (controller->lei >= 0) {
+   gpio_set_value(controller->lei, 1);
+   ndelay(controller->ndelay);
+   gpio_set_value(controller->lei, 0);
+   }
+   atomic_set(&controller->pending, 1);
+}
+
+static void led_nu801_set(struct led_classdev *led_cdev,
+ enum led_brightness value)
+{
+   struct led_nu801_led_data *led_dat =
+   container_of(led_cdev, struct led_nu801_led_data, cdev);
+   struct led_nu801_data *controller = led_dat->controller;
+
+   if (led_dat->level != value) {
+   led_dat->level = value;
+   if (atomic_dec_and_test(&controller->pending))
+   schedule_delayed_work(&led_dat->controller->work,
+ (HZ/1000) + 1);
+   }
+}
+
+static int __init led_nu801_create(struct led_nu801_data *con

[OpenWrt-Devel] [PATCH v4 1/5] ar71xx: add eth rx delay for qca955x platforms

2015-09-20 Thread Chris R Blake 
From: Chris R Blake 

This patch is to add support for qca955x_eth_rx_delay
to work with the qca955x SoC.

Signed-off-by: Chris R Blake 
---
 ...42-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch | 58 ++
 1 file changed, 58 insertions(+)
 create mode 100644 
target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch

diff --git 
a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch
 
b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch
new file mode 100644
index 000..75e216e
--- /dev/null
+++ 
b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch
@@ -0,0 +1,58 @@
+--- a/arch/mips/ath79/dev-eth.c
 b/arch/mips/ath79/dev-eth.c
+@@ -823,6 +825,32 @@
+   iounmap(base);
+ }
+
++void __init ath79_setup_qca955x_eth_rx_delay(unsigned int rxd,
++unsigned int rxdv)
++{
++  void __iomem *base;
++  u32 t;
++
++  rxd &= QCA955X_ETH_CFG_RXD_DELAY_MASK;
++  rxdv &= QCA955X_ETH_CFG_RDV_DELAY_MASK;
++
++  base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
++
++  t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
++
++  t &= ~(QCA955X_ETH_CFG_RXD_DELAY_MASK << 
QCA955X_ETH_CFG_RXD_DELAY_SHIFT |
++ QCA955X_ETH_CFG_RDV_DELAY_MASK << 
QCA955X_ETH_CFG_RDV_DELAY_SHIFT);
++
++  t |= (rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT |
++rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT);
++
++  __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
++  /* flush write */
++  __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
++
++  iounmap(base);
++}
++
+ static int ath79_eth_instance __initdata;
+ void __init ath79_register_eth(unsigned int id)
+ {
+--- a/arch/mips/ath79/dev-eth.h
 b/arch/mips/ath79/dev-eth.h
+@@ -49,5 +49,6 @@
+ void ath79_setup_ar934x_eth_cfg(u32 mask);
+ void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
+ void ath79_setup_qca955x_eth_cfg(u32 mask);
++void ath79_setup_qca955x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
+
+ #endif /* _ATH79_DEV_ETH_H */
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1098,5 +1098,11 @@
+
+ #define QCA955X_ETH_CFG_RGMII_EN  BIT(0)
+ #define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
++#define QCA955X_ETH_CFG_RXD_DELAY BIT(14)
++#define QCA955X_ETH_CFG_RXD_DELAY_MASK0x3
++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT   14
++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
++#define QCA955X_ETH_CFG_RDV_DELAY_MASK0x3
++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT   16
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
-- 
2.5.3
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[OpenWrt-Devel] [PATCH v4 2/5] ar71xx: add support for qca955x sgmii/serdes calibration

2015-09-20 Thread Chris R Blake 
From: Chris R Blake 

This patch is to add support for sgmii/serdes calibration from
within the OpenWRT environment. This is needed on boards that
do not use u-boot or do not have a pre-init process that runs
calibration.

Signed-off-by: Chris R Blake 
---
 ...S-ath79-add-qca955x-mac-sgmii-calibration.patch | 82 ++
 1 file changed, 82 insertions(+)
 create mode 100644 
target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch

diff --git 
a/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch
 
b/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch
new file mode 100644
index 000..eb7c5de
--- /dev/null
+++ 
b/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch
@@ -0,0 +1,82 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h   2015-08-05 
12:58:15.580496899 +0200
 b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h   2015-08-05 
13:52:32.590857293 +0200
+@@ -360,6 +360,7 @@
+ #define QCA955X_PLL_CLK_CTRL_REG  0x08
+ #define QCA955X_PLL_ETH_XMII_CONTROL_REG  0x28
+ #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
++#define QCA955X_PLL_ETH_SGMII_SERDES_REG  0x4c
+
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+@@ -392,6 +393,10 @@
+ #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL   BIT(21)
+ #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL   BIT(24)
+
++#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT  BIT(2)
++#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK   BIT(1)
++#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL   BIT(0)
++
+ #define QCA956X_PLL_CPU_CONFIG_REG0x00
+ #define QCA956X_PLL_CPU_CONFIG1_REG   0x04
+ #define QCA956X_PLL_DDR_CONFIG_REG0x08
+@@ -1104,5 +1109,11 @@
+ #define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
+ #define QCA955X_ETH_CFG_RDV_DELAY_MASK0x3
+ #define QCA955X_ETH_CFG_RDV_DELAY_SHIFT   16
++
++#define QCA955X_GMAC_REG_SGMII_SERDES 0x0018
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION  BIT(23)
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT23
++#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS   BIT(15)
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
+--- a/arch/mips/ath79/dev-eth.c2015-08-05 14:17:25.757504251 +0200
 b/arch/mips/ath79/dev-eth.c2015-08-05 14:09:54.716333554 +0200
+@@ -849,6 +849,37 @@ void __init ath79_setup_qca955x_eth_rx_d
+   iounmap(base);
+ }
+
++void __init ath79_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value)
++{
++  void __iomem *ethbase, *pllbase;
++  u32 t;
++
++  ethbase = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
++  pllbase = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
++
++  /* To Check the locking of the SGMII PLL */
++  t = __raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES);
++  t &= ~(QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK <<
++ QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT);
++  t |= (sgmii_value & QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK) <<
++   QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT;
++  __raw_writel(t, ethbase + QCA955X_GMAC_REG_SGMII_SERDES);
++
++  __raw_writel(QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT |
++   QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK |
++   QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL,
++   pllbase + QCA955X_PLL_ETH_SGMII_SERDES_REG);
++
++  ath79_device_reset_clear(QCA955X_RESET_SGMII_ANALOG);
++  ath79_device_reset_clear(QCA955X_RESET_SGMII);
++
++  while (!(__raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES) &
++  QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS));
++
++  iounmap(ethbase);
++  iounmap(pllbase);
++}
++
+ static int ath79_eth_instance __initdata;
+ void __init ath79_register_eth(unsigned int id)
+ {
+--- a/arch/mips/ath79/dev-eth.h2015-08-05 14:17:25.757504251 +0200
 b/arch/mips/ath79/dev-eth.h2015-08-05 13:58:20.292866210 +0200
+@@ -50,5 +50,6 @@ void ath79_setup_ar934x_eth_cfg(u32 mask
+ void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
+ void ath79_setup_qca955x_eth_cfg(u32 mask);
+ void ath79_setup_qca955x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
++void ath79_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value);
+
+ #endif /* _ATH79_DEV_ETH_H */
-- 
2.5.3
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[OpenWrt-Devel] [PATCH v3 1/2] ar71xx: Add ath79_register_m25p80_large to support >16MB SPI chips

2015-09-22 Thread Chris R Blake 
From: Chris R Blake 

The following patch is to add ath79_register_m25p80_large, which sets
is_flash to false to support bit banging. This is needed on some 32MB+
SPI chips, such as the S25FL256S1

Signed-off-by: Chris R Blake 
---
 target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c | 8 
 target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c 
b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c
index 9323b31..e5831d4 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c
@@ -106,6 +106,14 @@ static void add_mtd_concat_notifier(void)
register_mtd_user(¬);
 }
 
+void __init ath79_register_m25p80_large(struct flash_platform_data *pdata)
+{
+   ath79_spi_data.bus_num = 0;
+   ath79_spi_data.num_chipselect = 1;
+   ath79_spi0_cdata.is_flash = false;
+   ath79_spi_info[0].platform_data = pdata;
+   ath79_register_spi(&ath79_spi_data, ath79_spi_info, 1);
+}
 
 void __init ath79_register_m25p80_multi(struct flash_platform_data *pdata)
 {
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h 
b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h
index 637b41a..5e66016 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h
@@ -12,6 +12,7 @@
 #include 
 
 void ath79_register_m25p80(struct flash_platform_data *pdata) __init;
+void ath79_register_m25p80_large(struct flash_platform_data *pdata) __init;
 void ath79_register_m25p80_multi(struct flash_platform_data *pdata) __init;
 
 #endif /* _ATH79_DEV_M25P80_H */
-- 
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[OpenWrt-Devel] [PATCH v3 2/2] ar71xx: Add support for AirTight Networks C-55

2015-09-22 Thread Chris R Blake 
From: Chris R Blake 

This patch is to add support for the AirTight Networks C-55 Access Point

Signed-off-by: Chris R Blake 
---
 target/linux/ar71xx/base-files/etc/diag.sh |   3 +
 .../etc/hotplug.d/firmware/10-ath9k-eeprom |   8 ++
 .../ar71xx/base-files/etc/uci-defaults/01_leds |   6 +
 .../ar71xx/base-files/etc/uci-defaults/02_network  |   1 +
 target/linux/ar71xx/base-files/lib/ar71xx.sh   |   3 +
 .../base-files/lib/preinit/05_set_iface_mac_ar71xx |   5 +-
 .../ar71xx/base-files/lib/upgrade/platform.sh  |   1 +
 target/linux/ar71xx/config-4.1 |   1 +
 .../linux/ar71xx/files/arch/mips/ath79/mach-c55.c  | 132 +
 target/linux/ar71xx/generic/profiles/airtight.mk   |  17 +++
 target/linux/ar71xx/image/Makefile |   2 +
 .../817-MIPS-ath79-add-at-c55-support.patch|  39 ++
 12 files changed, 217 insertions(+), 1 deletion(-)
 create mode 100644 target/linux/ar71xx/files/arch/mips/ath79/mach-c55.c
 create mode 100644 target/linux/ar71xx/generic/profiles/airtight.mk
 create mode 100644 
target/linux/ar71xx/patches-4.1/817-MIPS-ath79-add-at-c55-support.patch

diff --git a/target/linux/ar71xx/base-files/etc/diag.sh 
b/target/linux/ar71xx/base-files/etc/diag.sh
index cfba6b4..5773186 100644
--- a/target/linux/ar71xx/base-files/etc/diag.sh
+++ b/target/linux/ar71xx/base-files/etc/diag.sh
@@ -53,6 +53,9 @@ get_status_led() {
bxu2000n-2-a1)
status_led="bhu:green:status"
;;
+   c-55)
+   status_led="c-55:green:pwr"
+   ;;
cap4200ag)
status_led="senao:green:pwr"
;;
diff --git 
a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom 
b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
index b5f0588..af94cae 100644
--- a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
+++ b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
@@ -38,6 +38,10 @@ board=$(ar71xx_board_name)
 case "$FIRMWARE" in
 "soc_wmac.eeprom")
case $board in
+   c-55)
+   ath9k_eeprom_extract "art" 4096 2048
+   ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary art 
0) +1)
+   ;;
r6100 | \
wndr3700v4 | \
wndr4300)
@@ -52,6 +56,10 @@ case "$FIRMWARE" in
 
 "pci_wmac0.eeprom")
case $board in
+   c-55)
+   ath9k_eeprom_extract "art" 20480 2048
+   ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary art 
0) +2)
+   ;;
wndr3700v4 | \
wndr4300)
ath9k_eeprom_extract "caldata" 20480 2048
diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds 
b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
index fac4751..d9e45bd 100644
--- a/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
+++ b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
@@ -85,6 +85,12 @@ bxu2000n-2-a1)
ucidef_set_led_wlan "wlan" "WLAN" "bhu:green:wlan" "phy0tpt"
;;
 
+c-55)
+   ucidef_set_led_netdev "lan_green" "LAN_GREEN" "c-55:green:lan" "eth0"
+   ucidef_set_led_wlan "wlan_amber" "WLAN_AMBER" "c-55:amber:wlan" 
"phy0tpt"
+   ucidef_set_led_wlan "wlan_green" "WLAN_GREEN" "c-55:green:wlan" 
"phy1tpt"
+   ;;
+
 cap4200ag)
ucidef_set_led_default "lan_green" "LAN_GREEN" "senao:green:lan" "1"
ucidef_set_led_wlan "wlan_amber" "WLAN_AMBER" "senao:amber:wlan" 
"phy0tpt"
diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network 
b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
index 880953c..d0e1847 100644
--- a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
+++ b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
@@ -341,6 +341,7 @@ dlan-pro-1200-ac)
 all0305 |\
 aw-nr580 |\
 bullet-m |\
+c-55 |\
 cap4200ag |\
 eap300v2 |\
 eap7660d |\
diff --git a/target/linux/ar71xx/base-files/lib/ar71xx.sh 
b/target/linux/ar71xx/base-files/lib/ar71xx.sh
index efb3d16..1174995 100755
--- a/target/linux/ar71xx/base-files/lib/ar71xx.sh
+++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh
@@ -398,6 +398,9 @@ ar71xx_board_detect() {
*AW-NR580)
name="aw-nr580"
;;
+   *C-55)
+   name="c-55"
+   ;;
*CAP4200AG)
name="cap4200ag"
;;
diff --git a/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx 
b/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar7

[OpenWrt-Devel] [PATCH v5 5/5] ar71xx: add support for Cisco's MR18

2015-09-22 Thread Chris R Blake 
From: Chris R Blake 

This patch adds support for Cisco's MR18.
Detailed instructions for the flashing the device can
be found in the OpenWrt forum thread:
<https://forum.openwrt.org/viewtopic.php?id=59248>

Signed-off-by: Chris R Blake 
---
 package/base-files/files/lib/functions/system.sh   |  17 ++
 target/linux/ar71xx/base-files/etc/diag.sh |   3 +
 .../etc/hotplug.d/firmware/10-ath9k-eeprom |  38 ++-
 .../ar71xx/base-files/etc/uci-defaults/01_leds |   4 +
 .../ar71xx/base-files/etc/uci-defaults/02_network  |   1 +
 target/linux/ar71xx/base-files/lib/ar71xx.sh   |   3 +
 .../base-files/lib/preinit/05_set_iface_mac_ar71xx |   4 +
 .../ar71xx/base-files/lib/upgrade/merakinand.sh| 137 +++
 .../ar71xx/base-files/lib/upgrade/platform.sh  |   7 +
 target/linux/ar71xx/config-4.1 |   1 +
 .../linux/ar71xx/files/arch/mips/ath79/mach-mr18.c | 254 +
 target/linux/ar71xx/image/Makefile |  34 +++
 target/linux/ar71xx/nand/config-default|   1 +
 target/linux/ar71xx/nand/profiles/meraki.mk|  17 ++
 .../817-MIPS-ath79-add-meraki-mr18-support.patch   |  41 
 15 files changed, 561 insertions(+), 1 deletion(-)
 create mode 100644 target/linux/ar71xx/base-files/lib/upgrade/merakinand.sh
 create mode 100644 target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c
 create mode 100644 target/linux/ar71xx/nand/profiles/meraki.mk
 create mode 100644 
target/linux/ar71xx/patches-4.1/817-MIPS-ath79-add-meraki-mr18-support.patch

diff --git a/package/base-files/files/lib/functions/system.sh 
b/package/base-files/files/lib/functions/system.sh
index 8d75a5a..928a429 100644
--- a/package/base-files/files/lib/functions/system.sh
+++ b/package/base-files/files/lib/functions/system.sh
@@ -41,6 +41,23 @@ mtd_get_mac_binary() {
dd bs=1 skip=$offset count=6 if=$part 2>/dev/null | hexdump -v -n 6 -e 
'5/1 "%02x:" 1/1 "%02x"'
 }
 
+mtd_get_mac_binary_ubi() {
+   local mtdname="$1"
+   local offset="$2"
+
+   . /lib/upgrade/nand.sh
+
+   local ubidev=$( nand_find_ubi $CI_UBIPART )
+   local part="$( nand_find_volume $ubidev $1 )"
+
+   if [ -z "$part" ]; then
+   echo "mtd_get_mac_binary: ubi partition $mtdname not found!" >&2
+   return
+   fi
+
+   dd bs=1 skip=$offset count=6 if=/dev/$part 2>/dev/null | hexdump -v -n 
6 -e '5/1 "%02x:" 1/1 "%02x"'
+}
+
 mtd_get_part_size() {
local part_name=$1
local first dev size erasesize name
diff --git a/target/linux/ar71xx/base-files/etc/diag.sh 
b/target/linux/ar71xx/base-files/etc/diag.sh
index cfba6b4..d6cc23f 100644
--- a/target/linux/ar71xx/base-files/etc/diag.sh
+++ b/target/linux/ar71xx/base-files/etc/diag.sh
@@ -144,6 +144,9 @@ get_status_led() {
mr16)
status_led="mr16:green:power"
;;
+   mr18)
+   status_led="mr18:green:tricolor0"
+   ;;
mr600)
status_led="mr600:orange:power"
;;
diff --git 
a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom 
b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
index b5f0588..bfab8bb 100644
--- a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
+++ b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
@@ -9,11 +9,14 @@ ath9k_eeprom_extract() {
local part=$1
local offset=$2
local count=$3
+   local ubidev=$( nand_find_ubi $CI_UBIPART )
local mtd
 
mtd=$(find_mtd_chardev $part)
[ -n "$mtd" ] || \
-   ath9k_eeprom_die "no mtd device found for partition $part"
+   mtd="/dev/$(nand_find_volume $ubidev $part)"
+   [ -n "$mtd" ] || \
+   ath9k_eeprom_die "no mtd device found for partition 
$part"
 
dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 
2>/dev/null || \
ath9k_eeprom_die "failed to extract from $mtd"
@@ -32,12 +35,21 @@ ath9k_patch_firmware_mac() {
 . /lib/ar71xx.sh
 . /lib/functions.sh
 . /lib/functions/system.sh
+. /lib/upgrade/nand.sh
 
 board=$(ar71xx_board_name)
 
 case "$FIRMWARE" in
 "soc_wmac.eeprom")
case $board in
+   mr18)
+   if [ -n "$(nand_find_volume ubi0 caldata)" ]; then
+   ath9k_eeprom_extract "caldata" 4096 2048
+   else
+   ath9k_eeprom_extract "odm-caldata" 4096 2048
+   fi
+   ath9k_patch_firmware_mac $(macaddr_add $(mtd_get_mac_binary_ubi 
board-config 102) +1)
+   ;;
r6100 | \
wndr3700

[OpenWrt-Devel] [PATCH v5 1/5] ar71xx: add eth rx delay for qca955x platforms

2015-09-22 Thread Chris R Blake 
From: Chris R Blake 

This patch is to add support for qca955x_eth_rx_delay
to work with the qca955x SoC.

Signed-off-by: Chris R Blake 
---
 ...42-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch | 58 ++
 1 file changed, 58 insertions(+)
 create mode 100644 
target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch

diff --git 
a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch
 
b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch
new file mode 100644
index 000..75e216e
--- /dev/null
+++ 
b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch
@@ -0,0 +1,58 @@
+--- a/arch/mips/ath79/dev-eth.c
 b/arch/mips/ath79/dev-eth.c
+@@ -823,6 +825,32 @@
+   iounmap(base);
+ }
+
++void __init ath79_setup_qca955x_eth_rx_delay(unsigned int rxd,
++unsigned int rxdv)
++{
++  void __iomem *base;
++  u32 t;
++
++  rxd &= QCA955X_ETH_CFG_RXD_DELAY_MASK;
++  rxdv &= QCA955X_ETH_CFG_RDV_DELAY_MASK;
++
++  base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
++
++  t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
++
++  t &= ~(QCA955X_ETH_CFG_RXD_DELAY_MASK << 
QCA955X_ETH_CFG_RXD_DELAY_SHIFT |
++ QCA955X_ETH_CFG_RDV_DELAY_MASK << 
QCA955X_ETH_CFG_RDV_DELAY_SHIFT);
++
++  t |= (rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT |
++rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT);
++
++  __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
++  /* flush write */
++  __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
++
++  iounmap(base);
++}
++
+ static int ath79_eth_instance __initdata;
+ void __init ath79_register_eth(unsigned int id)
+ {
+--- a/arch/mips/ath79/dev-eth.h
 b/arch/mips/ath79/dev-eth.h
+@@ -49,5 +49,6 @@
+ void ath79_setup_ar934x_eth_cfg(u32 mask);
+ void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
+ void ath79_setup_qca955x_eth_cfg(u32 mask);
++void ath79_setup_qca955x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
+
+ #endif /* _ATH79_DEV_ETH_H */
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1098,5 +1098,11 @@
+
+ #define QCA955X_ETH_CFG_RGMII_EN  BIT(0)
+ #define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
++#define QCA955X_ETH_CFG_RXD_DELAY BIT(14)
++#define QCA955X_ETH_CFG_RXD_DELAY_MASK0x3
++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT   14
++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
++#define QCA955X_ETH_CFG_RDV_DELAY_MASK0x3
++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT   16
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
-- 
2.5.3
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[OpenWrt-Devel] [PATCH v5 4/5] ar71xx: add LED driver NU801

2015-09-22 Thread Chris R Blake 
From: Chris R Blake 

The MR18 uses a 3-channel 16-bit PWM Constant Current Driver
for its status LED.

Signed-off-by: Chris R Blake 
---
 package/base-files/files/etc/init.d/led|   2 +-
 .../linux/ar71xx/files/drivers/leds/leds-nu801.c   | 396 +
 .../linux/ar71xx/files/include/linux/leds-nu801.h  |  38 ++
 target/linux/ar71xx/modules.mk |  16 +
 .../818-MIPS-ath79-add-nu801-led-driver.patch  |  26 ++
 5 files changed, 477 insertions(+), 1 deletion(-)
 create mode 100644 target/linux/ar71xx/files/drivers/leds/leds-nu801.c
 create mode 100644 target/linux/ar71xx/files/include/linux/leds-nu801.h
 create mode 100644 
target/linux/ar71xx/patches-4.1/818-MIPS-ath79-add-nu801-led-driver.patch

diff --git a/package/base-files/files/etc/init.d/led 
b/package/base-files/files/etc/init.d/led
index 3f45732..84cd028 100755
--- a/package/base-files/files/etc/init.d/led
+++ b/package/base-files/files/etc/init.d/led
@@ -44,7 +44,7 @@ load_led() {
ret="$?"
 
[ $default = 1 ] &&
-   echo 1 >/sys/class/leds/${sysfs}/brightness
+   cat /sys/class/leds/${sysfs}/max_brightness > 
/sys/class/leds/${sysfs}/brightness
 
[ $ret = 0 ] || {
echo >&2 "Skipping trigger '$trigger' for led '$name' 
due to missing kernel module"
diff --git a/target/linux/ar71xx/files/drivers/leds/leds-nu801.c 
b/target/linux/ar71xx/files/drivers/leds/leds-nu801.c
new file mode 100644
index 000..0dfc015
--- /dev/null
+++ b/target/linux/ar71xx/files/drivers/leds/leds-nu801.c
@@ -0,0 +1,396 @@
+/*
+ * LED driver for NU801
+ *
+ * Kevin Paul Herbert
+ * Copyright (c) 2012, Meraki, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#define MAX_NAME_LENGTH 24
+#define NUM_COLORS 3
+
+static const char * const led_nu801_colors[] = { "blue", "green", "red" };
+
+struct led_nu801_led_data {
+   struct led_classdev cdev;
+   struct led_nu801_data *controller;
+   enum led_brightness level;
+   char name[MAX_NAME_LENGTH];
+};
+
+struct led_nu801_data {
+   unsigned cki;
+   unsigned sdi;
+   int lei;
+   struct delayed_work work;
+   struct led_nu801_led_data *led_chain;
+   int num_leds;
+   const char *device_name;
+   const char *name;
+   u32 ndelay;
+   atomic_t pending;
+};
+
+static void led_nu801_work(struct work_struct *work)
+{
+   struct led_nu801_data   *controller =
+   container_of(work, struct led_nu801_data, work.work);
+   struct led_nu801_led_data *led;
+   u16 bit;
+   u16 brightness;
+   int index;
+
+   for (index = 0; index < controller->num_leds; index++) {
+   led = &controller->led_chain[index];
+   brightness = led->level << 8; /* To do: gamma correction */
+   for (bit = 0x8000; bit; bit = bit >> 1) {
+   gpio_set_value(controller->sdi,
+  (brightness & bit) != 0);
+   gpio_set_value(controller->cki, 1);
+   if (unlikely(((index == (controller->num_leds - 1)) &&
+ (bit == 1) &&
+ (controller->lei < 0 {
+   udelay(600);
+   } else {
+   ndelay(controller->ndelay);
+   }
+   gpio_set_value(controller->cki, 0);
+   ndelay(controller->ndelay);
+   }
+   }
+   if (controller->lei >= 0) {
+   gpio_set_value(controller->lei, 1);
+   ndelay(controller->ndelay);
+   gpio_set_value(controller->lei, 0);
+   }
+   atomic_set(&controller->pending, 1);
+}
+
+static void led_nu801_set(struct led_classdev *led_cdev,
+ enum led_brightness value)
+{
+   struct led_nu801_led_data *led_dat =
+   container_of(led_cdev, struct led_nu801_led_data, cdev);
+   struct led_nu801_data *controller = led_dat->controller;
+
+   if (led_dat->level != value) {
+   led_dat->level = value;
+   if (atomic_dec_and_test(&controller->pending))
+   schedule_delayed_work(&led_dat->controller->work,
+ (HZ/1000) + 1);
+   }
+}
+
+static int __init led_nu801_create(struct led_nu801_data *con

[OpenWrt-Devel] [PATCH v5 2/5] ar71xx: add support for qca955x sgmii/serdes calibration

2015-09-22 Thread Chris R Blake 
From: Chris R Blake 

This patch is to add support for sgmii/serdes calibration from
within the OpenWRT environment. This is needed on boards that
do not use u-boot or do not have a pre-init process that runs
calibration.

Signed-off-by: Chris R Blake 
---
 ...S-ath79-add-qca955x-mac-sgmii-calibration.patch | 82 ++
 1 file changed, 82 insertions(+)
 create mode 100644 
target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch

diff --git 
a/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch
 
b/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch
new file mode 100644
index 000..eb7c5de
--- /dev/null
+++ 
b/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch
@@ -0,0 +1,82 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h   2015-08-05 
12:58:15.580496899 +0200
 b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h   2015-08-05 
13:52:32.590857293 +0200
+@@ -360,6 +360,7 @@
+ #define QCA955X_PLL_CLK_CTRL_REG  0x08
+ #define QCA955X_PLL_ETH_XMII_CONTROL_REG  0x28
+ #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
++#define QCA955X_PLL_ETH_SGMII_SERDES_REG  0x4c
+
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+@@ -392,6 +393,10 @@
+ #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL   BIT(21)
+ #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL   BIT(24)
+
++#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT  BIT(2)
++#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK   BIT(1)
++#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL   BIT(0)
++
+ #define QCA956X_PLL_CPU_CONFIG_REG0x00
+ #define QCA956X_PLL_CPU_CONFIG1_REG   0x04
+ #define QCA956X_PLL_DDR_CONFIG_REG0x08
+@@ -1104,5 +1109,11 @@
+ #define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
+ #define QCA955X_ETH_CFG_RDV_DELAY_MASK0x3
+ #define QCA955X_ETH_CFG_RDV_DELAY_SHIFT   16
++
++#define QCA955X_GMAC_REG_SGMII_SERDES 0x0018
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION  BIT(23)
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT23
++#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS   BIT(15)
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
+--- a/arch/mips/ath79/dev-eth.c2015-08-05 14:17:25.757504251 +0200
 b/arch/mips/ath79/dev-eth.c2015-08-05 14:09:54.716333554 +0200
+@@ -849,6 +849,37 @@ void __init ath79_setup_qca955x_eth_rx_d
+   iounmap(base);
+ }
+
++void __init ath79_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value)
++{
++  void __iomem *ethbase, *pllbase;
++  u32 t;
++
++  ethbase = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
++  pllbase = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
++
++  /* To Check the locking of the SGMII PLL */
++  t = __raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES);
++  t &= ~(QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK <<
++ QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT);
++  t |= (sgmii_value & QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK) <<
++   QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT;
++  __raw_writel(t, ethbase + QCA955X_GMAC_REG_SGMII_SERDES);
++
++  __raw_writel(QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT |
++   QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK |
++   QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL,
++   pllbase + QCA955X_PLL_ETH_SGMII_SERDES_REG);
++
++  ath79_device_reset_clear(QCA955X_RESET_SGMII_ANALOG);
++  ath79_device_reset_clear(QCA955X_RESET_SGMII);
++
++  while (!(__raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES) &
++  QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS));
++
++  iounmap(ethbase);
++  iounmap(pllbase);
++}
++
+ static int ath79_eth_instance __initdata;
+ void __init ath79_register_eth(unsigned int id)
+ {
+--- a/arch/mips/ath79/dev-eth.h2015-08-05 14:17:25.757504251 +0200
 b/arch/mips/ath79/dev-eth.h2015-08-05 13:58:20.292866210 +0200
+@@ -50,5 +50,6 @@ void ath79_setup_ar934x_eth_cfg(u32 mask
+ void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
+ void ath79_setup_qca955x_eth_cfg(u32 mask);
+ void ath79_setup_qca955x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
++void ath79_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value);
+
+ #endif /* _ATH79_DEV_ETH_H */
-- 
2.5.3
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