Re: [OpenWrt-Devel] Dualradio 2.4/5GHz ath9k-Hardware which is deliverable?
* Etienne Champetier [02.07.2015 10:51]: > > is 2.4+5ghz ath9k really outdated? bye, bastian > > maybe you can explain why only ath9k (mesh? binary blob?) We like on 4 things: - ratecontrol in userspace (minstrel) - powercontrol in userspace (not upstream yet) - IBSS/adhoc together with AP-mode - a working driver (ath10k is far away from that) bye, bastian ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] alternative for "pyserial+python-mini"
Come on guys help me out with Python wiki page, it looks like I know much less about python that you and I'm the only one documenting this which is bad :) Take a look at latest version: http://wiki.openwrt.org/doc/software/python On 27 June 2015 at 22:42, Christian Mehlis wrote: > Am 26.06.2015 um 14:57 schrieb valent.turko...@gmail.com: >> >> Does micro-python have some alternative or replacement for pyserial? > > > you can use stty[1] from busybox to configure the tty. > After that every program can use regular read/write calls... > > [1] http://unixhelp.ed.ac.uk/CGI/man-cgi?stty > > Best > Christian > > ___ > openwrt-devel mailing list > openwrt-devel@lists.openwrt.org > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH 1/2] ar71xx: rework patch for qca953x/956x
On 2 July 2015 at 09:49, wrote:
> From: Miaoqing Pan
>
> Patch cherry-picked from the following location:
> https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e
>
> Changelist,
> - add more register defines
> - add EHCI support
> - fix GPIO pin count to 18
> - fix chained irq disabled
> - fix GMAC0/GMAC1 initial
> - fix WMAC irq number to 47
> - merge the changes of dev-eth.c from the patch to file.
>
> Signed-off-by: Miaoqing Pan
> ---
> .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 18 +-
> ...07-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 352
> +
> ...35-MIPS-ath79-add-support-for-QCA956x-SoC.patch | 183 ---
> .../736-MIPS-ath79-fix-chained-irq-disable.patch | 21 +-
> 4 files changed, 387 insertions(+), 187 deletions(-)
>
> diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
> b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
> index ae3db4c..ff94e2e 100644
> --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
> +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
> @@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned int id, u32
> phy_mask)
> case ATH79_SOC_AR9330:
> case ATH79_SOC_AR9331:
> case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> mdio_dev = &ath79_mdio1_device;
> mdio_data = &ath79_mdio1_data;
> break;
> @@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned int id, u32
> phy_mask)
> break;
>
> case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> mdio_data->builtin_switch = 1;
> break;
>
> @@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_data(unsigned int
> id)
> case ATH79_SOC_QCA9533:
> case ATH79_SOC_QCA9556:
> case ATH79_SOC_QCA9558:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> pll_10 = AR934X_PLL_VAL_10;
> pll_100 = AR934X_PLL_VAL_100;
> pll_1000 = AR934X_PLL_VAL_1000;
> @@ -627,6 +633,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
> case ATH79_SOC_AR9330:
> case ATH79_SOC_AR9331:
> case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
> break;
>
> @@ -687,7 +695,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
> case ATH79_SOC_AR7241:
> case ATH79_SOC_AR9330:
> case ATH79_SOC_AR9331:
> - case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
> break;
>
> @@ -697,6 +706,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
> case ATH79_SOC_AR9341:
> case ATH79_SOC_AR9342:
> case ATH79_SOC_AR9344:
> + case ATH79_SOC_QCA9533:
> switch (pdata->phy_if_mode) {
> case PHY_INTERFACE_MODE_MII:
> case PHY_INTERFACE_MODE_GMII:
> @@ -986,6 +996,7 @@ void __init ath79_register_eth(unsigned int id)
> case ATH79_SOC_AR9341:
> case ATH79_SOC_AR9342:
> case ATH79_SOC_AR9344:
> + case ATH79_SOC_QCA9533:
> if (id == 0) {
> pdata->reset_bit = AR934X_RESET_GE0_MAC |
>AR934X_RESET_GE0_MDIO;
> @@ -1017,7 +1028,8 @@ void __init ath79_register_eth(unsigned int id)
> pdata->fifo_cfg3 = 0x01f00140;
> break;
>
> - case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> if (id == 0) {
> pdata->reset_bit = AR933X_RESET_GE0_MAC |
>AR933X_RESET_GE0_MDIO;
> @@ -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned int id)
> case ATH79_SOC_AR9330:
> case ATH79_SOC_AR9331:
> case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> pdata->mii_bus_dev = &ath79_mdio1_device.dev;
> break;
>
This will not work for e.g. qca9563 (which has the same id as QCA9561)
because it has single ethernet MAC (GMAC0) which works in SGMII mode
only.
I have several patches regarding qca ethernet in my queue. Not sure
they are correct for 100% cases but will submit them for evaluation.
Regards,
Roman
__
Re: [OpenWrt-Devel] alternative for "pyserial+python-mini"
Will make time to update Python :) On Thu, Jul 2, 2015 at 11:51 AM, valent.turko...@gmail.com < valent.turko...@gmail.com> wrote: > Come on guys help me out with Python wiki page, it looks like I know > much less about python that you and I'm the only one documenting this > which is bad :) > > Take a look at latest version: > http://wiki.openwrt.org/doc/software/python > > On 27 June 2015 at 22:42, Christian Mehlis wrote: > > Am 26.06.2015 um 14:57 schrieb valent.turko...@gmail.com: > >> > >> Does micro-python have some alternative or replacement for pyserial? > > > > > > you can use stty[1] from busybox to configure the tty. > > After that every program can use regular read/write calls... > > > > [1] http://unixhelp.ed.ac.uk/CGI/man-cgi?stty > > > > Best > > Christian > > > > ___ > > openwrt-devel mailing list > > openwrt-devel@lists.openwrt.org > > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel > ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH 1/2] ar71xx: rework patch for qca953x/956x
No logic changes of qca956x. Just move the eth changes out of the 735 patch to
'dev-eth.c' file.
Regards,
Miaoqing
-Original Message-
From: Roman Yeryomin [mailto:leroi.li...@gmail.com]
Sent: Thursday, July 02, 2015 4:55 PM
To: Pan, Miaoqing
Cc: OpenWrt Development List
Subject: Re: [OpenWrt-Devel] [PATCH 1/2] ar71xx: rework patch for qca953x/956x
On 2 July 2015 at 09:49, wrote:
> From: Miaoqing Pan
>
> Patch cherry-picked from the following location:
> https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h
> =release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c
> 0e
>
> Changelist,
> - add more register defines
> - add EHCI support
> - fix GPIO pin count to 18
> - fix chained irq disabled
> - fix GMAC0/GMAC1 initial
> - fix WMAC irq number to 47
> - merge the changes of dev-eth.c from the patch to file.
>
> Signed-off-by: Miaoqing Pan
> ---
> .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 18 +-
> ...07-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 352
> + ...35-MIPS-ath79-add-support-for-QCA956x-SoC.patch |
> 183 ---
> .../736-MIPS-ath79-fix-chained-irq-disable.patch | 21 +-
> 4 files changed, 387 insertions(+), 187 deletions(-)
>
> diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
> b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
> index ae3db4c..ff94e2e 100644
> --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
> +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
> @@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned int id, u32
> phy_mask)
> case ATH79_SOC_AR9330:
> case ATH79_SOC_AR9331:
> case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> mdio_dev = &ath79_mdio1_device;
> mdio_data = &ath79_mdio1_data;
> break;
> @@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned int id, u32
> phy_mask)
> break;
>
> case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> mdio_data->builtin_switch = 1;
> break;
>
> @@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_data(unsigned int
> id)
> case ATH79_SOC_QCA9533:
> case ATH79_SOC_QCA9556:
> case ATH79_SOC_QCA9558:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> pll_10 = AR934X_PLL_VAL_10;
> pll_100 = AR934X_PLL_VAL_100;
> pll_1000 = AR934X_PLL_VAL_1000; @@ -627,6 +633,8 @@
> static int __init ath79_setup_phy_if_mode(unsigned int id,
> case ATH79_SOC_AR9330:
> case ATH79_SOC_AR9331:
> case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
> break;
>
> @@ -687,7 +695,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
> case ATH79_SOC_AR7241:
> case ATH79_SOC_AR9330:
> case ATH79_SOC_AR9331:
> - case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
> break;
>
> @@ -697,6 +706,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
> case ATH79_SOC_AR9341:
> case ATH79_SOC_AR9342:
> case ATH79_SOC_AR9344:
> + case ATH79_SOC_QCA9533:
> switch (pdata->phy_if_mode) {
> case PHY_INTERFACE_MODE_MII:
> case PHY_INTERFACE_MODE_GMII:
> @@ -986,6 +996,7 @@ void __init ath79_register_eth(unsigned int id)
> case ATH79_SOC_AR9341:
> case ATH79_SOC_AR9342:
> case ATH79_SOC_AR9344:
> + case ATH79_SOC_QCA9533:
> if (id == 0) {
> pdata->reset_bit = AR934X_RESET_GE0_MAC |
>AR934X_RESET_GE0_MDIO; @@
> -1017,7 +1028,8 @@ void __init ath79_register_eth(unsigned int id)
> pdata->fifo_cfg3 = 0x01f00140;
> break;
>
> - case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> if (id == 0) {
> pdata->reset_bit = AR933X_RESET_GE0_MAC |
>AR933X_RESET_GE0_MDIO; @@
> -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned int id)
> case ATH79_SOC_AR9330:
> case ATH79_SOC_AR9331:
> case ATH79_SOC_QCA9533:
> + case ATH79_SOC_QCA9561:
> + case ATH79_SOC_TP9343:
> pdata->mii_bus_dev = &ath79_md
Re: [OpenWrt-Devel] [PATCH 1/2] ar71xx: rework patch for qca953x/956x
Yes, sorry, forgot to mention it's broken now too.
On 2 July 2015 at 12:34, Pan, Miaoqing wrote:
> No logic changes of qca956x. Just move the eth changes out of the 735 patch
> to 'dev-eth.c' file.
>
> Regards,
> Miaoqing
>
> -Original Message-
> From: Roman Yeryomin [mailto:leroi.li...@gmail.com]
> Sent: Thursday, July 02, 2015 4:55 PM
> To: Pan, Miaoqing
> Cc: OpenWrt Development List
> Subject: Re: [OpenWrt-Devel] [PATCH 1/2] ar71xx: rework patch for qca953x/956x
>
> On 2 July 2015 at 09:49, wrote:
>> From: Miaoqing Pan
>>
>> Patch cherry-picked from the following location:
>> https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h
>> =release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c
>> 0e
>>
>> Changelist,
>> - add more register defines
>> - add EHCI support
>> - fix GPIO pin count to 18
>> - fix chained irq disabled
>> - fix GMAC0/GMAC1 initial
>> - fix WMAC irq number to 47
>> - merge the changes of dev-eth.c from the patch to file.
>>
>> Signed-off-by: Miaoqing Pan
>> ---
>> .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 18 +-
>> ...07-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 352
>> + ...35-MIPS-ath79-add-support-for-QCA956x-SoC.patch |
>> 183 ---
>> .../736-MIPS-ath79-fix-chained-irq-disable.patch | 21 +-
>> 4 files changed, 387 insertions(+), 187 deletions(-)
>>
>> diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
>> b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
>> index ae3db4c..ff94e2e 100644
>> --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
>> +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
>> @@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned int id, u32
>> phy_mask)
>> case ATH79_SOC_AR9330:
>> case ATH79_SOC_AR9331:
>> case ATH79_SOC_QCA9533:
>> + case ATH79_SOC_QCA9561:
>> + case ATH79_SOC_TP9343:
>> mdio_dev = &ath79_mdio1_device;
>> mdio_data = &ath79_mdio1_data;
>> break;
>> @@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned int id, u32
>> phy_mask)
>> break;
>>
>> case ATH79_SOC_QCA9533:
>> + case ATH79_SOC_QCA9561:
>> + case ATH79_SOC_TP9343:
>> mdio_data->builtin_switch = 1;
>> break;
>>
>> @@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_data(unsigned int
>> id)
>> case ATH79_SOC_QCA9533:
>> case ATH79_SOC_QCA9556:
>> case ATH79_SOC_QCA9558:
>> + case ATH79_SOC_QCA9561:
>> + case ATH79_SOC_TP9343:
>> pll_10 = AR934X_PLL_VAL_10;
>> pll_100 = AR934X_PLL_VAL_100;
>> pll_1000 = AR934X_PLL_VAL_1000; @@ -627,6 +633,8 @@
>> static int __init ath79_setup_phy_if_mode(unsigned int id,
>> case ATH79_SOC_AR9330:
>> case ATH79_SOC_AR9331:
>> case ATH79_SOC_QCA9533:
>> + case ATH79_SOC_QCA9561:
>> + case ATH79_SOC_TP9343:
>> pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
>> break;
>>
>> @@ -687,7 +695,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int
>> id,
>> case ATH79_SOC_AR7241:
>> case ATH79_SOC_AR9330:
>> case ATH79_SOC_AR9331:
>> - case ATH79_SOC_QCA9533:
>> + case ATH79_SOC_QCA9561:
>> + case ATH79_SOC_TP9343:
>> pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
>> break;
>>
>> @@ -697,6 +706,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int
>> id,
>> case ATH79_SOC_AR9341:
>> case ATH79_SOC_AR9342:
>> case ATH79_SOC_AR9344:
>> + case ATH79_SOC_QCA9533:
>> switch (pdata->phy_if_mode) {
>> case PHY_INTERFACE_MODE_MII:
>> case PHY_INTERFACE_MODE_GMII:
>> @@ -986,6 +996,7 @@ void __init ath79_register_eth(unsigned int id)
>> case ATH79_SOC_AR9341:
>> case ATH79_SOC_AR9342:
>> case ATH79_SOC_AR9344:
>> + case ATH79_SOC_QCA9533:
>> if (id == 0) {
>> pdata->reset_bit = AR934X_RESET_GE0_MAC |
>>AR934X_RESET_GE0_MDIO; @@
>> -1017,7 +1028,8 @@ void __init ath79_register_eth(unsigned int id)
>> pdata->fifo_cfg3 = 0x01f00140;
>> break;
>>
>> - case ATH79_SOC_QCA9533:
>> + case ATH79_SOC_QCA9561:
>> + case ATH79_SOC_TP9343:
>> if (id == 0) {
>> pdata->reset_bit = AR933X_RESET_GE0_MAC |
>>AR933X_RESET_GE0_MDIO; @@
>> -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned int id)
>> case ATH79_S
Re: [OpenWrt-Devel] [Olsr-dev] [ANNOUNCE - v1] olsrd v0.9.0.2 released
* Ferry Huberts [30.06.2015 18:38]: > We did a bug-fix release of olsrd v1. yesterday i updated the OpenWrt routing-packages for trunk|14.07|15.05 - thank you all! BTW: no issues so far when using 'musl' libc. as always: please compile, test and report 8-) bye, bastian ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] ramips and mips16
I don't really know the details of this, but I see that in target/linux/ramips/patches-3.18/100-mt7621-add-cpu-feature-overrides.patch there is a "#define cpu_has_mips16 1". but in target/linux/ramips/Makefile "mips16" is not one of the FEATURES. Should it be added? ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH v2 2/8] ath79: dev-eth: initialize clock for id 0 on AR934X
Signed-off-by: Günther Kelleter
---
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index ae3db4c..a64d397 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -249,9 +249,11 @@ void __init ath79_register_mdio(unsigned int id, u32
phy_mask)
case ATH79_SOC_AR9344:
if (id == 1) {
mdio_data->builtin_switch = 1;
- mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
- mdio_data->mdio_clock = 625;
+ } else {
+ mdio_data->builtin_switch = 0;
}
+ mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
+ mdio_data->mdio_clock = 625;
mdio_data->is_ar934x = 1;
break;
--
2.4.4.88.gac2ab0d
___
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[OpenWrt-Devel] [PATCH v2 6/8] generic: replace request_irq by request_threaded_irq to fix non working ledtrig-gpio
Signed-off-by: Günther Kelleter
---
.../835-fix-irq-request-ledtrig-gpio.patch| 19 +++
1 file changed, 19 insertions(+)
create mode 100644
target/linux/generic/patches-3.18/835-fix-irq-request-ledtrig-gpio.patch
diff --git
a/target/linux/generic/patches-3.18/835-fix-irq-request-ledtrig-gpio.patch
b/target/linux/generic/patches-3.18/835-fix-irq-request-ledtrig-gpio.patch
new file mode 100644
index 000..6378073
--- /dev/null
+++ b/target/linux/generic/patches-3.18/835-fix-irq-request-ledtrig-gpio.patch
@@ -0,0 +1,19 @@
+--- a/drivers/leds/trigger/ledtrig-gpio.c
b/drivers/leds/trigger/ledtrig-gpio.c
+@@ -161,9 +161,13 @@ static ssize_t gpio_trig_gpio_store(stru
+ return n;
+ }
+
+- ret = request_irq(gpio_to_irq(gpio), gpio_trig_irq,
+- IRQF_SHARED | IRQF_TRIGGER_RISING
+- | IRQF_TRIGGER_FALLING, "ledtrig-gpio", led);
++ ret = request_threaded_irq(
++ gpio_to_irq(gpio),
++ NULL,
++ gpio_trig_irq,
++ IRQF_SHARED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
++ "ledtrig-gpio",
++ led);
+ if (ret) {
+ dev_err(dev, "request_irq failed with error %d\n", ret);
+ } else {
--
2.4.4.88.gac2ab0d
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[OpenWrt-Devel] [PATCH v2 1/8] ar71xx: ag71xx: add pdata field supported
to allow target specific override of phydev->supported.
Signed-off-by: Günther Kelleter
---
.../ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h | 1 +
.../ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c| 5 +
2 files changed, 6 insertions(+)
diff --git
a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
index d46dc4e..aa7663b 100644
---
a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
+++
b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
@@ -30,6 +30,7 @@ struct ag71xx_platform_data {
u32 reset_bit;
u8 mac_addr[ETH_ALEN];
struct device *mii_bus_dev;
+ u32 supported;
u8 has_gbit:1;
u8 is_ar91xx:1;
diff --git
a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
index 9de77e9..0f5ec9c 100644
--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
@@ -146,6 +146,11 @@ static int ag71xx_phy_connect_multi(struct ag71xx *ag)
else
phydev->supported &= PHY_BASIC_FEATURES;
+ if (pdata->supported) {
+ dev_info(dev, "overriding phydev->supported (%08x)\n",
pdata->supported);
+ phydev->supported = pdata->supported;
+ }
+
phydev->advertising = phydev->supported;
dev_info(dev, "connected to PHY at %s [uid=%08x, driver=%s]\n",
--
2.4.4.88.gac2ab0d
___
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH v2 5/8] mac80211: make more ath10k firmwares selectable
The ath10k firmware version is now a choice in the config menu. Added options for older firmware versions (10.1 and 10.2). It seems that recent firmware versions don't always run properly and this provides the option to select an older (more stable) version instead. Signed-off-by: Günther Kelleter --- package/kernel/mac80211/Makefile | 35 +-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/package/kernel/mac80211/Makefile b/package/kernel/mac80211/Makefile index be26348..1182f14 100644 --- a/package/kernel/mac80211/Makefile +++ b/package/kernel/mac80211/Makefile @@ -624,13 +624,36 @@ endef define KernelPackage/ath10k/config if PACKAGE_kmod-ath10k + choice + prompt "ath10k Firmware version" + default ATH10K_API4_FW + config ATH10K_STA_FW bool "Firmware optimized for STA operation" - default n help Use the ath10k firmware optimized for wireless client instead of access point operation. + config ATH10K_API2_FW + bool "Firmware optimized for AP operation (v10.1 / API v2)" + help + Use the ath10k firmware from the 10.1 SDK using API v2 optimized + for access point operation + + config ATH10K_API3_FW + bool "Firmware optimized for AP operation (v10.2 / API v3)" + help + Use the ath10k firmware from the 10.2 SDK using API v3 optimized + for access point operation + + config ATH10K_API4_FW + bool "Firmware optimized for AP operation (v10.2.4 / API v4)" + help + Use the ath10k firmware from the 10.2.4 SDK using API v4 optimized + for access point operation + + endchoice + endif endef @@ -1862,7 +1885,15 @@ ifeq ($(CONFIG_ATH10K_STA_FW),y) $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/$(PKG_ATH10K_LINUX_FIRMWARE_SUBDIR)/main/firmware-2.bin_999.999.0.636 \ $(1)/lib/firmware/ath10k/QCA988X/hw2.0/firmware-2.bin -else +else ifeq ($(CONFIG_ATH10K_API2_FW),y) + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/$(PKG_ATH10K_LINUX_FIRMWARE_SUBDIR)/10.1/firmware-2.bin_10.1.467.2-1 \ + $(1)/lib/firmware/ath10k/QCA988X/hw2.0/firmware-2.bin +else ifeq ($(CONFIG_ATH10K_API3_FW),y) + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/$(PKG_ATH10K_LINUX_FIRMWARE_SUBDIR)/10.2/firmware-3.bin_10.2-00082-4-2 \ + $(1)/lib/firmware/ath10k/QCA988X/hw2.0/firmware-3.bin +else ifeq ($(CONFIG_ATH10K_API4_FW),y) $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/$(PKG_ATH10K_LINUX_FIRMWARE_SUBDIR)/10.2.4/firmware-4.bin_10.2.4.45 \ $(1)/lib/firmware/ath10k/QCA988X/hw2.0/firmware-4.bin -- 2.4.4.88.gac2ab0d ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH v2 4/8] ar71xx: add support to use gpio irqs
Signed-off-by: Günther Kelleter
---
.../739-MIPS-ath79-add-gpio-irq-support.patch | 241 +
1 file changed, 241 insertions(+)
create mode 100644
target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-irq-support.patch
diff --git
a/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-irq-support.patch
b/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-irq-support.patch
new file mode 100644
index 000..0262d66
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-irq-support.patch
@@ -0,0 +1,241 @@
+--- a/arch/mips/ath79/gpio.c
b/arch/mips/ath79/gpio.c
+@@ -20,9 +20,14 @@
+ #include
+ #include
+ #include
++#include
++#include
++
++#include
+
+ #include
+ #include
++#include
+ #include "common.h"
+
+ void __iomem *ath79_gpio_base;
+@@ -31,6 +36,13 @@ EXPORT_SYMBOL_GPL(ath79_gpio_base);
+ static unsigned long ath79_gpio_count;
+ static DEFINE_SPINLOCK(ath79_gpio_lock);
+
++/*
++ * gpio_both_edge is a bitmask of which gpio pins need to have
++ * the detect priority flipped from the interrupt handler to
++ * emulate IRQ_TYPE_EDGE_BOTH.
++ */
++static unsigned long gpio_both_edge = 0;
++
+ static void __ath79_gpio_set_value(unsigned gpio, int value)
+ {
+ void __iomem *base = ath79_gpio_base;
+@@ -209,6 +221,136 @@ void __init ath79_gpio_output_select(uns
+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+
++static int ath79_gpio_irq_type(struct irq_data *d, unsigned type)
++{
++ int offset = d->irq - ATH79_GPIO_IRQ_BASE;
++ void __iomem *base = ath79_gpio_base;
++ unsigned long flags;
++ unsigned long int_type;
++ unsigned long int_polarity;
++ unsigned long bit = (1 << offset);
++
++ spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++ int_type = __raw_readl(base + AR71XX_GPIO_REG_INT_TYPE);
++ int_polarity = __raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY);
++
++ gpio_both_edge &= ~bit;
++
++ switch (type) {
++ case IRQ_TYPE_EDGE_RISING:
++ int_type &= ~bit;
++ int_polarity |= bit;
++ break;
++
++ case IRQ_TYPE_EDGE_FALLING:
++ int_type &= ~bit;
++ int_polarity &= ~bit;
++ break;
++
++ case IRQ_TYPE_LEVEL_HIGH:
++ int_type |= bit;
++ int_polarity |= bit;
++ break;
++
++ case IRQ_TYPE_LEVEL_LOW:
++ int_type |= bit;
++ int_polarity &= ~bit;
++ break;
++
++ case IRQ_TYPE_EDGE_BOTH:
++ int_type |= bit;
++ /* set polarity based on current value */
++ if (gpio_get_value(offset)) {
++ int_polarity &= ~bit;
++ } else {
++ int_polarity |= bit;
++ }
++ /* flip this gpio in the interrupt handler */
++ gpio_both_edge |= bit;
++ break;
++
++ default:
++ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++ return -EINVAL;
++ }
++
++ __raw_writel(int_type, base + AR71XX_GPIO_REG_INT_TYPE);
++ __raw_writel(int_polarity, base + AR71XX_GPIO_REG_INT_POLARITY);
++
++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_MODE) | (1 <<
offset),
++ base + AR71XX_GPIO_REG_INT_MODE);
++
++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 <<
offset),
++ base + AR71XX_GPIO_REG_INT_ENABLE);
++
++ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++ return 0;
++}
++
++static void ath79_gpio_irq_enable(struct irq_data *d)
++{
++ int offset = d->irq - ATH79_GPIO_IRQ_BASE;
++ void __iomem *base = ath79_gpio_base;
++
++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) | (1 <<
offset),
++ base + AR71XX_GPIO_REG_INT_ENABLE);
++}
++
++static void ath79_gpio_irq_disable(struct irq_data *d)
++{
++ int offset = d->irq - ATH79_GPIO_IRQ_BASE;
++ void __iomem *base = ath79_gpio_base;
++
++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 <<
offset),
++ base + AR71XX_GPIO_REG_INT_ENABLE);
++}
++
++static struct irq_chip ath79_gpio_irqchip = {
++ .name = "GPIO",
++ .irq_enable = ath79_gpio_irq_enable,
++ .irq_disable = ath79_gpio_irq_disable,
++ .irq_set_type = ath79_gpio_irq_type,
++};
++
++static irqreturn_t ath79_gpio_irq(int irq, void *dev)
++{
++ void __iomem *base = ath79_gpio_base;
++ unsigned int stat = __raw_readl(base + AR71XX_GPIO_REG_INT_PENDING);
++
++ int irq_base = ATH79_GPIO_IRQ_BASE;
++
++ while (stat) {
++ int bit_num = __ffs(stat);
++ unsigned long bit = (1
[OpenWrt-Devel] [PATCH v2 7/8] base-files: added option to configure the gpio led trigger in uci-defaults
Signed-off-by: Günther Kelleter
---
package/base-files/files/etc/init.d/led | 7 +++
.../base-files/files/lib/functions/uci-defaults.sh | 20
2 files changed, 27 insertions(+)
diff --git a/package/base-files/files/etc/init.d/led
b/package/base-files/files/etc/init.d/led
index 1a57e8a..3f45732 100755
--- a/package/base-files/files/etc/init.d/led
+++ b/package/base-files/files/etc/init.d/led
@@ -26,6 +26,8 @@ load_led() {
config_get port_state $1 port_state
config_get delay $1 delay "150"
config_get message $1 message ""
+ config_get gpio $1 gpio "0"
+ config_get inverted $1 inverted "0"
if [ "$trigger" = "rssi" ]; then
# handled by rssileds userspace process
@@ -80,6 +82,11 @@ load_led() {
echo $delay > /sys/class/leds/${sysfs}/delay
;;
+ "gpio")
+ echo $gpio > /sys/class/leds/${sysfs}/gpio
+ echo $inverted > /sys/class/leds/${sysfs}/inverted
+ ;;
+
switch[0-9]*)
local port_mask
diff --git a/package/base-files/files/lib/functions/uci-defaults.sh
b/package/base-files/files/lib/functions/uci-defaults.sh
index 5a8809d..93997b2 100644
--- a/package/base-files/files/lib/functions/uci-defaults.sh
+++ b/package/base-files/files/lib/functions/uci-defaults.sh
@@ -157,6 +157,26 @@ EOF
UCIDEF_LEDS_CHANGED=1
}
+ucidef_set_led_gpio() {
+ local cfg="led_$1"
+ local name=$2
+ local sysfs=$3
+ local gpio=$4
+ local inverted=$5
+
+ uci -q get system.$cfg && return 0
+
+ uci batch
[OpenWrt-Devel] [PATCH v2 3/8] ar71xx: add support for the devolo dLAN pro 500 Wireless+
Signed-off-by: Günther Kelleter
---
target/linux/ar71xx/base-files/etc/diag.sh | 3 +
.../ar71xx/base-files/etc/uci-defaults/01_leds | 7 +
.../ar71xx/base-files/etc/uci-defaults/02_network | 4 +
target/linux/ar71xx/base-files/lib/ar71xx.sh | 3 +
.../ar71xx/base-files/lib/upgrade/platform.sh | 1 +
target/linux/ar71xx/config-3.18| 1 +
.../files/arch/mips/ath79/mach-dlan-pro-500-wp.c | 241 +
.../linux/ar71xx/generic/profiles/devolo-dlan.mk | 19 ++
target/linux/ar71xx/image/Makefile | 19 ++
.../610-MIPS-ath79-openwrt-machines.patch | 27 ++-
10 files changed, 319 insertions(+), 6 deletions(-)
create mode 100644
target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c
create mode 100644 target/linux/ar71xx/generic/profiles/devolo-dlan.mk
diff --git a/target/linux/ar71xx/base-files/etc/diag.sh
b/target/linux/ar71xx/base-files/etc/diag.sh
index c02efa8..4c530ce 100644
--- a/target/linux/ar71xx/base-files/etc/diag.sh
+++ b/target/linux/ar71xx/base-files/etc/diag.sh
@@ -70,6 +70,9 @@ get_status_led() {
dir-835-a1)
status_led="d-link:amber:power"
;;
+ dlan-pro-500-wp)
+ status_led="devolo:green:wlan-2g"
+ ;;
dragino2)
status_led="dragino2:red:system"
;;
diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
index 19814f4..f740d3b 100644
--- a/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
+++ b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
@@ -150,6 +150,13 @@ dir-825-c1)
ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "d-link:blue:wlan2g"
"phy0tpt"
;;
+dlan-pro-500-wp)
+ ucidef_set_led_default "power" "System Power" "devolo:green:status" "1"
+ ucidef_set_led_netdev "lan" "Ethernet Activity" "devolo:green:eth"
"br-lan"
+ ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "devolo:green:wlan-2g"
"phy0tpt"
+ ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "devolo:blue:wlan-5g" "none"
+ ;;
+
gl-inet)
ucidef_set_led_netdev "lan" "LAN" "gl-connect:green:lan" "eth1"
ucidef_set_led_wlan "wlan" "WLAN" "gl-connect:red:wlan" "phy0tpt"
diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
index 2fab4c2..bb7703f 100644
--- a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
+++ b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
@@ -299,6 +299,10 @@ esr900)
[ -n "$mac" ] && ucidef_set_interface_macaddr "wan" "$mac"
;;
+dlan-pro-500-wp)
+ ucidef_set_interface_lan "eth0 eth1"
+ ;;
+
all0305 |\
aw-nr580 |\
bullet-m |\
diff --git a/target/linux/ar71xx/base-files/lib/ar71xx.sh
b/target/linux/ar71xx/base-files/lib/ar71xx.sh
index 00e39ae..b30cb67 100755
--- a/target/linux/ar71xx/base-files/lib/ar71xx.sh
+++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh
@@ -414,6 +414,9 @@ ar71xx_board_detect() {
*"DIR-835 rev. A1")
name="dir-835-a1"
;;
+ *"dLAN pro 500 Wireless+")
+ name="dlan-pro-500-wp"
+ ;;
*"Dragino v2")
name="dragino2"
;;
diff --git a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
index 0f3ea9c..f3909ed 100755
--- a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
@@ -207,6 +207,7 @@ platform_check_image() {
dir-615-e4 | \
dir-825-c1 | \
dir-835-a1 | \
+ dlan-pro-500-wp | \
dragino2 | \
epg5000 | \
esr1750 | \
diff --git a/target/linux/ar71xx/config-3.18 b/target/linux/ar71xx/config-3.18
index 17f33bd..b506c7f 100644
--- a/target/linux/ar71xx/config-3.18
+++ b/target/linux/ar71xx/config-3.18
@@ -53,6 +53,7 @@ CONFIG_ATH79_MACH_DIR_600_A1=y
CONFIG_ATH79_MACH_DIR_615_C1=y
CONFIG_ATH79_MACH_DIR_825_B1=y
CONFIG_ATH79_MACH_DIR_825_C1=y
+CONFIG_ATH79_MACH_DLAN_PRO_500_WP=y
CONFIG_ATH79_MACH_DRAGINO2=y
CONFIG_ATH79_MACH_EAP300V2=y
CONFIG_ATH79_MACH_EAP7660D=y
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c
b/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c
new file mode 100644
index 000..4a144ae
--- /dev/null
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c
@@ -0,0 +1,241 @@
+/*
+ * devolo dLAN pro 500 Wireless+ support
+ *
+ * Copyright (c) 2013-2015 devolo AG
+ * Copyright (c) 2011-2012 Gabor Juhos
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVID
[OpenWrt-Devel] [PATCH v2 0/8] ar71xx: support for devolo dLAN devices
This patch set adds support for two devolo dLAN devices: dLAN pro 500 Wireless+ dLAN pro 1200+ Wifi ac It supports the wlan and ethernet interfaces. PLC support must be implemented in user space and will folow later when basic support is finally accepted Günther Kelleter (8): ar71xx: ag71xx: add pdata field supported ath79: dev-eth: initialize clock for id 0 on AR934X ar71xx: add support for the devolo dLAN pro 500 Wireless+ ar71xx: add support to use gpio irqs mac80211: make more ath10k firmwares selectable generic: replace request_irq by request_threaded_irq to fix non working ledtrig-gpio base-files: added option to configure the gpio led trigger in uci-defaults ar71xx: add support for the devolo dLAN pro 1200+ WiFi ac package/base-files/files/etc/init.d/led| 7 + .../base-files/files/lib/functions/uci-defaults.sh | 20 ++ package/kernel/mac80211/Makefile | 35 ++- target/linux/ar71xx/base-files/etc/diag.sh | 6 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 8 + .../ar71xx/base-files/etc/uci-defaults/01_leds | 13 ++ .../ar71xx/base-files/etc/uci-defaults/02_network | 10 + target/linux/ar71xx/base-files/lib/ar71xx.sh | 6 + .../ar71xx/base-files/lib/upgrade/platform.sh | 2 + target/linux/ar71xx/config-3.18| 2 + .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 6 +- .../files/arch/mips/ath79/mach-dlan-pro-1200-ac.c | 216 ++ .../files/arch/mips/ath79/mach-dlan-pro-500-wp.c | 241 + .../mips/include/asm/mach-ath79/ag71xx_platform.h | 1 + .../net/ethernet/atheros/ag71xx/ag71xx_phy.c | 5 + .../linux/ar71xx/generic/profiles/devolo-dlan.mk | 33 +++ target/linux/ar71xx/image/Makefile | 21 ++ .../610-MIPS-ath79-openwrt-machines.patch | 42 +++- .../739-MIPS-ath79-add-gpio-irq-support.patch | 241 + .../835-fix-irq-request-ledtrig-gpio.patch | 19 ++ 20 files changed, 924 insertions(+), 10 deletions(-) create mode 100644 target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-1200-ac.c create mode 100644 target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c create mode 100644 target/linux/ar71xx/generic/profiles/devolo-dlan.mk create mode 100644 target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-irq-support.patch create mode 100644 target/linux/generic/patches-3.18/835-fix-irq-request-ledtrig-gpio.patch -- 2.4.4.88.gac2ab0d ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH v2 8/8] ar71xx: add support for the devolo dLAN pro 1200+ WiFi ac
Signed-off-by: Günther Kelleter
---
target/linux/ar71xx/base-files/etc/diag.sh | 3 +
.../etc/hotplug.d/firmware/11-ath10k-caldata | 8 +
.../ar71xx/base-files/etc/uci-defaults/01_leds | 6 +
.../ar71xx/base-files/etc/uci-defaults/02_network | 6 +
target/linux/ar71xx/base-files/lib/ar71xx.sh | 3 +
.../ar71xx/base-files/lib/upgrade/platform.sh | 1 +
target/linux/ar71xx/config-3.18| 1 +
.../files/arch/mips/ath79/mach-dlan-pro-1200-ac.c | 216 +
.../linux/ar71xx/generic/profiles/devolo-dlan.mk | 14 ++
target/linux/ar71xx/image/Makefile | 2 +
.../610-MIPS-ath79-openwrt-machines.patch | 27 ++-
11 files changed, 281 insertions(+), 6 deletions(-)
create mode 100644
target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-1200-ac.c
diff --git a/target/linux/ar71xx/base-files/etc/diag.sh
b/target/linux/ar71xx/base-files/etc/diag.sh
index 4c530ce..a0ec52e 100644
--- a/target/linux/ar71xx/base-files/etc/diag.sh
+++ b/target/linux/ar71xx/base-files/etc/diag.sh
@@ -73,6 +73,9 @@ get_status_led() {
dlan-pro-500-wp)
status_led="devolo:green:wlan-2g"
;;
+ dlan-pro-1200-ac)
+ status_led="devolo:status:wlan"
+ ;;
dragino2)
status_led="dragino2:red:system"
;;
diff --git
a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
index 164d3ab..1b288ca 100644
--- a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
+++ b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
@@ -34,6 +34,14 @@ case "$FIRMWARE" in
esac
;;
+"ath10k/cal-pci-:00:00.0.bin")
+ case $board in
+ dlan-pro-1200-ac)
+ ath10kcal_from_file "/dev/$(cat /proc/mtd |grep "\"art\"" | cut
-d: -f1)" 20480 $ath10kcal_tmp
+ ;;
+ esac
+ ;;
+
*)
exit 1
;;
diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
index f740d3b..be0b4a0 100644
--- a/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
+++ b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
@@ -157,6 +157,12 @@ dlan-pro-500-wp)
ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "devolo:blue:wlan-5g" "none"
;;
+dlan-pro-1200-ac)
+ ucidef_set_led_wlan "wlan" "WLAN" "devolo:status:wlan" "phy0radio"
+ ucidef_set_led_gpio "plcw" "dLAN" "devolo:status:dlan" "17" "1"
+ ucidef_set_led_gpio "plcr" "dLAN" "devolo:error:dlan" "16" "0"
+ ;;
+
gl-inet)
ucidef_set_led_netdev "lan" "LAN" "gl-connect:green:lan" "eth1"
ucidef_set_led_wlan "wlan" "WLAN" "gl-connect:red:wlan" "phy0tpt"
diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
index bb7703f..357dcb3 100644
--- a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
+++ b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
@@ -303,6 +303,12 @@ dlan-pro-500-wp)
ucidef_set_interface_lan "eth0 eth1"
;;
+dlan-pro-1200-ac)
+ ucidef_set_interface_lan "eth0"
+ ucidef_add_switch "switch0" "1" "0"
+ ucidef_add_switch_vlan "switch0" "0" "0 2 3 4"
+ ;;
+
all0305 |\
aw-nr580 |\
bullet-m |\
diff --git a/target/linux/ar71xx/base-files/lib/ar71xx.sh
b/target/linux/ar71xx/base-files/lib/ar71xx.sh
index b30cb67..ff0695d 100755
--- a/target/linux/ar71xx/base-files/lib/ar71xx.sh
+++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh
@@ -417,6 +417,9 @@ ar71xx_board_detect() {
*"dLAN pro 500 Wireless+")
name="dlan-pro-500-wp"
;;
+ *"dLAN pro 1200+ WiFi ac")
+ name="dlan-pro-1200-ac"
+ ;;
*"Dragino v2")
name="dragino2"
;;
diff --git a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
index f3909ed..6690ed3 100755
--- a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
@@ -208,6 +208,7 @@ platform_check_image() {
dir-825-c1 | \
dir-835-a1 | \
dlan-pro-500-wp | \
+ dlan-pro-1200-ac | \
dragino2 | \
epg5000 | \
esr1750 | \
diff --git a/target/linux/ar71xx/config-3.18 b/target/linux/ar71xx/config-3.18
index b506c7f..5ef1a81 100644
--- a/target/linux/ar71xx/config-3.18
+++ b/target/linux/ar71xx/config-3.18
@@ -53,6 +53,7 @@ CONFIG_ATH79_MACH_DIR_600_A1=y
CONFIG_ATH79_MACH_DIR_615_C1=y
CONFIG_ATH79_MACH_DIR_825_B1=y
CONFIG_ATH79_MACH_DIR_825_C1=y
+CONFIG_ATH79_MACH_DLAN_PRO_1200_AC=y
CONFIG_ATH79_MACH_DLAN_PRO_500_WP=y
CONFIG_ATH79_MACH_DRAGINO2=y
CONFIG_ATH79_MACH_EAP300V2=y
di
Re: [OpenWrt-Devel] [PATCH V2 procd] service: start apps with LD_PRELOAD & lib for line buffering
On 20 June 2015 at 21:42, Rafał Miłecki wrote: > Using pipe automatically switches service to block buffering which kind > of breaks our logging. We won't get anything from FD until the buffer > gets filled fully or the service exits. This makes log messages appear > with an unwanted delay. > This adds a tiny libsetlbf.so that switches stdout to line buffering and > uses this lib for every logging-enabled service started by procd. Ping. ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] error 421 while creating new ticket
just for the admin: Warning: The ticket has been created, but an error occurred while sending notifications: (421, 'Unexpected failure, please try later') while submitting this new ticket: https://dev.openwrt.org/ticket/20029 bye, bastian ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH 1/2] ar71xx: rework patch for qca953x/956x
On 07/02/2015 08:49 AM, miaoq...@qti.qualcomm.com wrote: > From: Miaoqing Pan > > Patch cherry-picked from the following location: > https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e > > Changelist, > - add more register defines > - add EHCI support > - fix GPIO pin count to 18 > - fix chained irq disabled > - fix GMAC0/GMAC1 initial > - fix WMAC irq number to 47 > - merge the changes of dev-eth.c from the patch to file. > > Signed-off-by: Miaoqing Pan > --- > .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 18 +- > ...07-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 352 > + > ...35-MIPS-ath79-add-support-for-QCA956x-SoC.patch | 183 --- > .../736-MIPS-ath79-fix-chained-irq-disable.patch | 21 +- > 4 files changed, 387 insertions(+), 187 deletions(-) Hi, which OpenWrt tree did you base your patch on? I had some trouble getting it to apply to the current OpenWrt trunk to test it... I've attached a fixed up version that applies cleanly. I've noticed that this patch breaks the ethernet ports on the TP-LINK TL-WR841N v9 (which is based on the QCA9533 ver 1 rev 1). I've fixed it up using the following snippet, the Compex WPJ531 will probably need the same fix (it uses pretty much the same initialization code). --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c @@ -109,12 +109,18 @@ static void __init tl_ap143_setup(void) ath79_register_mdio(0, 0x0); /* LAN */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_switch_data.phy_poll_mask |= BIT(4); ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); ath79_register_eth(1); /* WAN */ ath79_switch_data.phy4_mii_en = 1; ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.phy_mask = BIT(4); ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); ath79_register_eth(0); Do you want to pick up this change and submit it together with an updated version of your patchset, or should I submit it myself? By the way, does the WMAC IRQ number fix have a noticable effect? WLAN was working fine on the TL-WR841N v9 both before and after your patch, so I'm wondering if it would be worth to backport it to my older Barrier-Breaker- and Chaos-Calmer-based branches. Apart from that, thanks for your patch! Matthias From a3f31e9039c21e12b7246f6c705333e418b9075b Mon Sep 17 00:00:00 2001 Message-Id: From: Miaoqing Pan Date: Thu, 2 Jul 2015 14:49:37 +0800 Subject: [PATCH] ar71xx: rework patch for qca953x/956x Patch cherry-picked from the following location: https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e Changelist, - add more register defines - add EHCI support - fix GPIO pin count to 18 - fix chained irq disabled - fix GMAC0/GMAC1 initial - fix WMAC irq number to 47 - merge the changes of dev-eth.c from the patch to file. Signed-off-by: Miaoqing Pan --- .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 18 +- ...07-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 326 +++-- ...35-MIPS-ath79-add-support-for-QCA956x-SoC.patch | 171 --- .../736-MIPS-ath79-fix-chained-irq-disable.patch | 21 +- 4 files changed, 379 insertions(+), 157 deletions(-) diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index ae3db4c..ff94e2e 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: mdio_dev = &ath79_mdio1_device; mdio_data = &ath79_mdio1_data; break; @@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) break; case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: mdio_data->builtin_switch = 1; break; @@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_data(unsigned int id) case ATH79_SOC_QCA9533: case ATH79_SOC_QCA9556: case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: pll_10 = AR934X_PLL_VAL_10; pll_100 = AR934X_PLL_VAL_100; pll_1000 = AR934X_PLL_VAL_1000; @@ -627,6 +633,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: pdata->phy_if_mod
Re: [OpenWrt-Devel] [PATCH] hostapd netifd wmm configuration for speedup wifi.
On 2015-06-30 11:05, N.Leiten wrote: > Speed up wifi up to 2 times in Access Point mode. On rt5350 platfrom I > got speed up from 35-40Mbit to 70-80Mbit, on ar71xx I got improvement > from 45Mbit to 100Mbit with this parameters set in hostapd.conf. It > seems that hostapd expects not only 'wmm_enabled=1' key but also > parameters for WMM. > > > Signed-off-by: Vadim Gamov I compared the internal values of the WMM settings inside hostapd before and after this patch, and they're identical. I also compared the speed on ar71xx, and it's identical too. I don't know what made a difference in your tests, but I don't see how this patch could have caused it. - Felix ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] asking for help about mt7620 restarting
Dear sir/Madam, recently, when we install our wireless router, we found when we run the reboot command, the board couldn't restart. We hope you could lend us a hand to solve this problem. We'll be quite grateful for what you do for us. By the way, our board is MT7620 equipped with 32M spi flash, and works under Openwrt trunk. We have set w25q256 in dts. Every other command works fine except reboot. Some people said it may be about the switch of spi flash between 3 byte and 4 byte. Could you tell us how to solve this problem or a fixed padding? We'll be quite grateful. Thanks. Looking forward to your reply as soon as possible. Your Sincerely Anna___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] asking for help about mt7620 restarting
Dear sir/Madam, recently, when we install our wireless router, we found when we run the reboot command, the board couldn't restart. We hope you could lend us a hand to solve this problem. We'll be quite grateful for what you do for us. By the way, our board is MT7620 equipped with 32M spi flash, and works under Openwrt trunk. We have set w25q256 in dts. Every other command works fine except reboot. Some people said it may be about the switch of spi flash between 3 byte and 4 byte. Could you tell us how to solve this problem or a fixed padding? We'll be quite grateful. Thanks. Looking forward to your reply as soon as possible. Your Sincerely Anna___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] help
Dear sir/Madam, recently, when we install our wireless router, we found when we run the reboot command, the board couldn't restart. We hope you could lend us a hand to solve this problem. We'll be quite grateful for what you do for us. By the way, our board is MT7620 equipped with 32M spi flash, and works under Openwrt trunk. We have set w25q256 in dts. Every other command works fine except reboot. Some people said it may be about the switch of spi flash between 3 byte and 4 byte. Could you tell us how to solve this problem or a fixed padding? We'll be quite grateful. Thanks. Looking forward to your reply as soon as possible. Your Sincerely Anna___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] help
How about "reboot -f " ? On 03/07/2015 12:00, ldy647 wrote: Dear sir/Madam, recently, when we install our wireless router, we found when we run the reboot command, the board couldn't restart. We hope you could lend us a hand to solve this problem. We'll be quite grateful for what you do for us. By the way, our board is MT7620 equipped with 32M spi flash, and works under Openwrt trunk. We have set w25q256 in dts. Every other command works fine except reboot. Some people said it may be about the switch of spi flash between 3 byte and 4 byte. Could you tell us how to solve this problem or a fixed padding? We'll be quite grateful. Thanks. Looking forward to your reply as soon as possible. Your Sincerely Anna ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH 1/2] ar71xx: rework patch for qca953x/956x
Thanks, go ahead with the updated version. My patch base on git://git.openwrt.org/openwrt.git. For WMAC IRQ number fix, WMAC(47) and GMAC(46) share the IP2 IRQ, so from the fist look, there is no effect without this fix. But it will cause IRQ storm. Miaoqing -Original Message- From: Matthias Schiffer [mailto:mschif...@universe-factory.net] Sent: Friday, July 03, 2015 5:10 AM To: Pan, Miaoqing Cc: openwrt-devel@lists.openwrt.org Subject: Re: [OpenWrt-Devel] [PATCH 1/2] ar71xx: rework patch for qca953x/956x On 07/02/2015 08:49 AM, miaoq...@qti.qualcomm.com wrote: > From: Miaoqing Pan > > Patch cherry-picked from the following location: > https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h > =release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c > 0e > > Changelist, > - add more register defines > - add EHCI support > - fix GPIO pin count to 18 > - fix chained irq disabled > - fix GMAC0/GMAC1 initial > - fix WMAC irq number to 47 > - merge the changes of dev-eth.c from the patch to file. > > Signed-off-by: Miaoqing Pan > --- > .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 18 +- > ...07-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 352 > + ...35-MIPS-ath79-add-support-for-QCA956x-SoC.patch | > 183 --- > .../736-MIPS-ath79-fix-chained-irq-disable.patch | 21 +- > 4 files changed, 387 insertions(+), 187 deletions(-) Hi, which OpenWrt tree did you base your patch on? I had some trouble getting it to apply to the current OpenWrt trunk to test it... I've attached a fixed up version that applies cleanly. I've noticed that this patch breaks the ethernet ports on the TP-LINK TL-WR841N v9 (which is based on the QCA9533 ver 1 rev 1). I've fixed it up using the following snippet, the Compex WPJ531 will probably need the same fix (it uses pretty much the same initialization code). --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c @@ -109,12 +109,18 @@ static void __init tl_ap143_setup(void) ath79_register_mdio(0, 0x0); /* LAN */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_switch_data.phy_poll_mask |= BIT(4); ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); ath79_register_eth(1); /* WAN */ ath79_switch_data.phy4_mii_en = 1; ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.phy_mask = BIT(4); ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); ath79_register_eth(0); Do you want to pick up this change and submit it together with an updated version of your patchset, or should I submit it myself? By the way, does the WMAC IRQ number fix have a noticable effect? WLAN was working fine on the TL-WR841N v9 both before and after your patch, so I'm wondering if it would be worth to backport it to my older Barrier-Breaker- and Chaos-Calmer-based branches. Apart from that, thanks for your patch! Matthias ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] asking for help about mt7620 restarting
Most SOCs don't support 4 bytes in boot stage. Try extended address mode, https://www.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/commit/?h=release/coconut_ioe4531_2.0&id=2c537127056384523e92a43bf645f34a26696a39 https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=9c00e9bc34dbb89812bc87bc1047849d1245bfb2 Miaoqing From: openwrt-devel [mailto:openwrt-devel-boun...@lists.openwrt.org] On Behalf Of ldy647 Sent: Friday, July 03, 2015 11:45 AM To: openwrt-devel@lists.openwrt.org Subject: [OpenWrt-Devel] asking for help about mt7620 restarting Dear sir/Madam, recently, when we install our wireless router, we found when we run the reboot command, the board couldn't restart. We hope you could lend us a hand to solve this problem. We'll be quite grateful for what you do for us. By the way, our board is MT7620 equipped with 32M spi flash, and works under Openwrt trunk. We have set w25q256 in dts. Every other command works fine except reboot. Some people said it may be about the switch of spi flash between 3 byte and 4 byte. Could you tell us how to solve this problem or a fixed padding? We'll be quite grateful. Thanks. Looking forward to your reply as soon as possible. Your Sincerely Anna ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH] [generic] ramips: adding support for OY-0001 Wireless Router
From: Tom Deng <2579131...@qq.com>
Adding support for OY-0001 Wireless Router.
OY-0001 is a wireless router made by oyewifi.com. Below is the details:
MT7620A, 128MB DDR2, 16MB FLASH, SD Slot, USB 2.0, 4 x LAN + 1 x WAN.
Signed-off-by: Tom Deng <2579131...@qq.com>
---
diff --git a/target/linux/ramips/base-files/etc/diag.sh
b/target/linux/ramips/base-files/etc/diag.sh
index 74b8867..35a64dd 100755
--- a/target/linux/ramips/base-files/etc/diag.sh
+++ b/target/linux/ramips/base-files/etc/diag.sh
@@ -186,6 +186,9 @@ get_status_led() {
f7c027)
status_led="belkin:orange:status"
;;
+oy-0001)
+status_led="oy:green:wifi"
+;;
na930)
status_led="na930:blue:power"
;;
diff --git a/target/linux/ramips/base-files/etc/uci-defaults/01_leds
b/target/linux/ramips/base-files/etc/uci-defaults/01_leds
index 5d6ed2b..265525a 100755
--- a/target/linux/ramips/base-files/etc/uci-defaults/01_leds
+++ b/target/linux/ramips/base-files/etc/uci-defaults/01_leds
@@ -199,6 +199,10 @@ case $board in
set_wifi_led "zbtlink:blue:air"
set_usb_led "zbtlink:blue:usb"
;;
+oy-0001)
+ucidef_set_led_default "power" "power" "oy:green:power" "1"
+set_wifi_led "oy:green:wifi"
+;;
wr8305rt)
ucidef_set_led_default "power" "power" "wr8305rt:sys" "1"
set_usb_led "wr8305rt:usb"
diff --git a/target/linux/ramips/base-files/etc/uci-defaults/02_network
b/target/linux/ramips/base-files/etc/uci-defaults/02_network
index c3ea489..b847a1b 100755
--- a/target/linux/ramips/base-files/etc/uci-defaults/02_network
+++ b/target/linux/ramips/base-files/etc/uci-defaults/02_network
@@ -104,6 +104,7 @@ ramips_setup_interfaces()
dir-615-h1 | \
hlk-rm04 | \
mzk-w300nh2 | \
+oy-0001 | \
mzk-750dhp)
ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2"
ucidef_add_switch "switch0" "1" "1"
@@ -221,6 +222,11 @@ ramips_setup_macs()
wan_mac=$(mtd_get_mac_binary devdata 7)
;;
+oy-0001)
+lan_mac=$(mtd_get_mac_binary factory 40)
+wan_mac=$(mtd_get_mac_binary factory 46)
+;;
+
w306r-v20)
lan_mac=$(cat /sys/class/net/eth0/address)
wan_mac=$(macaddr_add "$lan_mac" 5)
diff --git a/target/linux/ramips/base-files/lib/ramips.sh
b/target/linux/ramips/base-files/lib/ramips.sh
index fd03423..f95adc5 100755
--- a/target/linux/ramips/base-files/lib/ramips.sh
+++ b/target/linux/ramips/base-files/lib/ramips.sh
@@ -325,6 +325,9 @@ ramips_board_detect() {
*"Zbtlink ZBT-WA05")
name="zbt-wa05"
;;
+*"OY-0001")
+name="oy-0001"
+;;
*"ZBT WR8305RT")
name="wr8305rt"
;;
diff --git a/target/linux/ramips/base-files/lib/upgrade/platform.sh
b/target/linux/ramips/base-files/lib/upgrade/platform.sh
index ba69a89..ad35f9d 100755
--- a/target/linux/ramips/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ramips/base-files/lib/upgrade/platform.sh
@@ -96,6 +96,7 @@ platform_check_image() {
wmr300 |\
wr8305rt |\
wrtnode |\
+oy-0001 |\
x5 |\
x8 |\
zbt-wa05 |\
diff --git a/target/linux/ramips/dts/OY-0001.dts
b/target/linux/ramips/dts/OY-0001.dts
new file mode 100644
index 000..48b7099
--- /dev/null
+++ b/target/linux/ramips/dts/OY-0001.dts
@@ -0,0 +1,123 @@
+/dts-v1/;
+
+/include/ "mt7620a.dtsi"
+
+/ {
+compatible = "ralink,mt7620a-soc";
+model = "OY-0001";
+
+chosen {
+bootargs = "console=ttyS0,115200";
+};
+
+palmbus@1000 {
+gpio2: gpio@660 {
+status = "okay";
+};
+
+gpio3: gpio@688 {
+status = "okay";
+};
+
+spi@b00 {
+status = "okay";
+
+m25p80@0 {
+#address-cells = <1>;
+#size-cells = <1>;
+compatible = "w25q128";
+reg = <0 0>;
+linux,modalias = "m25p80", "w25q128";
+spi-max-frequency = <1000>;
+
+partition@0 {
+label = "u-boot";
+reg = <0x0 0x3>;
+read-only;
+};
+
+partition@3 {
+label = "u-boot-env";
+reg = <0x3 0x1>;
+read-only;
+};
+
+factory: partition@4 {
+label = "factory";
+reg = <0x4 0x1>;
+read-only;
+};
+
+partition@5 {
+label = "firmware";
+reg = <0x5 0xfb>;
+};
+
+};
+};
+};
+
+pinctrl {
+state_default: pinctrl0 {
+gpio {
+ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled",
"nd_sd";
+ralink,function = "gpio";
+};
+};
+};
+
