from:"James Zhu"

Re: [Mesa-dev] [PATCH 1/6] gallium\auxiliary\vl: Move dirty define to header file

2019-02-01 Thread James Zhu


On 2019-02-01 11:34 a.m., Christian König wrote:
> Am 01.02.19 um 17:28 schrieb Zhu, James:
>> Move dirty define to header file to share with compute shader.
>>
>> Signed-off-by: James Zhu 
>> ---
>>   src/gallium/auxiliary/vl/vl_compositor.c | 3 ---
>>   src/gallium/auxiliary/vl/vl_compositor.h | 2 ++
>>   2 files changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/gallium/auxiliary/vl/vl_compositor.c 
>> b/src/gallium/auxiliary/vl/vl_compositor.c
>> index 159a295..2c6d585 100644
>> --- a/src/gallium/auxiliary/vl/vl_compositor.c
>> +++ b/src/gallium/auxiliary/vl/vl_compositor.c
>> @@ -42,9 +42,6 @@
>>   #include "vl_types.h"
>>   #include "vl_compositor.h"
>>   -#define MIN_DIRTY (0)
>> -#define MAX_DIRTY (1 << 15)
>> -
>>   enum VS_OUTPUT
>>   {
>>  VS_O_VPOS = 0,
>> diff --git a/src/gallium/auxiliary/vl/vl_compositor.h 
>> b/src/gallium/auxiliary/vl/vl_compositor.h
>> index 8819176..d51b5f5 100644
>> --- a/src/gallium/auxiliary/vl/vl_compositor.h
>> +++ b/src/gallium/auxiliary/vl/vl_compositor.h
>> @@ -44,6 +44,8 @@ struct pipe_context;
>>    */
>>     #define VL_COMPOSITOR_MAX_LAYERS 16
>> +#define MIN_DIRTY (0)
>> +#define MAX_DIRTY (1 << 15)
>
> That needs a proper prefix.
>
> E.g. put VL_COMPOSITOR_ in front of the name and rename all usages.
Sure. James
>
> Christian.
>
>>     /* deinterlace allgorithem */
>>   enum vl_compositor_deinterlace
>
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Re: [Mesa-dev] [PATCH 6/6] gallium\auxiliary\vl: Add video compute shader render

2019-02-01 Thread James Zhu


On 2019-02-01 11:38 a.m., Christian König wrote:
> Am 01.02.19 um 17:28 schrieb Zhu, James:
>> Add video compute shader render. export CS_COMPOSITOR_RENDER=true
>> to enable video compute shader render.
>
> Ok that actually makes more sense, but I would either put everything 
> into one file or cleanly separate between gfx and compute implementation.

Don't want to jump too far at first. Plan to do in the future.

James

>
> Christian.
>
>>
>> Signed-off-by: James Zhu 
>> ---
>>   src/gallium/auxiliary/vl/vl_compositor.c | 19 +--
>>   1 file changed, 17 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/gallium/auxiliary/vl/vl_compositor.c 
>> b/src/gallium/auxiliary/vl/vl_compositor.c
>> index 7ee8402..66a8fc9 100644
>> --- a/src/gallium/auxiliary/vl/vl_compositor.c
>> +++ b/src/gallium/auxiliary/vl/vl_compositor.c
>> @@ -1376,8 +1376,8 @@ vl_compositor_convert_rgb_to_yuv(struct 
>> vl_compositor_state *s,
>>  s->pipe->flush(s->pipe, NULL, 0);
>>   }
>>   -void
>> -vl_compositor_render(struct vl_compositor_state *s,
>> +static void
>> +vl_compositor_gfx_render(struct vl_compositor_state *s,
>>    struct vl_compositor   *c,
>>    struct pipe_surface    *dst_surface,
>>    struct u_rect  *dirty_area,
>> @@ -1419,6 +1419,21 @@ vl_compositor_render(struct 
>> vl_compositor_state *s,
>>  draw_layers(c, s, dirty_area);
>>   }
>>   +void
>> +vl_compositor_render(struct vl_compositor_state *s,
>> + struct vl_compositor   *c,
>> + struct pipe_surface    *dst_surface,
>> + struct u_rect  *dirty_area,
>> + bool    clear_dirty)
>> +{
>> +   assert(s);
>> +
>> +   if (cs_compositor_render_enable && s->layers->cs)
>> +  vl_compositor_cs_render(s, c, dst_surface, dirty_area, 
>> clear_dirty);
>> +   else
>> +  vl_compositor_gfx_render(s, c, dst_surface, dirty_area, 
>> clear_dirty);
>> +}
>> +
>>   bool
>>   vl_compositor_init(struct vl_compositor *c, struct pipe_context *pipe)
>>   {
>
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Re: [Mesa-dev] [PATCH 1/6] gallium\auxiliary\vl: Move dirty define to header file

2019-02-01 Thread James Zhu

Thanks for point it out!

James

On 2019-02-01 2:33 p.m., Matt Turner wrote:
> My OCD is really bothered by the backslashes in the commit title. Can
> we use forward slashes like all the other commits?
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Re: [Mesa-dev] [PATCH 3/6] gallium\auxiliary\vl: Add compute shader to support video compositor render

2019-02-04 Thread James Zhu


On 2019-02-04 1:47 p.m., Liu, Leo wrote:
> On 2/1/19 11:28 AM, Zhu, James wrote:
>> Add compute shader to support video compositor render.
>>
>> Signed-off-by: James Zhu 
>> ---
>>src/gallium/auxiliary/Makefile.sources  |   2 +
>>src/gallium/auxiliary/meson.build   |   2 +
>>src/gallium/auxiliary/vl/vl_compositor_cs.c | 414 
>> 
>>src/gallium/auxiliary/vl/vl_compositor_cs.h |  56 
>>4 files changed, 474 insertions(+)
>>create mode 100644 src/gallium/auxiliary/vl/vl_compositor_cs.c
>>create mode 100644 src/gallium/auxiliary/vl/vl_compositor_cs.h
>>
>> diff --git a/src/gallium/auxiliary/Makefile.sources 
>> b/src/gallium/auxiliary/Makefile.sources
>> index 50e8808..df000f6 100644
>> --- a/src/gallium/auxiliary/Makefile.sources
>> +++ b/src/gallium/auxiliary/Makefile.sources
>> @@ -348,6 +348,8 @@ VL_SOURCES := \
>>  vl/vl_bicubic_filter.h \
>>  vl/vl_compositor.c \
>>  vl/vl_compositor.h \
>> +vl/vl_compositor_cs.c \
>> +vl/vl_compositor_cs.h \
>>  vl/vl_csc.c \
>>  vl/vl_csc.h \
>>  vl/vl_decoder.c \
>> diff --git a/src/gallium/auxiliary/meson.build 
>> b/src/gallium/auxiliary/meson.build
>> index 57f7e69..74e4b48 100644
>> --- a/src/gallium/auxiliary/meson.build
>> +++ b/src/gallium/auxiliary/meson.build
>> @@ -445,6 +445,8 @@ files_libgalliumvl = files(
>>  'vl/vl_bicubic_filter.h',
>>  'vl/vl_compositor.c',
>>  'vl/vl_compositor.h',
>> +  'vl/vl_compositor_cs.c',
>> +  'vl/vl_compositor_cs.h',
>>  'vl/vl_csc.c',
>>  'vl/vl_csc.h',
>>  'vl/vl_decoder.c',
>> diff --git a/src/gallium/auxiliary/vl/vl_compositor_cs.c 
>> b/src/gallium/auxiliary/vl/vl_compositor_cs.c
>> new file mode 100644
>> index 000..3cd1a76
>> --- /dev/null
>> +++ b/src/gallium/auxiliary/vl/vl_compositor_cs.c
>> @@ -0,0 +1,414 @@
>> +/**
>> + *
>> + * Copyright 2019 Advanced Micro Devices, Inc.
>> + * All Rights Reserved.
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the
>> + * "Software"), to deal in the Software without restriction, including
>> + * without limitation the rights to use, copy, modify, merge, publish,
>> + * distribute, sub license, and/or sell copies of the Software, and to
>> + * permit persons to whom the Software is furnished to do so, subject to
>> + * the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the
>> + * next paragraph) shall be included in all copies or substantial portions
>> + * of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
>> + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
>> + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
>> + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
>> + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>> + *
>> + * Authors: James Zhu 
>> + *
>> + **/
>> +
>> +#include 
>> +
>> +#include "tgsi/tgsi_text.h"
>> +#include "vl_compositor_cs.h"
>> +
>> +struct cs_viewport {
>> +   float scale_x;
>> +   float scale_y;
>> +   int translate_x;
>> +   int translate_y;
>> +   struct u_rect area;
>> +};
>> +
>> +char *compute_shader_video_buffer =
>> +  "COMP\n"
>> +  "PROPERTY CS_FIXED_BLOCK_WIDTH 8\n"
>> +  "PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n"
>> +  "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
>> +
>> +  "DCL SV[0], THREAD_ID\n"
>> +  "DCL SV[1], BLOCK_ID\n"
>> +
>> +  "DCL CONST[0..5]\n"
>> +  "DCL SVIEW[0..2], RECT, FLOAT\n"
>> +  "DCL SAMP[0..2]\n"
>> +
>> +  "DCL IMAGE[0], 2D, WR\n"
>> +  "DCL TEMP[0..7]\n"
>> +
>> +  "IMM[0] UINT32 { 8, 8, 1, 0}\n"
>> +  "IMM[1

Re: [Mesa-dev] [PATCH 3/6] gallium\auxiliary\vl: Add compute shader to support video compositor render

2019-02-04 Thread James Zhu


On 2019-02-04 2:15 p.m., Christian König wrote:
> Am 04.02.19 um 20:12 schrieb James Zhu:
>> On 2019-02-04 1:47 p.m., Liu, Leo wrote:
>>> On 2/1/19 11:28 AM, Zhu, James wrote:
>>>> Add compute shader to support video compositor render.
>>>>
>>>> Signed-off-by: James Zhu 
>>>> ---
>>>>     src/gallium/auxiliary/Makefile.sources  |   2 +
>>>>     src/gallium/auxiliary/meson.build   |   2 +
>>>>     src/gallium/auxiliary/vl/vl_compositor_cs.c | 414 
>>>> 
>>>>     src/gallium/auxiliary/vl/vl_compositor_cs.h |  56 
>>>>     4 files changed, 474 insertions(+)
>>>>     create mode 100644 src/gallium/auxiliary/vl/vl_compositor_cs.c
>>>>     create mode 100644 src/gallium/auxiliary/vl/vl_compositor_cs.h
>>>>
>>>> diff --git a/src/gallium/auxiliary/Makefile.sources 
>>>> b/src/gallium/auxiliary/Makefile.sources
>>>> index 50e8808..df000f6 100644
>>>> --- a/src/gallium/auxiliary/Makefile.sources
>>>> +++ b/src/gallium/auxiliary/Makefile.sources
>>>> @@ -348,6 +348,8 @@ VL_SOURCES := \
>>>>     vl/vl_bicubic_filter.h \
>>>>     vl/vl_compositor.c \
>>>>     vl/vl_compositor.h \
>>>> +    vl/vl_compositor_cs.c \
>>>> +    vl/vl_compositor_cs.h \
>>>>     vl/vl_csc.c \
>>>>     vl/vl_csc.h \
>>>>     vl/vl_decoder.c \
>>>> diff --git a/src/gallium/auxiliary/meson.build 
>>>> b/src/gallium/auxiliary/meson.build
>>>> index 57f7e69..74e4b48 100644
>>>> --- a/src/gallium/auxiliary/meson.build
>>>> +++ b/src/gallium/auxiliary/meson.build
>>>> @@ -445,6 +445,8 @@ files_libgalliumvl = files(
>>>>   'vl/vl_bicubic_filter.h',
>>>>   'vl/vl_compositor.c',
>>>>   'vl/vl_compositor.h',
>>>> +  'vl/vl_compositor_cs.c',
>>>> +  'vl/vl_compositor_cs.h',
>>>>   'vl/vl_csc.c', (refer to MI100 frame capture feature with 
>>>> computer shader support)
>>>>   'vl/vl_csc.h',
>>>>   'vl/vl_decoder.c',
>>>> diff --git a/src/gallium/auxiliary/vl/vl_compositor_cs.c 
>>>> b/src/gallium/auxiliary/vl/vl_compositor_cs.c
>>>> new file mode 100644
>>>> index 000..3cd1a76
>>>> --- /dev/null
>>>> +++ b/src/gallium/auxiliary/vl/vl_compositor_cs.c
>>>> @@ -0,0 +1,414 @@
>>>> +/**
>>>>  
>>>>
>>>> + *
>>>> + * Copyright 2019 Advanced Micro Devices, Inc.
>>>> + * All Rights Reserved.
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person 
>>>> obtaining a
>>>> + * copy of this software and associated documentation files (the
>>>> + * "Software"), to deal in the Software without restriction, 
>>>> including
>>>> + * without limitation the rights to use, copy, modify, merge, 
>>>> publish,
>>>> + * distribute, sub license, and/or sell copies of the Software, 
>>>> and to
>>>> + * permit persons to whom the Software is furnished to do so, 
>>>> subject to
>>>> + * the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice 
>>>> (including the
>>>> + * next paragraph) shall be included in all copies or substantial 
>>>> portions
>>>> + * of the Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
>>>> EXPRESS
>>>> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>>> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
>>>> NON-INFRINGEMENT.
>>>> + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
>>>> + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 
>>>> CONTRACT,
>>>> + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
>>>> + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>>>> + *
>>>> + * Authors: James Zhu 
>>>> + *
>>>> + 
>>>> **/
>>>> +
>>>&g

Re: [Mesa-dev] [PATCH v2 1/7] gallium/auxiliary/vl: Move dirty define to header file

2019-02-07 Thread James Zhu


On 2019-02-07 4:49 a.m., Christian König wrote:
> Patches #1, #2, #5, #7  are Reviewed-by: Christian König 
> 
>
> Patch #3 the csc_matrix need a better name since we now store more and 
> more additional info in there, but that can as well be a follow up patch.

csc_matrix is used by upper stack.Let me figure out how to use 2nd 
constant buffer to hold additional info.

James

>
> Patch #4 is Acked-by: Christian König 
>
> Patch #6 I think there was a simpler option for this.
>
> And when the compute shaders reach the same level of functionality as 
> the GFX shaders we should make this the default, depending on the 
> hardware capabilities.

Sure.

James

>
> Christian.
>
> Am 06.02.19 um 20:44 schrieb Zhu, James:
>> Move dirty define to header file to share with compute shader.
>>
>> Signed-off-by: James Zhu 
>> ---
>>   src/gallium/auxiliary/vl/vl_compositor.c | 15 ++-
>>   src/gallium/auxiliary/vl/vl_compositor.h |  2 ++
>>   2 files changed, 8 insertions(+), 9 deletions(-)
>>
>> diff --git a/src/gallium/auxiliary/vl/vl_compositor.c 
>> b/src/gallium/auxiliary/vl/vl_compositor.c
>> index 159a295..41f9e5e 100644
>> --- a/src/gallium/auxiliary/vl/vl_compositor.c
>> +++ b/src/gallium/auxiliary/vl/vl_compositor.c
>> @@ -42,9 +42,6 @@
>>   #include "vl_types.h"
>>   #include "vl_compositor.h"
>>   -#define MIN_DIRTY (0)
>> -#define MAX_DIRTY (1 << 15)
>> -
>>   enum VS_OUTPUT
>>   {
>>  VS_O_VPOS = 0,
>> @@ -899,8 +896,8 @@ gen_vertex_data(struct vl_compositor *c, struct 
>> vl_compositor_state *s, struct u
>>    dirty->y1 <= drawn.y1) {
>>    // We clear the dirty area anyway, no need for 
>> clear_render_target
>> -   dirty->x0 = dirty->y0 = MAX_DIRTY;
>> -   dirty->x1 = dirty->y1 = MIN_DIRTY;
>> +   dirty->x0 = dirty->y0 = VL_COMPOSITOR_MAX_DIRTY;
>> +   dirty->x1 = dirty->y1 = VL_COMPOSITOR_MIN_DIRTY;
>>   }
>>    }
>>     }
>> @@ -1030,8 +1027,8 @@ vl_compositor_reset_dirty_area(struct u_rect 
>> *dirty)
>>   {
>>  assert(dirty);
>>   -   dirty->x0 = dirty->y0 = MIN_DIRTY;
>> -   dirty->x1 = dirty->y1 = MAX_DIRTY;
>> +   dirty->x0 = dirty->y0 = VL_COMPOSITOR_MIN_DIRTY;
>> +   dirty->x1 = dirty->y1 = VL_COMPOSITOR_MAX_DIRTY;
>>   }
>>     void
>> @@ -1378,8 +1375,8 @@ vl_compositor_render(struct vl_compositor_state 
>> *s,
>>       c->pipe->clear_render_target(c->pipe, dst_surface, 
>> &s->clear_color,
>>  0, 0, dst_surface->width, 
>> dst_surface->height, false);
>> -  dirty_area->x0 = dirty_area->y0 = MAX_DIRTY;
>> -  dirty_area->x1 = dirty_area->y1 = MIN_DIRTY;
>> +  dirty_area->x0 = dirty_area->y0 = VL_COMPOSITOR_MAX_DIRTY;
>> +  dirty_area->x1 = dirty_area->y1 = VL_COMPOSITOR_MIN_DIRTY;
>>  }
>>    c->pipe->set_framebuffer_state(c->pipe, &c->fb_state);
>> diff --git a/src/gallium/auxiliary/vl/vl_compositor.h 
>> b/src/gallium/auxiliary/vl/vl_compositor.h
>> index 8819176..aa843c3 100644
>> --- a/src/gallium/auxiliary/vl/vl_compositor.h
>> +++ b/src/gallium/auxiliary/vl/vl_compositor.h
>> @@ -44,6 +44,8 @@ struct pipe_context;
>>    */
>>     #define VL_COMPOSITOR_MAX_LAYERS 16
>> +#define VL_COMPOSITOR_MIN_DIRTY (0)
>> +#define VL_COMPOSITOR_MAX_DIRTY (1 << 15)
>>     /* deinterlace allgorithem */
>>   enum vl_compositor_deinterlace
>
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Re: [Mesa-dev] [PATCH v2 1/7] gallium/auxiliary/vl: Move dirty define to header file

2019-02-07 Thread James Zhu


On 2019-02-07 9:23 a.m., Christian König wrote:
> Am 07.02.19 um 15:21 schrieb James Zhu:
>> On 2019-02-07 4:49 a.m., Christian König wrote:
>>> Patches #1, #2, #5, #7  are Reviewed-by: Christian König
>>> 
>>>
>>> Patch #3 the csc_matrix need a better name since we now store more and
>>> more additional info in there, but that can as well be a follow up 
>>> patch.
>> csc_matrix is used by upper stack.Let me figure out how to use 2nd
>> constant buffer to hold additional info.
>
> Actually you don't need to add a second one.
>
> We should just rename the variable because there is now more in the 
> buffer than the csc matrix.
>
> Something like shader_params or something similar.

Okay, let me just rename it.

James

>
> Christian.
>
>>
>> James
>>
>>> Patch #4 is Acked-by: Christian König 
>>>
>>> Patch #6 I think there was a simpler option for this.
>>>
>>> And when the compute shaders reach the same level of functionality as
>>> the GFX shaders we should make this the default, depending on the
>>> hardware capabilities.
>> Sure.
>>
>> James
>>
>>> Christian.
>>>
>>> Am 06.02.19 um 20:44 schrieb Zhu, James:
>>>> Move dirty define to header file to share with compute shader.
>>>>
>>>> Signed-off-by: James Zhu 
>>>> ---
>>>>    src/gallium/auxiliary/vl/vl_compositor.c | 15 ++-
>>>>    src/gallium/auxiliary/vl/vl_compositor.h |  2 ++
>>>>    2 files changed, 8 insertions(+), 9 deletions(-)
>>>>
>>>> diff --git a/src/gallium/auxiliary/vl/vl_compositor.c
>>>> b/src/gallium/auxiliary/vl/vl_compositor.c
>>>> index 159a295..41f9e5e 100644
>>>> --- a/src/gallium/auxiliary/vl/vl_compositor.c
>>>> +++ b/src/gallium/auxiliary/vl/vl_compositor.c
>>>> @@ -42,9 +42,6 @@
>>>>    #include "vl_types.h"
>>>>    #include "vl_compositor.h"
>>>>    -#define MIN_DIRTY (0)
>>>> -#define MAX_DIRTY (1 << 15)
>>>> -
>>>>    enum VS_OUTPUT
>>>>    {
>>>>   VS_O_VPOS = 0,
>>>> @@ -899,8 +896,8 @@ gen_vertex_data(struct vl_compositor *c, struct
>>>> vl_compositor_state *s, struct u
>>>>     dirty->y1 <= drawn.y1) {
>>>>     // We clear the dirty area anyway, no need for
>>>> clear_render_target
>>>> -   dirty->x0 = dirty->y0 = MAX_DIRTY;
>>>> -   dirty->x1 = dirty->y1 = MIN_DIRTY;
>>>> +   dirty->x0 = dirty->y0 = VL_COMPOSITOR_MAX_DIRTY;
>>>> +   dirty->x1 = dirty->y1 = VL_COMPOSITOR_MIN_DIRTY;
>>>>    }
>>>>     }
>>>>  }
>>>> @@ -1030,8 +1027,8 @@ vl_compositor_reset_dirty_area(struct u_rect
>>>> *dirty)
>>>>    {
>>>>   assert(dirty);
>>>>    -   dirty->x0 = dirty->y0 = MIN_DIRTY;
>>>> -   dirty->x1 = dirty->y1 = MAX_DIRTY;
>>>> +   dirty->x0 = dirty->y0 = VL_COMPOSITOR_MIN_DIRTY;
>>>> +   dirty->x1 = dirty->y1 = VL_COMPOSITOR_MAX_DIRTY;
>>>>    }
>>>>      void
>>>> @@ -1378,8 +1375,8 @@ vl_compositor_render(struct vl_compositor_state
>>>> *s,
>>>>        c->pipe->clear_render_target(c->pipe, dst_surface,
>>>> &s->clear_color,
>>>>   0, 0, dst_surface->width,
>>>> dst_surface->height, false);
>>>> -  dirty_area->x0 = dirty_area->y0 = MAX_DIRTY;
>>>> -  dirty_area->x1 = dirty_area->y1 = MIN_DIRTY;
>>>> +  dirty_area->x0 = dirty_area->y0 = VL_COMPOSITOR_MAX_DIRTY;
>>>> +  dirty_area->x1 = dirty_area->y1 = VL_COMPOSITOR_MIN_DIRTY;
>>>>   }
>>>>     c->pipe->set_framebuffer_state(c->pipe, &c->fb_state);
>>>> diff --git a/src/gallium/auxiliary/vl/vl_compositor.h
>>>> b/src/gallium/auxiliary/vl/vl_compositor.h
>>>> index 8819176..aa843c3 100644
>>>> --- a/src/gallium/auxiliary/vl/vl_compositor.h
>>>> +++ b/src/gallium/auxiliary/vl/vl_compositor.h
>>>> @@ -44,6 +44,8 @@ struct pipe_context;
>>>>     */
>>>>      #define VL_COMPOSITOR_MAX_LAYERS 16
>>>> +#define VL_COMPOSITOR_MIN_DIRTY (0)
>>>> +#define VL_COMPOSITOR_MAX_DIRTY (1 << 15)
>>>>      /* deinterlace allgorithem */
>>>>    enum vl_compositor_deinterlace
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Re: [Mesa-dev] [PATCH v3 5/6] gallium/auxiliary/vl: Add compute shader initilization, assign and cleanup

2019-02-08 Thread James Zhu


On 2019-02-08 6:33 a.m., Emil Velikov wrote:
> On Thu, 7 Feb 2019 at 16:37, Zhu, James  wrote:
>> Add compute shader initilization, assign and cleanup in vl_compositor API.
>>
>> Signed-off-by: James Zhu 
>> Reviewed-by: Christian König 
>> ---
>>   src/gallium/auxiliary/vl/vl_compositor.c | 31 
>> ++-
>>   src/gallium/auxiliary/vl/vl_compositor.h |  3 +++
>>   2 files changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/auxiliary/vl/vl_compositor.c 
>> b/src/gallium/auxiliary/vl/vl_compositor.c
>> index 4509913..da4b02d 100644
>> --- a/src/gallium/auxiliary/vl/vl_compositor.c
>> +++ b/src/gallium/auxiliary/vl/vl_compositor.c
>> @@ -28,12 +28,31 @@
>>   #include "util/u_sampler.h"
>>
>>   #include "vl_compositor_gfx.h"
>> +#include "vl_compositor_cs.h"
>>
>>   static bool
>>   init_shaders(struct vl_compositor *c)
>>   {
>>  assert(c);
>>
>> +   c->cs_video_buffer = vl_compositor_cs_create_shader(c, 
>> compute_shader_video_buffer);
>> +   if (!c->cs_video_buffer) {
>> +  debug_printf("Unable to create video_buffer compute shader.\n");
>> +  return false;
>> +   }
>> +
>> +   c->cs_weave_rgb = vl_compositor_cs_create_shader(c, 
>> compute_shader_weave);
>> +   if (!c->cs_weave_rgb) {
>> +  debug_printf("Unable to create weave_rgb compute shader.\n");
>> +  return false;
>> +   }
>> +
>> +   c->cs_rgba = vl_compositor_cs_create_shader(c, compute_shader_rgba);
>> +   if (!c->cs_rgba) {
>> +  debug_printf("Unable to create RGB-to-RGB compute shader.\n");
>> +  return false;
>> +   }
>> +
> This constructs compute shaders even when we don't need them.
> Can we have this behind a flag - say cs_compositor_render_enable or
> something else?

Yeah, I can add PIPE_CAP_COMPUTE check.

James

>
> -Emil
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Re: [Mesa-dev] [PATCH v3 5/6] gallium/auxiliary/vl: Add compute shader initilization, assign and cleanup

2019-02-08 Thread James Zhu

I combined patch5 and 6 into one patch. create compute shader only when pipe 
support it.

James.

On 2019-02-08 12:29 p.m., Marek Olšák wrote:
If compute is used, graphics shaders don't need to be created.

Marek

On Fri, Feb 8, 2019 at 9:02 AM James Zhu 
mailto:jam...@amd.com>> wrote:

On 2019-02-08 6:33 a.m., Emil Velikov wrote:
> On Thu, 7 Feb 2019 at 16:37, Zhu, James 
> mailto:james@amd.com>> wrote:
>> Add compute shader initilization, assign and cleanup in vl_compositor API.
>>
>> Signed-off-by: James Zhu mailto:james@amd.com>>
>> Reviewed-by: Christian König 
>> mailto:christian.koe...@amd.com>>
>> ---
>>   src/gallium/auxiliary/vl/vl_compositor.c | 31 
>> ++-
>>   src/gallium/auxiliary/vl/vl_compositor.h |  3 +++
>>   2 files changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/auxiliary/vl/vl_compositor.c 
>> b/src/gallium/auxiliary/vl/vl_compositor.c
>> index 4509913..da4b02d 100644
>> --- a/src/gallium/auxiliary/vl/vl_compositor.c
>> +++ b/src/gallium/auxiliary/vl/vl_compositor.c
>> @@ -28,12 +28,31 @@
>>   #include "util/u_sampler.h"
>>
>>   #include "vl_compositor_gfx.h"
>> +#include "vl_compositor_cs.h"
>>
>>   static bool
>>   init_shaders(struct vl_compositor *c)
>>   {
>>  assert(c);
>>
>> +   c->cs_video_buffer = vl_compositor_cs_create_shader(c, 
>> compute_shader_video_buffer);
>> +   if (!c->cs_video_buffer) {
>> +  debug_printf("Unable to create video_buffer compute shader.\n");
>> +  return false;
>> +   }
>> +
>> +   c->cs_weave_rgb = vl_compositor_cs_create_shader(c, 
>> compute_shader_weave);
>> +   if (!c->cs_weave_rgb) {
>> +  debug_printf("Unable to create weave_rgb compute shader.\n");
>> +  return false;
>> +   }
>> +
>> +   c->cs_rgba = vl_compositor_cs_create_shader(c, compute_shader_rgba);
>> +   if (!c->cs_rgba) {
>> +  debug_printf("Unable to create RGB-to-RGB compute shader.\n");
>> +  return false;
>> +   }
>> +
> This constructs compute shaders even when we don't need them.
> Can we have this behind a flag - say cs_compositor_render_enable or
> something else?

Yeah, I can add PIPE_CAP_COMPUTE check.

James

>
> -Emil
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Re: [Mesa-dev] [PATCH v6 5/5] gallium/auxiliary/vl: Add video compositor compute shader render

2019-02-14 Thread James Zhu


On 2019-02-14 4:44 p.m., Marek Olšák wrote:
This still creates gfx shaders. If we switch MM to compute IBs, calling any gfx 
function will crash.

Right now only fs_video_buffer/fs_weave_rgb/fs_rgba have compute shader 
replacement.

The other gfx shader will be converted to compute shader later.

 James.

Marek

On Tue, Feb 12, 2019, 2:53 PM Zhu, James 
mailto:james@amd.com> wrote:
Add compute shader initilization, assign and cleanup in vl_compositor API.
Set video compositor compute shader render as default when pipe support it.

Signed-off-by: James Zhu mailto:james@amd.com>>
Reviewed-by: Christian König 
mailto:christian.koe...@amd.com>>
---
 src/gallium/auxiliary/vl/vl_compositor.c | 106 +++
 src/gallium/auxiliary/vl/vl_compositor.h |   5 ++
 2 files changed, 83 insertions(+), 28 deletions(-)

diff --git a/src/gallium/auxiliary/vl/vl_compositor.c 
b/src/gallium/auxiliary/vl/vl_compositor.c
index 4509913..8731ad9 100644
--- a/src/gallium/auxiliary/vl/vl_compositor.c
+++ b/src/gallium/auxiliary/vl/vl_compositor.c
@@ -28,6 +28,7 @@
 #include "util/u_sampler.h"

 #include "vl_compositor_gfx.h"
+#include "vl_compositor_cs.h"

 static bool
 init_shaders(struct vl_compositor *c)
@@ -40,18 +41,6 @@ init_shaders(struct vl_compositor *c)
   return false;
}

-   c->fs_video_buffer = create_frag_shader_video_buffer(c);
-   if (!c->fs_video_buffer) {
-  debug_printf("Unable to create YCbCr-to-RGB fragment shader.\n");
-  return false;
-   }
-
-   c->fs_weave_rgb = create_frag_shader_weave_rgb(c);
-   if (!c->fs_weave_rgb) {
-  debug_printf("Unable to create YCbCr-to-RGB weave fragment shader.\n");
-  return false;
-   }
-
c->fs_yuv.weave.y = create_frag_shader_deint_yuv(c, true, true);
c->fs_yuv.weave.uv = create_frag_shader_deint_yuv(c, false, true);
c->fs_yuv.bob.y = create_frag_shader_deint_yuv(c, true, false);
@@ -74,12 +63,6 @@ init_shaders(struct vl_compositor *c)
   return false;
}

-   c->fs_rgba = create_frag_shader_rgba(c);
-   if (!c->fs_rgba) {
-  debug_printf("Unable to create RGB-to-RGB fragment shader.\n");
-  return false;
-   }
-
c->fs_rgb_yuv.y = create_frag_shader_rgb_yuv(c, true);
c->fs_rgb_yuv.uv = create_frag_shader_rgb_yuv(c, false);
if (!c->fs_rgb_yuv.y || !c->fs_rgb_yuv.uv) {
@@ -87,6 +70,44 @@ init_shaders(struct vl_compositor *c)
   return false;
}

+   if (c->pipe_compute_supported) {
+  c->cs_video_buffer = vl_compositor_cs_create_shader(c, 
compute_shader_video_buffer);
+  if (!c->cs_video_buffer) {
+ debug_printf("Unable to create video_buffer compute shader.\n");
+ return false;
+  }
+
+  c->cs_weave_rgb = vl_compositor_cs_create_shader(c, 
compute_shader_weave);
+  if (!c->cs_weave_rgb) {
+ debug_printf("Unable to create weave_rgb compute shader.\n");
+ return false;
+  }
+
+  c->cs_rgba = vl_compositor_cs_create_shader(c, compute_shader_rgba);
+  if (!c->cs_rgba) {
+ debug_printf("Unable to create RGB-to-RGB compute shader.\n");
+ return false;
+  }
+   } else {
+  c->fs_video_buffer = create_frag_shader_video_buffer(c);
+  if (!c->fs_video_buffer) {
+ debug_printf("Unable to create YCbCr-to-RGB fragment shader.\n");
+ return false;
+  }
+
+  c->fs_weave_rgb = create_frag_shader_weave_rgb(c);
+  if (!c->fs_weave_rgb) {
+ debug_printf("Unable to create YCbCr-to-RGB weave fragment 
shader.\n");
+ return false;
+  }
+
+  c->fs_rgba = create_frag_shader_rgba(c);
+  if (!c->fs_rgba) {
+ debug_printf("Unable to create RGB-to-RGB fragment shader.\n");
+ return false;
+  }
+   }
+
return true;
 }

@@ -95,17 +116,24 @@ static void cleanup_shaders(struct vl_compositor *c)
assert(c);

c->pipe->delete_vs_state(c->pipe, c->vs);
-   c->pipe->delete_fs_state(c->pipe, c->fs_video_buffer);
-   c->pipe->delete_fs_state(c->pipe, c->fs_weave_rgb);
c->pipe->delete_fs_state(c->pipe, c->fs_yuv.weave.y);
c->pipe->delete_fs_state(c->pipe, c->fs_yuv.weave.uv);
c->pipe->delete_fs_state(c->pipe, c->fs_yuv.bob.y);
c->pipe->delete_fs_state(c->pipe, c->fs_yuv.bob.uv);
c->pipe->delete_fs_state(c->pipe, c->fs_palette.yuv);
c->pipe->delete_fs_state(c->pipe, c->fs_palette.rgb);
-   c->pipe->delete_fs_state(c->pipe, c->fs_rgba);
c->pipe->delete_fs_state(c->pipe, c->fs_rgb_yuv.y);
c->pipe->delete_fs_state(c->pipe, c->fs_rgb_yuv.uv);
+
+   if (c->pipe_compute_supported) {
+  c->pipe->delete_compute_state(c->pipe, c-

Re: [Mesa-dev] [PATCH v3] gallium/auxiliary/vl: Fix transparent issue on compute shader with rgba

2019-02-20 Thread James Zhu

Hi Filipe,

Can I have your name in the Tested-by list for this patch?

Thanks!

James Zhu


On 2019-02-15 4:19 p.m., Zhu, James wrote:

Fixes: 9364d66cb7f7 (Add video compositor compute shader render)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109646
Problem 1,4: they are caused by imcomplete blend comute shader
implementation. So Reverts rgba back to frament shader.

Signed-off-by: James Zhu <mailto:james@amd.com>
---
 src/gallium/auxiliary/vl/vl_compositor.c | 17 +++--
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/src/gallium/auxiliary/vl/vl_compositor.c 
b/src/gallium/auxiliary/vl/vl_compositor.c
index 8731ad9..a8f3620 100644
--- a/src/gallium/auxiliary/vl/vl_compositor.c
+++ b/src/gallium/auxiliary/vl/vl_compositor.c
@@ -100,12 +100,12 @@ init_shaders(struct vl_compositor *c)
  debug_printf("Unable to create YCbCr-to-RGB weave fragment 
shader.\n");
  return false;
   }
+   }

-  c->fs_rgba = create_frag_shader_rgba(c);
-  if (!c->fs_rgba) {
- debug_printf("Unable to create RGB-to-RGB fragment shader.\n");
- return false;
-  }
+   c->fs_rgba = create_frag_shader_rgba(c);
+   if (!c->fs_rgba) {
+  debug_printf("Unable to create RGB-to-RGB fragment shader.\n");
+  return false;
}

return true;
@@ -132,8 +132,8 @@ static void cleanup_shaders(struct vl_compositor *c)
} else {
   c->pipe->delete_fs_state(c->pipe, c->fs_video_buffer);
   c->pipe->delete_fs_state(c->pipe, c->fs_weave_rgb);
-  c->pipe->delete_fs_state(c->pipe, c->fs_rgba);
}
+   c->pipe->delete_fs_state(c->pipe, c->fs_rgba);
 }

 static bool
@@ -642,10 +642,7 @@ vl_compositor_set_rgba_layer(struct vl_compositor_state *s,
assert(layer < VL_COMPOSITOR_MAX_LAYERS);

s->used_layers |= 1 << layer;
-   if (c->pipe_compute_supported)
-  s->layers[layer].cs = c->cs_rgba;
-   else
-  s->layers[layer].fs = c->fs_rgba;
+   s->layers[layer].fs = c->fs_rgba;
s->layers[layer].samplers[0] = c->sampler_linear;
s->layers[layer].samplers[1] = NULL;
s->layers[layer].samplers[2] = NULL;

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Re: [Mesa-dev] [PATCH] gallium/auxiliary/vl: Fix duplicate symbol build errors.

2019-02-21 Thread James Zhu


On 2019-02-19 10:58 a.m., Emil Velikov wrote:
> On Tue, 19 Feb 2019 at 03:32, Vinson Lee  wrote:
>>CXXLDgallium_dri.la
>> duplicate symbol _compute_shader_video_buffer in:
>>  
>> ../../../../src/gallium/auxiliary/.libs/libgalliumvl.a(libgalliumvl_la-vl_compositor.o)
>>  
>> ../../../../src/gallium/auxiliary/.libs/libgalliumvl.a(libgalliumvl_la-vl_compositor_cs.o)
>> duplicate symbol _compute_shader_weave in:
>>  
>> ../../../../src/gallium/auxiliary/.libs/libgalliumvl.a(libgalliumvl_la-vl_compositor.o)
>>  
>> ../../../../src/gallium/auxiliary/.libs/libgalliumvl.a(libgalliumvl_la-vl_compositor_cs.o)
>> duplicate symbol _compute_shader_rgba in:
>>  
>> ../../../../src/gallium/auxiliary/.libs/libgalliumvl.a(libgalliumvl_la-vl_compositor.o)
>>  
>> ../../../../src/gallium/auxiliary/.libs/libgalliumvl.a(libgalliumvl_la-vl_compositor_cs.o)
>>
>> Fixes: 9364d66cb7f7 ("gallium/auxiliary/vl: Add video compositor compute 
>> shader render")
>> Signed-off-by: Vinson Lee 
>> ---
>>   src/gallium/auxiliary/vl/vl_compositor_cs.h | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/gallium/auxiliary/vl/vl_compositor_cs.h 
>> b/src/gallium/auxiliary/vl/vl_compositor_cs.h
>> index 7a203d327eda..a73a8755fc2a 100644
>> --- a/src/gallium/auxiliary/vl/vl_compositor_cs.h
>> +++ b/src/gallium/auxiliary/vl/vl_compositor_cs.h
>> @@ -32,9 +32,9 @@
>>
>>   #include "vl_compositor.h"
>>
>> -char *compute_shader_video_buffer;
>> -char *compute_shader_weave;
>> -char *compute_shader_rgba;
>> +extern char *compute_shader_video_buffer;
>> +extern char *compute_shader_weave;
>> +extern char *compute_shader_rgba;
>>
> Please make them also "const" - in both here and C file.
>
> With that the patch is
> Reviewed-by: Emil Velikov 

Agreed!

This patch is Reviewed-by: James Zhu 

James

>
> Thanks
> Emil
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Re: [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode

2018-02-19 Thread James Zhu




On 2018-02-16 01:31 PM, Mark Thompson wrote:

On 16/02/18 17:53, James Zhu wrote:

Hi Mark,

I couldn't reproduce the issue on my Polaris 11 to run mpv / ffmpeg about 1.5 
hours.

one terminal run:

ffmpeg -y -hwaccel vaapi -hwaccel_device /dev/dri/renderD128 
-hwaccel_output_format vaapi -i video/Mr.Right.mp4 -an -c:v hevc_vaapi -bf 0 
out.mp4

the other  terminal run:

mpv --fs --loop --no-audio --vo gpu --gpu-context=x11egl --hwdec=vaapi 
video/Mr.Right.mp4
But it has some failure with vaDeriveImage. I am not  sure if this failure 
matters, the video still can play without any other error,

If it's calling vaDeriveImage() at all that suggests it isn't using the proper 
interop path, and may be falling back to software decode.  This should work in 
recent versions of mpv with git Mesa and libva - maybe have a look at the 
verbose output and see what it's actually doing?
I think you are right, it should fall back to software decode. During 
the weekend test, my system hung also with legacy VAAPI test output setting.



mpv --fs --loop --no-audio --vo vaapi  --hwdec=vaapi video/Mr.Right.mp4

No error reported with this command line.

I haven't tried the legacy VAAPI test output, I'll try later to see if that 
also triggers the failure for me.


I don't think that this sort of issue should block the patches in Mesa because 
it looks likely that it is a kernel issue somehow - userspace shouldn't be able 
to nuke the GPU at all.  Still, the feature is essentially unusable for me 
because of this problem, and I imagine it will apply to at least some other 
people with setups which are match mine in some way as yet unknown.
Yeah, if there are no more comments from the community. We will push the 
patches to the upstream tomorrow.


Thanks,

- Mark


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[Mesa-dev] [PATCH] drm/amdgpu:Fixed wrong emit frame size for enc

2018-02-27 Thread James Zhu

Emit frame size should match with corresponding function,
uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write

Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index a3e64e2..f26f515 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1580,7 +1580,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_enc_ring_vm_funcs = {
.set_wptr = uvd_v6_0_enc_ring_set_wptr,
.emit_frame_size =
4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
-   6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
+   5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1, /* uvd_v6_0_enc_ring_insert_end */
.emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] drm/amdgpu:Fixed wrong emit frame size for enc

2018-02-27 Thread James Zhu


wrong tag, re-submit again


On 2018-02-27 10:00 AM, James Zhu wrote:

Emit frame size should match with corresponding function,
uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index a3e64e2..f26f515 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1580,7 +1580,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_enc_ring_vm_funcs = {
.set_wptr = uvd_v6_0_enc_ring_set_wptr,
.emit_frame_size =
4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
-   6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
+   5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1, /* uvd_v6_0_enc_ring_insert_end */
.emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */


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[Mesa-dev] [PATCH 6/8] drivers/radeon:add uvd hevc enc files in Makefile list

2018-02-05 Thread James Zhu

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/Makefile.sources | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index b756d72..f8ee860 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -15,6 +15,9 @@ C_SOURCES := \
radeon_vcn_enc_1_2.c \
radeon_vcn_enc.c \
radeon_vcn_enc.h \
+   radeon_uvd_enc_1_1.c \
+   radeon_uvd_enc.c \
+   radeon_uvd_enc.h \
radeon_vce_40_2_2.c \
radeon_vce_50.c \
radeon_vce_52.c \
-- 
2.7.4

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[Mesa-dev] [PATCH 4/8] drivers/radeon:add uvd hevc enc hw ib implementation

2018-02-05 Thread James Zhu

Implement required IBs for UVD HEVC encode.

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 965 
 1 file changed, 965 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
new file mode 100644
index 000..668799d
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -0,0 +1,965 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = 
(value))
+#define RADEON_ENC_BEGIN(cmd) { \
+   uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
+RADEON_ENC_CS(cmd)
+#define RADEON_ENC_READ(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READ, (domain), (off))
+#define RADEON_ENC_WRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_WRITE, (domain), (off))
+#define RADEON_ENC_READWRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READWRITE, (domain), (off))
+#define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] 
- begin) * 4; \
+   enc->total_task_size += *begin;}
+
+static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
+static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
+
+static void radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc, struct 
pb_buffer *buf,
+ enum 
radeon_bo_usage usage, enum radeon_bo_domain domain,
+ signed offset)
+{
+   enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  
domain, RADEON_PRIO_VCE);
+   uint64_t addr;
+   addr = enc->ws->buffer_get_virtual_address(buf);
+   addr = addr + offset;
+   RADEON_ENC_CS(addr >> 32);
+   RADEON_ENC_CS(addr);
+}
+
+static void radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder 
*enc, bool set)
+{
+   if (set != enc->emulation_prevention) {
+   enc->emulation_prevention = set;
+   enc->num_zeros = 0;
+   }
+}
+
+static void radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc, 
unsigned char byte)
+{
+   if (enc->byte_index == 0)
+   enc->cs->current.buf[enc->cs->current.cdw] = 0;
+   enc->cs->current.buf[enc->cs->current.cdw] |= ((unsigned int)(byte) << 
index_to_shifts[enc->byte_index]);
+   enc->byte_index++;
+
+   if (enc->byte_index >= 4) {
+   enc->byte_index = 0;
+   enc->cs->current.cdw++;
+   }
+}
+
+static void radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder 
*enc, unsigned char byte)
+{
+   if(enc->emulation_prevention) {
+   if((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) 
|| (byte == 0x03))) {
+radeon_uvd_enc_output_one_byte(enc, 0x03);
+enc->bits_output += 8;
+enc->num_zeros = 0;
+}
+enc->num_zer

[Mesa-dev] [PATCH 7/8] drivers/radeonsi:create uvd hevc enc entry

2018-02-05 Thread James Zhu

Add UVD hevc encode pipe video codec creation entry

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeonsi/si_uvd.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c
index 64f2f8e..fa43a96 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -31,7 +31,8 @@
 #include "radeon/radeon_vce.h"
 #include "radeon/radeon_vcn_dec.h"
 #include "radeon/radeon_vcn_enc.h"
-
+#include "radeon/radeon_uvd_enc.h"
+#include "util/u_video.h"
 /**
  * creates an video buffer with an UVD compatible memory layout
  */
@@ -146,9 +147,13 @@ struct pipe_video_codec *si_uvd_create_decoder(struct 
pipe_context *context,
struct si_context *ctx = (struct si_context *)context;
bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
 
-   if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
-   return (vcn) ? radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer) :
-   si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+   if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
+   return (vcn) ? radeon_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer) :
+   
radeon_uvd_create_encoder(context, templ, ctx->b.ws, si_vce_get_buffer);
+   } else
+   return si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   }
 
return (vcn) ?  radeon_create_decoder(context, templ) :
si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
-- 
2.7.4

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[Mesa-dev] [PATCH 3/8] drivers/radeon:add uvd hevc enc hw interface header

2018-02-05 Thread James Zhu

Add hevc encode hardware interface for UVD

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.h | 459 
 1 file changed, 459 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.h 
b/src/gallium/drivers/radeon/radeon_uvd_enc.h
new file mode 100644
index 000..5a132a7
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.h
@@ -0,0 +1,459 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#ifndef _RADEON_UVD_ENC_H
+#define _RADEON_UVD_ENC_H
+
+#define RENC_UVD_FW_INTERFACE_MAJOR_VERSION 1
+#define RENC_UVD_FW_INTERFACE_MINOR_VERSION 1
+
+#define RENC_UVD_IB_PARAM_SESSION_INFO  0x0001
+#define RENC_UVD_IB_PARAM_TASK_INFO 0x0002
+#define RENC_UVD_IB_PARAM_SESSION_INIT  0x0003
+#define RENC_UVD_IB_PARAM_LAYER_CONTROL 0x0004
+#define RENC_UVD_IB_PARAM_LAYER_SELECT  0x0005
+#define RENC_UVD_IB_PARAM_SLICE_CONTROL 0x0006
+#define RENC_UVD_IB_PARAM_SPEC_MISC 0x0007
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x0008
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x0009
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x000a
+#define RENC_UVD_IB_PARAM_SLICE_HEADER  0x000b
+#define RENC_UVD_IB_PARAM_ENCODE_PARAMS 0x000c
+#define RENC_UVD_IB_PARAM_QUALITY_PARAMS0x000d
+#define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER 0x000e
+#define RENC_UVD_IB_PARAM_INTRA_REFRESH 0x000f
+#define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0010
+#define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER0x0011
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER   0x0012
+#define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER0x0013
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL0x0014
+
+#define RENC_UVD_IB_OP_INITIALIZE   0x0801
+#define RENC_UVD_IB_OP_CLOSE_SESSION0x0802
+#define RENC_UVD_IB_OP_ENCODE   0x0803
+#define RENC_UVD_IB_OP_INIT_RC  0x0804
+#define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x0805
+#define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE  0x0806
+#define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE0x0807
+#define RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE0x0808
+
+#define RENC_UVD_IF_MAJOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MAJOR_VERSION_SHIFT 16
+#define RENC_UVD_IF_MINOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MINOR_VERSION_SHIFT 0
+
+#define RENC_UVD_PREENCODE_MODE_NONE0x
+#define RENC_UVD_PREENCODE_MODE_1X  0x0001
+#define RENC_UVD_PREENCODE_MODE_2X  0x0002
+#define RENC_UVD_PREENCODE_MODE_4X  0x0004
+
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS  0x
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_BITS  0x0001
+
+#define RENC_UVD_RATE_CONTROL_METHOD_NONE   0x
+#define RENC_UVD_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR0x0001
+#define RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR   0x0002
+#define RENC_UVD_RATE_CONTROL_METHOD_CBR0x0003
+
+#define RENC_UVD_NALU_TYPE_AUD  0x0001
+#define RE

[Mesa-dev] [PATCH 5/8] drivers/radeon:add uvd hevc enc functions

2018-02-05 Thread James Zhu

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
 1   |  21 ++
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 340 
 2 files changed, 361 insertions(+)
 create mode 100644 1
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/1 b/1
new file mode 100644
index 000..51dd09e
--- /dev/null
+++ b/1
@@ -0,0 +1,21 @@
+r c80294d drivers/radeon:Add uvd hevc enc hw interface header
+pick 2d924d5 drivers/radeon:add uvd hevc enc hw ib implementation
+
+# Rebase f2b9031..2d924d5 onto f2b9031 (2 command(s))
+#
+# Commands:
+# p, pick = use commit
+# r, reword = use commit, but edit the commit message
+# e, edit = use commit, but stop for amending
+# s, squash = use commit, but meld into previous commit
+# f, fixup = like "squash", but discard this commit's log message
+# x, exec = run command (the rest of the line) using shell
+# d, drop = remove commit
+#
+# These lines can be re-ordered; they are executed from top to bottom.
+#
+# If you remove a line here THAT COMMIT WILL BE LOST.
+#
+# However, if you remove everything, the rebase will be aborted.
+#
+# Note that empty commits are commented out
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 000..6eb6cda
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,340 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc, struct 
pipe_h265_enc_picture_desc *picture)
+{
+  struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
+(pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_I);
+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) 
/ 2;
+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
+  enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+  enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+  enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.log2_max_poc = 0;
+  for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+ i = (i >> 1);
+  enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+  enc->enc_pic.pic_width_in_luma_samples = 
pic->seq.pic_width_in_luma_samples;
+  enc->enc_pic.pic_height_in_luma_samples = 
pic->seq.pic_height_in_luma_samples;
+  enc->enc_pic.log2_diff_max_min_luma_codi

[Mesa-dev] [PATCH 2/8] amdgpu/drm:add uvd hevc enc support in amdgpu cs

2018-02-05 Thread James Zhu

Signed-off-by: James Zhu 
---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 1927a3a..6f305b7 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -376,6 +376,7 @@ static bool amdgpu_cs_has_user_fence(struct 
amdgpu_cs_context *cs)
 {
return cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE &&
+  cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC;
 }
@@ -818,6 +819,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD;
   break;
 
+   case RING_UVD_ENC:
+  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD_ENC;
+  break;
+
case RING_VCE:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCE;
   break;
@@ -1533,6 +1538,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
   ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
   break;
case RING_UVD:
+   case RING_UVD_ENC:
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x8000); /* type2 nop packet */
   break;
-- 
2.7.4

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[Mesa-dev] [PATCH 1/8] amd/common:add uvd hevc enc support check in hw query

2018-02-05 Thread James Zhu

Based on amdgpu hardware query information to check if UVD hevc enc support

Signed-off-by: James Zhu 
---
 src/amd/common/ac_gpu_info.c | 10 +-
 src/amd/common/ac_gpu_info.h |  1 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6d9dcb5..2494967 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -98,7 +98,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 {
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
-   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = 
{}, vcn_dec = {}, vcn_enc = {};
+   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc 
= {}, vce = {}, vcn_dec = {}, vcn_enc = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
int r, i, j;
drmDevicePtr devinfo;
@@ -166,6 +166,12 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
return false;
}
 
+   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
+   if (r) {
+   fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) 
failed.\n");
+   return false;
+   }
+
if (info->drm_major == 3 && info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, 
&vcn_dec);
if (r) {
@@ -275,6 +281,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
vce.available_rings ? vce_version : 0;
+   info->uvd_enc_supported =
+   uvd_enc.available_rings ? true : false;
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
info->has_syncobj_wait_for_submit = info->has_syncobj && 
info->drm_minor >= 20;
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index cca3e98..6b120d1 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -65,6 +65,7 @@ struct radeon_info {
uint32_tnum_compute_rings;
uint32_tuvd_fw_version;
uint32_tvce_fw_version;
+   booluvd_enc_supported;
uint32_tme_fw_version;
uint32_tme_fw_feature;
uint32_tpfp_fw_version;
-- 
2.7.4

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[Mesa-dev] [PATCH 8/8] drivers/radeonsi: enable uvd encode for HEVC main

2018-02-05 Thread James Zhu

Enable UVD encode for HEVC main profile

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeonsi/si_get.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 8002362..64f76b4 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -24,6 +24,7 @@
 #include "si_pipe.h"
 #include "radeon/radeon_video.h"
 #include "radeon/radeon_vce.h"
+#include "radeon/radeon_uvd_enc.h"
 #include "ac_llvm_util.h"
 #include "vl/vl_decoder.h"
 #include "vl/vl_video_buffer.h"
@@ -587,7 +588,8 @@ static int si_get_video_param(struct pipe_screen *screen,
(si_vce_is_fw_version_supported(sscreen) ||
sscreen->info.family == CHIP_RAVEN)) ||
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
-   sscreen->info.family == CHIP_RAVEN);
+   (sscreen->info.family == CHIP_RAVEN ||
+   si_radeon_uvd_enc_supported(sscreen)));
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
case PIPE_VIDEO_CAP_MAX_WIDTH:
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 5/8] drivers/radeon:add uvd hevc enc functions

2018-02-05 Thread James Zhu




On 2018-02-05 01:04 PM, Alex Deucher wrote:

On Mon, Feb 5, 2018 at 12:16 PM, James Zhu  wrote:

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
  1   |  21 ++
  src/gallium/drivers/radeon/radeon_uvd_enc.c | 340 
  2 files changed, 361 insertions(+)
  create mode 100644 1
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/1 b/1
new file mode 100644
index 000..51dd09e
--- /dev/null
+++ b/1
@@ -0,0 +1,21 @@
+r c80294d drivers/radeon:Add uvd hevc enc hw interface header
+pick 2d924d5 drivers/radeon:add uvd hevc enc hw ib implementation
+
+# Rebase f2b9031..2d924d5 onto f2b9031 (2 command(s))
+#
+# Commands:
+# p, pick = use commit
+# r, reword = use commit, but edit the commit message
+# e, edit = use commit, but stop for amending
+# s, squash = use commit, but meld into previous commit
+# f, fixup = like "squash", but discard this commit's log message
+# x, exec = run command (the rest of the line) using shell
+# d, drop = remove commit
+#
+# These lines can be re-ordered; they are executed from top to bottom.
+#
+# If you remove a line here THAT COMMIT WILL BE LOST.
+#
+# However, if you remove everything, the rebase will be aborted.
+#
+# Note that empty commits are commented out

Looks like some garbage got accidently added here.

Removed garbage file. send out version 2 patches.

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 000..6eb6cda
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,340 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc, struct 
pipe_h265_enc_picture_desc *picture)
+{
+  struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
+(pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_I);
+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) 
/ 2;
+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
+  enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+  enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+  enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.log2_max_poc = 0;
+  for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+ i = (i >> 1);
+  enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+  enc->

[Mesa-dev] [PATCH 5/8] drivers/radeon:add uvd hevc enc functions

2018-02-05 Thread James Zhu

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 340 
 1 file changed, 340 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 000..6eb6cda
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,340 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc, struct 
pipe_h265_enc_picture_desc *picture)
+{
+  struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
+(pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_I);
+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) 
/ 2;
+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
+  enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+  enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+  enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.log2_max_poc = 0;
+  for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+ i = (i >> 1);
+  enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+  enc->enc_pic.pic_width_in_luma_samples = 
pic->seq.pic_width_in_luma_samples;
+  enc->enc_pic.pic_height_in_luma_samples = 
pic->seq.pic_height_in_luma_samples;
+  enc->enc_pic.log2_diff_max_min_luma_coding_block_size = 
pic->seq.log2_diff_max_min_luma_coding_block_size;
+  enc->enc_pic.log2_min_transform_block_size_minus2 = 
pic->seq.log2_min_transform_block_size_minus2;
+  enc->enc_pic.log2_diff_max_min_transform_block_size = 
pic->seq.log2_diff_max_min_transform_block_size;
+  enc->enc_pic.max_transform_hierarchy_depth_inter = 
pic->seq.max_transform_hierarchy_depth_inter;
+  enc->enc_pic.max_transform_hierarchy_depth_intra = 
pic->seq.max_transform_hierarchy_depth_intra;
+  enc->enc_pic.log2_parallel_merge_level_minus2 = 
pic->pic.log2_parallel_merge_level_minus2;
+  enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
+  enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
+  enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
+  enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
+  enc->enc_pic.sample_adaptive_offset_enable

[Mesa-dev] [PATCH 7/8] drivers/radeonsi:create uvd hevc enc entry

2018-02-05 Thread James Zhu

Add UVD hevc encode pipe video codec creation entry

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeonsi/si_uvd.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c
index 64f2f8e..0dea60d 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -31,6 +31,8 @@
 #include "radeon/radeon_vce.h"
 #include "radeon/radeon_vcn_dec.h"
 #include "radeon/radeon_vcn_enc.h"
+#include "radeon/radeon_uvd_enc.h"
+#include "util/u_video.h"
 
 /**
  * creates an video buffer with an UVD compatible memory layout
@@ -146,9 +148,16 @@ struct pipe_video_codec *si_uvd_create_decoder(struct 
pipe_context *context,
struct si_context *ctx = (struct si_context *)context;
bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
 
-   if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
-   return (vcn) ? radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer) :
-   si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+   if (vcn) {
+   radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   } else {
+   if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC)
+   radeon_uvd_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer);
+   else
+   si_vce_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer);
+   }
+   }
 
return (vcn) ?  radeon_create_decoder(context, templ) :
si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
-- 
2.7.4

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[Mesa-dev] [PATCH v2 7/8] radeonsi:create uvd hevc enc entry

2018-02-06 Thread James Zhu

Add UVD hevc encode pipe video codec creation entry

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeonsi/si_uvd.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c
index 64f2f8e..3906bbd 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -31,6 +31,8 @@
 #include "radeon/radeon_vce.h"
 #include "radeon/radeon_vcn_dec.h"
 #include "radeon/radeon_vcn_enc.h"
+#include "radeon/radeon_uvd_enc.h"
+#include "util/u_video.h"
 
 /**
  * creates an video buffer with an UVD compatible memory layout
@@ -146,9 +148,16 @@ struct pipe_video_codec *si_uvd_create_decoder(struct 
pipe_context *context,
struct si_context *ctx = (struct si_context *)context;
bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
 
-   if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
-   return (vcn) ? radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer) :
-   si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+   if (vcn) {
+   radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   } else {
+   if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC)
+   return radeon_uvd_create_encoder(context, 
templ, ctx->b.ws, si_vce_get_buffer);
+   else
+   return si_vce_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer);
+   }
+   }
 
return (vcn) ?  radeon_create_decoder(context, templ) :
si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
-- 
2.7.4

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[Mesa-dev] [PATCH v2 5/8] radeon/uvd:add uvd hevc enc functions

2018-02-06 Thread James Zhu

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 370 
 1 file changed, 370 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 000..f162589
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,370 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void
+radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
+ struct pipe_h265_enc_picture_desc *pic)
+{
+   enc->enc_pic.picture_type = pic->picture_type;
+   enc->enc_pic.frame_num = pic->frame_num;
+   enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+   enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+   enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+   enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+   enc->enc_pic.not_referenced = pic->not_referenced;
+   enc->enc_pic.is_idr = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR)
+  || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
+   enc->enc_pic.crop_left = 0;
+   enc->enc_pic.crop_right =
+  (align(enc->base.width, 16) - enc->base.width) / 2;
+   enc->enc_pic.crop_top = 0;
+   enc->enc_pic.crop_bottom =
+  (align(enc->base.height, 16) - enc->base.height) / 2;
+   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.log2_max_poc = 0;
+   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+  i = (i >> 1);
+   enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+   enc->enc_pic.pic_width_in_luma_samples =
+  pic->seq.pic_width_in_luma_samples;
+   enc->enc_pic.pic_height_in_luma_samples =
+  pic->seq.pic_height_in_luma_samples;
+   enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
+  pic->seq.log2_diff_max_min_luma_coding_block_size;
+   enc->enc_pic.log2_min_transform_block_size_minus2 =
+  pic->seq.log2_min_transform_block_size_minus2;
+   enc->enc_pic.log2_diff_max_min_transform_block_size =
+  pic->seq.log2_diff_max_min_transform_block_size;
+   enc->enc_pic.max_transform_hierarchy_depth_inter =
+  pic->seq.max_transform_hierarchy_depth_inter;
+   enc->enc_pic.max_transform_hierarchy_depth_intra =
+  pic->seq.max_transform_hierarchy_depth_intra;
+   enc->enc_pic.log2_parallel_merge_level_minus2 =
+  pic->pic.log2_parallel_merge_level_minus2;
+   enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
+   enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
+   enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
+   enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
+   enc->enc_pic.sample_adaptive_offset_enabled_flag =
+  pic->seq.sample_adaptive_offset_enabled_flag;
+   enc->enc_pic.pcm_enabled_flag = pic->seq.pcm_enab

[Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode

2018-02-06 Thread James Zhu

The whole series are the updated version. Changes are made mainly based 
on the comments from prevous code review from Alex, Leo and Boyuan

James Zhu (8):
  amd/common:add uvd hevc enc support check in hw query
  winsys/amdgpu:add uvd hevc enc support in amdgpu cs
  radeon/uvd:add uvd hevc enc hw interface header
  radeon/uvd:add uvd hevc enc hw ib implementation
  radeon/uvd:add uvd hevc enc functions
  radeon/uvd:add uvd hevc enc files in Makefile list
  radeonsi:create uvd hevc enc entry
  radeonsi: enable uvd encode for HEVC main

 src/amd/common/ac_gpu_info.c|   10 +-
 src/amd/common/ac_gpu_info.h|1 +
 src/gallium/drivers/radeon/Makefile.sources |3 +
 src/gallium/drivers/radeon/radeon_uvd_enc.c |  370 
 src/gallium/drivers/radeon/radeon_uvd_enc.h |  471 ++
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1115 +++
 src/gallium/drivers/radeonsi/si_get.c   |4 +-
 src/gallium/drivers/radeonsi/si_uvd.c   |   15 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c   |6 +
 9 files changed, 1990 insertions(+), 5 deletions(-)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

-- 
2.7.4

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[Mesa-dev] [PATCH v2 3/8] radeon/uvd:add uvd hevc enc hw interface header

2018-02-06 Thread James Zhu

Add hevc encode hardware interface for UVD

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.h | 471 
 1 file changed, 471 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.h 
b/src/gallium/drivers/radeon/radeon_uvd_enc.h
new file mode 100644
index 000..1cca0d2
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.h
@@ -0,0 +1,471 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#ifndef _RADEON_UVD_ENC_H
+#define _RADEON_UVD_ENC_H
+
+#define RENC_UVD_FW_INTERFACE_MAJOR_VERSION 1
+#define RENC_UVD_FW_INTERFACE_MINOR_VERSION 1
+
+#define RENC_UVD_IB_PARAM_SESSION_INFO  0x0001
+#define RENC_UVD_IB_PARAM_TASK_INFO 0x0002
+#define RENC_UVD_IB_PARAM_SESSION_INIT  0x0003
+#define RENC_UVD_IB_PARAM_LAYER_CONTROL 0x0004
+#define RENC_UVD_IB_PARAM_LAYER_SELECT  0x0005
+#define RENC_UVD_IB_PARAM_SLICE_CONTROL 0x0006
+#define RENC_UVD_IB_PARAM_SPEC_MISC 0x0007
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x0008
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x0009
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x000a
+#define RENC_UVD_IB_PARAM_SLICE_HEADER  0x000b
+#define RENC_UVD_IB_PARAM_ENCODE_PARAMS 0x000c
+#define RENC_UVD_IB_PARAM_QUALITY_PARAMS0x000d
+#define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER 0x000e
+#define RENC_UVD_IB_PARAM_INTRA_REFRESH 0x000f
+#define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0010
+#define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER0x0011
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER   0x0012
+#define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER0x0013
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL0x0014
+
+#define RENC_UVD_IB_OP_INITIALIZE   0x0801
+#define RENC_UVD_IB_OP_CLOSE_SESSION0x0802
+#define RENC_UVD_IB_OP_ENCODE   0x0803
+#define RENC_UVD_IB_OP_INIT_RC  0x0804
+#define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x0805
+#define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE  0x0806
+#define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE0x0807
+#define RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE0x0808
+
+#define RENC_UVD_IF_MAJOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MAJOR_VERSION_SHIFT 16
+#define RENC_UVD_IF_MINOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MINOR_VERSION_SHIFT 0
+
+#define RENC_UVD_PREENCODE_MODE_NONE0x
+#define RENC_UVD_PREENCODE_MODE_1X  0x0001
+#define RENC_UVD_PREENCODE_MODE_2X  0x0002
+#define RENC_UVD_PREENCODE_MODE_4X  0x0004
+
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS  0x
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_BITS  0x0001
+
+#define RENC_UVD_RATE_CONTROL_METHOD_NONE   0x
+#define RENC_UVD_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR0x0001
+#define RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR   0x0002
+#define RENC_UVD_RATE_CONTROL_METHOD_CBR0x0003
+
+#define RENC_UVD_NALU_TYPE_AUD  0x0001
+#define RE

[Mesa-dev] [PATCH v2 4/8] radeon/uvd:add uvd hevc enc hw ib implementation

2018-02-06 Thread James Zhu

Implement required IBs for UVD HEVC encode.

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1115 +++
 1 file changed, 1115 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
new file mode 100644
index 000..17a39c2
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -0,0 +1,1115 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = 
(value))
+#define RADEON_ENC_BEGIN(cmd) { \
+   uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
+RADEON_ENC_CS(cmd)
+#define RADEON_ENC_READ(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READ, (domain), (off))
+#define RADEON_ENC_WRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_WRITE, (domain), (off))
+#define RADEON_ENC_READWRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READWRITE, (domain), (off))
+#define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] 
- begin) * 4; \
+   enc->total_task_size += *begin;}
+
+static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
+static const unsigned index_to_shifts[4] = { 24, 16, 8, 0 };
+
+static void
+radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc,
+  struct pb_buffer *buf, enum radeon_bo_usage usage,
+  enum radeon_bo_domain domain, signed offset)
+{
+   enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_VCE);
+   uint64_t addr;
+   addr = enc->ws->buffer_get_virtual_address(buf);
+   addr = addr + offset;
+   RADEON_ENC_CS(addr >> 32);
+   RADEON_ENC_CS(addr);
+}
+
+static void
+radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc,
+bool set)
+{
+   if (set != enc->emulation_prevention) {
+  enc->emulation_prevention = set;
+  enc->num_zeros = 0;
+   }
+}
+
+static void
+radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc,
+   unsigned char byte)
+{
+   if (enc->byte_index == 0)
+  enc->cs->current.buf[enc->cs->current.cdw] = 0;
+   enc->cs->current.buf[enc->cs->current.cdw] |=
+  ((unsigned int) (byte) << index_to_shifts[enc->byte_index]);
+   enc->byte_index++;
+
+   if (enc->byte_index >= 4) {
+  enc->byte_index = 0;
+  enc->cs->current.cdw++;
+   }
+}
+
+static void
+radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc,
+unsigned char byte)
+{
+   if (enc->emulation_prevention) {
+  if ((enc->num_zeros >= 2)
+  && ((byte == 0x00) || (byte == 0x01) || (byte == 0x03))) {
+ radeon_uvd_enc_output_one_byte(enc, 0x03);
+ enc->bits_output += 8;
+ enc->num_zeros = 0;
+  }
+  enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
+   }
+}
+
+static void
+radeon_uvd_enc_code_fixed_bi

[Mesa-dev] [PATCH v2 1/8] amd/common:add uvd hevc enc support check in hw query

2018-02-06 Thread James Zhu

Based on amdgpu hardware query information to check if UVD hevc enc support

Signed-off-by: James Zhu 
---
 src/amd/common/ac_gpu_info.c | 10 +-
 src/amd/common/ac_gpu_info.h |  1 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6d9dcb5..2494967 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -98,7 +98,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 {
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
-   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = 
{}, vcn_dec = {}, vcn_enc = {};
+   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc 
= {}, vce = {}, vcn_dec = {}, vcn_enc = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
int r, i, j;
drmDevicePtr devinfo;
@@ -166,6 +166,12 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
return false;
}
 
+   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
+   if (r) {
+   fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) 
failed.\n");
+   return false;
+   }
+
if (info->drm_major == 3 && info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, 
&vcn_dec);
if (r) {
@@ -275,6 +281,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
vce.available_rings ? vce_version : 0;
+   info->uvd_enc_supported =
+   uvd_enc.available_rings ? true : false;
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
info->has_syncobj_wait_for_submit = info->has_syncobj && 
info->drm_minor >= 20;
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index cca3e98..36714ee 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -65,6 +65,7 @@ struct radeon_info {
uint32_tnum_compute_rings;
uint32_tuvd_fw_version;
uint32_tvce_fw_version;
+   booluvd_enc_supported;
uint32_tme_fw_version;
uint32_tme_fw_feature;
uint32_tpfp_fw_version;
-- 
2.7.4

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[Mesa-dev] [PATCH v2 8/8] radeonsi: enable uvd encode for HEVC main

2018-02-06 Thread James Zhu

Enable UVD encode for HEVC main profile

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeonsi/si_get.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 8002362..64f76b4 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -24,6 +24,7 @@
 #include "si_pipe.h"
 #include "radeon/radeon_video.h"
 #include "radeon/radeon_vce.h"
+#include "radeon/radeon_uvd_enc.h"
 #include "ac_llvm_util.h"
 #include "vl/vl_decoder.h"
 #include "vl/vl_video_buffer.h"
@@ -587,7 +588,8 @@ static int si_get_video_param(struct pipe_screen *screen,
(si_vce_is_fw_version_supported(sscreen) ||
sscreen->info.family == CHIP_RAVEN)) ||
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
-   sscreen->info.family == CHIP_RAVEN);
+   (sscreen->info.family == CHIP_RAVEN ||
+   si_radeon_uvd_enc_supported(sscreen)));
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
case PIPE_VIDEO_CAP_MAX_WIDTH:
-- 
2.7.4

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[Mesa-dev] [PATCH v2 2/8] winsys/amdgpu:add uvd hevc enc support in amdgpu cs

2018-02-06 Thread James Zhu

Support UVD HEVC encode in amdgpu cs

Signed-off-by: James Zhu 
---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 1927a3a..92d5394 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -376,6 +376,7 @@ static bool amdgpu_cs_has_user_fence(struct 
amdgpu_cs_context *cs)
 {
return cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE &&
+  cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC;
 }
@@ -818,6 +819,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD;
   break;
 
+   case RING_UVD_ENC:
+  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD_ENC;
+  break;
+
case RING_VCE:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCE;
   break;
@@ -1533,6 +1538,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
   ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
   break;
case RING_UVD:
+   case RING_UVD_ENC:
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x8000); /* type2 nop packet */
   break;
-- 
2.7.4

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[Mesa-dev] [PATCH v2 6/8] radeon/uvd:add uvd hevc enc files in Makefile list

2018-02-06 Thread James Zhu

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/Makefile.sources | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index b756d72..f8ee860 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -15,6 +15,9 @@ C_SOURCES := \
radeon_vcn_enc_1_2.c \
radeon_vcn_enc.c \
radeon_vcn_enc.h \
+   radeon_uvd_enc_1_1.c \
+   radeon_uvd_enc.c \
+   radeon_uvd_enc.h \
radeon_vce_40_2_2.c \
radeon_vce_50.c \
radeon_vce_52.c \
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 7/8] drivers/radeonsi:create uvd hevc enc entry

2018-02-06 Thread James Zhu


Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-06 08:56 AM, Leo Liu wrote:

General comments:

1. The patch title: please refer to previous commits under the directory,

https://cgit.freedesktop.org/mesa/mesa/log/src/gallium/drivers/radeon

Normally either "radeon/uvd" or "radeonsi"

Applies to changes on other directory.

2. Code style and indentation refer to:

https://cgit.freedesktop.org/mesa/mesa/tree/docs/codingstyle.html

3. If you have changes on the initial version, you'd better to add v2, 
v3. It's good practice in that way.

please refer to lots of commits in Mesa.

4. Once you resend your v2 version, you'd better to add 
"--in-reply-to="message-id", so that the newer patch will be in the 
same thread with your initial patch.



Leo

On 02/05/2018 04:14 PM, James Zhu wrote:

Add UVD hevc encode pipe video codec creation entry

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeonsi/si_uvd.c | 15 ---
  1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c

index 64f2f8e..0dea60d 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -31,6 +31,8 @@
  #include "radeon/radeon_vce.h"
  #include "radeon/radeon_vcn_dec.h"
  #include "radeon/radeon_vcn_enc.h"
+#include "radeon/radeon_uvd_enc.h"
+#include "util/u_video.h"
    /**
   * creates an video buffer with an UVD compatible memory layout
@@ -146,9 +148,16 @@ struct pipe_video_codec 
*si_uvd_create_decoder(struct pipe_context *context,

  struct si_context *ctx = (struct si_context *)context;
  bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
  -    if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
-    return (vcn) ? radeon_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer) :
-   si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+    if (vcn) {
+    radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    } else {
+    if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC)
+    radeon_uvd_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    else
+    si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    }
+    }
    return (vcn) ? radeon_create_decoder(context, templ) :
  si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);




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Re: [Mesa-dev] [PATCH 7/8] drivers/radeonsi:create uvd hevc enc entry

2018-02-06 Thread James Zhu


Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-05 03:25 PM, Boyuan Zhang wrote:



On 2018-02-05 12:16 PM, James Zhu wrote:

Add UVD hevc encode pipe video codec creation entry

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeonsi/si_uvd.c | 13 +
  1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c

index 64f2f8e..fa43a96 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -31,7 +31,8 @@
  #include "radeon/radeon_vce.h"
  #include "radeon/radeon_vcn_dec.h"
  #include "radeon/radeon_vcn_enc.h"
-
+#include "radeon/radeon_uvd_enc.h"
+#include "util/u_video.h"

Could you add back the blank line please?

  /**
   * creates an video buffer with an UVD compatible memory layout
   */
@@ -146,9 +147,13 @@ struct pipe_video_codec 
*si_uvd_create_decoder(struct pipe_context *context,

  struct si_context *ctx = (struct si_context *)context;
  bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
  -    if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
-    return (vcn) ? radeon_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer) :
-   si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+    if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
+    return (vcn) ? radeon_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer) :
+    radeon_uvd_create_encoder(context, 
templ, ctx->b.ws, si_vce_get_buffer);

+    } else
+    return si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    }
It seems that this change will break the original logic for vcn h.264 
encode case, please fix it.


Thanks,
Boyuan


    return (vcn) ? radeon_create_decoder(context, templ) :
  si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);




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Re: [Mesa-dev] [PATCH 5/8] drivers/radeon:add uvd hevc enc functions

2018-02-06 Thread James Zhu


Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-06 10:27 AM, Boyuan Zhang wrote:



On 2018-02-05 02:41 PM, James Zhu wrote:

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeon/radeon_uvd_enc.c | 340 


  1 file changed, 340 insertions(+)
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c

new file mode 100644
index 000..6eb6cda
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,340 @@
+/** 


+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person 
obtaining a

+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, 
subject to

+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial 
portions

+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
EXPRESS

+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
NON-INFRINGEMENT.

+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 
CONTRACT,

+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ 
**/

+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc, 
struct pipe_h265_enc_picture_desc *picture)

+{
+  struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;


This line is unnecessary. Same type on both sides.


+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
+    (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_I);

+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - 
enc->base.width) / 2;

+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;

+  enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+  enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+  enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.log2_max_poc = 0;
+  for (int i = enc->enc_pic.max_poc; i != 0; 
enc->enc_pic.log2_max_poc++)

+ i = (i >> 1);
+  enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+  enc->enc_pic.pic_width_in_luma_samples = 
pic->seq.pic_width_in_luma_samples;
+  enc->enc_pic.pic_height_in_luma_samples = 
pic->seq.pic_height_in_luma_samples;
+  enc->enc_pic.log2_diff_max_min_luma_coding_block_size = 
pic->seq.log2_diff_max_min_luma_coding_block_size;
+  enc->enc_pic.log2_min_transform_block_size_minus2 = 
pic->seq.log2_min_transform_block_size_minus2;
+  enc->enc_pic.log2_diff_max_min_transform_block_size = 
pic->seq.log2_diff_max_min_transform_block_size;
+  enc->enc_pic.max_transform_hierarchy_depth_inter = 
pic->seq.max_transform_hierarchy_depth_inter;
+  enc->enc_pic.max_transform_hierarchy_depth_intra = 
pic->seq.max_transform_hierarchy_depth_intra;
+  enc->enc_pic.log2_parallel_merge_level_minus2 = 
pic->pic.log2_parallel_merge_level_minus2;
+  enc->enc_pic.bit_depth_luma_minus8 = 
pic->seq.bit_depth_luma_minus8;
+  enc-&

Re: [Mesa-dev] [PATCH 5/8] drivers/radeon:add uvd hevc enc functions

2018-02-06 Thread James Zhu


Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-05 02:30 PM, James Zhu wrote:



On 2018-02-05 01:04 PM, Alex Deucher wrote:

On Mon, Feb 5, 2018 at 12:16 PM, James Zhu  wrote:

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
  1   |  21 ++
  src/gallium/drivers/radeon/radeon_uvd_enc.c | 340 


  2 files changed, 361 insertions(+)
  create mode 100644 1
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/1 b/1
new file mode 100644
index 000..51dd09e
--- /dev/null
+++ b/1
@@ -0,0 +1,21 @@
+r c80294d drivers/radeon:Add uvd hevc enc hw interface header
+pick 2d924d5 drivers/radeon:add uvd hevc enc hw ib implementation
+
+# Rebase f2b9031..2d924d5 onto f2b9031 (2 command(s))
+#
+# Commands:
+# p, pick = use commit
+# r, reword = use commit, but edit the commit message
+# e, edit = use commit, but stop for amending
+# s, squash = use commit, but meld into previous commit
+# f, fixup = like "squash", but discard this commit's log message
+# x, exec = run command (the rest of the line) using shell
+# d, drop = remove commit
+#
+# These lines can be re-ordered; they are executed from top to bottom.
+#
+# If you remove a line here THAT COMMIT WILL BE LOST.
+#
+# However, if you remove everything, the rebase will be aborted.
+#
+# Note that empty commits are commented out

Looks like some garbage got accidently added here.

Removed garbage file. send out version 2 patches.
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c

new file mode 100644
index 000..6eb6cda
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,340 @@
+/** 


+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person 
obtaining a

+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, 
subject to

+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including 
the
+ * next paragraph) shall be included in all copies or substantial 
portions

+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
EXPRESS

+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE 
FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 
CONTRACT,

+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ 
**/

+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder 
*enc, struct pipe_h265_enc_picture_desc *picture)

+{
+  struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;

+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
+    (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_I);

+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - 
enc->base.width) / 2;

+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;

+  enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+  enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+  enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.log2_max_poc = 0;
+  for (int i = enc->enc_pic.max_poc; i != 0; 
enc->

Re: [Mesa-dev] [PATCH 8/8] drivers/radeonsi: enable uvd encode for HEVC main

2018-02-06 Thread James Zhu


Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-06 11:13 AM, Boyuan Zhang wrote:

this patch is Reviewed-by: Boyuan Zhang 


On 2018-02-05 12:16 PM, James Zhu wrote:

Enable UVD encode for HEVC main profile

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeonsi/si_get.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c

index 8002362..64f76b4 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -24,6 +24,7 @@
  #include "si_pipe.h"
  #include "radeon/radeon_video.h"
  #include "radeon/radeon_vce.h"
+#include "radeon/radeon_uvd_enc.h"
  #include "ac_llvm_util.h"
  #include "vl/vl_decoder.h"
  #include "vl/vl_video_buffer.h"
@@ -587,7 +588,8 @@ static int si_get_video_param(struct pipe_screen 
*screen,

  (si_vce_is_fw_version_supported(sscreen) ||
  sscreen->info.family == CHIP_RAVEN)) ||
  (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
-    sscreen->info.family == CHIP_RAVEN);
+    (sscreen->info.family == CHIP_RAVEN ||
+    si_radeon_uvd_enc_supported(sscreen)));
  case PIPE_VIDEO_CAP_NPOT_TEXTURES:
  return 1;
  case PIPE_VIDEO_CAP_MAX_WIDTH:




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Re: [Mesa-dev] [PATCH 2/8] amdgpu/drm:add uvd hevc enc support in amdgpu cs

2018-02-06 Thread James Zhu


Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-05 04:12 PM, Boyuan Zhang wrote:



On 2018-02-05 12:16 PM, James Zhu wrote:

Signed-off-by: James Zhu 
---
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

index 1927a3a..6f305b7 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -376,6 +376,7 @@ static bool amdgpu_cs_has_user_fence(struct 
amdgpu_cs_context *cs)

  {
 return cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD &&
    cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE &&
+  cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC &&
    cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC &&
    cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC;
  }
@@ -818,6 +819,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,

    cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD;
    break;
  +   case RING_UVD_ENC:
+   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD_ENC;
+   break;
+


Please follow previous indentation, use space instead of tab here.

Also, the patch name might better be changed to winsys/amdgpu.

With those fixed, this patch is
Reviewed-by: Boyuan Zhang 

Thanks,
Boyuan



 case RING_VCE:
    cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCE;
    break;
@@ -1533,6 +1538,7 @@ static int amdgpu_cs_flush(struct 
radeon_winsys_cs *rcs,
    ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) 
* 4;

    break;
 case RING_UVD:
+   case RING_UVD_ENC:
    while (rcs->current.cdw & 15)
   radeon_emit(rcs, 0x8000); /* type2 nop packet */
    break;




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[Mesa-dev] [PATCH V3 1/8] amd/common:add uvd hevc enc support check in hw query

2018-02-07 Thread James Zhu

Based on amdgpu hardware query information to check if UVD hevc enc support

Signed-off-by: James Zhu 
---
 src/amd/common/ac_gpu_info.c | 12 +++-
 src/amd/common/ac_gpu_info.h |  1 +
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6d9dcb5..3156df6 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -98,7 +98,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 {
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
-   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = 
{}, vcn_dec = {}, vcn_enc = {};
+   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc 
= {}, vce = {}, vcn_dec = {}, vcn_enc = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
int r, i, j;
drmDevicePtr devinfo;
@@ -167,6 +167,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
 
if (info->drm_major == 3 && info->drm_minor >= 17) {
+   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, 
&uvd_enc);
+   if (r) {
+   fprintf(stderr, "amdgpu: 
amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
+   return false;
+   }
+   }
+
+   if (info->drm_major == 3 && info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, 
&vcn_dec);
if (r) {
fprintf(stderr, "amdgpu: 
amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
@@ -275,6 +283,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
vce.available_rings ? vce_version : 0;
+   info->uvd_enc_supported =
+   uvd_enc.available_rings ? true : false;
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
info->has_syncobj_wait_for_submit = info->has_syncobj && 
info->drm_minor >= 20;
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index cca3e98..36714ee 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -65,6 +65,7 @@ struct radeon_info {
uint32_tnum_compute_rings;
uint32_tuvd_fw_version;
uint32_tvce_fw_version;
+   booluvd_enc_supported;
uint32_tme_fw_version;
uint32_tme_fw_feature;
uint32_tpfp_fw_version;
-- 
2.7.4

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Re: [Mesa-dev] [PATCH v2 6/8] radeon/uvd:add uvd hevc enc files in Makefile list

2018-02-07 Thread James Zhu




On 2018-02-07 09:48 AM, Christian König wrote:

Am 07.02.2018 um 15:47 schrieb Leo Liu:



On 02/06/2018 03:05 PM, James Zhu wrote:

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeon/Makefile.sources | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources

index b756d72..f8ee860 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -15,6 +15,9 @@ C_SOURCES := \
  radeon_vcn_enc_1_2.c \
  radeon_vcn_enc.c \
  radeon_vcn_enc.h \
+    radeon_uvd_enc_1_1.c \
+    radeon_uvd_enc.c \
+    radeon_uvd_enc.h \

We need to add this to Meson build as well, like VCN ENC does.


And we usually add files to Makefile.source and Meson when they are 
first added/used.


So adding all at once is not the usual approach.

Christian.

Since it needs change other patches, I will keep all at once this time. 
Next time, I will update build list when file is first-time added/used.

thanks! James



Leo


  radeon_vce_40_2_2.c \
  radeon_vce_50.c \
  radeon_vce_52.c \


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[Mesa-dev] [PATCH v3 6/8] radeon/uvd:add uvd hevc enc files in build list

2018-02-07 Thread James Zhu

add uvd hevc enc files in meson.build and Makefile.sources

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/Makefile.sources | 3 +++
 src/gallium/drivers/radeon/meson.build  | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index b756d72..f8ee860 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -15,6 +15,9 @@ C_SOURCES := \
radeon_vcn_enc_1_2.c \
radeon_vcn_enc.c \
radeon_vcn_enc.h \
+   radeon_uvd_enc_1_1.c \
+   radeon_uvd_enc.c \
+   radeon_uvd_enc.h \
radeon_vce_40_2_2.c \
radeon_vce_50.c \
radeon_vce_52.c \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index 6857df3..582a5ff 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -35,6 +35,9 @@ files_libradeon = files(
   'radeon_vcn_enc.h',
   'radeon_vcn_dec.c',
   'radeon_vcn_dec.h',
+  'radeon_uvd_enc_1_1.c',
+  'radeon_uvd_enc.c',
+  'radeon_uvd_enc.h',
   'radeon_vce_40_2_2.c',
   'radeon_vce_50.c',
   'radeon_vce_52.c',
-- 
2.7.4

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Re: [Mesa-dev] [PATCH v2 3/8] radeon/uvd:add uvd hevc enc hw interface header

2018-02-09 Thread James Zhu


in order keep the patch order for tacking. I will update at final update


On 2018-02-07 05:40 PM, Boyuan Zhang wrote:


Better to add it to Makefile.source and Meson in this patch. Other 
than this,


this patch is Reviewed-by: Boyuan Zhang 


On 2018-02-06 03:05 PM, James Zhu wrote:

Add hevc encode hardware interface for UVD

Signed-off-by: James Zhu
---
  src/gallium/drivers/radeon/radeon_uvd_enc.h | 471 
  1 file changed, 471 insertions(+)
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.h 
b/src/gallium/drivers/radeon/radeon_uvd_enc.h
new file mode 100644
index 000..1cca0d2
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.h
@@ -0,0 +1,471 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#ifndef _RADEON_UVD_ENC_H
+#define _RADEON_UVD_ENC_H
+
+#define RENC_UVD_FW_INTERFACE_MAJOR_VERSION 1
+#define RENC_UVD_FW_INTERFACE_MINOR_VERSION 1
+
+#define RENC_UVD_IB_PARAM_SESSION_INFO  0x0001
+#define RENC_UVD_IB_PARAM_TASK_INFO 0x0002
+#define RENC_UVD_IB_PARAM_SESSION_INIT  0x0003
+#define RENC_UVD_IB_PARAM_LAYER_CONTROL 0x0004
+#define RENC_UVD_IB_PARAM_LAYER_SELECT  0x0005
+#define RENC_UVD_IB_PARAM_SLICE_CONTROL 0x0006
+#define RENC_UVD_IB_PARAM_SPEC_MISC 0x0007
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x0008
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x0009
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x000a
+#define RENC_UVD_IB_PARAM_SLICE_HEADER  0x000b
+#define RENC_UVD_IB_PARAM_ENCODE_PARAMS 0x000c
+#define RENC_UVD_IB_PARAM_QUALITY_PARAMS0x000d
+#define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER 0x000e
+#define RENC_UVD_IB_PARAM_INTRA_REFRESH 0x000f
+#define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0010
+#define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER0x0011
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER   0x0012
+#define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER0x0013
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL0x0014
+
+#define RENC_UVD_IB_OP_INITIALIZE   0x0801
+#define RENC_UVD_IB_OP_CLOSE_SESSION0x0802
+#define RENC_UVD_IB_OP_ENCODE   0x0803
+#define RENC_UVD_IB_OP_INIT_RC  0x0804
+#define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x0805
+#define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE  0x0806
+#define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE0x0807
+#define RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE0x0808
+
+#define RENC_UVD_IF_MAJOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MAJOR_VERSION_SHIFT 16
+#define RENC_UVD_IF_MINOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MINOR_VERSION_SHIFT 0
+
+#define RENC_UVD_PREENCODE_MODE_NONE0x
+#define RENC_UVD_PREENCODE_MODE_1X  0x0001
+#define RENC_UVD_PREENCODE_MODE_2X  0x0002
+#define RENC_UVD_PREENCODE_MODE_4X  0x0004
+
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS  0x
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_BITS  0x0001
+
+#define RENC_UVD_RATE_CONTROL_METHOD_NONE

[Mesa-dev] [PATCH v3 3/8] radeon/uvd:add uvd hevc enc hw interface header

2018-02-09 Thread James Zhu

Add hevc encode hardware interface for UVD

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.h | 471 
 1 file changed, 471 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.h 
b/src/gallium/drivers/radeon/radeon_uvd_enc.h
new file mode 100644
index 000..ef9d37d
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.h
@@ -0,0 +1,471 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#ifndef _RADEON_UVD_ENC_H
+#define _RADEON_UVD_ENC_H
+
+#define RENC_UVD_FW_INTERFACE_MAJOR_VERSION 1
+#define RENC_UVD_FW_INTERFACE_MINOR_VERSION 1
+
+#define RENC_UVD_IB_PARAM_SESSION_INFO  0x0001
+#define RENC_UVD_IB_PARAM_TASK_INFO 0x0002
+#define RENC_UVD_IB_PARAM_SESSION_INIT  0x0003
+#define RENC_UVD_IB_PARAM_LAYER_CONTROL 0x0004
+#define RENC_UVD_IB_PARAM_LAYER_SELECT  0x0005
+#define RENC_UVD_IB_PARAM_SLICE_CONTROL 0x0006
+#define RENC_UVD_IB_PARAM_SPEC_MISC 0x0007
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x0008
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x0009
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x000a
+#define RENC_UVD_IB_PARAM_SLICE_HEADER  0x000b
+#define RENC_UVD_IB_PARAM_ENCODE_PARAMS 0x000c
+#define RENC_UVD_IB_PARAM_QUALITY_PARAMS0x000d
+#define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER 0x000e
+#define RENC_UVD_IB_PARAM_INTRA_REFRESH 0x000f
+#define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0010
+#define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER0x0011
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER   0x0012
+#define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER0x0013
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL0x0014
+
+#define RENC_UVD_IB_OP_INITIALIZE   0x0801
+#define RENC_UVD_IB_OP_CLOSE_SESSION0x0802
+#define RENC_UVD_IB_OP_ENCODE   0x0803
+#define RENC_UVD_IB_OP_INIT_RC  0x0804
+#define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x0805
+#define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE  0x0806
+#define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE0x0807
+#define RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE0x0808
+
+#define RENC_UVD_IF_MAJOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MAJOR_VERSION_SHIFT 16
+#define RENC_UVD_IF_MINOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MINOR_VERSION_SHIFT 0
+
+#define RENC_UVD_PREENCODE_MODE_NONE0x
+#define RENC_UVD_PREENCODE_MODE_1X  0x0001
+#define RENC_UVD_PREENCODE_MODE_2X  0x0002
+#define RENC_UVD_PREENCODE_MODE_4X  0x0004
+
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS  0x
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_BITS  0x0001
+
+#define RENC_UVD_RATE_CONTROL_METHOD_NONE   0x
+#define RENC_UVD_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR0x0001
+#define RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR   0x0002
+#define RENC_UVD_RATE_CONTROL_METHOD_CBR0x0003
+
+#define RENC_UVD_NALU_TYPE_AUD  0x0001
+#define RE

[Mesa-dev] [PATCH v3 4/8] radeon/uvd:add uvd hevc enc hw ib implementation

2018-02-09 Thread James Zhu

Implement required IBs for UVD HEVC encode.

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1115 +++
 1 file changed, 1115 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
new file mode 100644
index 000..2b8156e
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -0,0 +1,1115 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = 
(value))
+#define RADEON_ENC_BEGIN(cmd) { \
+   uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
+RADEON_ENC_CS(cmd)
+#define RADEON_ENC_READ(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READ, (domain), (off))
+#define RADEON_ENC_WRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_WRITE, (domain), (off))
+#define RADEON_ENC_READWRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READWRITE, (domain), (off))
+#define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] 
- begin) * 4; \
+   enc->total_task_size += *begin;}
+
+static const unsigned index_to_shifts[4] = { 24, 16, 8, 0 };
+
+static void
+radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc,
+  struct pb_buffer *buf, enum radeon_bo_usage usage,
+  enum radeon_bo_domain domain, signed offset)
+{
+   enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_VCE);
+   uint64_t addr;
+   addr = enc->ws->buffer_get_virtual_address(buf);
+   addr = addr + offset;
+   RADEON_ENC_CS(addr >> 32);
+   RADEON_ENC_CS(addr);
+}
+
+static void
+radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc,
+bool set)
+{
+   if (set != enc->emulation_prevention) {
+  enc->emulation_prevention = set;
+  enc->num_zeros = 0;
+   }
+}
+
+static void
+radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc,
+   unsigned char byte)
+{
+   if (enc->byte_index == 0)
+  enc->cs->current.buf[enc->cs->current.cdw] = 0;
+   enc->cs->current.buf[enc->cs->current.cdw] |=
+  ((unsigned int) (byte) << index_to_shifts[enc->byte_index]);
+   enc->byte_index++;
+
+   if (enc->byte_index >= 4) {
+  enc->byte_index = 0;
+  enc->cs->current.cdw++;
+   }
+}
+
+static void
+radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc,
+unsigned char byte)
+{
+   if (enc->emulation_prevention) {
+  if ((enc->num_zeros >= 2)
+  && ((byte == 0x00) || (byte == 0x01) || (byte == 0x03))) {
+ radeon_uvd_enc_output_one_byte(enc, 0x03);
+ enc->bits_output += 8;
+ enc->num_zeros = 0;
+  }
+  enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
+   }
+}
+
+static void
+radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder *enc,
+   unsigned int value, uns

[Mesa-dev] [PATCH v3 5/8] radeon/uvd:add uvd hevc enc functions

2018-02-09 Thread James Zhu

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 381 
 1 file changed, 381 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 000..ad8b951
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,381 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define UVD_HEVC_LEVEL_1   30
+#define UVD_HEVC_LEVEL_2   60
+#define UVD_HEVC_LEVEL_2_1 63
+#define UVD_HEVC_LEVEL_3   90
+#define UVD_HEVC_LEVEL_3_1 93
+#define UVD_HEVC_LEVEL_4   120
+#define UVD_HEVC_LEVEL_4_1 123
+#define UVD_HEVC_LEVEL_5   150
+#define UVD_HEVC_LEVEL_5_1 153
+#define UVD_HEVC_LEVEL_5_2 156
+#define UVD_HEVC_LEVEL_6   180
+#define UVD_HEVC_LEVEL_6_1 183
+#define UVD_HEVC_LEVEL_6_2 186
+
+static void
+radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
+ struct pipe_h265_enc_picture_desc *pic)
+{
+   enc->enc_pic.picture_type = pic->picture_type;
+   enc->enc_pic.frame_num = pic->frame_num;
+   enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+   enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+   enc->enc_pic.not_referenced = pic->not_referenced;
+   enc->enc_pic.is_iframe =
+  (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR)
+  || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
+   enc->enc_pic.crop_left = 0;
+   enc->enc_pic.crop_right =
+  (align(enc->base.width, 16) - enc->base.width) / 2;
+   enc->enc_pic.crop_top = 0;
+   enc->enc_pic.crop_bottom =
+  (align(enc->base.height, 16) - enc->base.height) / 2;
+   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.log2_max_poc = 0;
+   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+  i = (i >> 1);
+   enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+   enc->enc_pic.pic_width_in_luma_samples =
+  pic->seq.pic_width_in_luma_samples;
+   enc->enc_pic.pic_height_in_luma_samples =
+  pic->seq.pic_height_in_luma_samples;
+   enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
+  pic->seq.log2_diff_max_min_luma_coding_block_size;
+   enc->enc_pic.log2_min_transform_block_size_minus2 =
+  pic->seq.log2_min_transform_block_size_minus2;
+   enc->enc_pic.log2_diff_max_min_transform_block_size =
+  pic->seq.log2_diff_max_min_transform_block_size;
+   enc->enc_pic.max_transform_hierarchy_depth_inter =
+  pic->seq.max_transform_hierarchy_depth_inter;
+   enc->enc_pic.max_transform_hierarchy_depth_intra =
+  pic->seq.max_transform_hierarchy_depth_intra;
+   enc->enc_pic.log2_parallel_merge_level_minus2 =
+  pic->pic.log2_parallel_merge_level_minus2;
+   enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
+   enc->enc_

Re: [Mesa-dev] [PATCH v2 5/8] radeon/uvd:add uvd hevc enc functions

2018-02-09 Thread James Zhu


Hi Mark,

thanks for point them out. [PATCH v3 3/8] / [PATCH v3 4/8] / [PATCH v3 
5/8] update according.


James.


On 2018-02-08 05:23 PM, Mark Thompson wrote:

On 06/02/18 20:05, James Zhu wrote:

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeon/radeon_uvd_enc.c | 370 
  1 file changed, 370 insertions(+)
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 000..f162589
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,370 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void
+radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
+ struct pipe_h265_enc_picture_desc *pic)
+{
+   enc->enc_pic.picture_type = pic->picture_type;
+   enc->enc_pic.frame_num = pic->frame_num;
+   enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+   enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+   enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+   enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+   enc->enc_pic.not_referenced = pic->not_referenced;
+   enc->enc_pic.is_idr = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR)
+  || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);

Looks very suspicious?  I would expect that only IDR frames would be IDR.


+   enc->enc_pic.crop_left = 0;
+   enc->enc_pic.crop_right =
+  (align(enc->base.width, 16) - enc->base.width) / 2;
+   enc->enc_pic.crop_top = 0;
+   enc->enc_pic.crop_bottom =
+  (align(enc->base.height, 16) - enc->base.height) / 2;
+   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.log2_max_poc = 0;
+   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+  i = (i >> 1);
+   enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+   enc->enc_pic.pic_width_in_luma_samples =
+  pic->seq.pic_width_in_luma_samples;
+   enc->enc_pic.pic_height_in_luma_samples =
+  pic->seq.pic_height_in_luma_samples;
+   enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
+  pic->seq.log2_diff_max_min_luma_coding_block_size;
+   enc->enc_pic.log2_min_transform_block_size_minus2 =
+  pic->seq.log2_min_transform_block_size_minus2;
+   enc->enc_pic.log2_diff_max_min_transform_block_size =
+  pic->seq.log2_diff_max_min_transform_block_size;
+   enc->enc_pic.max_transform_hierarchy_depth_inter =
+  pic->seq.max_transform_hierarchy_depth_inter;
+   enc->enc_pic.max_transform_hierarchy_depth_intra =
+  pic->seq.max_transform_hierarchy_depth_intra;
+   enc->enc_pic.log2_parallel_merge_level_minus2 =
+  pic->pic.log2_parallel_merge_level_minus2;
+   enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
+   enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
+   enc->enc_pic.nal_unit_type

[Mesa-dev] [PATCH v4 3/8] radeon/uvd:add uvd hevc enc hw interface header

2018-02-12 Thread James Zhu

Add hevc encode hardware interface for UVD

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.h | 469 
 1 file changed, 469 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.h 
b/src/gallium/drivers/radeon/radeon_uvd_enc.h
new file mode 100644
index 000..20c340d
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.h
@@ -0,0 +1,469 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#ifndef _RADEON_UVD_ENC_H
+#define _RADEON_UVD_ENC_H
+
+#define RENC_UVD_FW_INTERFACE_MAJOR_VERSION 1
+#define RENC_UVD_FW_INTERFACE_MINOR_VERSION 1
+
+#define RENC_UVD_IB_PARAM_SESSION_INFO  0x0001
+#define RENC_UVD_IB_PARAM_TASK_INFO 0x0002
+#define RENC_UVD_IB_PARAM_SESSION_INIT  0x0003
+#define RENC_UVD_IB_PARAM_LAYER_CONTROL 0x0004
+#define RENC_UVD_IB_PARAM_LAYER_SELECT  0x0005
+#define RENC_UVD_IB_PARAM_SLICE_CONTROL 0x0006
+#define RENC_UVD_IB_PARAM_SPEC_MISC 0x0007
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x0008
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x0009
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x000a
+#define RENC_UVD_IB_PARAM_SLICE_HEADER  0x000b
+#define RENC_UVD_IB_PARAM_ENCODE_PARAMS 0x000c
+#define RENC_UVD_IB_PARAM_QUALITY_PARAMS0x000d
+#define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER 0x000e
+#define RENC_UVD_IB_PARAM_INTRA_REFRESH 0x000f
+#define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0010
+#define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER0x0011
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER   0x0012
+#define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER0x0013
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL0x0014
+
+#define RENC_UVD_IB_OP_INITIALIZE   0x0801
+#define RENC_UVD_IB_OP_CLOSE_SESSION0x0802
+#define RENC_UVD_IB_OP_ENCODE   0x0803
+#define RENC_UVD_IB_OP_INIT_RC  0x0804
+#define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x0805
+#define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE  0x0806
+#define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE0x0807
+#define RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE0x0808
+
+#define RENC_UVD_IF_MAJOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MAJOR_VERSION_SHIFT 16
+#define RENC_UVD_IF_MINOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MINOR_VERSION_SHIFT 0
+
+#define RENC_UVD_PREENCODE_MODE_NONE0x
+#define RENC_UVD_PREENCODE_MODE_1X  0x0001
+#define RENC_UVD_PREENCODE_MODE_2X  0x0002
+#define RENC_UVD_PREENCODE_MODE_4X  0x0004
+
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS  0x
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_BITS  0x0001
+
+#define RENC_UVD_RATE_CONTROL_METHOD_NONE   0x
+#define RENC_UVD_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR0x0001
+#define RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR   0x0002
+#define RENC_UVD_RATE_CONTROL_METHOD_CBR0x0003
+
+#define RENC_UVD_NALU_TYPE_AUD  0x0001
+#define RE

[Mesa-dev] [PATCH v4 5/8] radeon/uvd:add uvd hevc enc functions

2018-02-12 Thread James Zhu

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 381 
 1 file changed, 381 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 000..94bd26a
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,381 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define UVD_HEVC_LEVEL_1   30
+#define UVD_HEVC_LEVEL_2   60
+#define UVD_HEVC_LEVEL_2_1 63
+#define UVD_HEVC_LEVEL_3   90
+#define UVD_HEVC_LEVEL_3_1 93
+#define UVD_HEVC_LEVEL_4   120
+#define UVD_HEVC_LEVEL_4_1 123
+#define UVD_HEVC_LEVEL_5   150
+#define UVD_HEVC_LEVEL_5_1 153
+#define UVD_HEVC_LEVEL_5_2 156
+#define UVD_HEVC_LEVEL_6   180
+#define UVD_HEVC_LEVEL_6_1 183
+#define UVD_HEVC_LEVEL_6_2 186
+
+static void
+radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
+ struct pipe_h265_enc_picture_desc *pic)
+{
+   enc->enc_pic.picture_type = pic->picture_type;
+   enc->enc_pic.frame_num = pic->frame_num;
+   enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+   enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+   enc->enc_pic.not_referenced = pic->not_referenced;
+   enc->enc_pic.is_iframe =
+  (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR)
+  || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
+   enc->enc_pic.crop_left = 0;
+   enc->enc_pic.crop_right =
+  (align(enc->base.width, 16) - enc->base.width) / 2;
+   enc->enc_pic.crop_top = 0;
+   enc->enc_pic.crop_bottom =
+  (align(enc->base.height, 16) - enc->base.height) / 2;
+   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.log2_max_poc = 0;
+   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+  i = (i >> 1);
+   enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+   enc->enc_pic.pic_width_in_luma_samples =
+  pic->seq.pic_width_in_luma_samples;
+   enc->enc_pic.pic_height_in_luma_samples =
+  pic->seq.pic_height_in_luma_samples;
+   enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
+  pic->seq.log2_diff_max_min_luma_coding_block_size;
+   enc->enc_pic.log2_min_transform_block_size_minus2 =
+  pic->seq.log2_min_transform_block_size_minus2;
+   enc->enc_pic.log2_diff_max_min_transform_block_size =
+  pic->seq.log2_diff_max_min_transform_block_size;
+   enc->enc_pic.max_transform_hierarchy_depth_inter =
+  pic->seq.max_transform_hierarchy_depth_inter;
+   enc->enc_pic.max_transform_hierarchy_depth_intra =
+  pic->seq.max_transform_hierarchy_depth_intra;
+   enc->enc_pic.log2_parallel_merge_level_minus2 =
+  pic->pic.log2_parallel_merge_level_minus2;
+   enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
+   enc->enc_

[Mesa-dev] [PATCH v4 4/8] radeon/uvd:add uvd hevc enc hw ib implementation

2018-02-12 Thread James Zhu

Implement required IBs for UVD HEVC encode.

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1131 +++
 1 file changed, 1131 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
new file mode 100644
index 000..e507bae
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -0,0 +1,1131 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = 
(value))
+#define RADEON_ENC_BEGIN(cmd) { \
+   uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
+RADEON_ENC_CS(cmd)
+#define RADEON_ENC_READ(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READ, (domain), (off))
+#define RADEON_ENC_WRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_WRITE, (domain), (off))
+#define RADEON_ENC_READWRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READWRITE, (domain), (off))
+#define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] 
- begin) * 4; \
+   enc->total_task_size += *begin;}
+
+static const unsigned index_to_shifts[4] = { 24, 16, 8, 0 };
+
+static void
+radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc,
+  struct pb_buffer *buf, enum radeon_bo_usage usage,
+  enum radeon_bo_domain domain, signed offset)
+{
+   enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_VCE);
+   uint64_t addr;
+   addr = enc->ws->buffer_get_virtual_address(buf);
+   addr = addr + offset;
+   RADEON_ENC_CS(addr >> 32);
+   RADEON_ENC_CS(addr);
+}
+
+static void
+radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc,
+bool set)
+{
+   if (set != enc->emulation_prevention) {
+  enc->emulation_prevention = set;
+  enc->num_zeros = 0;
+   }
+}
+
+static void
+radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc,
+   unsigned char byte)
+{
+   if (enc->byte_index == 0)
+  enc->cs->current.buf[enc->cs->current.cdw] = 0;
+   enc->cs->current.buf[enc->cs->current.cdw] |=
+  ((unsigned int) (byte) << index_to_shifts[enc->byte_index]);
+   enc->byte_index++;
+
+   if (enc->byte_index >= 4) {
+  enc->byte_index = 0;
+  enc->cs->current.cdw++;
+   }
+}
+
+static void
+radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc,
+unsigned char byte)
+{
+   if (enc->emulation_prevention) {
+  if ((enc->num_zeros >= 2)
+  && ((byte == 0x00) || (byte == 0x01) || (byte == 0x03))) {
+ radeon_uvd_enc_output_one_byte(enc, 0x03);
+ enc->bits_output += 8;
+ enc->num_zeros = 0;
+  }
+  enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
+   }
+}
+
+static void
+radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder *enc,
+   unsigned int value, uns

Re: [Mesa-dev] [PATCH v2 4/8] radeon/uvd:add uvd hevc enc hw ib implementation

2018-02-12 Thread James Zhu


Hi Mark,

thanks for point them out. [PATCH v4 3/8] / [PATCH v4 4/8] / [PATCH v4 
5/8] update accordingly.


James.


On 2018-02-08 05:13 PM, Mark Thompson wrote:

On 06/02/18 20:05, James Zhu wrote:

Implement required IBs for UVD HEVC encode.

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1115 +++
  1 file changed, 1115 insertions(+)
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
new file mode 100644
index 000..17a39c2
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -0,0 +1,1115 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = 
(value))
+#define RADEON_ENC_BEGIN(cmd) { \
+   uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
+RADEON_ENC_CS(cmd)
+#define RADEON_ENC_READ(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READ, (domain), (off))
+#define RADEON_ENC_WRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_WRITE, (domain), (off))
+#define RADEON_ENC_READWRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READWRITE, (domain), (off))
+#define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] 
- begin) * 4; \
+   enc->total_task_size += *begin;}
+
+static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };

This looks very suspicious in an H.265 file, because those are H.264 profile 
values...


+static const unsigned index_to_shifts[4] = { 24, 16, 8, 0 };
+
...
+
+static void
+radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder *enc)
+{
+   enc->enc_pic.session_init.aligned_picture_width =
+  align(enc->base.width, 64);

Do you really need to pad width to 64 rather than the MinCbSizeY?


+   enc->enc_pic.session_init.aligned_picture_height =
+  align(enc->base.height, 16);
+   enc->enc_pic.session_init.padding_width =
+  enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
+   enc->enc_pic.session_init.padding_height =
+  enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
+   enc->enc_pic.session_init.pre_encode_mode = RENC_UVD_PREENCODE_MODE_NONE;
+   enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
+
+   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INIT);
+   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
+   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
+   RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
+   RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
+   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
+   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
+   RADEON_ENC_END();
+}
+
...
+
+static void
+radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
+{
+   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
+   RADEON_ENC_CS(RENC_UVD_NALU_TYPE_SPS);
+   uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
+   int i;
+
+   radeon_uvd_enc_reset

[Mesa-dev] [PATCH v5 4/8] radeon/uvd:add uvd hevc enc hw ib implementation

2018-02-13 Thread James Zhu

Implement required IBs for UVD HEVC encode.

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1132 +++
 1 file changed, 1132 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
new file mode 100644
index 000..42a9fa9
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -0,0 +1,1132 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = 
(value))
+#define RADEON_ENC_BEGIN(cmd) { \
+   uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
+RADEON_ENC_CS(cmd)
+#define RADEON_ENC_READ(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READ, (domain), (off))
+#define RADEON_ENC_WRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_WRITE, (domain), (off))
+#define RADEON_ENC_READWRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READWRITE, (domain), (off))
+#define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] 
- begin) * 4; \
+   enc->total_task_size += *begin;}
+
+static const unsigned index_to_shifts[4] = { 24, 16, 8, 0 };
+
+static void
+radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc,
+  struct pb_buffer *buf, enum radeon_bo_usage usage,
+  enum radeon_bo_domain domain, signed offset)
+{
+   enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_VCE);
+   uint64_t addr;
+   addr = enc->ws->buffer_get_virtual_address(buf);
+   addr = addr + offset;
+   RADEON_ENC_CS(addr >> 32);
+   RADEON_ENC_CS(addr);
+}
+
+static void
+radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc,
+bool set)
+{
+   if (set != enc->emulation_prevention) {
+  enc->emulation_prevention = set;
+  enc->num_zeros = 0;
+   }
+}
+
+static void
+radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc,
+   unsigned char byte)
+{
+   if (enc->byte_index == 0)
+  enc->cs->current.buf[enc->cs->current.cdw] = 0;
+   enc->cs->current.buf[enc->cs->current.cdw] |=
+  ((unsigned int) (byte) << index_to_shifts[enc->byte_index]);
+   enc->byte_index++;
+
+   if (enc->byte_index >= 4) {
+  enc->byte_index = 0;
+  enc->cs->current.cdw++;
+   }
+}
+
+static void
+radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc,
+unsigned char byte)
+{
+   if (enc->emulation_prevention) {
+  if ((enc->num_zeros >= 2)
+  && ((byte == 0x00) || (byte == 0x01)
+   || (byte == 0x02) || (byte == 0x03))) {
+ radeon_uvd_enc_output_one_byte(enc, 0x03);
+ enc->bits_output += 8;
+ enc->num_zeros = 0;
+  }
+  enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
+   }
+}
+
+static void
+radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder *enc,
+

Re: [Mesa-dev] [PATCH v3 4/8] radeon/uvd:add uvd hevc enc hw ib implementation

2018-02-13 Thread James Zhu




On 2018-02-10 11:20 AM, Mark Thompson wrote:

On 09/02/18 20:35, James Zhu wrote:

Implement required IBs for UVD HEVC encode.

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1115 +++
  1 file changed, 1115 insertions(+)
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
new file mode 100644
index 000..2b8156e
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -0,0 +1,1115 @@
...
+
+static void
+radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc,
+unsigned char byte)
+{
+   if (enc->emulation_prevention) {
+  if ((enc->num_zeros >= 2)
+  && ((byte == 0x00) || (byte == 0x01) || (byte == 0x03))) {

Shouldn't { 0, 0, 2 } also trigger emulation prevention?  Or am I not 
understanding what this function does?


Hi, Mark,
You are right. should add 00 00 02 case.
pls check the update in PATCH v5 4/8
Thanks! James

+ radeon_uvd_enc_output_one_byte(enc, 0x03);
+ enc->bits_output += 8;
+ enc->num_zeros = 0;
+  }
+  enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
+   }
+}
+
...

Thanks,

- Mark


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Re: [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode

2018-02-13 Thread James Zhu


Hi Mark,

Did you still encounter hung issue?

If yes, could you share me with your play and transcode streams and command 
line,
then I can try to reproduce at my side.

Thanks & Best Regards!

James Zhu

On 2018-02-10 11:06 AM, Mark Thompson wrote:


On 08/02/18 23:05, Mark Thompson wrote:

On 08/02/18 22:37, Alex Deucher wrote:

On Thu, Feb 8, 2018 at 5:28 PM, Mark Thompson  wrote:

On 06/02/18 20:05, James Zhu wrote:

The whole series are the updated version. Changes are made mainly based
on the comments from prevous code review from Alex, Leo and Boyuan

James Zhu (8):
   amd/common:add uvd hevc enc support check in hw query
   winsys/amdgpu:add uvd hevc enc support in amdgpu cs
   radeon/uvd:add uvd hevc enc hw interface header
   radeon/uvd:add uvd hevc enc hw ib implementation
   radeon/uvd:add uvd hevc enc functions
   radeon/uvd:add uvd hevc enc files in Makefile list
   radeonsi:create uvd hevc enc entry
   radeonsi: enable uvd encode for HEVC main

  src/amd/common/ac_gpu_info.c|   10 +-
  src/amd/common/ac_gpu_info.h|1 +
  src/gallium/drivers/radeon/Makefile.sources |3 +
  src/gallium/drivers/radeon/radeon_uvd_enc.c |  370 
  src/gallium/drivers/radeon/radeon_uvd_enc.h |  471 ++
  src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1115 +++
  src/gallium/drivers/radeonsi/si_get.c   |4 +-
  src/gallium/drivers/radeonsi/si_uvd.c   |   15 +-
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c   |6 +
  9 files changed, 1990 insertions(+), 5 deletions(-)
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c


Can you explain what the requirements are for using this (hardware, firmware, 
software)?

 From what I can find it should be on Polaris and Vega, but I haven't succeeded 
in getting it working on Polaris.

Yes, polaris and vega10.  For polaris, you'll need a kernel that
enables the uvd enc rings.  Patches went upstream last year, 4.14 I
think?  4.15 is a good bet.

Ah, that's where I'm going wrong - despite the dates it's not actually in 4.14, 
so I need 4.15.


  As for the polaris firmware, you'll need
version FW_1_130_16 or newer:
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/commit/?id=2a713be25a44bd6cec90d8affc54b246a2ca9c7b

Right, I have the encoder working with 4.15.2 on an RX 460 / Polaris 11 with 
firmware 1.130_16.

There seems to be some issue with using both encode and playback at the same 
time?  It hangs the amdgpu driver and all userspaces processes interacting with 
it become stuck and unkillable, requiring a reboot to recover.  It's completely 
repeatable, and only needs a few seconds to die when both mpv (playback) and 
ffmpeg (transcode) are running at the same time.

There is no message at all from the stuck driver, but I end up with hung tasks 
like:

[ 1209.317130] INFO: task kworker/u24:0:5 blocked for more than 120 seconds.
[ 1209.317132]   Not tainted 4.15.2 #2
[ 1209.317133] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this 
message.
[ 1209.317133] kworker/u24:0   D0 5  2 0x8000
[ 1209.317137] Workqueue: events_unbound commit_work
[ 1209.317138] Call Trace:
[ 1209.317142]  ? __schedule+0x26b/0x840
[ 1209.317144]  ? __update_load_avg_se.isra.37+0x1b6/0x1c0
[ 1209.317145]  schedule+0x28/0x80
[ 1209.317146]  schedule_timeout+0x1de/0x360
[ 1209.317177]  ? dce110_timing_generator_get_position+0x51/0x60 [amdgpu]
[ 1209.317199]  ? dce110_timing_generator_get_crtc_scanoutpos+0x6b/0xa0 [amdgpu]
[ 1209.317201]  dma_fence_default_wait+0x1f6/0x280
[ 1209.317203]  ? dma_fence_release+0x90/0x90
[ 1209.317204]  dma_fence_wait_timeout+0x33/0xe0
[ 1209.317205]  reservation_object_wait_timeout_rcu+0x198/0x340
[ 1209.317227]  amdgpu_dm_do_flip+0x112/0x350 [amdgpu]
[ 1209.317248]  amdgpu_dm_atomic_commit_tail+0x8a4/0x9a0 [amdgpu]
[ 1209.317250]  ? pick_next_task_fair+0x14f/0x5f0
[ 1209.317251]  commit_tail+0x3a/0x70
[ 1209.317252]  process_one_work+0x17c/0x370
[ 1209.317253]  worker_thread+0x2e/0x370
[ 1209.317255]  ? process_one_work+0x370/0x370
[ 1209.317256]  kthread+0x111/0x130
[ 1209.317257]  ? kthread_create_worker_on_cpu+0x70/0x70
[ 1209.317258]  ret_from_fork+0x1f/0x30
[ 1330.152054] INFO: task kworker/u24:0:5 blocked for more than 120 seconds.
[ 1330.152056]   Not tainted 4.15.2 #2
[ 1330.152056] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this 
message.
[ 1330.152057] kworker/u24:0   D0 5  2 0x8000
[ 1330.152059] Workqueue: events_unbound commit_work
[ 1330.152060] Call Trace:
[ 1330.152063]  ? __schedule+0x26b/0x840
[ 1330.152065]  ? __update_load_avg_se.isra.37+0x1b6/0x1c0
[ 1330.152066]  schedule+0x2

[Mesa-dev] [PATCH v6 1/7] amd/common:add uvd hevc enc support check in hw query

2018-02-16 Thread James Zhu

Based on amdgpu hardware query information to check if UVD hevc enc support

Signed-off-by: James Zhu 
Reviewed-by: Marek Olšák 
---
 src/amd/common/ac_gpu_info.c | 12 +++-
 src/amd/common/ac_gpu_info.h |  1 +
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6d9dcb5..3156df6 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -98,7 +98,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 {
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
-   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = 
{}, vcn_dec = {}, vcn_enc = {};
+   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc 
= {}, vce = {}, vcn_dec = {}, vcn_enc = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
int r, i, j;
drmDevicePtr devinfo;
@@ -167,6 +167,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
 
if (info->drm_major == 3 && info->drm_minor >= 17) {
+   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, 
&uvd_enc);
+   if (r) {
+   fprintf(stderr, "amdgpu: 
amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
+   return false;
+   }
+   }
+
+   if (info->drm_major == 3 && info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, 
&vcn_dec);
if (r) {
fprintf(stderr, "amdgpu: 
amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
@@ -275,6 +283,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
vce.available_rings ? vce_version : 0;
+   info->uvd_enc_supported =
+   uvd_enc.available_rings ? true : false;
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
info->has_syncobj_wait_for_submit = info->has_syncobj && 
info->drm_minor >= 20;
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index cca3e98..36714ee 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -65,6 +65,7 @@ struct radeon_info {
uint32_tnum_compute_rings;
uint32_tuvd_fw_version;
uint32_tvce_fw_version;
+   booluvd_enc_supported;
uint32_tme_fw_version;
uint32_tme_fw_feature;
uint32_tpfp_fw_version;
-- 
2.7.4

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[Mesa-dev] [PATCH v6 0/7] The 6th version for UVD HEVC encode

2018-02-16 Thread James Zhu

The whole series are the updated version. Changes are made mainly
based on the comments from prevous code review from Alex, Leo, 
Boyuan, Bas, Marek, Christian and Mark

James Zhu (7):
  amd/common:add uvd hevc enc support check in hw query
  winsys/amdgpu:add uvd hevc enc support in amdgpu cs
  radeon/uvd:add uvd hevc enc hw interface header
  radeon/uvd:add uvd hevc enc hw ib implementation
  radeon/uvd:add uvd hevc enc functions
  radeonsi:create uvd hevc enc entry
  radeonsi: enable uvd encode for HEVC main

 src/amd/common/ac_gpu_info.c|   12 +-
 src/amd/common/ac_gpu_info.h|1 +
 src/gallium/drivers/radeon/Makefile.sources |3 +
 src/gallium/drivers/radeon/meson.build  |3 +
 src/gallium/drivers/radeon/radeon_uvd_enc.c |  381 
 src/gallium/drivers/radeon/radeon_uvd_enc.h |  469 ++
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1132 +++
 src/gallium/drivers/radeonsi/si_get.c   |4 +-
 src/gallium/drivers/radeonsi/si_uvd.c   |   15 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c   |6 +
 10 files changed, 2021 insertions(+), 5 deletions(-)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

-- 
2.7.4

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[Mesa-dev] [PATCH v6 2/7] winsys/amdgpu:add uvd hevc enc support in amdgpu cs

2018-02-16 Thread James Zhu

Support UVD HEVC encode in amdgpu cs

Signed-off-by: James Zhu 
Reviewed-by: Boyuan Zhang 
---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 1927a3a..92d5394 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -376,6 +376,7 @@ static bool amdgpu_cs_has_user_fence(struct 
amdgpu_cs_context *cs)
 {
return cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE &&
+  cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC;
 }
@@ -818,6 +819,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD;
   break;
 
+   case RING_UVD_ENC:
+  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD_ENC;
+  break;
+
case RING_VCE:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCE;
   break;
@@ -1533,6 +1538,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
   ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
   break;
case RING_UVD:
+   case RING_UVD_ENC:
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x8000); /* type2 nop packet */
   break;
-- 
2.7.4

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[Mesa-dev] [PATCH v6 3/7] radeon/uvd:add uvd hevc enc hw interface header

2018-02-16 Thread James Zhu

Add hevc encode hardware interface for UVD

Signed-off-by: James Zhu 
Reviewed-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/Makefile.sources |   1 +
 src/gallium/drivers/radeon/meson.build  |   1 +
 src/gallium/drivers/radeon/radeon_uvd_enc.h | 469 
 3 files changed, 471 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index b756d72..5445625 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -15,6 +15,7 @@ C_SOURCES := \
radeon_vcn_enc_1_2.c \
radeon_vcn_enc.c \
radeon_vcn_enc.h \
+   radeon_uvd_enc.h \
radeon_vce_40_2_2.c \
radeon_vce_50.c \
radeon_vce_52.c \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index 6857df3..f587f17 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -35,6 +35,7 @@ files_libradeon = files(
   'radeon_vcn_enc.h',
   'radeon_vcn_dec.c',
   'radeon_vcn_dec.h',
+  'radeon_uvd_enc.h',
   'radeon_vce_40_2_2.c',
   'radeon_vce_50.c',
   'radeon_vce_52.c',
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.h 
b/src/gallium/drivers/radeon/radeon_uvd_enc.h
new file mode 100644
index 000..20c340d
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.h
@@ -0,0 +1,469 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#ifndef _RADEON_UVD_ENC_H
+#define _RADEON_UVD_ENC_H
+
+#define RENC_UVD_FW_INTERFACE_MAJOR_VERSION 1
+#define RENC_UVD_FW_INTERFACE_MINOR_VERSION 1
+
+#define RENC_UVD_IB_PARAM_SESSION_INFO  0x0001
+#define RENC_UVD_IB_PARAM_TASK_INFO 0x0002
+#define RENC_UVD_IB_PARAM_SESSION_INIT  0x0003
+#define RENC_UVD_IB_PARAM_LAYER_CONTROL 0x0004
+#define RENC_UVD_IB_PARAM_LAYER_SELECT  0x0005
+#define RENC_UVD_IB_PARAM_SLICE_CONTROL 0x0006
+#define RENC_UVD_IB_PARAM_SPEC_MISC 0x0007
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x0008
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x0009
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x000a
+#define RENC_UVD_IB_PARAM_SLICE_HEADER  0x000b
+#define RENC_UVD_IB_PARAM_ENCODE_PARAMS 0x000c
+#define RENC_UVD_IB_PARAM_QUALITY_PARAMS0x000d
+#define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER 0x000e
+#define RENC_UVD_IB_PARAM_INTRA_REFRESH 0x000f
+#define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0010
+#define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER0x0011
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER   0x0012
+#define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER0x0013
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL0x0014
+
+#define RENC_UVD_IB_OP_INITIALIZE   0x0801
+#define RENC_UVD_IB_OP_CLOSE_SESSION0x0802
+#define RENC_UVD_IB_OP_ENCODE   0x0803
+#define RENC_UVD_IB_OP_INIT_RC  0x0804
+#define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x0805
+#define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE  0x0806
+#define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE0x0807
+#define RENC_UVD_I

[Mesa-dev] [PATCH v6 5/7] radeon/uvd:add uvd hevc enc functions

2018-02-16 Thread James Zhu

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
Reviewed-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/Makefile.sources |   1 +
 src/gallium/drivers/radeon/meson.build  |   1 +
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 381 
 3 files changed, 383 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index 061d1e1..f8ee860 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -16,6 +16,7 @@ C_SOURCES := \
radeon_vcn_enc.c \
radeon_vcn_enc.h \
radeon_uvd_enc_1_1.c \
+   radeon_uvd_enc.c \
radeon_uvd_enc.h \
radeon_vce_40_2_2.c \
radeon_vce_50.c \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index 1bc5e83..582a5ff 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -36,6 +36,7 @@ files_libradeon = files(
   'radeon_vcn_dec.c',
   'radeon_vcn_dec.h',
   'radeon_uvd_enc_1_1.c',
+  'radeon_uvd_enc.c',
   'radeon_uvd_enc.h',
   'radeon_vce_40_2_2.c',
   'radeon_vce_50.c',
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 000..94bd26a
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,381 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define UVD_HEVC_LEVEL_1   30
+#define UVD_HEVC_LEVEL_2   60
+#define UVD_HEVC_LEVEL_2_1 63
+#define UVD_HEVC_LEVEL_3   90
+#define UVD_HEVC_LEVEL_3_1 93
+#define UVD_HEVC_LEVEL_4   120
+#define UVD_HEVC_LEVEL_4_1 123
+#define UVD_HEVC_LEVEL_5   150
+#define UVD_HEVC_LEVEL_5_1 153
+#define UVD_HEVC_LEVEL_5_2 156
+#define UVD_HEVC_LEVEL_6   180
+#define UVD_HEVC_LEVEL_6_1 183
+#define UVD_HEVC_LEVEL_6_2 186
+
+static void
+radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
+ struct pipe_h265_enc_picture_desc *pic)
+{
+   enc->enc_pic.picture_type = pic->picture_type;
+   enc->enc_pic.frame_num = pic->frame_num;
+   enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+   enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+   enc->enc_pic.not_referenced = pic->not_referenced;
+   enc->enc_pic.is_iframe =
+  (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR)
+  || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
+   enc->enc_pic.crop_left = 0;
+   enc->enc_pic.crop_right =
+  (align(enc->base.width, 16) - enc->base.width) / 2;
+   enc->enc_pic.crop_top = 0;
+   enc->enc_pic.crop_bottom =
+  (align(enc->base.height, 16) - enc->base.height) / 2;
+   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.log2_max_poc = 0;
+   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+

[Mesa-dev] [PATCH v6 6/7] radeonsi:create uvd hevc enc entry

2018-02-16 Thread James Zhu

Add UVD hevc encode pipe video codec creation entry

Signed-off-by: James Zhu 
Reviewed-by: Boyuan Zhang 
---
 src/gallium/drivers/radeonsi/si_uvd.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c
index 64f2f8e..3906bbd 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -31,6 +31,8 @@
 #include "radeon/radeon_vce.h"
 #include "radeon/radeon_vcn_dec.h"
 #include "radeon/radeon_vcn_enc.h"
+#include "radeon/radeon_uvd_enc.h"
+#include "util/u_video.h"
 
 /**
  * creates an video buffer with an UVD compatible memory layout
@@ -146,9 +148,16 @@ struct pipe_video_codec *si_uvd_create_decoder(struct 
pipe_context *context,
struct si_context *ctx = (struct si_context *)context;
bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
 
-   if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
-   return (vcn) ? radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer) :
-   si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+   if (vcn) {
+   radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   } else {
+   if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC)
+   return radeon_uvd_create_encoder(context, 
templ, ctx->b.ws, si_vce_get_buffer);
+   else
+   return si_vce_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer);
+   }
+   }
 
return (vcn) ?  radeon_create_decoder(context, templ) :
si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
-- 
2.7.4

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[Mesa-dev] [PATCH v6 4/7] radeon/uvd:add uvd hevc enc hw ib implementation

2018-02-16 Thread James Zhu

Implement required IBs for UVD HEVC encode.

Signed-off-by: James Zhu 
Reviewed-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/Makefile.sources |1 +
 src/gallium/drivers/radeon/meson.build  |1 +
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1132 +++
 3 files changed, 1134 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index 5445625..061d1e1 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -15,6 +15,7 @@ C_SOURCES := \
radeon_vcn_enc_1_2.c \
radeon_vcn_enc.c \
radeon_vcn_enc.h \
+   radeon_uvd_enc_1_1.c \
radeon_uvd_enc.h \
radeon_vce_40_2_2.c \
radeon_vce_50.c \
diff --git a/src/gallium/drivers/radeon/meson.build 
b/src/gallium/drivers/radeon/meson.build
index f587f17..1bc5e83 100644
--- a/src/gallium/drivers/radeon/meson.build
+++ b/src/gallium/drivers/radeon/meson.build
@@ -35,6 +35,7 @@ files_libradeon = files(
   'radeon_vcn_enc.h',
   'radeon_vcn_dec.c',
   'radeon_vcn_dec.h',
+  'radeon_uvd_enc_1_1.c',
   'radeon_uvd_enc.h',
   'radeon_vce_40_2_2.c',
   'radeon_vce_50.c',
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
new file mode 100644
index 000..42a9fa9
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -0,0 +1,1132 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = 
(value))
+#define RADEON_ENC_BEGIN(cmd) { \
+   uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
+RADEON_ENC_CS(cmd)
+#define RADEON_ENC_READ(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READ, (domain), (off))
+#define RADEON_ENC_WRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_WRITE, (domain), (off))
+#define RADEON_ENC_READWRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READWRITE, (domain), (off))
+#define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] 
- begin) * 4; \
+   enc->total_task_size += *begin;}
+
+static const unsigned index_to_shifts[4] = { 24, 16, 8, 0 };
+
+static void
+radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc,
+  struct pb_buffer *buf, enum radeon_bo_usage usage,
+  enum radeon_bo_domain domain, signed offset)
+{
+   enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_VCE);
+   uint64_t addr;
+   addr = enc->ws->buffer_get_virtual_address(buf);
+   addr = addr + offset;
+   RADEON_ENC_CS(addr >> 32);
+   RADEON_ENC_CS(addr);
+}
+
+static void
+radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc,
+bool set)
+{
+   if (set != enc->emulation_prevention) {
+  enc->emulation_prevention = set;
+  enc->num_zeros = 0;
+   }
+}
+
+static void
+radeon_uvd_enc_output_one_byte(struct radeon

[Mesa-dev] [PATCH v6 7/7] radeonsi: enable uvd encode for HEVC main

2018-02-16 Thread James Zhu

Enable UVD encode for HEVC main profile

Signed-off-by: James Zhu 
Reviewed-by: Boyuan Zhang 
---
 src/gallium/drivers/radeonsi/si_get.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index ef03a96..a7cdcda 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -24,6 +24,7 @@
 #include "si_pipe.h"
 #include "radeon/radeon_video.h"
 #include "radeon/radeon_vce.h"
+#include "radeon/radeon_uvd_enc.h"
 #include "ac_llvm_util.h"
 #include "vl/vl_decoder.h"
 #include "vl/vl_video_buffer.h"
@@ -579,7 +580,8 @@ static int si_get_video_param(struct pipe_screen *screen,
(si_vce_is_fw_version_supported(sscreen) ||
sscreen->info.family == CHIP_RAVEN)) ||
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
-   sscreen->info.family == CHIP_RAVEN);
+   (sscreen->info.family == CHIP_RAVEN ||
+   si_radeon_uvd_enc_supported(sscreen)));
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
case PIPE_VIDEO_CAP_MAX_WIDTH:
-- 
2.7.4

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[Mesa-dev] [PATCH] radeonsi: fix Segmentation fault during vaapi enc test

2020-04-06 Thread James Zhu

Fix Segmentation fault duiring vaapi enc test on Arcturus.

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeonsi/si_compute_blit.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c 
b/src/gallium/drivers/radeonsi/si_compute_blit.c
index 6e3b07c..a56676a 100644
--- a/src/gallium/drivers/radeonsi/si_compute_blit.c
+++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
@@ -63,7 +63,8 @@ static void si_launch_grid_internal(struct si_context *sctx, 
struct pipe_grid_in
sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
sctx->render_cond_force_off = true;
/* Skip decompression to prevent infinite recursion. */
-   sctx->blitter->running = true;
+   if (sctx->blitter)
+  blitter->running = true;
 
/* Dispatch compute. */
sctx->b.launch_grid(&sctx->b, info);
@@ -72,7 +73,8 @@ static void si_launch_grid_internal(struct si_context *sctx, 
struct pipe_grid_in
sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
sctx->render_cond_force_off = false;
-   sctx->blitter->running = false;
+   if (sctx->blitter)
+  sctx->blitter->running = false;
 }
 
 static void si_compute_clear_12bytes_buffer(struct si_context *sctx, struct 
pipe_resource *dst,
-- 
2.7.4

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[Mesa-dev] [PATCH v2] radeonsi: fix Segmentation fault during vaapi enc test

2020-04-06 Thread James Zhu

Fix Segmentation fault duiring vaapi enc test on Arcturus.
v2: fix typo

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeonsi/si_compute_blit.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c 
b/src/gallium/drivers/radeonsi/si_compute_blit.c
index 6e3b07c..0a81c68 100644
--- a/src/gallium/drivers/radeonsi/si_compute_blit.c
+++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
@@ -63,7 +63,8 @@ static void si_launch_grid_internal(struct si_context *sctx, 
struct pipe_grid_in
sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
sctx->render_cond_force_off = true;
/* Skip decompression to prevent infinite recursion. */
-   sctx->blitter->running = true;
+   if (sctx->blitter)
+  sctx->blitter->running = true;
 
/* Dispatch compute. */
sctx->b.launch_grid(&sctx->b, info);
@@ -72,7 +73,8 @@ static void si_launch_grid_internal(struct si_context *sctx, 
struct pipe_grid_in
sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
sctx->render_cond_force_off = false;
-   sctx->blitter->running = false;
+   if (sctx->blitter)
+  sctx->blitter->running = false;
 }
 
 static void si_compute_clear_12bytes_buffer(struct si_context *sctx, struct 
pipe_resource *dst,
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] radeon/vcn/vp9: search the render target from the whole list

2019-03-28 Thread James Zhu

This Patch is  Tested-by: James Zhu 

On 2019-03-28 9:08 a.m., Liu, Leo wrote:
> The number of render targets could be more than max of references,
> so we search the full list of the render pictures for the current
> render target index
>
> https://bugs.freedesktop.org/show_bug.cgi?id=109648
>
> Signed-off-by: Leo Liu 
> Cc: 
> ---
>   src/gallium/drivers/radeon/radeon_vcn_dec.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
> b/src/gallium/drivers/radeon/radeon_vcn_dec.c
> index d165c55f835..688cef90103 100644
> --- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
> +++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
> @@ -491,7 +491,7 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct 
> radeon_decoder *dec,
>   
>   assert(dec->base.max_references + 1 <= 16);
>   
> - for (i = 0 ; i < dec->base.max_references + 1 ; ++i) {
> + for (i = 0 ; i < 16 ; ++i) {
>   if (dec->render_pic_list[i] && dec->render_pic_list[i] == 
> target) {
>   result.curr_pic_idx =
>   
> (uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
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Re: [Mesa-dev] [PATCH] radeon/vcn/vp9: search the render target from the whole list

2019-03-29 Thread James Zhu

This Patch is  Acked-by: James Zhu

On 2019-03-28 9:08 a.m., Liu, Leo wrote:
> The number of render targets could be more than max of references,
> so we search the full list of the render pictures for the current
> render target index
>
> https://bugs.freedesktop.org/show_bug.cgi?id=109648
>
> Signed-off-by: Leo Liu 
> Cc: 
> ---
>   src/gallium/drivers/radeon/radeon_vcn_dec.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
> b/src/gallium/drivers/radeon/radeon_vcn_dec.c
> index d165c55f835..688cef90103 100644
> --- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
> +++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
> @@ -491,7 +491,7 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct 
> radeon_decoder *dec,
>   
>   assert(dec->base.max_references + 1 <= 16);
>   
> - for (i = 0 ; i < dec->base.max_references + 1 ; ++i) {
> + for (i = 0 ; i < 16 ; ++i) {
>   if (dec->render_pic_list[i] && dec->render_pic_list[i] == 
> target) {
>   result.curr_pic_idx =
>   
> (uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
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Re: [Mesa-dev] gallium/auxiliary/vl: Add barrier/unbind after compute shader launch - vdpau sigfault - bisected

2019-04-06 Thread James Zhu

Hello Dieter,

Thanks for your report! Just send out patch for review.

Best Regards!

James Zhu

On 2019-04-05 7:46 p.m., Dieter Nützel wrote:
> Hello James,
>
> sorry that I have to report that the mentioned commit sigfault with 
> 'mplayer -vo vdpau xxx' for radeonsi on my Polaris 20.
>
> BISECTED
>
> 0f416b85fbb2a3988ddc2c81540e9aadfd63d6ae is the first bad commit
> commit 0f416b85fbb2a3988ddc2c81540e9aadfd63d6ae
> Author: James Zhu 
> Date:   Fri Mar 29 15:59:39 2019 -0400
>
>     gallium/auxiliary/vl: Add barrier/unbind after compute shader launch.
>
>     Add memory barrier sync for multiple launch cases, and unbind 
> completed
>     resources after launch.
>
>     Signed-off-by: James Zhu 
>     Reviewed-by: Marek Olšák 
>
> :04 04 332a2b7a783ef82312e5dbd18f7fed200882d5fe 
> 1fb67385017edc9a65dd4eda7b26628427fdf1f6 M src
>
> Reverting it SOLVED 'mplayer -vo vdpau xxx' for me.
>
> Dieter
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Re: [Mesa-dev] [PATCH] radeonsi: fix a crash when unbinding sampler states

2019-04-08 Thread James Zhu


On 2019-04-08 2:25 p.m., Marek Olšák wrote:
> From: Marek Olšák 
>
> ---
>   src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 244ba5a7bec..ac40ed27f91 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -942,21 +942,21 @@ void si_update_ps_colorbuf0_slot(struct si_context 
> *sctx)
>   static void si_bind_sampler_states(struct pipe_context *ctx,
>  enum pipe_shader_type shader,
>  unsigned start, unsigned count, void 
> **states)
>   {
>   struct si_context *sctx = (struct si_context *)ctx;
>   struct si_samplers *samplers = &sctx->samplers[shader];
>   struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, 
> shader);
>   struct si_sampler_state **sstates = (struct si_sampler_state**)states;
>   int i;
>   
> - if (!count || shader >= SI_NUM_SHADERS)
> + if (!count || shader >= SI_NUM_SHADERS || !sstates)

if sstates == NULL, it means we want to unbind samplers->sampler_states 
from current setting.

So I think it is better not just bypass it.

James

>   return;
>   
>   for (i = 0; i < count; i++) {
>   unsigned slot = start + i;
>   unsigned desc_slot = si_get_sampler_slot(slot);
>   
>   if (!sstates[i] ||
>   sstates[i] == samplers->sampler_states[slot])
>   continue;
>   
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Re: [Mesa-dev] [PATCH] radeonsi: fix a crash when unbinding sampler states

2019-04-08 Thread James Zhu


On 2019-04-08 2:39 p.m., Marek Olšák wrote:
On Mon, Apr 8, 2019 at 2:33 PM James Zhu 
mailto:jam...@amd.com>> wrote:

On 2019-04-08 2:25 p.m., Marek Olšák wrote:
> From: Marek Olšák mailto:marek.ol...@amd.com>>
>
> ---
>   src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 244ba5a7bec..ac40ed27f91 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -942,21 +942,21 @@ void si_update_ps_colorbuf0_slot(struct si_context 
> *sctx)
>   static void si_bind_sampler_states(struct pipe_context *ctx,
>  enum pipe_shader_type shader,
>  unsigned start, unsigned count, void 
> **states)
>   {
>   struct si_context *sctx = (struct si_context *)ctx;
>   struct si_samplers *samplers = &sctx->samplers[shader];
>   struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, 
> shader);
>   struct si_sampler_state **sstates = (struct si_sampler_state**)states;
>   int i;
>
> - if (!count || shader >= SI_NUM_SHADERS)
> + if (!count || shader >= SI_NUM_SHADERS || !sstates)

if sstates == NULL, it means we want to unbind samplers->sampler_states
from current setting.

So I think it is better not just bypass it.

The driver never unbinds constant state objects. If sstates[i] == NULL, it's 
not unbound. sstates == NULL is a similar case.

Then we should not call unbind sampler state after compute shader launch. Since 
it is doing nothing.

James

It's not a standard behavior, but the driver has been doing it for a very long 
time.

Marek
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Re: [Mesa-dev] [PATCH] radeonsi: fix a crash when unbinding sampler states

2019-04-08 Thread James Zhu

This patch is Acked-by: James Zhu <mailto:james@amd.com>

On 2019-04-08 3:02 p.m., Marek Olšák wrote:
On Mon, Apr 8, 2019 at 2:45 PM James Zhu 
mailto:jam...@amd.com>> wrote:


On 2019-04-08 2:39 p.m., Marek Olšák wrote:
On Mon, Apr 8, 2019 at 2:33 PM James Zhu 
mailto:jam...@amd.com>> wrote:

On 2019-04-08 2:25 p.m., Marek Olšák wrote:
> From: Marek Olšák mailto:marek.ol...@amd.com>>
>
> ---
>   src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 244ba5a7bec..ac40ed27f91 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -942,21 +942,21 @@ void si_update_ps_colorbuf0_slot(struct si_context 
> *sctx)
>   static void si_bind_sampler_states(struct pipe_context *ctx,
>  enum pipe_shader_type shader,
>  unsigned start, unsigned count, void 
> **states)
>   {
>   struct si_context *sctx = (struct si_context *)ctx;
>   struct si_samplers *samplers = &sctx->samplers[shader];
>   struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, 
> shader);
>   struct si_sampler_state **sstates = (struct si_sampler_state**)states;
>   int i;
>
> - if (!count || shader >= SI_NUM_SHADERS)
> + if (!count || shader >= SI_NUM_SHADERS || !sstates)

if sstates == NULL, it means we want to unbind samplers->sampler_states
from current setting.

So I think it is better not just bypass it.

The driver never unbinds constant state objects. If sstates[i] == NULL, it's 
not unbound. sstates == NULL is a similar case.

Then we should not call unbind sampler state after compute shader launch. Since 
it is doing nothing.

You are right.

Marek
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