Re: [Mesa-dev] [Mesa-stable] [PATCH] clover: Check the return value of pipe_loader_probe() when probing for devices
Emil Velikov writes: > On 28 November 2015 at 17:06, Francisco Jerez wrote: > >> ... you're free to propose such a change as a >> separate series as long as you fix the documentation, all users and >> back-ends of pipe-loader, if you consider it worth doing -- I personally >> don't. >> > That what I was wondering about. Thanks > >> I don't think it boils down to that. ... > > I got the idea that you approve of the patch the first time around, > despite it (the approval) blurring with the lengthy justification of > the improved version. > There was something fishy going on in this patch, it was obviously papering over a bug elsewhere, so a justification was more than appropriate IMO... > Perhaps we (I'm also guilty on that one) can use a more explicit > "looks good, but let's we use X, because ..." approach. Otherwise > things tend to get a bit strange ? > > Thanks > Emil signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] st/va: add missing break statement
Earlier commit factored out the mpeg4 IQ matrix handling into separate function, although it forgot to add a break in its case statement. Thus the data ended up partially overwritten as the mpeg4 and h265 structs are members of the desc union. Spotted by Coverity (CID 1341052) Fixes: 64761a841db "st/va: move MPEG4 functions into separate file" Cc: Christian König Cc: Julien Isorce Signed-off-by: Emil Velikov --- src/gallium/state_trackers/va/picture.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/state_trackers/va/picture.c b/src/gallium/state_trackers/va/picture.c index 5f703eb..34e7d55 100644 --- a/src/gallium/state_trackers/va/picture.c +++ b/src/gallium/state_trackers/va/picture.c @@ -281,6 +281,7 @@ handleIQMatrixBuffer(vlVaContext *context, vlVaBuffer *buf) case PIPE_VIDEO_FORMAT_MPEG4: vlVaHandleIQMatrixBufferMPEG4(context, buf); + break; case PIPE_VIDEO_FORMAT_HEVC: assert(buf->size >= sizeof(VAIQMatrixBufferH264) && buf->num_elements == 1); -- 2.6.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] st/va: add missing break statement
On 29.11.2015 12:48, Emil Velikov wrote: Earlier commit factored out the mpeg4 IQ matrix handling into separate function, although it forgot to add a break in its case statement. Thus the data ended up partially overwritten as the mpeg4 and h265 structs are members of the desc union. Spotted by Coverity (CID 1341052) Fixes: 64761a841db "st/va: move MPEG4 functions into separate file" Cc: Christian König Cc: Julien Isorce Signed-off-by: Emil Velikov Crap, stupid typo. Patch is Reviewed-by: Christian König --- src/gallium/state_trackers/va/picture.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/state_trackers/va/picture.c b/src/gallium/state_trackers/va/picture.c index 5f703eb..34e7d55 100644 --- a/src/gallium/state_trackers/va/picture.c +++ b/src/gallium/state_trackers/va/picture.c @@ -281,6 +281,7 @@ handleIQMatrixBuffer(vlVaContext *context, vlVaBuffer *buf) case PIPE_VIDEO_FORMAT_MPEG4: vlVaHandleIQMatrixBufferMPEG4(context, buf); + break; case PIPE_VIDEO_FORMAT_HEVC: assert(buf->size >= sizeof(VAIQMatrixBufferH264) && buf->num_elements == 1); ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] st/va: add missing break statement
On 29 November 2015 at 11:52, Christian König wrote: > On 29.11.2015 12:48, Emil Velikov wrote: >> >> Earlier commit factored out the mpeg4 IQ matrix handling into separate >> function, although it forgot to add a break in its case statement. >> Thus the data ended up partially overwritten as the mpeg4 and h265 >> structs are members of the desc union. >> >> Spotted by Coverity (CID 1341052) >> >> Fixes: 64761a841db "st/va: move MPEG4 functions into separate file" >> Cc: Christian König >> Cc: Julien Isorce >> Signed-off-by: Emil Velikov > > > Crap, stupid typo. Patch is Reviewed-by: Christian König > > That's why I like static analysis tools - didn't spot the missing break either :-) Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] gallium/tests: fix build with clang compiler
Nested functions are supported as an extension in GNU C, but Clang
don't support them.
This fixes compilation errors when (manually) building compute.c,
or by setting --enable-gallium-tests to the configure script.
Changes from v2:
- fix typo
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75165
Signed-off-by: Samuel Pitoiset
---
src/gallium/tests/trivial/compute.c | 643 +---
1 file changed, 370 insertions(+), 273 deletions(-)
diff --git a/src/gallium/tests/trivial/compute.c
b/src/gallium/tests/trivial/compute.c
index bcdfb11..5472cf6 100644
--- a/src/gallium/tests/trivial/compute.c
+++ b/src/gallium/tests/trivial/compute.c
@@ -428,6 +428,35 @@ static void launch_grid(struct context *ctx, const uint
*block_layout,
pipe->launch_grid(pipe, block_layout, grid_layout, pc, input);
}
+/* test_system_values */
+static void test_system_values_init(void *p, int s, int x, int y)
+{
+*(uint32_t *)p = 0xdeadbeef;
+}
+
+static void test_system_values_expect(void *p, int s, int x, int y)
+{
+int id = x / 16, sv = (x % 16) / 4, c = x % 4;
+int tid[] = { id % 20, (id % 240) / 20, id / 240, 0 };
+int bsz[] = { 4, 3, 5, 1};
+int gsz[] = { 5, 4, 1, 1};
+
+switch (sv) {
+case 0:
+*(uint32_t *)p = tid[c] / bsz[c];
+break;
+case 1:
+*(uint32_t *)p = bsz[c];
+break;
+case 2:
+*(uint32_t *)p = gsz[c];
+break;
+case 3:
+*(uint32_t *)p = tid[c] % bsz[c];
+break;
+}
+}
+
static void test_system_values(struct context *ctx)
{
const char *src = "COMP\n"
@@ -461,44 +490,36 @@ static void test_system_values(struct context *ctx)
" STORE RES[0].xyzw, TEMP[0], SV[3]\n"
" RET\n"
"ENDSUB\n";
-void init(void *p, int s, int x, int y) {
-*(uint32_t *)p = 0xdeadbeef;
-}
-void expect(void *p, int s, int x, int y) {
-int id = x / 16, sv = (x % 16) / 4, c = x % 4;
-int tid[] = { id % 20, (id % 240) / 20, id / 240, 0 };
-int bsz[] = { 4, 3, 5, 1};
-int gsz[] = { 5, 4, 1, 1};
-
-switch (sv) {
-case 0:
-*(uint32_t *)p = tid[c] / bsz[c];
-break;
-case 1:
-*(uint32_t *)p = bsz[c];
-break;
-case 2:
-*(uint32_t *)p = gsz[c];
-break;
-case 3:
-*(uint32_t *)p = tid[c] % bsz[c];
-break;
-}
-}
printf("- %s\n", __func__);
init_prog(ctx, 0, 0, 0, src, NULL);
init_tex(ctx, 0, PIPE_BUFFER, true, PIPE_FORMAT_R32_FLOAT,
- 76800, 0, init);
+ 76800, 0, test_system_values_init);
init_compute_resources(ctx, (int []) { 0, -1 });
launch_grid(ctx, (uint []){4, 3, 5}, (uint []){5, 4, 1}, 0, NULL);
-check_tex(ctx, 0, expect, NULL);
+check_tex(ctx, 0, test_system_values_expect, NULL);
destroy_compute_resources(ctx);
destroy_tex(ctx);
destroy_prog(ctx);
}
+/* test_resource_access */
+static void test_resource_access_init0(void *p, int s, int x, int y)
+{
+*(float *)p = 8.0 - (float)x;
+}
+
+static void test_resource_access_init1(void *p, int s, int x, int y)
+{
+*(uint32_t *)p = 0xdeadbeef;
+}
+
+static void test_resource_access_expect(void *p, int s, int x, int y)
+{
+*(float *)p = 8.0 - (float)((x + 4 * y) & 0x3f);
+}
+
static void test_resource_access(struct context *ctx)
{
const char *src = "COMP\n"
@@ -519,31 +540,33 @@ static void test_resource_access(struct context *ctx)
" STORE RES[1].xyzw, TEMP[1], TEMP[0]\n"
" RET\n"
"ENDSUB\n";
-void init0(void *p, int s, int x, int y) {
-*(float *)p = 8.0 - (float)x;
-}
-void init1(void *p, int s, int x, int y) {
-*(uint32_t *)p = 0xdeadbeef;
-}
-void expect(void *p, int s, int x, int y) {
-*(float *)p = 8.0 - (float)((x + 4*y) & 0x3f);
-}
printf("- %s\n", __func__);
init_prog(ctx, 0, 0, 0, src, NULL);
init_tex(ctx, 0, PIPE_BUFFER, true, PIPE_FORMAT_R32_FLOAT,
- 256, 0, init0);
+ 256, 0, test_resource_access_init0);
init_tex(ctx, 1, PIPE_TEXTURE_2D, true, PIPE_FORMAT_R32_FLOAT,
- 60, 12, init1);
+ 60, 12, test_resource_access_init1);
init_compute_resources(ctx, (int []) { 0, 1, -1 });
launch_grid(ctx, (uint []){1, 1, 1}, (uint []){15, 12, 1}, 0, NULL);
-chec
[Mesa-dev] [PATCH] nv50/ir: do not call textureMask() for non-texture ops
This fixes a segmentation fault with the 'test_surface_st' test from
src/gallium/tests/trivial/compute.c on Fermi.
While we are it, apply the same change for Tesla.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 7859c8e..7b183ea 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -2046,7 +2046,8 @@
RegAlloc::InsertConstraintsPass::texConstraintNVC0(TexInstruction *tex)
{
int n, s;
- textureMask(tex);
+ if (isTextureOp(tex->op))
+ textureMask(tex);
if (tex->op == OP_TXQ) {
s = tex->srcCount(0xff);
@@ -2077,7 +2078,8 @@
RegAlloc::InsertConstraintsPass::texConstraintNV50(TexInstruction *tex)
if (pred)
tex->setPredicate(tex->cc, NULL);
- textureMask(tex);
+ if (isTextureOp(tex->op))
+ textureMask(tex);
assert(tex->defExists(0) && tex->srcExists(0));
// make src and def count match
--
2.6.2
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Re: [Mesa-dev] [PATCH] nv50/ir: do not call textureMask() for non-texture ops
Under what circumstances can you get into this code and not be a texture op?
On Sun, Nov 29, 2015 at 9:57 AM, Samuel Pitoiset
wrote:
> This fixes a segmentation fault with the 'test_surface_st' test from
> src/gallium/tests/trivial/compute.c on Fermi.
>
> While we are it, apply the same change for Tesla.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
> index 7859c8e..7b183ea 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
> @@ -2046,7 +2046,8 @@
> RegAlloc::InsertConstraintsPass::texConstraintNVC0(TexInstruction *tex)
> {
> int n, s;
>
> - textureMask(tex);
> + if (isTextureOp(tex->op))
> + textureMask(tex);
>
> if (tex->op == OP_TXQ) {
>s = tex->srcCount(0xff);
> @@ -2077,7 +2078,8 @@
> RegAlloc::InsertConstraintsPass::texConstraintNV50(TexInstruction *tex)
> if (pred)
>tex->setPredicate(tex->cc, NULL);
>
> - textureMask(tex);
> + if (isTextureOp(tex->op))
> + textureMask(tex);
>
> assert(tex->defExists(0) && tex->srcExists(0));
> // make src and def count match
> --
> 2.6.2
>
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Re: [Mesa-dev] [PATCH 3/3] xvmc: force assertion in XvMC tests
Hi Giuseppe, On 28 November 2015 at 15:43, Giuseppe Bilotta wrote: > This follows the src/util/u_atomic_test model of undefining NDEBUG > unconditionally throughouth the XvMC tests, to force asserts regardless > of debug mode. > > Signed-off-by: Giuseppe Bilotta > --- > src/gallium/state_trackers/xvmc/tests/test_blocks.c | 2 ++ > src/gallium/state_trackers/xvmc/tests/test_context.c| 2 ++ > src/gallium/state_trackers/xvmc/tests/test_rendering.c | 2 ++ > src/gallium/state_trackers/xvmc/tests/test_subpicture.c | 2 ++ > src/gallium/state_trackers/xvmc/tests/test_surface.c| 2 ++ > 5 files changed, 10 insertions(+) > > diff --git a/src/gallium/state_trackers/xvmc/tests/test_blocks.c > b/src/gallium/state_trackers/xvmc/tests/test_blocks.c > index a35838f..4c89951 100644 > --- a/src/gallium/state_trackers/xvmc/tests/test_blocks.c > +++ b/src/gallium/state_trackers/xvmc/tests/test_blocks.c > @@ -25,6 +25,8 @@ > * > **/ > > +/* Force assertions, even on debug builds. */ The comment should say "...even on release builds". Same for the rest of the patch. I've always wondered if anyone will get to fixing these - be that with current approach or reworking the tests. -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/3] misc janitorial
Hi Giuseppe, On 28 November 2015 at 15:43, Giuseppe Bilotta wrote: > The second and third patches are mostly aimed at removing non-spurious > compiler warnings. The first one is just minor whitespace cleanup in the > general area of code touched by the second patch. > > Giuseppe Bilotta (3): > radeon: whitespace cleanup > radeon: const correctness > xvmc: force assertion in XvMC tests > With the small comment in patch 3 addressed the series is Reviewed-by: Emil Velikov If you're looking for an easy task - there is one in radeon/r200. Currently we have a lot of nasty in-tree symlinks, symbol duplication and hacks to get around it. Let me know if you'd like more info/tips on how to tackle it. Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 91888] EGL Wayland software rendering no longer work after regression
https://bugs.freedesktop.org/show_bug.cgi?id=91888 --- Comment #8 from Emil Velikov --- (In reply to nerdopolis1 from comment #7) > It seems that mesa master's software rendering also causes some problems > with SDL v2, and the testgl2 application that is in their repository for > Wayland > > Reverting Mesa to 10.6 allows this application to work > > otherwise I get > > libEGL Debug: EGL user error 0x3001 (EGL_NOT_INITIALIZED) in eglInitilize Mind opening up a separate bug, and attaching a test case that does not depend on SDL. Wayland support is not amongst my priority list, so if I have to debug SDL/Qt/etc. I will likely go to near the bottom of my list. -- You are receiving this mail because: You are the QA Contact for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 91888] EGL Wayland software rendering no longer work after regression
https://bugs.freedesktop.org/show_bug.cgi?id=91888 --- Comment #9 from Emil Velikov --- For future reference the qtwayland bug is https://bugreports.qt.io/browse/QTBUG-48166 -- You are receiving this mail because: You are the QA Contact for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] clover: Check the return value of pipe_loader_probe() when probing for devices
This patch fixes the issue for me (eg.
https://bugs.freedesktop.org/show_bug.cgi?id=93091#c8).
Thanks Tom.
Tested-by: Samuel Pitoiset
On 11/28/2015 03:52 AM, Tom Stellard wrote:
When probing for devices, clover will call pipe_loader_probe() twice.
The first time to retrieve the number of devices, and then second time
to retrieve the device structures.
We currently assume that the return value of both calls will be the
same, but this will not be the case if a device happens to disappear
between the two calls.
This patch removes this assumption and checks the return value of the
second pipe_loader_probe() call to ensure it does not try to initialize
devices that no longer exits.
CC:
---
src/gallium/state_trackers/clover/core/platform.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/state_trackers/clover/core/platform.cpp
b/src/gallium/state_trackers/clover/core/platform.cpp
index 328b71c..689d692 100644
--- a/src/gallium/state_trackers/clover/core/platform.cpp
+++ b/src/gallium/state_trackers/clover/core/platform.cpp
@@ -28,9 +28,10 @@ platform::platform() : adaptor_range(evals(), devs) {
int n = pipe_loader_probe(NULL, 0);
std::vector ldevs(n);
- pipe_loader_probe(&ldevs.front(), n);
+ n = pipe_loader_probe(&ldevs.front(), n);
- for (pipe_loader_device *ldev : ldevs) {
+ for (int i = 0; i < n; ++i) {
+ pipe_loader_device *ldev = ldevs[i];
try {
devs.push_back(create(*this, ldev));
} catch (error &) {
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[Mesa-dev] [PATCH v2] targets/dri: android: use WHOLE static libraries
By using whole static libraries the android buildsystem provides whole-archive (alike) solution. This means that we don't need to worry about the order of the static libraries and any reverse, recursive or circular dependencies that they have between one another. Without this the linker will discard any unused hunks of one library and we'll end up with unresolved symbols as those are required by another static library. This issue has become more prominent with the introduction of pipe-loader. Whole static libraries has been used in i915/i965 for a very long time, so we might do the same. v2: - Better commit message (Ilia) - Keep external dependencies as [normal] static libs (Mauro) Cc: mesa-sta...@lists.freedesktop.org Cc: Mauro Rossi Reported-by: Mauro Rossi Signed-off-by: Emil Velikov --- src/gallium/targets/dri/Android.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/targets/dri/Android.mk b/src/gallium/targets/dri/Android.mk index 2d9610e..9118fef 100644 --- a/src/gallium/targets/dri/Android.mk +++ b/src/gallium/targets/dri/Android.mk @@ -100,7 +100,7 @@ ifneq ($(filter nouveau r600g,$(MESA_GPU_DRIVERS)),) LOCAL_SHARED_LIBRARIES += $(if $(filter true,$(MESA_LOLLIPOP_BUILD)),libc++,libstlport) endif -LOCAL_STATIC_LIBRARIES := \ +LOCAL_WHOLE_STATIC_LIBRARIES := \ $(gallium_DRIVERS) \ libmesa_st_dri \ libmesa_st_mesa \ @@ -112,6 +112,8 @@ LOCAL_STATIC_LIBRARIES := \ libmesa_util \ libmesa_loader \ +LOCAL_STATIC_LIBRARIES := + ifeq ($(MESA_ENABLE_LLVM),true) LOCAL_STATIC_LIBRARIES += \ libLLVMR600CodeGen \ -- 2.6.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] egl/dri2: expose srgb configs when KHR_gl_colorspace is available
Otherwise the user has no way of using it, and we'll try to access the linear one. v2: - Bail out when KHR_gl_colorspace is missing and srgb is set (Marek) Cc: Mauro Rossi Cc: Chih-Wei Huang Cc: "11.0 11.1" Fixes: c2c2e9ab604(egl: implement EGL_KHR_gl_colorspace (v2)) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91596 Signed-off-by: Emil Velikov --- Mauro, I thought you already tested this but I cannot find any traces. Thanks Emil src/egl/drivers/dri2/egl_dri2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index d34b161..8f50f0c 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -235,6 +235,8 @@ dri2_add_config(_EGLDisplay *disp, const __DRIconfig *dri_config, int id, case __DRI_ATTRIB_FRAMEBUFFER_SRGB_CAPABLE: srgb = value != 0; + if (!disp->Extensions.KHR_gl_colorspace && srgb) +return NULL; break; default: -- 2.6.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] vl/buffers: fixes vl_video_buffer_formats for RGBX
On 27 November 2015 at 08:57, Julien Isorce wrote: > Signed-off-by: Julien Isorce > --- > src/gallium/auxiliary/vl/vl_video_buffer.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/gallium/auxiliary/vl/vl_video_buffer.c > b/src/gallium/auxiliary/vl/vl_video_buffer.c > index 62f4aa9..b3f6ff5 100644 > --- a/src/gallium/auxiliary/vl/vl_video_buffer.c > +++ b/src/gallium/auxiliary/vl/vl_video_buffer.c > @@ -115,7 +115,7 @@ vl_video_buffer_formats(struct pipe_screen *screen, enum > pipe_format format) >return const_resource_formats_VUYA; > > case PIPE_FORMAT_R8G8B8X8_UNORM: > - return const_resource_formats_VUYX; > + return const_resource_formats_YUVX; > > case PIPE_FORMAT_B8G8R8X8_UNORM: >return const_resource_formats_VUYX; Oops copy/pasta mistake :-) Please add the following before pushing Fixes: 42a5e143a8d "vl/buffers: add RGBX and BGRX to the supported formats" Cc: mesa-sta...@lists.freedesktop.org Reviewed-by: Emil Velikov Next time when you're around please make the const_resource_formats_* arrays static. Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] egl/dri2: expose srgb configs when KHR_gl_colorspace is available
Hi Emil, I confirm I tested on lollipop-x86 with i965 on Intel HD4000, X3100 and nouveau with GT210, and I saw no regressions on android-x86. Mauro 2015-11-29 17:48 GMT+01:00 Emil Velikov : > Otherwise the user has no way of using it, and we'll try to access the > linear one. > > v2: > - Bail out when KHR_gl_colorspace is missing and srgb is set (Marek) > > Cc: Mauro Rossi > Cc: Chih-Wei Huang > Cc: "11.0 11.1" > Fixes: c2c2e9ab604(egl: implement EGL_KHR_gl_colorspace (v2)) > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91596 > Signed-off-by: Emil Velikov > --- > > Mauro, I thought you already tested this but I cannot find any traces. > > Thanks > Emil > > src/egl/drivers/dri2/egl_dri2.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/src/egl/drivers/dri2/egl_dri2.c > b/src/egl/drivers/dri2/egl_dri2.c > index d34b161..8f50f0c 100644 > --- a/src/egl/drivers/dri2/egl_dri2.c > +++ b/src/egl/drivers/dri2/egl_dri2.c > @@ -235,6 +235,8 @@ dri2_add_config(_EGLDisplay *disp, const __DRIconfig > *dri_config, int id, > >case __DRI_ATTRIB_FRAMEBUFFER_SRGB_CAPABLE: > srgb = value != 0; > + if (!disp->Extensions.KHR_gl_colorspace && srgb) > +return NULL; > break; > >default: > -- > 2.6.2 > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/3v2] xvmc: force assertion in XvMC tests
This follows the src/util/u_atomic_test.c model of undefining NDEBUG unconditionally throughouth the XvMC tests, to force asserts regardless of debug mode. The comment on u_atomic_test.c is also fixed (read 'debug' where it should have been 'release'). v2: s/debug/release/ in relevant comments Signed-off-by: Giuseppe Bilotta --- src/gallium/state_trackers/xvmc/tests/test_blocks.c | 2 ++ src/gallium/state_trackers/xvmc/tests/test_context.c| 2 ++ src/gallium/state_trackers/xvmc/tests/test_rendering.c | 2 ++ src/gallium/state_trackers/xvmc/tests/test_subpicture.c | 2 ++ src/gallium/state_trackers/xvmc/tests/test_surface.c| 2 ++ src/util/u_atomic_test.c| 2 +- 6 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/xvmc/tests/test_blocks.c b/src/gallium/state_trackers/xvmc/tests/test_blocks.c index a35838f..53c29bc 100644 --- a/src/gallium/state_trackers/xvmc/tests/test_blocks.c +++ b/src/gallium/state_trackers/xvmc/tests/test_blocks.c @@ -25,6 +25,8 @@ * **/ +/* Force assertions, even on release builds. */ +#undef NDEBUG #include #include #include diff --git a/src/gallium/state_trackers/xvmc/tests/test_context.c b/src/gallium/state_trackers/xvmc/tests/test_context.c index 344ac76..81d26fc 100644 --- a/src/gallium/state_trackers/xvmc/tests/test_context.c +++ b/src/gallium/state_trackers/xvmc/tests/test_context.c @@ -25,6 +25,8 @@ * **/ +/* Force assertions, even on release builds. */ +#undef NDEBUG #include #include #include diff --git a/src/gallium/state_trackers/xvmc/tests/test_rendering.c b/src/gallium/state_trackers/xvmc/tests/test_rendering.c index b3b3794..c5494ec 100644 --- a/src/gallium/state_trackers/xvmc/tests/test_rendering.c +++ b/src/gallium/state_trackers/xvmc/tests/test_rendering.c @@ -25,6 +25,8 @@ * **/ +/* Force assertions, even on release builds. */ +#undef NDEBUG #include #include #include diff --git a/src/gallium/state_trackers/xvmc/tests/test_subpicture.c b/src/gallium/state_trackers/xvmc/tests/test_subpicture.c index 57ba1c7..006972f 100644 --- a/src/gallium/state_trackers/xvmc/tests/test_subpicture.c +++ b/src/gallium/state_trackers/xvmc/tests/test_subpicture.c @@ -25,6 +25,8 @@ * **/ +/* Force assertions, even on release builds. */ +#undef NDEBUG #include #include #include diff --git a/src/gallium/state_trackers/xvmc/tests/test_surface.c b/src/gallium/state_trackers/xvmc/tests/test_surface.c index 964ca82..d5a121d 100644 --- a/src/gallium/state_trackers/xvmc/tests/test_surface.c +++ b/src/gallium/state_trackers/xvmc/tests/test_surface.c @@ -25,6 +25,8 @@ * **/ +/* Force assertions, even on release builds. */ +#undef NDEBUG #include #include #include diff --git a/src/util/u_atomic_test.c b/src/util/u_atomic_test.c index 7844f61..7a77768 100644 --- a/src/util/u_atomic_test.c +++ b/src/util/u_atomic_test.c @@ -26,7 +26,7 @@ **/ -/* Force assertions, even on debug builds. */ +/* Force assertions, even on release builds. */ #undef NDEBUG -- 2.6.0.rc2.233.g6dd8a9a.dirty ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] st/va: ensure linear memory for dmabuf
On 27 November 2015 at 08:57, Julien Isorce wrote:
> In order to do zero-copy between two different devices
> the memory should not be tiled.
>
> This is currently no way to set pipe_resource template's flag
> from pipe_video_buffer template. So disabled_tiling is added.
>
> Choosed "disable" prefix so that CALLOC keeps tiling enabled
> by default.
>
> Tested with GStreamer on a laptop that has 2 GPUs:
> 1- gstvaapidecode:
>HW decoding and dmabuf export with nouveau driver on Nvidia GPU.
> 2- glimagesink:
>EGLImage imports dmabuf on Intel GPU.
>
> Note that tiling is working if 1 and 2 are done on the same GPU.
> So it is up to the application to set or not the flag:
> VA_SURFACE_EXTBUF_DESC_ENABLE_TILING
>
> Signed-off-by: Julien Isorce
> ---
> src/gallium/auxiliary/vl/vl_video_buffer.c | 3 +++
> src/gallium/include/pipe/p_video_codec.h | 1 +
> src/gallium/state_trackers/va/surface.c| 5 +
> 3 files changed, 9 insertions(+)
>
> diff --git a/src/gallium/auxiliary/vl/vl_video_buffer.c
> b/src/gallium/auxiliary/vl/vl_video_buffer.c
> index 6cd2557..62f4aa9 100644
> --- a/src/gallium/auxiliary/vl/vl_video_buffer.c
> +++ b/src/gallium/auxiliary/vl/vl_video_buffer.c
> @@ -253,6 +253,9 @@ vl_video_buffer_template(struct pipe_resource *templ,
> templ->bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET;
> templ->usage = usage;
>
> + if (tmpl->disable_tiling)
> + templ->bind |= PIPE_BIND_LINEAR;
> +
> if (plane > 0) {
>if (tmpl->chroma_format == PIPE_VIDEO_CHROMA_FORMAT_420) {
> templ->width0 /= 2;
> diff --git a/src/gallium/include/pipe/p_video_codec.h
> b/src/gallium/include/pipe/p_video_codec.h
> index 196d00b..dbfffd9 100644
> --- a/src/gallium/include/pipe/p_video_codec.h
> +++ b/src/gallium/include/pipe/p_video_codec.h
> @@ -125,6 +125,7 @@ struct pipe_video_buffer
> enum pipe_video_chroma_format chroma_format;
> unsigned width;
> unsigned height;
> + bool disable_tiling;
> bool interlaced;
>
> /**
> diff --git a/src/gallium/state_trackers/va/surface.c
> b/src/gallium/state_trackers/va/surface.c
> index c052c8f..f7043ad 100644
> --- a/src/gallium/state_trackers/va/surface.c
> +++ b/src/gallium/state_trackers/va/surface.c
> @@ -616,6 +616,11 @@ vlVaCreateSurfaces2(VADriverContextP ctx, unsigned int
> format,
>
>switch (memory_type) {
>case VA_SURFACE_ATTRIB_MEM_TYPE_VA:
> + /* The application will clear the TILING flag when the surface is
> + * intended to be exported as dmabuf. */
> + templat.disable_tiling = memory_attibute &&
> +!(memory_attibute->flags & VA_SURFACE_EXTBUF_DESC_ENABLE_TILING);
The condition seems to be flipped, no ? Currently it's doing
"disable_tiling = ENABLE_TILING_BIT_SET"
Other than that, the idea is ok imho, although I'd appreciate
Christian and others' feedback.
A few things worth mentioning while looking around for this:
- suface_from_external_memory should (must) also know about disable_tiling.
- missing R in function name ^^ suRface_ ...
- sometimes radeon (see r600_video_buffer_create) completely
overwrites the existing flags, as opposed to just set the linear bit.
Bug, intentional, worth adding a comment ?
- in many cases nouveau won't create a linear surface as it's not
using the above vl helper (hint, earlier suggesting about
reworking/cleaning things up a bit, hint)
Thanks
Emil
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Re: [Mesa-dev] [PATCH 0/3] misc janitorial
Hello Emil, On Sun, Nov 29, 2015 at 4:21 PM, Emil Velikov wrote: > With the small comment in patch 3 addressed the series is > Reviewed-by: Emil Velikov Thanks. I was pretty sure the comment was wrong when I copied it over from the other file, but I thought I might have been missing something obvious, so I left it as is. Re-sent with the comment fixed (also in the file I copied it from). > If you're looking for an easy task - there is one in radeon/r200. > Currently we have a lot of nasty in-tree symlinks, symbol duplication > and hacks to get around it. Let me know if you'd like more info/tips > on how to tackle it. Easy tasks is exactly what I'm after, since I do these things more as a way to do something useful when taking a break from actual work ;-). I'll give it a first look now, but be ready for me to come back asking for some hints ;-) -- Giuseppe "Oblomov" Bilotta ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 93103] llvm symbols leak through, cause trouble with software rendering in llvm-linked software
https://bugs.freedesktop.org/show_bug.cgi?id=93103 --- Comment #15 from Emil Velikov --- The commit mentioned addresses only their autoconf (more like gnumake really) build. Current upstream covers both builds with should be identical auto-generated (?) LD version scripts. Small aside (C symbols): on my system llvm 3.7 provides some 130+ that are not part of the API. This is 20% of out of the total ~800 (note: haven't checked for preprocessor macros). -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 91888] EGL Wayland software rendering no longer work after regression
https://bugs.freedesktop.org/show_bug.cgi?id=91888 --- Comment #10 from nerdopol...@verizon.net --- unfortunately, if I knew how to write a test case... -- You are receiving this mail because: You are the QA Contact for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] st/va: ensure linear memory for dmabuf
On 29.11.2015 18:26, Emil Velikov wrote:
On 27 November 2015 at 08:57, Julien Isorce wrote:
In order to do zero-copy between two different devices
the memory should not be tiled.
This is currently no way to set pipe_resource template's flag
from pipe_video_buffer template. So disabled_tiling is added.
Choosed "disable" prefix so that CALLOC keeps tiling enabled
by default.
Tested with GStreamer on a laptop that has 2 GPUs:
1- gstvaapidecode:
HW decoding and dmabuf export with nouveau driver on Nvidia GPU.
2- glimagesink:
EGLImage imports dmabuf on Intel GPU.
Note that tiling is working if 1 and 2 are done on the same GPU.
So it is up to the application to set or not the flag:
VA_SURFACE_EXTBUF_DESC_ENABLE_TILING
Signed-off-by: Julien Isorce
---
src/gallium/auxiliary/vl/vl_video_buffer.c | 3 +++
src/gallium/include/pipe/p_video_codec.h | 1 +
src/gallium/state_trackers/va/surface.c| 5 +
3 files changed, 9 insertions(+)
diff --git a/src/gallium/auxiliary/vl/vl_video_buffer.c
b/src/gallium/auxiliary/vl/vl_video_buffer.c
index 6cd2557..62f4aa9 100644
--- a/src/gallium/auxiliary/vl/vl_video_buffer.c
+++ b/src/gallium/auxiliary/vl/vl_video_buffer.c
@@ -253,6 +253,9 @@ vl_video_buffer_template(struct pipe_resource *templ,
templ->bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET;
templ->usage = usage;
+ if (tmpl->disable_tiling)
+ templ->bind |= PIPE_BIND_LINEAR;
+
if (plane > 0) {
if (tmpl->chroma_format == PIPE_VIDEO_CHROMA_FORMAT_420) {
templ->width0 /= 2;
diff --git a/src/gallium/include/pipe/p_video_codec.h
b/src/gallium/include/pipe/p_video_codec.h
index 196d00b..dbfffd9 100644
--- a/src/gallium/include/pipe/p_video_codec.h
+++ b/src/gallium/include/pipe/p_video_codec.h
@@ -125,6 +125,7 @@ struct pipe_video_buffer
enum pipe_video_chroma_format chroma_format;
unsigned width;
unsigned height;
+ bool disable_tiling;
bool interlaced;
/**
diff --git a/src/gallium/state_trackers/va/surface.c
b/src/gallium/state_trackers/va/surface.c
index c052c8f..f7043ad 100644
--- a/src/gallium/state_trackers/va/surface.c
+++ b/src/gallium/state_trackers/va/surface.c
@@ -616,6 +616,11 @@ vlVaCreateSurfaces2(VADriverContextP ctx, unsigned int
format,
switch (memory_type) {
case VA_SURFACE_ATTRIB_MEM_TYPE_VA:
+ /* The application will clear the TILING flag when the surface is
+ * intended to be exported as dmabuf. */
+ templat.disable_tiling = memory_attibute &&
+!(memory_attibute->flags & VA_SURFACE_EXTBUF_DESC_ENABLE_TILING);
The condition seems to be flipped, no ? Currently it's doing
"disable_tiling = ENABLE_TILING_BIT_SET"
Other than that, the idea is ok imho, although I'd appreciate
Christian and others' feedback.
A few things worth mentioning while looking around for this:
- suface_from_external_memory should (must) also know about disable_tiling.
- missing R in function name ^^ suRface_ ...
- sometimes radeon (see r600_video_buffer_create) completely
overwrites the existing flags, as opposed to just set the linear bit.
Bug, intentional, worth adding a comment ?
- in many cases nouveau won't create a linear surface as it's not
using the above vl helper (hint, earlier suggesting about
reworking/cleaning things up a bit, hint)
Yeah, agree deduplicating that code would probably be a good idea.
I would also prefer to have all the bind flags in the pipe_video_buffer
as well.
Regards,
Christian.
Thanks
Emil
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Re: [Mesa-dev] [PATCH 15/23] meta: Use internal functions for buffer object and VAO access
On Mon, Nov 9, 2015 at 4:56 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> Signed-off-by: Ian Romanick
> ---
> src/mesa/drivers/common/meta.c | 76
> --
> 1 file changed, 43 insertions(+), 33 deletions(-)
>
> diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
> index 8cf0bf9..3507927 100644
> --- a/src/mesa/drivers/common/meta.c
> +++ b/src/mesa/drivers/common/meta.c
> @@ -342,12 +342,16 @@ _mesa_meta_setup_vertex_objects(struct gl_context *ctx,
> GLuint VBO;
>
> if (*VAO == 0) {
> + struct gl_vertex_array_object *array_obj;
>assert(*buf_obj == NULL);
>
>/* create vertex array object */
>_mesa_GenVertexArrays(1, VAO);
>_mesa_BindVertexArray(*VAO);
>
> + array_obj = _mesa_lookup_vao(ctx, *VAO);
> + assert(array_obj != NULL);
> +
>/* create vertex array buffer */
>_mesa_CreateBuffers(1, &VBO);
>*buf_obj = _mesa_lookup_bufferobj(ctx, VBO);
> @@ -360,8 +364,8 @@ _mesa_meta_setup_vertex_objects(struct gl_context *ctx,
>assert(*buf_obj != NULL && (*buf_obj)->Name == VBO);
>assert(*buf_obj != ctx->Array.ArrayBufferObj);
>
> - _mesa_NamedBufferData(VBO, 4 * sizeof(struct vertex), NULL,
> -GL_DYNAMIC_DRAW);
> + _mesa_buffer_data(ctx, *buf_obj, GL_NONE, 4 * sizeof(struct vertex),
> NULL,
> +GL_DYNAMIC_DRAW, __func__);
>
>assert((*buf_obj)->Size == 4 * sizeof(struct vertex));
>
> @@ -369,45 +373,51 @@ _mesa_meta_setup_vertex_objects(struct gl_context *ctx,
>if (use_generic_attributes) {
> assert(color_size == 0);
>
> - _mesa_VertexArrayAttribFormat(*VAO, 0, vertex_size, GL_FLOAT,
> - GL_FALSE, OFFSET(x));
> - _mesa_VertexArrayVertexBuffer(*VAO, 0, VBO, 0,
> - sizeof(struct vertex));
> - _mesa_EnableVertexAttribArray(0);
> -
> + _mesa_update_array_format(ctx, array_obj, VERT_ATTRIB_GENERIC(0),
> + vertex_size, GL_FLOAT, GL_RGBA, GL_FALSE,
> + GL_FALSE, GL_FALSE,
> + offsetof(struct vertex, x), true);
> + _mesa_bind_vertex_buffer(ctx, array_obj, VERT_ATTRIB_GENERIC(0),
> + *buf_obj, 0, sizeof(struct vertex));
> + _mesa_enable_vertex_array_attrib(ctx, array_obj,
> + VERT_ATTRIB_GENERIC(0));
> if (texcoord_size > 0) {
> -_mesa_VertexArrayAttribFormat(*VAO, 1, texcoord_size, GL_FLOAT,
> - GL_FALSE, OFFSET(tex));
> -_mesa_VertexArrayVertexBuffer(*VAO, 1, VBO, 0,
> - sizeof(struct vertex));
> -_mesa_EnableVertexAttribArray(1);
> +_mesa_update_array_format(ctx, array_obj, VERT_ATTRIB_GENERIC(1),
> + texcoord_size, GL_FLOAT, GL_RGBA,
> + GL_FALSE, GL_FALSE, GL_FALSE,
> + offsetof(struct vertex, tex), false);
> +_mesa_bind_vertex_buffer(ctx, array_obj, VERT_ATTRIB_GENERIC(1),
> + *buf_obj, 0, sizeof(struct vertex));
> +_mesa_enable_vertex_array_attrib(ctx, array_obj,
> + VERT_ATTRIB_GENERIC(1));
> }
>} else {
> - _mesa_BindBuffer(GL_ARRAY_BUFFER, VBO);
> - _mesa_VertexPointer(vertex_size, GL_FLOAT, sizeof(struct vertex),
> - OFFSET(x));
> - _mesa_EnableClientState(GL_VERTEX_ARRAY);
> + _mesa_update_array_format(ctx, array_obj, VERT_ATTRIB_POS,
> + vertex_size, GL_FLOAT, GL_RGBA, GL_FALSE,
> + GL_FALSE, GL_FALSE,
> + offsetof(struct vertex, x), true);
> + _mesa_bind_vertex_buffer(ctx, array_obj, VERT_ATTRIB_POS,
> + *buf_obj, 0, sizeof(struct vertex));
> + _mesa_enable_vertex_array_attrib(ctx, array_obj, VERT_ATTRIB_POS);
>
> if (texcoord_size > 0) {
> -_mesa_TexCoordPointer(texcoord_size, GL_FLOAT,
> - sizeof(struct vertex), OFFSET(tex));
> -_mesa_EnableClientState(GL_TEXTURE_COORD_ARRAY);
> +_mesa_update_array_format(ctx, array_obj, VERT_ATTRIB_TEX(0),
> + vertex_size, GL_FLOAT, GL_RGBA,
> GL_FALSE,
In the similar block above, you pass texcoord_size instead of
vertex_size. Is this difference here intentional?
Coverity suggests there might be a copy-n-paste mistake, but it looks
to me like this^ might be the problem rather than what Coverity says.
*** CID 1341051: Incorrect expression (CO
Re: [Mesa-dev] [PATCH] docs: add freedreno to GL3.txt
On 11/24/2015 12:37 PM, Ilia Mirkin wrote: > The Adreno A4xx GPU should be capable of a large fraction if not > all of the desktop GL 4.5 features. > > Signed-off-by: Ilia Mirkin > --- > docs/GL3.txt | 70 > ++-- > 1 file changed, 35 insertions(+), 35 deletions(-) > > diff --git a/docs/GL3.txt b/docs/GL3.txt > index ad6b95e..43933bd 100644 > --- a/docs/GL3.txt > +++ b/docs/GL3.txt > @@ -18,7 +18,7 @@ are exposed in the 3.0 context as extensions. > Feature Status > - > > > -GL 3.0, GLSL 1.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, > softpipe > +GL 3.0, GLSL 1.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, > softpipe, freedreno > >glBindFragDataLocation, glGetFragDataLocation DONE >Conditional rendering (GL_NV_conditional_render) DONE () > @@ -45,12 +45,12 @@ GL 3.0, GLSL 1.30 --- all DONE: i965, nv50, nvc0, r600, > radeonsi, llvmpipe, soft >glVertexAttribI commands DONE >Depth format cube texturesDONE () >GLX_ARB_create_context (GLX 1.4 is required) DONE > - Multisample anti-aliasing DONE (llvmpipe (*), > softpipe (*)) > + Multisample anti-aliasing DONE (llvmpipe (*), > softpipe (*), freedreno (*)) > > -(*) llvmpipe and softpipe have fake Multisample anti-aliasing support > +(*) llvmpipe, softpipe, and freedreno have fake Multisample anti-aliasing > support > > > -GL 3.1, GLSL 1.40 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, > softpipe > +GL 3.1, GLSL 1.40 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, > softpipe, freedreno > >Forward compatible context support/deprecations DONE () >Instanced drawing (GL_ARB_draw_instanced) DONE () > @@ -67,34 +67,34 @@ GL 3.2, GLSL 1.50 --- all DONE: i965, nv50, nvc0, r600, > radeonsi, llvmpipe, soft > >Core/compatibility profiles DONE >Geometry shaders DONE () > - BGRA vertex order (GL_ARB_vertex_array_bgra) DONE () > - Base vertex offset(GL_ARB_draw_elements_base_vertex) DONE () > - Frag shader coord (GL_ARB_fragment_coord_conventions) DONE () > - Provoking vertex (GL_ARB_provoking_vertex)DONE () > - Seamless cubemaps (GL_ARB_seamless_cube_map) DONE () > + BGRA vertex order (GL_ARB_vertex_array_bgra) DONE (freedreno) > + Base vertex offset(GL_ARB_draw_elements_base_vertex) DONE (freedreno) > + Frag shader coord (GL_ARB_fragment_coord_conventions) DONE (freedreno) > + Provoking vertex (GL_ARB_provoking_vertex)DONE (freedreno) > + Seamless cubemaps (GL_ARB_seamless_cube_map) DONE (freedreno) >Multisample textures (GL_ARB_texture_multisample) DONE () > - Frag depth clamp (GL_ARB_depth_clamp) DONE () > - Fence objects (GL_ARB_sync) DONE () > + Frag depth clamp (GL_ARB_depth_clamp) DONE (freedreno) > + Fence objects (GL_ARB_sync) DONE (freedreno) >GLX_ARB_create_context_profileDONE > > > GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, > softpipe > > - GL_ARB_blend_func_extendedDONE () > + GL_ARB_blend_func_extendedDONE (freedreno/a3xx) >GL_ARB_explicit_attrib_location DONE (all drivers > that support GLSL) > - GL_ARB_occlusion_query2 DONE () > + GL_ARB_occlusion_query2 DONE (freedreno) >GL_ARB_sampler_objectsDONE (all drivers) > - GL_ARB_shader_bit_encodingDONE () > - GL_ARB_texture_rgb10_a2ui DONE () > - GL_ARB_texture_swizzleDONE () > + GL_ARB_shader_bit_encodingDONE (freedreno) > + GL_ARB_texture_rgb10_a2ui DONE (freedreno) > + GL_ARB_texture_swizzleDONE (freedreno) >GL_ARB_timer_queryDONE () > - GL_ARB_instanced_arrays DONE () > - GL_ARB_vertex_type_2_10_10_10_rev DONE () > + GL_ARB_instanced_arrays DONE (freedreno) > + GL_ARB_vertex_type_2_10_10_10_rev DONE (freedreno) > > > GL 4.0, GLSL 4.00 --- all DONE: nvc0, radeonsi > > - GL_ARB_draw_buffers_blendDONE (i965, nv50, > r600, llvmpipe, softpipe) > + GL_ARB_draw_buffers_blendDONE (i965, nv50, > r600, llvmpipe, softpip
Re: [Mesa-dev] [PATCH v2] i965: Handle lum, intensity and missing components in the fast clear
On 23 November 2015 at 16:17, Neil Roberts wrote: > I've pushed this patch to master but I think it would be a good > candidate to go on the 11.1 branch as well. Do I have to do something to > make that happen? > You've done enough (adding mesa-stable in the to/cc list). I've pulled the patch for 11.1.0-rc2. Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] mesa: remove ARB_geometry_shader4
On 11/25/2015 03:16 AM, Marta Lofstedt wrote:
> From: Marta Lofstedt
>
> No drivers currently implement ARB_geometry_shader4, nor are there
> any plans to implement it. We only support the version of geometry
> shaders that was incorporated into OpenGL 3.2 / GLSL 1.50.
>
> Signed-off-by: Marta Lofstedt
> ---
> src/mapi/glapi/gen/ARB_geometry_shader4.xml | 57
> -
> src/mapi/glapi/gen/Makefile.am | 1 -
> src/mapi/glapi/gen/gl_API.xml | 2 +-
> src/mesa/main/api_validate.c| 2 +-
> src/mesa/main/config.h | 2 +-
> src/mesa/main/context.h | 3 +-
> src/mesa/main/dlist.c | 55
> src/mesa/main/get.c | 7
> src/mesa/main/get_hash_params.py| 12 ++
> src/mesa/main/mtypes.h | 3 +-
> src/mesa/main/tests/enum_strings.cpp| 6 ---
> 11 files changed, 9 insertions(+), 141 deletions(-)
> delete mode 100644 src/mapi/glapi/gen/ARB_geometry_shader4.xml
>
> diff --git a/src/mapi/glapi/gen/ARB_geometry_shader4.xml
> b/src/mapi/glapi/gen/ARB_geometry_shader4.xml
> deleted file mode 100644
> index 280e7a0..000
> --- a/src/mapi/glapi/gen/ARB_geometry_shader4.xml
> +++ /dev/null
> @@ -1,57 +0,0 @@
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> - alias="FramebufferTextureLayer">
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
> diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
> index a5a26a6..40b0e65 100644
> --- a/src/mapi/glapi/gen/Makefile.am
> +++ b/src/mapi/glapi/gen/Makefile.am
> @@ -133,7 +133,6 @@ API_XML = \
> ARB_ES3_compatibility.xml \
> ARB_framebuffer_no_attachments.xml \
> ARB_framebuffer_object.xml \
> - ARB_geometry_shader4.xml \
> ARB_get_program_binary.xml \
> ARB_get_texture_sub_image.xml \
> ARB_gpu_shader_fp64.xml \
> diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
> index ec83cd4..6243bdd 100644
> --- a/src/mapi/glapi/gen/gl_API.xml
> +++ b/src/mapi/glapi/gen/gl_API.xml
> @@ -7975,7 +7975,7 @@
>
>
>
> - xmlns:xi="http://www.w3.org/2001/XInclude"/>
> +
>
>
>
> diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
> index a490189..cbfb6b5 100644
> --- a/src/mesa/main/api_validate.c
> +++ b/src/mesa/main/api_validate.c
> @@ -170,7 +170,7 @@ _mesa_valid_prim_mode(struct gl_context *ctx, GLenum
> mode, const char *name)
>return GL_FALSE;
> }
>
> - /* From the ARB_geometry_shader4 spec:
> + /* From the OpenGL 4.5 specification, section 11.3.1:
> *
> * The error INVALID_OPERATION is generated if Begin, or any command that
> * implicitly calls Begin, is called when a geometry shader is active and:
> diff --git a/src/mesa/main/config.h b/src/mesa/main/config.h
> index f29de5f..2d53e2f 100644
> --- a/src/mesa/main/config.h
> +++ b/src/mesa/main/config.h
> @@ -246,7 +246,7 @@
> #define MAX_FEEDBACK_BUFFERS 4
> #define MAX_FEEDBACK_ATTRIBS 32
>
> -/** For GL_ARB_geometry_shader4 */
> +/** For geometry shader */
> /*@{*/
> #define MAX_GEOMETRY_UNIFORM_COMPONENTS 512
> #define MAX_GEOMETRY_OUTPUT_VERTICES 256
> diff --git a/src/mesa/main/context.h b/src/mesa/main/context.h
> index 4798b1f..8b64f45 100644
> --- a/src/mesa/main/context.h
> +++ b/src/mesa/main/context.h
> @@ -330,8 +330,7 @@ _mesa_is_gles31(const struct gl_context *ctx)
> static inline bool
> _mesa_has_geometry_shaders(const struct gl_context *ctx)
> {
> - return _mesa_is_desktop_gl(ctx) &&
> - (ctx->Version >= 32 || ctx->Extensions.ARB_geometry_shader4);
> + return _mesa_is_desktop_gl(ctx) && ctx->Version >= 32;
> }
>
>
> diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
> index 2b65b2e..ba2e670 100644
> --- a/src/mesa/main/dlist.c
> +++ b/src/mesa/main/dlist.c
> @@ -457,11 +457,6 @@ typedef enum
> OPCODE_SAMPLER_PARAMETERIIV,
> OPCODE_SAMPLER_PARAMETERUIV,
>
> - /* GL_ARB_geometry_shader4 */
> - OPCODE_PROGRAM_PARAMETERI,
> - OPCODE_FRAMEBUFFER_TEXTURE,
> - OPCODE_FRAMEBUFFER_TEXTURE_FACE,
> -
> /* GL_ARB_sync */
> OPCODE_WAIT_SYNC,
>
> @@ -7554,44 +7549,6 @@ save_SamplerParameterIuiv(GLuint sampler, GLenum
> pname, const GLuint *params)
> }
> }
>
> -/* GL_ARB_geometry_shader4 */
> -static void GLAPIENTRY
> -save_ProgramParameteri(GLuint program, GLenum pname, GLint value)
> -{
> - Node *n;
> - GET_CURRENT_CONTEXT(ctx);
> - ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
Re: [Mesa-dev] [PATCH v2] mesa: remove ARB_geometry_shader4
On Sunday, November 29, 2015 02:17:06 PM Ian Romanick wrote:
> On 11/25/2015 03:16 AM, Marta Lofstedt wrote:
> > From: Marta Lofstedt
> >
> > No drivers currently implement ARB_geometry_shader4, nor are there
> > any plans to implement it. We only support the version of geometry
> > shaders that was incorporated into OpenGL 3.2 / GLSL 1.50.
> >
> > Signed-off-by: Marta Lofstedt
> > ---
> > src/mapi/glapi/gen/ARB_geometry_shader4.xml | 57
> > -
> > src/mapi/glapi/gen/Makefile.am | 1 -
> > src/mapi/glapi/gen/gl_API.xml | 2 +-
> > src/mesa/main/api_validate.c| 2 +-
> > src/mesa/main/config.h | 2 +-
> > src/mesa/main/context.h | 3 +-
> > src/mesa/main/dlist.c | 55
> >
> > src/mesa/main/get.c | 7
> > src/mesa/main/get_hash_params.py| 12 ++
> > src/mesa/main/mtypes.h | 3 +-
> > src/mesa/main/tests/enum_strings.cpp| 6 ---
> > 11 files changed, 9 insertions(+), 141 deletions(-)
> > delete mode 100644 src/mapi/glapi/gen/ARB_geometry_shader4.xml
> >
> > diff --git a/src/mapi/glapi/gen/ARB_geometry_shader4.xml
> > b/src/mapi/glapi/gen/ARB_geometry_shader4.xml
> > deleted file mode 100644
> > index 280e7a0..000
> > --- a/src/mapi/glapi/gen/ARB_geometry_shader4.xml
> > +++ /dev/null
> > @@ -1,57 +0,0 @@
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > - > alias="FramebufferTextureLayer">
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
> > index a5a26a6..40b0e65 100644
> > --- a/src/mapi/glapi/gen/Makefile.am
> > +++ b/src/mapi/glapi/gen/Makefile.am
> > @@ -133,7 +133,6 @@ API_XML = \
> > ARB_ES3_compatibility.xml \
> > ARB_framebuffer_no_attachments.xml \
> > ARB_framebuffer_object.xml \
> > - ARB_geometry_shader4.xml \
> > ARB_get_program_binary.xml \
> > ARB_get_texture_sub_image.xml \
> > ARB_gpu_shader_fp64.xml \
> > diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
> > index ec83cd4..6243bdd 100644
> > --- a/src/mapi/glapi/gen/gl_API.xml
> > +++ b/src/mapi/glapi/gen/gl_API.xml
> > @@ -7975,7 +7975,7 @@
> >
> >
> >
> > - > xmlns:xi="http://www.w3.org/2001/XInclude"/>
> > +
> >
> >
> >
> > diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
> > index a490189..cbfb6b5 100644
> > --- a/src/mesa/main/api_validate.c
> > +++ b/src/mesa/main/api_validate.c
> > @@ -170,7 +170,7 @@ _mesa_valid_prim_mode(struct gl_context *ctx, GLenum
> > mode, const char *name)
> >return GL_FALSE;
> > }
> >
> > - /* From the ARB_geometry_shader4 spec:
> > + /* From the OpenGL 4.5 specification, section 11.3.1:
> > *
> > * The error INVALID_OPERATION is generated if Begin, or any command
> > that
> > * implicitly calls Begin, is called when a geometry shader is active
> > and:
> > diff --git a/src/mesa/main/config.h b/src/mesa/main/config.h
> > index f29de5f..2d53e2f 100644
> > --- a/src/mesa/main/config.h
> > +++ b/src/mesa/main/config.h
> > @@ -246,7 +246,7 @@
> > #define MAX_FEEDBACK_BUFFERS 4
> > #define MAX_FEEDBACK_ATTRIBS 32
> >
> > -/** For GL_ARB_geometry_shader4 */
> > +/** For geometry shader */
> > /*@{*/
> > #define MAX_GEOMETRY_UNIFORM_COMPONENTS 512
> > #define MAX_GEOMETRY_OUTPUT_VERTICES 256
> > diff --git a/src/mesa/main/context.h b/src/mesa/main/context.h
> > index 4798b1f..8b64f45 100644
> > --- a/src/mesa/main/context.h
> > +++ b/src/mesa/main/context.h
> > @@ -330,8 +330,7 @@ _mesa_is_gles31(const struct gl_context *ctx)
> > static inline bool
> > _mesa_has_geometry_shaders(const struct gl_context *ctx)
> > {
> > - return _mesa_is_desktop_gl(ctx) &&
> > - (ctx->Version >= 32 || ctx->Extensions.ARB_geometry_shader4);
> > + return _mesa_is_desktop_gl(ctx) && ctx->Version >= 32;
> > }
> >
> >
> > diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
> > index 2b65b2e..ba2e670 100644
> > --- a/src/mesa/main/dlist.c
> > +++ b/src/mesa/main/dlist.c
> > @@ -457,11 +457,6 @@ typedef enum
> > OPCODE_SAMPLER_PARAMETERIIV,
> > OPCODE_SAMPLER_PARAMETERUIV,
> >
> > - /* GL_ARB_geometry_shader4 */
> > - OPCODE_PROGRAM_PARAMETERI,
> > - OPCODE_FRAMEBUFFER_TEXTURE,
> > - OPCODE_FRAMEBUFFER_TEXTURE_FACE,
> > -
> >
[Mesa-dev] [PATCH] r600: split out common alu_writes pattern.
From: Dave Airlie
This just splits out a common pattern into an inline function
to make things cleaner to read.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_asm.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 45824f2..29515f2 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -37,6 +37,11 @@
#define NUM_OF_CYCLES 3
#define NUM_OF_COMPONENTS 4
+static inline bool alu_writes(struct r600_bytecode_alu *alu)
+{
+ return alu->dst.write || alu->is_op3;
+}
+
static inline unsigned int r600_bytecode_get_num_operands(
struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
{
@@ -592,7 +597,7 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
return r;
for (i = 0; i < max_slots; ++i) {
- if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) &&
!prev[i]->dst.rel) {
+ if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
if (is_alu_64bit_inst(bc, prev[i])) {
gpr[i] = -1;
@@ -800,8 +805,8 @@ static int merge_inst_groups(struct r600_bytecode *bc,
struct r600_bytecode_alu
result[4] = slots[i];
} else if (is_alu_any_unit_inst(bc, prev[i])) {
if (slots[i]->dst.sel ==
prev[i]->dst.sel &&
- (slots[i]->dst.write == 1 ||
slots[i]->is_op3) &&
- (prev[i]->dst.write == 1 ||
prev[i]->is_op3))
+ alu_writes(slots[i]) &&
+ alu_writes(prev[i]))
return 0;
result[i] = slots[i];
@@ -816,8 +821,8 @@ static int merge_inst_groups(struct r600_bytecode *bc,
struct r600_bytecode_alu
if (max_slots == 5 && slots[i] && prev[4] &&
slots[i]->dst.sel == prev[4]->dst.sel &&
slots[i]->dst.chan == prev[4]->dst.chan
&&
- (slots[i]->dst.write == 1 ||
slots[i]->is_op3) &&
- (prev[4]->dst.write == 1 ||
prev[4]->is_op3))
+ alu_writes(slots[i]) &&
+ alu_writes(prev[4]))
return 0;
result[i] = slots[i];
@@ -857,7 +862,7 @@ static int merge_inst_groups(struct r600_bytecode *bc,
struct r600_bytecode_alu
continue;
for (j = 0; j < max_slots; ++j) {
- if (!prev[j] || !(prev[j]->dst.write ||
prev[j]->is_op3))
+ if (!prev[j] || !alu_writes(prev[j]))
continue;
/* If it's relative then we can't determin
which gpr is really used. */
@@ -1846,7 +1851,7 @@ static int print_dst(struct r600_bytecode_alu *alu)
reg_char = 'T';
}
- if (alu->dst.write || alu->is_op3) {
+ if (alu_writes(alu)) {
o += fprintf(stderr, "%c", reg_char);
o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
} else {
--
2.5.0
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[Mesa-dev] [PATCH] r600: move per-type settings into a switch statement
From: Dave Airlie
This will allow adding tess stuff much cleaner later.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 560197c..019fef7 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1909,13 +1909,21 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
shader->processor_type = ctx.type;
ctx.bc->type = shader->processor_type;
- if (ctx.type == TGSI_PROCESSOR_VERTEX) {
+ switch (ctx.type) {
+ case TGSI_PROCESSOR_VERTEX:
shader->vs_as_gs_a = key.vs.as_gs_a;
shader->vs_as_es = key.vs.as_es;
+ if (shader->vs_as_es)
+ ring_outputs = true;
+ break;
+ case TGSI_PROCESSOR_GEOMETRY:
+ ring_outputs = true;
+ break;
+ case TGSI_PROCESSOR_FRAGMENT:
+ shader->two_side = key.ps.color_two_side;
+ break;
}
- ring_outputs = shader->vs_as_es || ctx.type == TGSI_PROCESSOR_GEOMETRY;
-
if (shader->vs_as_es) {
ctx.gs_for_vs = &rctx->gs_shader->current->shader;
} else {
@@ -1936,8 +1944,6 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
shader->nr_ps_color_exports = 0;
shader->nr_ps_max_color_exports = 0;
- if (ctx.type == TGSI_PROCESSOR_FRAGMENT)
- shader->two_side = key.ps.color_two_side;
/* register allocations */
/* Values [0,127] correspond to GPR[0..127].
--
2.5.0
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Re: [Mesa-dev] [PATCH] r600: split out common alu_writes pattern.
On Mon, 30 Nov 2015 01:18:18 +0100, Dave Airlie wrote:
From: Dave Airlie
This just splits out a common pattern into an inline function
to make things cleaner to read.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_asm.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 45824f2..29515f2 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -37,6 +37,11 @@
#define NUM_OF_CYCLES 3
#define NUM_OF_COMPONENTS 4
+static inline bool alu_writes(struct r600_bytecode_alu *alu)
+{
+ return alu->dst.write || alu->is_op3;
+}
+
static inline unsigned int r600_bytecode_get_num_operands(
struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
{
@@ -592,7 +597,7 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
return r;
for (i = 0; i < max_slots; ++i) {
- if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) &&
!prev[i]->dst.rel) {
+ if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
if (is_alu_64bit_inst(bc, prev[i])) {
gpr[i] = -1;
@@ -800,8 +805,8 @@ static int merge_inst_groups(struct r600_bytecode *bc,
struct r600_bytecode_alu
result[4] = slots[i];
} else if (is_alu_any_unit_inst(bc, prev[i])) {
if (slots[i]->dst.sel == prev[i]->dst.sel
&&
- (slots[i]->dst.write == 1 ||
slots[i]->is_op3) &&
- (prev[i]->dst.write == 1 ||
prev[i]->is_op3))
+ alu_writes(slots[i]) &&
+ alu_writes(prev[i]))
return 0;
result[i] = slots[i];
@@ -816,8 +821,8 @@ static int merge_inst_groups(struct r600_bytecode *bc,
struct r600_bytecode_alu
if (max_slots == 5 && slots[i] && prev[4] &&
slots[i]->dst.sel == prev[4]->dst.sel &&
slots[i]->dst.chan == prev[4]->dst.chan
&&
- (slots[i]->dst.write == 1 || slots[i]->is_op3)
&&
- (prev[4]->dst.write == 1 ||
prev[4]->is_op3))
+ alu_writes(slots[i]) &&
+ alu_writes(prev[4]))
return 0;
result[i] = slots[i];
@@ -857,7 +862,7 @@ static int merge_inst_groups(struct r600_bytecode *bc,
struct r600_bytecode_alu
continue;
for (j = 0; j < max_slots; ++j) {
- if (!prev[j] || !(prev[j]->dst.write ||
prev[j]->is_op3))
+ if (!prev[j] || !alu_writes(prev[j]))
continue;
/* If it's relative then we can't determin
which gpr is really used. */
@@ -1846,7 +1851,7 @@ static int print_dst(struct r600_bytecode_alu *alu)
reg_char = 'T';
}
- if (alu->dst.write || alu->is_op3) {
+ if (alu_writes(alu)) {
o += fprintf(stderr, "%c", reg_char);
o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
} else {
Reviewed-by: Glenn Kennard
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Re: [Mesa-dev] [PATCH] r600: move per-type settings into a switch statement
On Mon, 30 Nov 2015 01:38:03 +0100, Dave Airlie wrote:
From: Dave Airlie
This will allow adding tess stuff much cleaner later.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 560197c..019fef7 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1909,13 +1909,21 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
shader->processor_type = ctx.type;
ctx.bc->type = shader->processor_type;
- if (ctx.type == TGSI_PROCESSOR_VERTEX) {
+ switch (ctx.type) {
+ case TGSI_PROCESSOR_VERTEX:
shader->vs_as_gs_a = key.vs.as_gs_a;
shader->vs_as_es = key.vs.as_es;
+ if (shader->vs_as_es)
+ ring_outputs = true;
+ break;
+ case TGSI_PROCESSOR_GEOMETRY:
+ ring_outputs = true;
+ break;
+ case TGSI_PROCESSOR_FRAGMENT:
+ shader->two_side = key.ps.color_two_side;
+ break;
}
- ring_outputs = shader->vs_as_es || ctx.type == TGSI_PROCESSOR_GEOMETRY;
-
if (shader->vs_as_es) {
ctx.gs_for_vs = &rctx->gs_shader->current->shader;
} else {
@@ -1936,8 +1944,6 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
shader->nr_ps_color_exports = 0;
shader->nr_ps_max_color_exports = 0;
- if (ctx.type == TGSI_PROCESSOR_FRAGMENT)
- shader->two_side = key.ps.color_two_side;
/* register allocations */
/* Values [0,127] correspond to GPR[0..127].
Reviewed-by: Glenn Kennard
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Re: [Mesa-dev] [PATCH v2 21/42] glsl: Add default matrix ordering in lower_buffer_access
On 2015-11-26 01:10:03, Iago Toral wrote:
> On Wed, 2015-11-25 at 11:59 -0800, Jordan Justen wrote:
> > On 2015-11-25 01:32:37, Iago Toral wrote:
> > >
> > > On Tue, 2015-11-17 at 21:54 -0800, Jordan Justen wrote:
> > > > For compute shader shared variable we will set a default of column
> > > > major.
> > > >
> > > > Signed-off-by: Jordan Justen
> > > > ---
> > > > src/glsl/lower_buffer_access.cpp | 5 +++--
> > > > src/glsl/lower_buffer_access.h | 10 ++
> > > > 2 files changed, 13 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/src/glsl/lower_buffer_access.cpp
> > > > b/src/glsl/lower_buffer_access.cpp
> > > > index 297ed69..66e7abe 100644
> > > > --- a/src/glsl/lower_buffer_access.cpp
> > > > +++ b/src/glsl/lower_buffer_access.cpp
> > > > @@ -281,8 +281,9 @@
> > > > lower_buffer_access::is_dereferenced_thing_row_major(const ir_rvalue
> > > > *deref)
> > > >
> > > > switch (matrix_layout) {
> > > > case GLSL_MATRIX_LAYOUT_INHERITED:
> > > > -assert(!matrix);
> > > > -return false;
> > > > +assert(default_matrix_layout !=
> > > > GLSL_MATRIX_LAYOUT_INHERITED ||
> > > > + !matrix);
> > > > +return default_matrix_layout ==
> > > > GLSL_MATRIX_LAYOUT_ROW_MAJOR;
> > >
> > > I am not sure I understand this. If shared variables are column major by
> > > default, then isn't that the same behavior we have for ubos and ssbos?
> > > In what case is this needed?
> >
> > I think some code must walk the interface blocks an assign the
> > interface matrix layouts to matrices which are set to inherit their
> > layout.
>
> Yes, there is code for that in ast_to_hir.cpp, see
> ast_interface_block::hir().
>
> > Since shared variables are not part of an interface block, this
> > doesn't happen for matrices in shared variables. This leads to us
> > hitting the previous assert(!matrix) code.
>
> Ok, I see.
>
> > Instead of this change we could also go through and mark all matrices
> > in shared variables with a layout other than 'inherited' at an earlier
> > stage.
>
> Probably not worth it if we can handle it here without extra cost. Maybe
> we can make the code more obvious though.
>
> How about this instead?:
>
> case GLSL_MATRIX_LAYOUT_INHERITED: {
>/* For interface block matrix variables we handle inherited layouts
> * at HIR generation time, but we don't do that for shared
> * variables, which are always column-major
> */
>ir_variable *var = deref->variable_referenced();
>assert((var->is_in_buffer_block() && !matrix) ||
> var->data.mode == ir_var_shader_shared)
>return false;
> }
Yeah, I like your idea better. Thanks!
-Jordan
>
> >
> > >
> > > > case GLSL_MATRIX_LAYOUT_COLUMN_MAJOR:
> > > > return false;
> > > > case GLSL_MATRIX_LAYOUT_ROW_MAJOR:
> > > > diff --git a/src/glsl/lower_buffer_access.h
> > > > b/src/glsl/lower_buffer_access.h
> > > > index f8e1070..82b35ed 100644
> > > > --- a/src/glsl/lower_buffer_access.h
> > > > +++ b/src/glsl/lower_buffer_access.h
> > > > @@ -39,6 +39,14 @@ namespace lower_buffer_access {
> > > >
> > > > class lower_buffer_access : public ir_rvalue_enter_visitor {
> > > > public:
> > > > + lower_buffer_access() :
> > > > + default_matrix_layout(GLSL_MATRIX_LAYOUT_INHERITED)
> > > > + {}
> > > > +
> > > > + lower_buffer_access(enum glsl_matrix_layout default_matrix_layout) :
> > > > + default_matrix_layout(default_matrix_layout)
> > > > + {}
> > > > +
> > > > virtual void
> > > > insert_buffer_access(void *mem_ctx, ir_dereference *deref,
> > > > const glsl_type *type, ir_rvalue *offset,
> > > > @@ -55,6 +63,8 @@ public:
> > > > ir_rvalue **offset, unsigned *const_offset,
> > > > bool *row_major, int *matrix_columns,
> > > > unsigned packing);
> > > > +
> > > > + enum glsl_matrix_layout default_matrix_layout;
> > > > };
> > > >
> > > > } /* namespace lower_buffer_access */
> > >
> > >
> > >
> >
>
>
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Re: [Mesa-dev] [PATCH v2 22/42] glsl: Don't lower_variable_index_to_cond_assign for shared variables
On 2015-11-25 00:12:15, Iago Toral wrote: > On Tue, 2015-11-17 at 21:54 -0800, Jordan Justen wrote: > > Signed-off-by: Jordan Justen > > --- > > src/glsl/lower_variable_index_to_cond_assign.cpp | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/src/glsl/lower_variable_index_to_cond_assign.cpp > > b/src/glsl/lower_variable_index_to_cond_assign.cpp > > index 1ab3afe..a1ba934 100644 > > --- a/src/glsl/lower_variable_index_to_cond_assign.cpp > > +++ b/src/glsl/lower_variable_index_to_cond_assign.cpp > > @@ -378,6 +378,9 @@ public: > >case ir_var_shader_storage: > >return this->lower_uniforms; > > > > + case ir_var_shader_shared: > > + return false; > > I suppose the right thing to do here is to add a lower_shared_variables > parameter to this and take its value from a compiler option that we set > to false, like we do with the other types, but I guess this is good > enough for now: Yeah, I mostly implemented that twice, but both times I ended up thinking, maybe we should wait to see what different drivers actually end up needing for shared variables. I think we made a similar choise with SSBO. Right now, SSBOs follow the EmitNoIndirectUniform setting, but it might be possible that a driver needs to handle UBOs and SSBOs differently. -Jordan > Reviewed-by: Iago Toral Quiroga > > >case ir_var_function_in: > >case ir_var_const_in: > > return this->lower_temps; > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [RFC] r600g: evergreen/cayman tessellation support
Hi, Patchbomb time, this set of patches is a first pass at add adding ARB_tessellation_shader support to the r600g driver. Only Evergreen and newer GPUs support tessellation. On any of the GPUs that support native FP64, this will enable OpenGL 4.1 on them. The first bunch of patches are a bit of a driver rework to get things in better shape for tessellation, they shouldn't cause any regressions. This runs heaven on cayman and should pass all the piglits unless I've done something wrong. Development hit two HW programming fun times, one with tess and dynamic GPR interaction requiring disabling dynamic GPRs, and one with programming of some SIMD registers to block TESS shaders on one unit. These fixed most of the hangs we saw during development. This doesn't contain SB support yet, Glenn has started working on it. Currently tested hw: working: CAYMAN, REDWOOD, BARTS, TURKS hangs on any tessellation: CAYMAN hangs differently at least with heaven: SUMO This patchset doesn't block it on any GPUs, but when merged it probably should. Also available at: http://cgit.freedesktop.org/~airlied/mesa/log/?h=r600g-tess-submit Thanks to Glenn Kennard for lots of discussion and testing. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 06/53] r600: move selecting shaders into earlier code.
From: Dave Airlie
select the ps/gs/vs in that order then process the results.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state_common.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index b6d739d..6042976 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1319,9 +1319,12 @@ static bool r600_update_derived_state(struct
r600_context *rctx)
update_gs_block_state(rctx, rctx->gs_shader != NULL);
- if (rctx->gs_shader) {
+ if (rctx->gs_shader)
SELECT_SHADER_OR_FAIL(gs);
+ SELECT_SHADER_OR_FAIL(vs);
+
+ if (rctx->gs_shader) {
if (!rctx->shader_stages.geom_enable) {
rctx->shader_stages.geom_enable = true;
r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
@@ -1336,8 +1339,6 @@ static bool r600_update_derived_state(struct r600_context
*rctx)
rctx->b.streamout.enabled_stream_buffers_mask =
rctx->gs_shader->current->gs_copy_shader->enabled_stream_buffers_mask;
}
- SELECT_SHADER_OR_FAIL(vs);
-
/* vs_shader is used as ES */
if (unlikely(vs_dirty ||
rctx->hw_shader_stages[R600_HW_STAGE_ES].shader != rctx->vs_shader->current)) {
update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_ES], rctx->vs_shader->current);
@@ -1350,8 +1351,6 @@ static bool r600_update_derived_state(struct r600_context
*rctx)
r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
}
- SELECT_SHADER_OR_FAIL(vs);
-
if (unlikely(vs_dirty ||
rctx->hw_shader_stages[R600_HW_STAGE_VS].shader != rctx->vs_shader->current)) {
update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_VS], rctx->vs_shader->current);
--
2.5.0
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[Mesa-dev] [PATCH 01/53] r600/shader: split address get out to a function.
From: Dave Airlie
This will be used in the tess shaders.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index d25fc3b..6233753 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -598,6 +598,11 @@ static int select_twoside_color(struct r600_shader_ctx
*ctx, int front, int back
return 0;
}
+static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
+{
+ return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
+}
+
static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
{
int i;
@@ -7188,7 +7193,7 @@ static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
struct r600_bytecode_alu alu;
int r;
int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
- unsigned reg = inst->Dst[0].Register.Index > 0 ?
ctx->bc->index_reg[inst->Dst[0].Register.Index - 1] : ctx->bc->ar_reg;
+ unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
assert(inst->Dst[0].Register.Index < 3);
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
--
2.5.0
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[Mesa-dev] [PATCH 11/53] r600/sb: add support for GDS to the sb decoder/dump.
From: Dave Airlie
This just adds support to the decoder, not actual SB support.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc.h | 6 ++--
src/gallium/drivers/r600/sb/sb_bc_decoder.cpp | 43 ++-
src/gallium/drivers/r600/sb/sb_bc_dump.cpp| 24 +--
src/gallium/drivers/r600/sb/sb_bc_fmt_def.inc | 28 +
4 files changed, 89 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc.h
b/src/gallium/drivers/r600/sb/sb_bc.h
index 9c2a917..5b1bbbd 100644
--- a/src/gallium/drivers/r600/sb/sb_bc.h
+++ b/src/gallium/drivers/r600/sb/sb_bc.h
@@ -535,11 +535,11 @@ struct bc_fetch {
unsigned resource_id:8;
unsigned src_gpr:7;
- unsigned src_rel:1;
+ unsigned src_rel:2; /* GDS expands to 2 bits */
unsigned src_sel[4];
unsigned dst_gpr:7;
- unsigned dst_rel:1;
+ unsigned dst_rel:2; /* GDS expands to 2 bits */
unsigned dst_sel[4];
unsigned alt_const:1;
@@ -573,6 +573,7 @@ struct bc_fetch {
unsigned endian_swap:2;
unsigned mega_fetch:1;
+ unsigned src2_gpr:7; /* for GDS */
void set_op(unsigned op) { this->op = op; op_ptr = r600_isa_fetch(op); }
};
@@ -739,6 +740,7 @@ private:
int decode_cf_mem(unsigned &i, bc_cf &bc);
int decode_fetch_vtx(unsigned &i, bc_fetch &bc);
+ int decode_fetch_gds(unsigned &i, bc_fetch &bc);
};
// bytecode format definition
diff --git a/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
b/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
index 5fe8f50..7626920 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
@@ -373,7 +373,20 @@ int bc_decoder::decode_fetch(unsigned & i, bc_fetch& bc) {
unsigned fetch_opcode = dw0 & 0x1F;
- bc.set_op(r600_isa_fetch_by_opcode(ctx.isa, fetch_opcode));
+ if (fetch_opcode == 2) { // MEM_INST_MEM
+ unsigned mem_op = (dw0 >> 8) & 0x7;
+ unsigned gds_op;
+ if (mem_op == 4) {
+ gds_op = (dw1 >> 9) & 0x1f;
+ fetch_opcode = FETCH_OP_GDS_ADD + gds_op;
+ } else if (mem_op == 5)
+ fetch_opcode = FETCH_OP_TF_WRITE;
+ bc.set_op(fetch_opcode);
+ } else
+ bc.set_op(r600_isa_fetch_by_opcode(ctx.isa, fetch_opcode));
+
+ if (bc.op_ptr->flags & FF_GDS)
+ return decode_fetch_gds(i, bc);
if (bc.op_ptr->flags & FF_VTX)
return decode_fetch_vtx(i, bc);
@@ -439,6 +452,34 @@ int bc_decoder::decode_fetch(unsigned & i, bc_fetch& bc) {
return r;
}
+int bc_decoder::decode_fetch_gds(unsigned & i, bc_fetch& bc) {
+ int r = 0;
+ uint32_t dw0 = dw[i];
+ uint32_t dw1 = dw[i+1];
+ uint32_t dw2 = dw[i+2];
+ i+= 4;
+ assert(i <= ndw);
+
+ MEM_GDS_WORD0_EGCM w0(dw0);
+ bc.src_gpr = w0.get_SRC_GPR();
+ bc.src_rel = w0.get_SRC_REL();
+ bc.src_sel[0] = w0.get_SRC_SEL_X();
+ bc.src_sel[1] = w0.get_SRC_SEL_Y();
+ bc.src_sel[2] = w0.get_SRC_SEL_Z();
+
+ MEM_GDS_WORD1_EGCM w1(dw1);
+ bc.dst_gpr = w1.get_DST_GPR();
+ bc.dst_rel = w1.get_DST_REL();
+ bc.src2_gpr = w1.get_SRC_GPR();
+
+ MEM_GDS_WORD2_EGCM w2(dw2);
+ bc.dst_sel[0] = w2.get_DST_SEL_X();
+ bc.dst_sel[1] = w2.get_DST_SEL_Y();
+ bc.dst_sel[2] = w2.get_DST_SEL_Z();
+ bc.dst_sel[3] = w2.get_DST_SEL_W();
+ return r;
+}
+
int bc_decoder::decode_fetch_vtx(unsigned & i, bc_fetch& bc) {
int r = 0;
uint32_t dw0 = dw[i];
diff --git a/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
b/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
index 3c70ea7..3c051ad 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
@@ -425,23 +425,26 @@ bc_dump::bc_dump(shader& s, bytecode* bc) :
void bc_dump::dump(fetch_node& n) {
sb_ostringstream s;
static const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
+ unsigned gds = n.bc.op_ptr->flags & FF_GDS;
s << n.bc.op_ptr->name;
fill_to(s, 20);
- s << "R";
- print_sel(s, n.bc.dst_gpr, n.bc.dst_rel, INDEX_LOOP, 0);
- s << ".";
- for (int k = 0; k < 4; ++k)
- s << chans[n.bc.dst_sel[k]];
- s << ", ";
+ if (!gds) {
+ s << "R";
+ print_sel(s, n.bc.dst_gpr, n.bc.dst_rel, INDEX_LOOP, 0);
+ s << ".";
+ for (int k = 0; k < 4; ++k)
+ s << chans[n.bc.dst_sel[k]];
+ s << ", ";
+ }
s << "R";
print_sel(s, n.bc.src_gpr, n.bc.src_rel, INDEX_LOOP, 0);
s << ".";
unsigned vtx = n.bc.op_ptr->flags & FF_VTX;
- unsigned num_src_comp = vtx ? ctx.is_cayman() ? 2 : 1 : 4;
+ unsigned num_src_comp = gds ? 3 :
[Mesa-dev] [PATCH 02/53] r600: introduce HW shader stage defines
From: Dave Airlie Add a list of defines for the HW stages. We will use this for GPR calculations amongst other things. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/r600_pipe.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index bbb55ad..36fa1c9 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -81,6 +81,17 @@ */ #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4])) +/* HW stages */ +#define R600_HW_STAGE_PS 0 +#define R600_HW_STAGE_VS 1 +#define R600_HW_STAGE_GS 2 +#define R600_HW_STAGE_ES 3 +#define EG_HW_STAGE_LS 4 +#define EG_HW_STAGE_HS 5 + +#define R600_NUM_HW_STAGES 4 +#define EG_NUM_HW_STAGES 6 + #ifdef PIPE_ARCH_BIG_ENDIAN #define R600_BIG_ENDIAN 1 #else -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 09/53] r600: use macros for updating the various stages.
From: Dave Airlie
These macros will make things easier to see when tess
is added to the mix.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state_common.c | 40 +---
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 36afbd6..bc9c3b6 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1294,6 +1294,26 @@ static void r600_update_clip_state(struct r600_context
*rctx,
return false; \
} while(0)
+#define UPDATE_SHADER(hw, sw) do { \
+ if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader !=
rctx->sw##_shader->current)) \
+ update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)],
rctx->sw##_shader->current); \
+ } while(0)
+
+#define UPDATE_SHADER_CLIP(hw, sw) do {
\
+ if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader !=
rctx->sw##_shader->current)) { \
+ update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)],
rctx->sw##_shader->current); \
+ clip_so_current = rctx->sw##_shader->current; \
+ } \
+ } while(0)
+
+#define UPDATE_SHADER_GS(hw, hw2, sw) do { \
+ if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader !=
rctx->sw##_shader->current)) { \
+ update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)],
rctx->sw##_shader->current); \
+ update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)],
rctx->sw##_shader->current->gs_copy_shader); \
+ clip_so_current =
rctx->sw##_shader->current->gs_copy_shader; \
+ } \
+ } while(0)
+
#define SET_NULL_SHADER(hw) do {
\
if (rctx->hw_shader_stages[(hw)].shader)\
update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)],
NULL); \
@@ -1338,17 +1358,11 @@ static bool r600_update_derived_state(struct
r600_context *rctx)
}
/* gs_shader provides GS and VS (copy shader) */
- if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader !=
rctx->gs_shader->current)) {
- update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_GS], rctx->gs_shader->current);
- update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_VS],
rctx->gs_shader->current->gs_copy_shader);
-
- clip_so_current =
rctx->gs_shader->current->gs_copy_shader;
- }
+ UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
/* vs_shader is used as ES */
- if (unlikely(vs_dirty ||
rctx->hw_shader_stages[R600_HW_STAGE_ES].shader != rctx->vs_shader->current)) {
- update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_ES], rctx->vs_shader->current);
- }
+ UPDATE_SHADER(R600_HW_STAGE_ES, vs);
+
} else {
if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
SET_NULL_SHADER(R600_HW_STAGE_GS);
@@ -1357,11 +1371,7 @@ static bool r600_update_derived_state(struct
r600_context *rctx)
r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
}
- if (unlikely(vs_dirty ||
rctx->hw_shader_stages[R600_HW_STAGE_VS].shader != rctx->vs_shader->current)) {
- update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_VS], rctx->vs_shader->current);
-
- clip_so_current = rctx->vs_shader->current;
- }
+ UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
}
/* Update clip misc state. */
@@ -1399,8 +1409,8 @@ static bool r600_update_derived_state(struct r600_context
*rctx)
}
r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
- update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_PS], rctx->ps_shader->current);
}
+ UPDATE_SHADER(R600_HW_STAGE_PS, ps);
if (rctx->b.chip_class >= EVERGREEN) {
evergreen_update_db_shader_control(rctx);
--
2.5.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 03/53] r600: make adjust_gprs use hw stages.
From: Dave Airlie
This changes the r600 specific GPR adjustment code
to use the stage defines, and arrays.
This is prep work for the tess changes later.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_pipe.h | 2 +-
src/gallium/drivers/r600/r600_state.c | 117 ++
2 files changed, 64 insertions(+), 55 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 36fa1c9..0e57efe 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -432,7 +432,7 @@ struct r600_context {
/* Hardware info. */
boolean has_vertex_cache;
boolean keep_tiling_flags;
- unsigneddefault_ps_gprs, default_vs_gprs;
+ unsigneddefault_gprs[EG_NUM_HW_STAGES];
unsignedr6xx_num_clause_temp_gprs;
/* Miscellaneous state objects. */
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index c2d4abc..a16d4bd 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2044,57 +2044,62 @@ static void r600_emit_gs_rings(struct r600_context
*rctx, struct r600_atom *a)
/* Adjust GPR allocation on R6xx/R7xx */
bool r600_adjust_gprs(struct r600_context *rctx)
{
- unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
- unsigned num_vs_gprs, num_es_gprs, num_gs_gprs;
- unsigned new_num_ps_gprs = num_ps_gprs;
- unsigned new_num_vs_gprs, new_num_es_gprs, new_num_gs_gprs;
- unsigned cur_num_ps_gprs =
G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
- unsigned cur_num_vs_gprs =
G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
- unsigned cur_num_gs_gprs =
G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
- unsigned cur_num_es_gprs =
G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
- unsigned def_num_ps_gprs = rctx->default_ps_gprs;
- unsigned def_num_vs_gprs = rctx->default_vs_gprs;
- unsigned def_num_gs_gprs = 0;
- unsigned def_num_es_gprs = 0;
+ unsigned num_gprs[R600_NUM_HW_STAGES];
+ unsigned new_gprs[R600_NUM_HW_STAGES];
+ unsigned cur_gprs[R600_NUM_HW_STAGES];
+ unsigned def_gprs[R600_NUM_HW_STAGES];
unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
- /* hardware will reserve twice num_clause_temp_gprs */
- unsigned max_gprs = def_num_gs_gprs + def_num_es_gprs + def_num_ps_gprs
+ def_num_vs_gprs + def_num_clause_temp_gprs * 2;
+ unsigned max_gprs;
unsigned tmp, tmp2;
+ unsigned i;
+ bool need_recalc = false, use_default = true;
+
+ /* hardware will reserve twice num_clause_temp_gprs */
+ max_gprs = def_num_clause_temp_gprs * 2;
+ for (i = 0; i < R600_NUM_HW_STAGES; i++) {
+ def_gprs[i] = rctx->default_gprs[i];
+ max_gprs += def_gprs[i];
+ }
+ cur_gprs[R600_HW_STAGE_PS] =
G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
+ cur_gprs[R600_HW_STAGE_VS] =
G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
+ cur_gprs[R600_HW_STAGE_GS] =
G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
+ cur_gprs[R600_HW_STAGE_ES] =
G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
+
+ num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
if (rctx->gs_shader) {
- num_es_gprs = rctx->vs_shader->current->shader.bc.ngpr;
- num_gs_gprs = rctx->gs_shader->current->shader.bc.ngpr;
- num_vs_gprs =
rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
+ num_gprs[R600_HW_STAGE_ES] =
rctx->vs_shader->current->shader.bc.ngpr;
+ num_gprs[R600_HW_STAGE_GS] =
rctx->gs_shader->current->shader.bc.ngpr;
+ num_gprs[R600_HW_STAGE_VS] =
rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
} else {
- num_es_gprs = 0;
- num_gs_gprs = 0;
- num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
+ num_gprs[R600_HW_STAGE_ES] = 0;
+ num_gprs[R600_HW_STAGE_GS] = 0;
+ num_gprs[R600_HW_STAGE_VS] =
rctx->vs_shader->current->shader.bc.ngpr;
+ }
+
+ for (i = 0; i < R600_NUM_HW_STAGES; i++) {
+ new_gprs[i] = num_gprs[i];
+ if (new_gprs[i] > cur_gprs[i])
+ need_recalc = true;
+ if (new_gprs[i] > def_gprs[i])
+ use_default = false;
}
- new_num_vs_gprs = num_vs_gprs;
- new_num_es_gprs = num_es_gprs;
- new_num_gs_gprs = num_gs_gprs;
/* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_
[Mesa-dev] [PATCH 12/53] r600: add support for LDS instruction encoding.
From: Dave Airlie
These are used in tessellation shaders to read/write values
between VS/TCS/TES.
This splits the eg alu assembler out to handle these
instructions.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/eg_asm.c | 75 +
src/gallium/drivers/r600/eg_sq.h| 39 +++
src/gallium/drivers/r600/r600_asm.c | 28 +-
src/gallium/drivers/r600/r600_asm.h | 4 ++
4 files changed, 144 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/eg_asm.c
b/src/gallium/drivers/r600/eg_asm.c
index f555649..46683c1 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -216,3 +216,78 @@ int eg_bytecode_gds_build(struct r600_bytecode *bc, struct
r600_bytecode_gds *gd
S_SQ_MEM_GDS_WORD2_DST_SEL_W(gds->dst_sel_w);
return 0;
}
+
+int eg_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu
*alu, unsigned id)
+{
+ if (alu->is_lds_idx_op) {
+ assert(!alu->src[0].abs && !alu->src[1].abs &&
!alu->src[2].abs);
+ assert(!alu->src[0].neg && !alu->src[1].neg &&
!alu->src[2].neg);
+ bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
+ S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
+ S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
+ S_SQ_ALU_WORD0_LDS_IDX_OP_IDX_OFFSET_4(alu->lds_idx >>
4) |
+ S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
+ S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
+ S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
+ S_SQ_ALU_WORD0_LDS_IDX_OP_IDX_OFFSET_5(alu->lds_idx >>
5) |
+ S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
+ S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
+ S_SQ_ALU_WORD0_LAST(alu->last);
+ } else {
+ bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
+ S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
+ S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
+ S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
+ S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
+ S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
+ S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
+ S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
+ S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
+ S_SQ_ALU_WORD0_LAST(alu->last);
+ }
+
+ /* don't replace gpr by pv or ps for destination register */
+ if (alu->is_lds_idx_op) {
+ unsigned lds_op = r600_isa_alu_opcode(bc->isa->hw_class,
alu->op);
+ bc->bytecode[id++] =
+ S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
+ S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
+ S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
+ S_SQ_ALU_WORD1_LDS_IDX_OP_IDX_OFFSET_1(alu->lds_idx >>
1) |
+
+ S_SQ_ALU_WORD1_OP3_ALU_INST(lds_op & 0xff) |
+ S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
+ S_SQ_ALU_WORD1_LDS_IDX_OP_LDS_OP((lds_op >> 8) & 0xff) |
+ S_SQ_ALU_WORD1_LDS_IDX_OP_IDX_OFFSET_0(alu->lds_idx) |
+ S_SQ_ALU_WORD1_LDS_IDX_OP_IDX_OFFSET_2(alu->lds_idx >>
2) |
+ S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
+ S_SQ_ALU_WORD1_LDS_IDX_OP_IDX_OFFSET_3(alu->lds_idx >>
3);
+
+ } else if (alu->is_op3) {
+ assert(!alu->src[0].abs && !alu->src[1].abs &&
!alu->src[2].abs);
+ bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
+ S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
+ S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
+ S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
+
S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
+
S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
+
S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
+
S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
+
S_SQ_ALU_WORD1_OP3_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) |
+
S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
+ } else {
+ bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
+ S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
+ S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
+
[Mesa-dev] [PATCH 10/53] r600: add support for GDS clause to the assembler.
From: Dave Airlie
This just adds enough for the tessellation shaders,
which require TF_WRITE to work.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/eg_asm.c | 23 +++
src/gallium/drivers/r600/eg_sq.h| 21 ++
src/gallium/drivers/r600/r600_asm.c | 82 +
src/gallium/drivers/r600/r600_asm.h | 23 ++-
4 files changed, 148 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/eg_asm.c
b/src/gallium/drivers/r600/eg_asm.c
index c32d317..f555649 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -193,3 +193,26 @@ int egcm_load_index_reg(struct r600_bytecode *bc, unsigned
id, bool inside_alu_c
return 0;
}
+
+int eg_bytecode_gds_build(struct r600_bytecode *bc, struct r600_bytecode_gds
*gds, unsigned id)
+{
+ unsigned opcode = r600_isa_fetch_opcode(bc->isa->hw_class, gds->op) >>
8;
+ bc->bytecode[id++] = S_SQ_MEM_GDS_WORD0_MEM_INST(2) |
+ S_SQ_MEM_GDS_WORD0_MEM_OP(opcode) |
+ S_SQ_MEM_GDS_WORD0_SRC_GPR(gds->src_gpr) |
+ S_SQ_MEM_GDS_WORD0_SRC_REL(gds->src_rel) |
+ S_SQ_MEM_GDS_WORD0_SRC_SEL_X(gds->src_sel_x) |
+ S_SQ_MEM_GDS_WORD0_SRC_SEL_Y(gds->src_sel_y) |
+ S_SQ_MEM_GDS_WORD0_SRC_SEL_Z(gds->src_sel_z);
+
+ bc->bytecode[id++] = S_SQ_MEM_GDS_WORD1_DST_GPR(gds->dst_gpr) |
+ S_SQ_MEM_GDS_WORD1_DST_REL(gds->dst_rel) |
+ S_SQ_MEM_GDS_WORD1_GDS_OP(gds->gds_op) |
+ S_SQ_MEM_GDS_WORD1_SRC_GPR(gds->src_gpr2);
+
+ bc->bytecode[id++] = S_SQ_MEM_GDS_WORD2_DST_SEL_X(gds->dst_sel_x) |
+ S_SQ_MEM_GDS_WORD2_DST_SEL_Y(gds->dst_sel_y) |
+ S_SQ_MEM_GDS_WORD2_DST_SEL_Z(gds->dst_sel_z) |
+ S_SQ_MEM_GDS_WORD2_DST_SEL_W(gds->dst_sel_w);
+ return 0;
+}
diff --git a/src/gallium/drivers/r600/eg_sq.h b/src/gallium/drivers/r600/eg_sq.h
index 97e230f..3074cfe 100644
--- a/src/gallium/drivers/r600/eg_sq.h
+++ b/src/gallium/drivers/r600/eg_sq.h
@@ -514,6 +514,27 @@
#define G_SQ_TEX_WORD2_SRC_SEL_W(x)(((x) >>
29) & 0x7)
#define C_SQ_TEX_WORD2_SRC_SEL_W 0x1FFF
+#define P_SQ_MEM_GDS_WORD0
+#define S_SQ_MEM_GDS_WORD0_MEM_INST(x) (((x) &
0x1f) << 0)
+#define S_SQ_MEM_GDS_WORD0_MEM_OP(x) (((x) &
0x7) << 8)
+#define S_SQ_MEM_GDS_WORD0_SRC_GPR(x) (((x) &
0x7f) << 11)
+#define S_SQ_MEM_GDS_WORD0_SRC_REL(x) (((x) &
0x3) << 18)
+#define S_SQ_MEM_GDS_WORD0_SRC_SEL_X(x)(((x) &
0x7) << 20)
+#define S_SQ_MEM_GDS_WORD0_SRC_SEL_Y(x)(((x) &
0x7) << 23)
+#define S_SQ_MEM_GDS_WORD0_SRC_SEL_Z(x)(((x) &
0x7) << 26)
+
+#define P_SQ_MEM_GDS_WORD1
+#define S_SQ_MEM_GDS_WORD1_DST_GPR(x) (((x) &
0x7f) << 0)
+#define S_SQ_MEM_GDS_WORD1_DST_REL(x) (((x) &
0x3) << 7)
+#define S_SQ_MEM_GDS_WORD1_GDS_OP(x) (((x) &
0x3f) << 9)
+#define S_SQ_MEM_GDS_WORD1_SRC_GPR(x) (((x) &
0x7f) << 16)
+
+#define P_SQ_MEM_GDS_WORD2
+#define S_SQ_MEM_GDS_WORD2_DST_SEL_X(x)(((x) &
0x7) << 0)
+#define S_SQ_MEM_GDS_WORD2_DST_SEL_Y(x)(((x) &
0x7) << 3)
+#define S_SQ_MEM_GDS_WORD2_DST_SEL_Z(x)(((x) &
0x7) << 6)
+#define S_SQ_MEM_GDS_WORD2_DST_SEL_W(x)(((x) &
0x7) << 9)
+
#define V_SQ_CF_COND_ACTIVE 0x00
#define V_SQ_CF_COND_FALSE 0x01
#define V_SQ_CF_COND_BOOL 0x02
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 91faa82..41e9c19 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -61,6 +61,7 @@ static struct r600_bytecode_cf *r600_bytecode_cf(void)
LIST_INITHEAD(&cf->alu);
LIST_INITHEAD(&cf->vtx);
LIST_INITHEAD(&cf->tex);
+ LIST_INITHEAD(&cf->gds);
return cf;
}
@@ -94,6 +95,16 @@ static struct r600_bytecode_tex *r600_bytecode_tex(void)
return tex;
}
+static struct r600_bytecode_gds *r600_bytecode_gds(void)
+{
+ struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds);
+
+ if (gds == NULL)
+ return NULL;
+ LIST_INITHEAD(&gds->list);
+ return gds;
+}
+
static unsigned stack_entry_size(enum radeon_family chip) {
/* Wavefront size:
* 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
@@ -1412,6 +1423,33 @@ int r600_bytecode_add_tex(struct r600_bytecode *bc,
const struct r600_bytecode_t
return 0;
}
+int r600_bytecode_a
[Mesa-dev] [PATCH 08/53] r600: add SET_NULL_SHADER macro.
From: Dave Airlie
This is used to set a hw shader to NULL.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state_common.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index b107f8a..36afbd6 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1294,6 +1294,11 @@ static void r600_update_clip_state(struct r600_context
*rctx,
return false; \
} while(0)
+#define SET_NULL_SHADER(hw) do {
\
+ if (rctx->hw_shader_stages[(hw)].shader)\
+ update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)],
NULL); \
+ } while (0)
+
static bool r600_update_derived_state(struct r600_context *rctx)
{
struct pipe_context * ctx = (struct pipe_context*)rctx;
@@ -1346,8 +1351,8 @@ static bool r600_update_derived_state(struct r600_context
*rctx)
}
} else {
if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
- update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_GS], NULL);
- update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_ES], NULL);
+ SET_NULL_SHADER(R600_HW_STAGE_GS);
+ SET_NULL_SHADER(R600_HW_STAGE_ES);
rctx->shader_stages.geom_enable = false;
r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
}
--
2.5.0
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[Mesa-dev] [PATCH 07/53] r600: move clip misc and streamout stream updates to a single place
From: Dave Airlie
This will be updated in a macro later.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state_common.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 6042976..b107f8a 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1300,6 +1300,8 @@ static bool r600_update_derived_state(struct r600_context
*rctx)
bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
bool blend_disable;
bool need_buf_const;
+ struct r600_pipe_shader *clip_so_current = NULL;
+
if (!rctx->blitter->running) {
unsigned i;
@@ -1334,9 +1336,8 @@ static bool r600_update_derived_state(struct r600_context
*rctx)
if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader !=
rctx->gs_shader->current)) {
update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_GS], rctx->gs_shader->current);
update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_VS],
rctx->gs_shader->current->gs_copy_shader);
- /* Update clip misc state. */
- r600_update_clip_state(rctx,
rctx->gs_shader->current->gs_copy_shader);
- rctx->b.streamout.enabled_stream_buffers_mask =
rctx->gs_shader->current->gs_copy_shader->enabled_stream_buffers_mask;
+
+ clip_so_current =
rctx->gs_shader->current->gs_copy_shader;
}
/* vs_shader is used as ES */
@@ -1354,12 +1355,16 @@ static bool r600_update_derived_state(struct
r600_context *rctx)
if (unlikely(vs_dirty ||
rctx->hw_shader_stages[R600_HW_STAGE_VS].shader != rctx->vs_shader->current)) {
update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_VS], rctx->vs_shader->current);
- /* Update clip misc state. */
- r600_update_clip_state(rctx, rctx->vs_shader->current);
- rctx->b.streamout.enabled_stream_buffers_mask =
rctx->vs_shader->current->enabled_stream_buffers_mask;
+ clip_so_current = rctx->vs_shader->current;
}
}
+ /* Update clip misc state. */
+ if (clip_so_current) {
+ r600_update_clip_state(rctx, clip_so_current);
+ rctx->b.streamout.enabled_stream_buffers_mask =
clip_so_current->enabled_stream_buffers_mask;
+ }
+
if (unlikely(ps_dirty ||
rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
rctx->rasterizer->sprite_coord_enable !=
rctx->ps_shader->current->sprite_coord_enable ||
rctx->rasterizer->flatshade !=
rctx->ps_shader->current->flatshade)) {
--
2.5.0
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[Mesa-dev] [PATCH 19/53] r600/blit: add tcs/tes shader saves.
From: Dave Airlie Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/r600_blit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index 8a90489..8aa3c97 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -60,6 +60,8 @@ static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_fetch_shader.cso); util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader); util_blitter_save_geometry_shader(rctx->blitter, rctx->gs_shader); + util_blitter_save_tessctrl_shader(rctx->blitter, rctx->tcs_shader); + util_blitter_save_tesseval_shader(rctx->blitter, rctx->tes_shader); util_blitter_save_so_targets(rctx->blitter, rctx->b.streamout.num_targets, (struct pipe_stream_output_target**)rctx->b.streamout.targets); util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer_state.cso); -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 22/53] r600: hook up constants/samplers/sampler view for tessellation
From: Dave Airlie
This hooks the resources to the correct hw shaders when tess
is enabled.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_state.c | 90 +++---
src/gallium/drivers/r600/r600_pipe.h | 2 +-
2 files changed, 82 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 7467925..75d1d6a 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1978,13 +1978,22 @@ static void evergreen_emit_constant_buffers(struct
r600_context *rctx,
state->dirty_mask = 0;
}
+/* VS constants can be in VS/ES (same space) or LS if tess is enabled */
static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx,
struct r600_atom *atom)
{
- evergreen_emit_constant_buffers(rctx,
&rctx->constbuf_state[PIPE_SHADER_VERTEX],
- EG_FETCH_CONSTANTS_OFFSET_VS,
- R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
- R_028980_ALU_CONST_CACHE_VS_0,
- 0 /* PKT3 flags */);
+ if (rctx->vs_shader->current->shader.vs_as_ls) {
+ evergreen_emit_constant_buffers(rctx,
&rctx->constbuf_state[PIPE_SHADER_VERTEX],
+ EG_FETCH_CONSTANTS_OFFSET_LS,
+
R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
+ R_028F40_ALU_CONST_CACHE_LS_0,
+ 0 /* PKT3 flags */);
+ } else {
+ evergreen_emit_constant_buffers(rctx,
&rctx->constbuf_state[PIPE_SHADER_VERTEX],
+ EG_FETCH_CONSTANTS_OFFSET_VS,
+
R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+ R_028980_ALU_CONST_CACHE_VS_0,
+ 0 /* PKT3 flags */);
+ }
}
static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx,
struct r600_atom *atom)
@@ -2014,6 +2023,29 @@ static void evergreen_emit_cs_constant_buffers(struct
r600_context *rctx, struct
RADEON_CP_PACKET3_COMPUTE_MODE);
}
+/* tes constants can be emitted to VS or ES - which are common */
+static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx,
struct r600_atom *atom)
+{
+ if (!rctx->tes_shader)
+ return;
+ evergreen_emit_constant_buffers(rctx,
&rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
+ EG_FETCH_CONSTANTS_OFFSET_VS,
+ R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+ R_028980_ALU_CONST_CACHE_VS_0,
+ 0);
+}
+
+static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx,
struct r600_atom *atom)
+{
+ if (!rctx->tes_shader)
+ return;
+ evergreen_emit_constant_buffers(rctx,
&rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
+ EG_FETCH_CONSTANTS_OFFSET_HS,
+ R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
+ R_028F00_ALU_CONST_CACHE_HS_0,
+ 0);
+}
+
static void evergreen_emit_sampler_views(struct r600_context *rctx,
struct r600_samplerview_state *state,
unsigned resource_id_base, unsigned
pkt_flags)
@@ -2049,8 +2081,13 @@ static void evergreen_emit_sampler_views(struct
r600_context *rctx,
static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct
r600_atom *atom)
{
- evergreen_emit_sampler_views(rctx,
&rctx->samplers[PIPE_SHADER_VERTEX].views,
-EG_FETCH_CONSTANTS_OFFSET_VS +
R600_MAX_CONST_BUFFERS, 0);
+ if (rctx->vs_shader->current->shader.vs_as_ls) {
+ evergreen_emit_sampler_views(rctx,
&rctx->samplers[PIPE_SHADER_VERTEX].views,
+EG_FETCH_CONSTANTS_OFFSET_LS +
R600_MAX_CONST_BUFFERS, 0);
+ } else {
+ evergreen_emit_sampler_views(rctx,
&rctx->samplers[PIPE_SHADER_VERTEX].views,
+EG_FETCH_CONSTANTS_OFFSET_VS +
R600_MAX_CONST_BUFFERS, 0);
+ }
}
static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct
r600_atom *atom)
@@ -2059,6 +2096,18 @@ static void evergreen_emit_gs_sampler_views(struct
r600_context *rctx, struct r6
EG_FETCH_CONSTANTS_OFFSET_GS +
R600_MAX_CONST_BUFFERS, 0);
}
+static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, st
[Mesa-dev] [PATCH 15/53] r600: add PATCHES to the pipe conversion.
From: Dave Airlie This just converts the value to the hw value. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/r600_state_common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index bc9c3b6..3319a26 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -117,6 +117,7 @@ static unsigned r600_conv_pipe_prim(unsigned prim) [PIPE_PRIM_LINE_STRIP_ADJACENCY]= V_008958_DI_PT_LINESTRIP_ADJ, [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ, [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]= V_008958_DI_PT_TRISTRIP_ADJ, + [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH, [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST }; assert(prim < Elements(prim_conv)); -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 25/53] r600: fix masks for two of the unused evergreen regs.
From: Dave Airlie Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/evergreend.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h index 3f60e3e..ebe8c4a 100644 --- a/src/gallium/drivers/r600/evergreend.h +++ b/src/gallium/drivers/r600/evergreend.h @@ -2146,14 +2146,14 @@ #define C_028B5C_SIZE 0xFF00 #define S_028B5C_PATCH_CP_SIZE(x) (((x) & 0x1FFF) << 8) #define G_028B5C_PATCH_CP_SIZE(x) (((x) >> 8) & 0x1FFF) -#define C_028B5C_PATCH_CP_SIZE 0xFFFE00FF +#define C_028B5C_PATCH_CP_SIZE 0xFFE000FF #define R_028B60_VGT_HS_SIZE 0x00028B60 #define S_028B60_SIZE(x)(((x) & 0xFF) << 0) #define G_028B60_SIZE(x)(((x) >> 0) & 0xFF) #define C_028B60_SIZE 0xFF00 #define S_028B60_PATCH_CP_SIZE(x) (((x) & 0x1FFF) << 8) #define G_028B60_PATCH_CP_SIZE(x) (((x) >> 8) & 0x1FFF) -#define C_028B60_PATCH_CP_SIZE 0xFFFE00FF +#define C_028B60_PATCH_CP_SIZE 0xFFE000FF #define R_028B64_VGT_LS_HS_ALLOC 0x00028B64 #define S_028B64_HS_TOTAL_OUTPUT(x) (((x) & 0x1FFF) << 0) #define G_028B64_HS_TOTAL_OUTPUT(x) (((x) >> 0) & 0x1FFF) -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 27/53] r600: workout bitmask for the used tcs inputs/outputs.
From: Dave Airlie
This is used later to setup the constants to be given
to the tessellation shaders.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_pipe.h | 3 +++
src/gallium/drivers/r600/r600_state_common.c | 25 +
2 files changed, 28 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index e23f7cf..ae04c8c 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -330,6 +330,9 @@ struct r600_pipe_shader_selector {
unsignedgs_max_out_vertices;
unsignedgs_num_invocations;
+ /* TCS/VS */
+ uint64_tlds_patch_outputs_written_mask;
+ uint64_tlds_outputs_written_mask;
unsignednr_ps_max_color_exports;
};
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 48ecd7d..eab36d3 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -855,6 +855,7 @@ static void *r600_create_shader_state(struct pipe_context
*ctx,
unsigned pipe_shader_type)
{
struct r600_pipe_shader_selector *sel =
CALLOC_STRUCT(r600_pipe_shader_selector);
+ int i;
sel->type = pipe_shader_type;
sel->tokens = tgsi_dup_tokens(state->tokens);
@@ -870,6 +871,30 @@ static void *r600_create_shader_state(struct pipe_context
*ctx,
sel->gs_num_invocations =
sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
break;
+ case PIPE_SHADER_VERTEX:
+ case PIPE_SHADER_TESS_CTRL:
+ sel->lds_patch_outputs_written_mask = 0;
+ sel->lds_outputs_written_mask = 0;
+
+ for (i = 0; i < sel->info.num_outputs; i++) {
+ unsigned name = sel->info.output_semantic_name[i];
+ unsigned index = sel->info.output_semantic_index[i];
+
+ switch (name) {
+ case TGSI_SEMANTIC_TESSINNER:
+ case TGSI_SEMANTIC_TESSOUTER:
+ case TGSI_SEMANTIC_PATCH:
+ sel->lds_patch_outputs_written_mask |=
+ 1llu << r600_get_lds_unique_index(name,
index);
+ break;
+ default:
+ sel->lds_outputs_written_mask |=
+ 1llu << r600_get_lds_unique_index(name,
index);
+ }
+ }
+ break;
+ default:
+ break;
}
return sel;
--
2.5.0
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[Mesa-dev] [PATCH 13/53] r600g/sb: Support LDS ops in SB bytecode I/O
From: Glenn Kennard
This just adds the LDS ops to the SB bytecode reader/writers.
Signed-off-by: Glenn Kennard
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc.h | 2 +
src/gallium/drivers/r600/sb/sb_bc_builder.cpp | 31 +++
src/gallium/drivers/r600/sb/sb_bc_decoder.cpp | 55 ++-
src/gallium/drivers/r600/sb/sb_bc_dump.cpp| 26 +
4 files changed, 105 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc.h
b/src/gallium/drivers/r600/sb/sb_bc.h
index 5b1bbbd..d2e8da0 100644
--- a/src/gallium/drivers/r600/sb/sb_bc.h
+++ b/src/gallium/drivers/r600/sb/sb_bc.h
@@ -518,6 +518,8 @@ struct bc_alu {
unsigned slot:3;
+ unsigned lds_idx_offset:6;
+
alu_op_flags slot_flags;
void set_op(unsigned op) {
diff --git a/src/gallium/drivers/r600/sb/sb_bc_builder.cpp
b/src/gallium/drivers/r600/sb/sb_bc_builder.cpp
index 55e2a85..5dec169 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_builder.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_builder.cpp
@@ -371,6 +371,37 @@ int bc_builder::build_alu(alu_node* n) {
const bc_alu &bc = n->bc;
const alu_op_info *aop = bc.op_ptr;
+ if (n->bc.op_ptr->flags & AF_LDS) {
+ assert(ctx.is_egcm());
+ bb << ALU_WORD0_LDS_IDX_OP_EGCM()
+ .SRC0_SEL(bc.src[0].sel)
+ .SRC0_REL(bc.src[0].rel)
+ .SRC0_CHAN(bc.src[0].chan)
+ .IDX_OFFSET_4((bc.lds_idx_offset >> 4) & 1)
+ .SRC1_SEL(bc.src[1].sel)
+ .SRC1_REL(bc.src[1].rel)
+ .SRC1_CHAN(bc.src[1].chan)
+ .IDX_OFFSET_5((bc.lds_idx_offset >> 5) & 1)
+ .INDEX_MODE(bc.index_mode)
+ .PRED_SEL(bc.pred_sel)
+ .LAST(bc.last);
+
+ bb << ALU_WORD1_LDS_IDX_OP_EGCM()
+ .SRC2_SEL(bc.src[2].sel)
+ .SRC2_REL(bc.src[2].rel)
+ .SRC2_CHAN(bc.src[2].chan)
+ .IDX_OFFSET_1((bc.lds_idx_offset >> 1) & 1)
+ .ALU_INST(ctx.alu_opcode(ALU_OP3_LDS_IDX_OP))
+ .BANK_SWIZZLE(bc.bank_swizzle)
+ .LDS_OP((bc.op_ptr->opcode[1] >> 8) & 0xff)
+ .IDX_OFFSET_0((bc.lds_idx_offset >> 0) & 1)
+ .IDX_OFFSET_2((bc.lds_idx_offset >> 2) & 1)
+ .DST_CHAN(bc.dst_chan)
+ .IDX_OFFSET_3((bc.lds_idx_offset >> 3) & 1);
+
+ return 0;
+ }
+
bb << ALU_WORD0_ALL()
.INDEX_MODE(bc.index_mode)
.LAST(bc.last)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
b/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
index 7626920..c43403a 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
@@ -310,16 +310,53 @@ int bc_decoder::decode_alu(unsigned & i, bc_alu& bc) {
ALU_WORD1_OP3_ALL w1(dw1);
bc.set_op(r600_isa_alu_by_opcode(ctx.isa, w1.get_ALU_INST(),
1));
- bc.bank_swizzle = w1.get_BANK_SWIZZLE();
- bc.clamp = w1.get_CLAMP();
- bc.dst_chan = w1.get_DST_CHAN();
- bc.dst_gpr = w1.get_DST_GPR();
- bc.dst_rel = w1.get_DST_REL();
+ if (bc.op == ALU_OP3_LDS_IDX_OP) {
+ ALU_WORD0_LDS_IDX_OP_EGCM iw0(dw0);
+ ALU_WORD1_LDS_IDX_OP_EGCM iw1(dw1);
+ bc.index_mode = iw0.get_INDEX_MODE();
+ bc.last = iw0.get_LAST();
+ bc.pred_sel = iw0.get_PRED_SEL();
+ bc.src[0].chan = iw0.get_SRC0_CHAN();
+ bc.src[0].sel = iw0.get_SRC0_SEL();
+ bc.src[0].rel = iw0.get_SRC0_REL();
+
+ bc.src[1].chan = iw0.get_SRC1_CHAN();
+ bc.src[1].sel = iw0.get_SRC1_SEL();
+ bc.src[1].rel = iw0.get_SRC1_REL();
+
+ bc.bank_swizzle = iw1.get_BANK_SWIZZLE();
+ bc.src[2].chan = iw1.get_SRC2_CHAN();
+ bc.src[2].sel = iw1.get_SRC2_SEL();
+ bc.src[2].rel = iw1.get_SRC2_REL();
+ bc.dst_chan = iw1.get_DST_CHAN();
+ // TODO: clean up
+ for (size_t k = 0; k < sizeof(alu_op_table) /
sizeof(alu_op_table[0]); k++) {
+ if (((alu_op_table[k].opcode[1] >> 8) & 0xff)
== iw1.get_LDS_OP()) {
+ bc.op_ptr = &alu_op_table[k];
+ bc.op = k;
+ break;
+ }
+ }
+
[Mesa-dev] [PATCH 05/53] r600: use a macro to remove common shader selection code.
From: Dave Airlie
This function is going to get a lot messier with tessellation
so I'm going to use some macros to try and clean some bits
of common code up.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state_common.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index b544abb..b6d739d 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1288,6 +1288,11 @@ static void r600_update_clip_state(struct r600_context
*rctx,
r600_mark_atom_dirty(rctx,
&rctx->clip_misc_state.atom);
}
}
+#define SELECT_SHADER_OR_FAIL(x) do { \
+ r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
+ if (unlikely(!rctx->x##_shader))\
+ return false; \
+ } while(0)
static bool r600_update_derived_state(struct r600_context *rctx)
{
@@ -1310,16 +1315,12 @@ static bool r600_update_derived_state(struct
r600_context *rctx)
}
}
- r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
- if (unlikely(!rctx->ps_shader->current))
- return false;
+ SELECT_SHADER_OR_FAIL(ps);
update_gs_block_state(rctx, rctx->gs_shader != NULL);
if (rctx->gs_shader) {
- r600_shader_select(ctx, rctx->gs_shader, &gs_dirty);
- if (unlikely(!rctx->gs_shader->current))
- return false;
+ SELECT_SHADER_OR_FAIL(gs);
if (!rctx->shader_stages.geom_enable) {
rctx->shader_stages.geom_enable = true;
@@ -1335,9 +1336,7 @@ static bool r600_update_derived_state(struct r600_context
*rctx)
rctx->b.streamout.enabled_stream_buffers_mask =
rctx->gs_shader->current->gs_copy_shader->enabled_stream_buffers_mask;
}
- r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
- if (unlikely(!rctx->vs_shader->current))
- return false;
+ SELECT_SHADER_OR_FAIL(vs);
/* vs_shader is used as ES */
if (unlikely(vs_dirty ||
rctx->hw_shader_stages[R600_HW_STAGE_ES].shader != rctx->vs_shader->current)) {
@@ -1351,9 +1350,7 @@ static bool r600_update_derived_state(struct r600_context
*rctx)
r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
}
- r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
- if (unlikely(!rctx->vs_shader->current))
- return false;
+ SELECT_SHADER_OR_FAIL(vs);
if (unlikely(vs_dirty ||
rctx->hw_shader_stages[R600_HW_STAGE_VS].shader != rctx->vs_shader->current)) {
update_shader_atom(ctx,
&rctx->hw_shader_stages[R600_HW_STAGE_VS], rctx->vs_shader->current);
--
2.5.0
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[Mesa-dev] [PATCH 24/53] r600: add set_tess_state callback.
From: Dave Airlie
This just stores the values in the context to be used later
when emitting the constant buffers.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_state.c | 12 +++-
src/gallium/drivers/r600/r600_pipe.h | 1 +
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 9bcd5cb..4d448d1 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3598,6 +3598,16 @@ fallback:
src, src_level, src_box);
}
+static void evergreen_set_tess_state(struct pipe_context *ctx,
+const float default_outer_level[4],
+const float default_inner_level[2])
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
+ memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
+}
+
void evergreen_init_state_functions(struct r600_context *rctx)
{
unsigned id = 1;
@@ -3680,7 +3690,7 @@ void evergreen_init_state_functions(struct r600_context
*rctx)
rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
rctx->b.b.set_min_samples = evergreen_set_min_samples;
rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
-
+ rctx->b.b.set_tess_state = evergreen_set_tess_state;
if (rctx->b.chip_class == EVERGREEN)
rctx->b.b.get_sample_position = evergreen_get_sample_position;
else
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 66af81e..e23f7cf 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -521,6 +521,7 @@ struct r600_context {
void*sb_context;
struct r600_isa *isa;
float sample_positions[4 * 16];
+ float tess_state[8];
};
static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
--
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[Mesa-dev] [PATCH 23/53] r600/eg: init tess registers to defaults
From: Dave Airlie This initialises the tess min/max using fglrx values, and also initialises a number of other registers related to tessellation. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/evergreen_state.c | 34 +- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 75d1d6a..9bcd5cb 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -2332,7 +2332,7 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) struct r600_command_buffer *cb = &rctx->start_cs_cmd; int tmp, i; - r600_init_command_buffer(cb, 326); + r600_init_command_buffer(cb, 336); /* This must be first. */ r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); @@ -2366,9 +2366,9 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ - r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ - r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ - r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ + r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ + r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ + r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */ r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ @@ -2477,11 +2477,16 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2); r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */ r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */ - r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0); + r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2); + r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */ + r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */ + r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0); eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF); eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF); eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF); + eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF); + eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF); } void evergreen_init_common_regs(struct r600_command_buffer *cb, @@ -2614,7 +2619,7 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) return; } - r600_init_command_buffer(cb, 330); + r600_init_command_buffer(cb, 342); /* This must be first. */ r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); @@ -2821,9 +2826,9 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ - r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ - r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ - r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ + r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ + r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ + r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */ r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ @@ -2927,11 +2932,20 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */ r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */ - r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0); + r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7); + r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */ + r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */ + r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */ + r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */ + r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */ + r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */ + r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */ eg_store_loop_const(cb
[Mesa-dev] [PATCH 26/53] r600: port over the get_lds_unique_index from radeonsi
From: Dave Airlie
On r600 this needs to subtract 9 due to texcoord interactions.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 38 ++
src/gallium/drivers/r600/r600_shader.h | 1 +
2 files changed, 39 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index b7d21fb..8e50cc3 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -568,6 +568,44 @@ static int r600_spi_sid(struct r600_shader_io * io)
return index;
};
+/* we need this to get a common lds index for vs/tcs/tes input/outputs */
+int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
+{
+ switch (semantic_name) {
+ case TGSI_SEMANTIC_POSITION:
+ return 0;
+ case TGSI_SEMANTIC_PSIZE:
+ return 1;
+ case TGSI_SEMANTIC_CLIPDIST:
+ assert(index <= 1);
+ return 2 + index;
+ case TGSI_SEMANTIC_GENERIC:
+ if (index <= 63-4)
+ return 4 + index - 9;
+ else
+ /* same explanation as in the default statement,
+* the only user hitting this is st/nine.
+*/
+ return 0;
+
+ /* patch indices are completely separate and thus start from 0 */
+ case TGSI_SEMANTIC_TESSOUTER:
+ return 0;
+ case TGSI_SEMANTIC_TESSINNER:
+ return 1;
+ case TGSI_SEMANTIC_PATCH:
+ return 2 + index;
+
+ default:
+ /* Don't fail here. The result of this function is only used
+* for LS, TCS, TES, and GS, where legacy GL semantics can't
+* occur, but this function is called for all vertex shaders
+* before it's known whether LS will be compiled or not.
+*/
+ return 0;
+ }
+}
+
/* turn input into interpolate on EG */
static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
{
diff --git a/src/gallium/drivers/r600/r600_shader.h
b/src/gallium/drivers/r600/r600_shader.h
index 398e7da..f5b1c4b 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -154,6 +154,7 @@ struct r600_pipe_shader {
TGSI_INTERPOLATE_LOC_CENTER/SAMPLE/COUNT. Other input values return -1. */
int eg_get_interpolator_index(unsigned interpolate, unsigned location);
+int r600_get_lds_unique_index(unsigned semantic_name, unsigned index);
#ifdef __cplusplus
} // extern "C"
--
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[Mesa-dev] [PATCH 04/53] r600: move to using hw stages array for hw stage atoms
From: Dave Airlie
This moves to using an array of hw stages for the atoms.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_state.c | 8 +++-
src/gallium/drivers/r600/r600_hw_context.c | 8
src/gallium/drivers/r600/r600_pipe.h | 7 ++-
src/gallium/drivers/r600/r600_state.c| 8 +++-
src/gallium/drivers/r600/r600_state_common.c | 25 -
5 files changed, 24 insertions(+), 32 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 5333761..fd4c8b5 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3496,7 +3496,7 @@ fallback:
void evergreen_init_state_functions(struct r600_context *rctx)
{
unsigned id = 1;
-
+ unsigned i;
/* !!!
* To avoid GPU lockup registers must be emited in a specific order
* (no kidding ...). The order below is important and have been
@@ -3555,10 +3555,8 @@ void evergreen_init_state_functions(struct r600_context
*rctx)
r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
- r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader,
23);
- r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader,
0);
- r600_init_atom(rctx, &rctx->geometry_shader.atom, id++,
r600_emit_shader, 0);
- r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader,
0);
+ for (i = 0; i < EG_NUM_HW_STAGES; i++)
+ r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++,
r600_emit_shader, 0);
r600_init_atom(rctx, &rctx->shader_stages.atom, id++,
evergreen_emit_shader_stages, 6);
r600_init_atom(rctx, &rctx->gs_rings.atom, id++,
evergreen_emit_gs_rings, 26);
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index 6409f0b..13b6918 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -300,7 +300,7 @@ void r600_begin_new_cs(struct r600_context *ctx)
r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom);
r600_mark_atom_dirty(ctx, &ctx->db_state.atom);
r600_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
- r600_mark_atom_dirty(ctx, &ctx->pixel_shader.atom);
+ r600_mark_atom_dirty(ctx,
&ctx->hw_shader_stages[R600_HW_STAGE_PS].atom);
r600_mark_atom_dirty(ctx, &ctx->poly_offset_state.atom);
r600_mark_atom_dirty(ctx, &ctx->vgt_state.atom);
r600_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
@@ -315,13 +315,13 @@ void r600_begin_new_cs(struct r600_context *ctx)
}
r600_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
r600_mark_atom_dirty(ctx, &ctx->vertex_fetch_shader.atom);
- r600_mark_atom_dirty(ctx, &ctx->export_shader.atom);
+ r600_mark_atom_dirty(ctx,
&ctx->hw_shader_stages[R600_HW_STAGE_ES].atom);
r600_mark_atom_dirty(ctx, &ctx->shader_stages.atom);
if (ctx->gs_shader) {
- r600_mark_atom_dirty(ctx, &ctx->geometry_shader.atom);
+ r600_mark_atom_dirty(ctx,
&ctx->hw_shader_stages[R600_HW_STAGE_GS].atom);
r600_mark_atom_dirty(ctx, &ctx->gs_rings.atom);
}
- r600_mark_atom_dirty(ctx, &ctx->vertex_shader.atom);
+ r600_mark_atom_dirty(ctx,
&ctx->hw_shader_stages[R600_HW_STAGE_VS].atom);
r600_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
r600_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 0e57efe..0ca4052 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -38,7 +38,7 @@
#include "tgsi/tgsi_scan.h"
-#define R600_NUM_ATOMS 43
+#define R600_NUM_ATOMS 45
#define R600_MAX_VIEWPORTS 16
@@ -481,10 +481,7 @@ struct r600_context {
struct r600_viewport_state viewport;
/* Shaders and shader resources. */
struct r600_cso_state vertex_fetch_shader;
- struct r600_shader_statevertex_shader;
- struct r600_shader_statepixel_shader;
- struct r600_shader_stategeometry_shader;
- struct r600_shader_stateexport_shader;
+ struct r600_shader_statehw_shader_stages[EG_NUM_HW_STAGES];
struct r600_cs_shader_state cs_shader_state;
struct r600_shader_stages_state shader_stages;
struct r600_gs_rings_state gs_rings;
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index a16d4bd..9638c66 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -3063,7 +3063,7 @@ fallback:
void r600_init_state_functi
[Mesa-dev] [PATCH 42/53] r600/shader: handle TES exports and streamout
From: Dave Airlie
when tessellation is enabled the TES shader is responsible
for handling streamout and exports.
This adds the streamout and export workarounds to TES,
and also makes sure TES sets up spi_sid.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index b306c6e..d2cc927 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -836,7 +836,8 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
ctx->shader->output[i].interpolate =
d->Interp.Interpolate;
ctx->shader->output[i].write_mask =
d->Declaration.UsageMask;
if (ctx->type == TGSI_PROCESSOR_VERTEX ||
- ctx->type == TGSI_PROCESSOR_GEOMETRY) {
+ ctx->type == TGSI_PROCESSOR_GEOMETRY ||
+ ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
ctx->shader->output[i].spi_sid =
r600_spi_sid(&ctx->shader->output[i]);
switch (d->Semantic.Name) {
case TGSI_SEMANTIC_CLIPDIST:
@@ -3202,10 +3203,15 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
}
/* Add stream outputs. */
- if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
- so.num_outputs && !use_llvm)
- emit_streamout(&ctx, &so, -1, NULL);
-
+ if (!use_llvm && so.num_outputs) {
+ bool emit = false;
+ if (!lds_outputs && !ring_outputs && ctx.type ==
TGSI_PROCESSOR_VERTEX)
+ emit = true;
+ if (!ring_outputs && ctx.type == TGSI_PROCESSOR_TESS_EVAL)
+ emit = true;
+ if (emit)
+ emit_streamout(&ctx, &so, -1, NULL);
+ }
pipeshader->enabled_stream_buffers_mask =
ctx.enabled_stream_buffers_mask;
convert_edgeflag_to_int(&ctx);
@@ -3243,6 +3249,7 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
output[j].op = CF_OP_EXPORT;
switch (ctx.type) {
case TGSI_PROCESSOR_VERTEX:
+ case TGSI_PROCESSOR_TESS_EVAL:
switch (shader->output[i].name) {
case TGSI_SEMANTIC_POSITION:
output[j].array_base = 60;
@@ -3386,6 +3393,8 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
goto out_err;
}
break;
+ case TGSI_PROCESSOR_TESS_CTRL:
+ break;
default:
R600_ERR("unsupported processor type %d\n",
ctx.type);
r = -EINVAL;
@@ -3399,7 +3408,7 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
}
/* add fake position export */
- if (ctx.type == TGSI_PROCESSOR_VERTEX && pos_emitted == false) {
+ if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type ==
TGSI_PROCESSOR_TESS_EVAL) && pos_emitted == false) {
memset(&output[j], 0, sizeof(struct
r600_bytecode_output));
output[j].gpr = 0;
output[j].elem_size = 3;
@@ -3415,7 +3424,7 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
}
/* add fake param output for vertex shader if no param is
exported */
- if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
+ if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type ==
TGSI_PROCESSOR_TESS_EVAL) && next_param_base == 0) {
memset(&output[j], 0, sizeof(struct
r600_bytecode_output));
output[j].gpr = 0;
output[j].elem_size = 3;
--
2.5.0
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[Mesa-dev] [PATCH 17/53] r600: update correct hw shaders depending on configuration.
From: Dave Airlie
This updates the tess hw shaders from the sw ones routing
things correctly.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 52bff96..d13d2d7 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -209,6 +209,15 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
/* Build state. */
switch (shader->shader.processor_type) {
+ case TGSI_PROCESSOR_TESS_CTRL:
+ evergreen_update_hs_state(ctx, shader);
+ break;
+ case TGSI_PROCESSOR_TESS_EVAL:
+ if (key.tes.as_es)
+ evergreen_update_es_state(ctx, shader);
+ else
+ evergreen_update_vs_state(ctx, shader);
+ break;
case TGSI_PROCESSOR_GEOMETRY:
if (rctx->b.chip_class >= EVERGREEN) {
evergreen_update_gs_state(ctx, shader);
@@ -221,7 +230,9 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
case TGSI_PROCESSOR_VERTEX:
export_shader = key.vs.as_es;
if (rctx->b.chip_class >= EVERGREEN) {
- if (export_shader)
+ if (key.vs.as_ls)
+ evergreen_update_ls_state(ctx, shader);
+ else if (key.vs.as_es)
evergreen_update_es_state(ctx, shader);
else
evergreen_update_vs_state(ctx, shader);
--
2.5.0
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[Mesa-dev] [PATCH 16/53] r600: add shader key entries for tcs and tes.
From: Dave Airlie
with tessellation vs can now run on ls, and tes can
run on vs or es, tcs runs on hs.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_hw_context.c | 4
src/gallium/drivers/r600/r600_pipe.h | 4
src/gallium/drivers/r600/r600_shader.c | 13 +++--
src/gallium/drivers/r600/r600_shader.h | 20
src/gallium/drivers/r600/r600_state_common.c | 11 ++-
5 files changed, 49 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index 13b6918..b7845b5 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -321,6 +321,10 @@ void r600_begin_new_cs(struct r600_context *ctx)
r600_mark_atom_dirty(ctx,
&ctx->hw_shader_stages[R600_HW_STAGE_GS].atom);
r600_mark_atom_dirty(ctx, &ctx->gs_rings.atom);
}
+ if (ctx->tes_shader) {
+ r600_mark_atom_dirty(ctx,
&ctx->hw_shader_stages[EG_HW_STAGE_HS].atom);
+ r600_mark_atom_dirty(ctx,
&ctx->hw_shader_stages[EG_HW_STAGE_LS].atom);
+ }
r600_mark_atom_dirty(ctx,
&ctx->hw_shader_stages[R600_HW_STAGE_VS].atom);
r600_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
r600_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index f351996..3dc1118 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -500,6 +500,10 @@ struct r600_context {
struct r600_pipe_shader_selector *ps_shader;
struct r600_pipe_shader_selector *vs_shader;
struct r600_pipe_shader_selector *gs_shader;
+
+ struct r600_pipe_shader_selector *tcs_shader;
+ struct r600_pipe_shader_selector *tes_shader;
+
struct r600_rasterizer_state*rasterizer;
boolalpha_to_one;
boolforce_blend_disable;
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 6233753..52bff96 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1918,12 +1918,21 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
case TGSI_PROCESSOR_VERTEX:
shader->vs_as_gs_a = key.vs.as_gs_a;
shader->vs_as_es = key.vs.as_es;
+ shader->vs_as_ls = key.vs.as_ls;
if (shader->vs_as_es)
ring_outputs = true;
break;
case TGSI_PROCESSOR_GEOMETRY:
ring_outputs = true;
break;
+ case TGSI_PROCESSOR_TESS_CTRL:
+ shader->tcs_prim_mode = key.tcs.prim_mode;
+ break;
+ case TGSI_PROCESSOR_TESS_EVAL:
+ shader->tes_as_es = key.tes.as_es;
+ if (shader->tes_as_es)
+ ring_outputs = true;
+ break;
case TGSI_PROCESSOR_FRAGMENT:
shader->two_side = key.ps.color_two_side;
break;
@@ -1931,7 +1940,7 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
break;
}
- if (shader->vs_as_es) {
+ if (shader->vs_as_es || shader->tes_as_es) {
ctx.gs_for_vs = &rctx->gs_shader->current->shader;
} else {
ctx.gs_for_vs = NULL;
@@ -2337,7 +2346,7 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
convert_edgeflag_to_int(&ctx);
if (ring_outputs) {
- if (shader->vs_as_es) {
+ if (shader->vs_as_es || shader->tes_as_es) {
ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
ctx.gs_export_gpr_tregs[1] = -1;
ctx.gs_export_gpr_tregs[2] = -1;
diff --git a/src/gallium/drivers/r600/r600_shader.h
b/src/gallium/drivers/r600/r600_shader.h
index 2040f73..398e7da 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -30,6 +30,16 @@
extern "C" {
#endif
+/* Valid shader configurations:
+ *
+ * API shaders VS | TCS | TES | GS |pass| PS
+ * are compiled as: | | ||thru|
+ * | | |||
+ * Only VS & PS: VS | -- | -- | -- | -- | PS
+ * With GS: ES | -- | -- | GS | VS | PS
+ * With Tessel.: LS | HS | VS | -- | -- | PS
+ * With both:LS | HS | ES | GS | VS | PS
+ */
struct r600_shader_io {
unsignedname;
@@ -86,7 +96,10 @@ struct r600_shader {
unsignedmax_arrays;
unsignednum_arrays;
unsignedvs_as_es;
+ unsignedvs_as_ls;
unsignedvs_as_gs_a;
+ unsignedtes_as_es;
+
[Mesa-dev] [PATCH 34/53] r600/eg: workaround bug with tess shader and dynamic GPRs.
From: Dave Airlie
When using tessellation on eg/ni chipsets, we must disable
dynamic GPRs to workaround a hw bug where the GPU hangs
when too many things get queued.
This implements something like the r600 code to emit
the transition between static and dynamic GPRs, and to
statically allocate GPRs when tessellation is enabled.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_compute.c | 6 +-
src/gallium/drivers/r600/evergreen_state.c | 222 ---
src/gallium/drivers/r600/r600_hw_context.c | 2 +-
src/gallium/drivers/r600/r600_pipe.h | 8 +-
src/gallium/drivers/r600/r600_state_common.c | 7 +
5 files changed, 185 insertions(+), 60 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 010d109..c07cee1 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -432,6 +432,10 @@ static void compute_emit_cs(struct r600_context *ctx,
const uint *block_layout,
*/
r600_emit_command_buffer(cs, &ctx->start_compute_cs_cmd);
+ /* emit config state */
+ if (ctx->b.chip_class == EVERGREEN)
+ r600_emit_atom(ctx, &ctx->config_state.atom);
+
ctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
r600_flush_emit(ctx);
@@ -791,7 +795,7 @@ void evergreen_init_atom_start_compute_cs(struct
r600_context *ctx)
/* Config Registers */
if (ctx->b.chip_class < CAYMAN)
- evergreen_init_common_regs(cb, ctx->b.chip_class, ctx->b.family,
+ evergreen_init_common_regs(ctx, cb, ctx->b.chip_class,
ctx->b.family,
ctx->screen->b.info.drm_minor);
else
cayman_init_common_regs(cb, ctx->b.chip_class, ctx->b.family,
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index edc6f28..b3109c7 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -869,6 +869,33 @@ evergreen_create_sampler_view(struct pipe_context *ctx,
tex->width0, tex->height0,
0);
}
+static void evergreen_emit_config_state(struct r600_context *rctx, struct
r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
+ struct r600_config_state *a = (struct r600_config_state*)atom;
+
+ radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
+ if (a->dyn_gpr_enabled) {
+ radeon_emit(cs,
S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
+ radeon_emit(cs, 0);
+ radeon_emit(cs, 0);
+ } else {
+ radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
+ radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
+ radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
+ }
+ radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ,
(a->dyn_gpr_enabled << 8));
+ if (a->dyn_gpr_enabled) {
+ radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
+ S_028838_PS_GPRS(0x1e) |
+ S_028838_VS_GPRS(0x1e) |
+ S_028838_GS_GPRS(0x1e) |
+ S_028838_ES_GPRS(0x1e) |
+ S_028838_HS_GPRS(0x1e) |
+ S_028838_LS_GPRS(0x1e)); /* workaround
for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e ==
240 / 8*/
+ }
+}
+
static void evergreen_emit_clip_state(struct r600_context *rctx, struct
r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
@@ -2553,10 +2580,10 @@ static void cayman_init_atom_start_cs(struct
r600_context *rctx)
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4),
0x01000FFF);
}
-void evergreen_init_common_regs(struct r600_command_buffer *cb,
- enum chip_class ctx_chip_class,
- enum radeon_family ctx_family,
- int ctx_drm_minor)
+void evergreen_init_common_regs(struct r600_context *rctx, struct
r600_command_buffer *cb,
+ enum chip_class ctx_chip_class,
+ enum radeon_family ctx_family,
+ int ctx_drm_minor)
{
int ps_prio;
int vs_prio;
@@ -2567,31 +2594,23 @@ void evergreen_init_common_regs(struct
r600_command_buffer *cb,
int cs_prio;
int ls_prio;
- int num_ps_gprs;
- int num_vs_gprs;
- int num_gs_gprs;
- int num_es_gprs;
- int num_hs_gprs;
- int num_ls_gprs;
- int num_temp_gprs;
-
unsigned tmp;
ps_prio = 0;
vs_prio = 1;
gs_prio = 2;
es_prio = 3;
- hs_prio = 0;
- ls_prio = 0;
+ hs_p
[Mesa-dev] [PATCH 28/53] r600: hook TES/TCS shaders to the selection logic.
From: Dave Airlie
This hooks the TES/TCS bindings to the HW stages up.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state_common.c | 34 ++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index eab36d3..73e9494 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1411,6 +1411,7 @@ static bool r600_update_derived_state(struct r600_context
*rctx)
{
struct pipe_context * ctx = (struct pipe_context*)rctx;
bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
+ bool tcs_dirty = false, tes_dirty = false;
bool blend_disable;
bool need_buf_const;
struct r600_pipe_shader *clip_so_current = NULL;
@@ -1432,11 +1433,25 @@ static bool r600_update_derived_state(struct
r600_context *rctx)
SELECT_SHADER_OR_FAIL(ps);
+ r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
+
update_gs_block_state(rctx, rctx->gs_shader != NULL);
if (rctx->gs_shader)
SELECT_SHADER_OR_FAIL(gs);
+ /* Hull Shader */
+ if (rctx->tcs_shader) {
+ SELECT_SHADER_OR_FAIL(tcs);
+
+ UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
+ } else
+ SET_NULL_SHADER(EG_HW_STAGE_HS);
+
+ if (rctx->tes_shader) {
+ SELECT_SHADER_OR_FAIL(tes);
+ }
+
SELECT_SHADER_OR_FAIL(vs);
if (rctx->gs_shader) {
@@ -1449,8 +1464,16 @@ static bool r600_update_derived_state(struct
r600_context *rctx)
UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
/* vs_shader is used as ES */
- UPDATE_SHADER(R600_HW_STAGE_ES, vs);
+ if (rctx->tes_shader) {
+ /* VS goes to LS, TES goes to ES */
+ UPDATE_SHADER(R600_HW_STAGE_ES, tes);
+ UPDATE_SHADER(EG_HW_STAGE_LS, vs);
+ } else {
+ /* vs_shader is used as ES */
+ UPDATE_SHADER(R600_HW_STAGE_ES, vs);
+ SET_NULL_SHADER(EG_HW_STAGE_LS);
+ }
} else {
if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
SET_NULL_SHADER(R600_HW_STAGE_GS);
@@ -1459,7 +1482,14 @@ static bool r600_update_derived_state(struct
r600_context *rctx)
r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
}
- UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
+ if (rctx->tes_shader) {
+ /* if TES is loaded and no geometry, TES runs on hw VS,
VS runs on hw LS */
+ UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
+ UPDATE_SHADER(EG_HW_STAGE_LS, vs);
+ } else {
+ SET_NULL_SHADER(EG_HW_STAGE_LS);
+ UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
+ }
}
/* Update clip misc state. */
--
2.5.0
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[Mesa-dev] [PATCH 36/53] r600/shader: add function to get tess constants info
From: Dave Airlie
This function retrieves the tess input/output info
from the tess constant buffer that is bound to the shader.
This uses a vfetch to get the values into the shader.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 91 +-
1 file changed, 90 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index e335d29..950bbf9 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -330,6 +330,8 @@ struct r600_shader_ctx {
int gs_export_gpr_tregs[4];
const struct pipe_stream_output_info*gs_stream_output_info;
unsignedenabled_stream_buffers_mask;
+ unsignedtess_input_info; /* temp with
tess input offsets */
+ unsignedtess_output_info; /* temp with
tess input offsets */
};
struct r600_shader_tgsi_instruction {
@@ -1994,6 +1996,78 @@ static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx, const struct pipe_st
return 0;
}
+
+static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
+{
+ int r;
+ struct r600_bytecode_vtx vtx;
+ int temp_val = ctx->temp_reg;
+ /* need to store the TCS output somewhere */
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ temp_val, 0,
+ V_SQ_ALU_SRC_LITERAL, 0,
+ 0, 0);
+ if (r)
+ return r;
+
+ /* used by VS/TCS */
+ if (ctx->tess_input_info) {
+ /* fetch tcs input values into resv space */
+ memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
+ vtx.op = FETCH_OP_VFETCH;
+ vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
+ vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
+ vtx.mega_fetch_count = 16;
+ vtx.data_format = FMT_32_32_32_32;
+ vtx.num_format_all = 2;
+ vtx.format_comp_all = 1;
+ vtx.use_const_fields = 0;
+ vtx.endian = r600_endian_swap(32);
+ vtx.srf_mode_all = 1;
+ vtx.offset = 0;
+ vtx.dst_gpr = ctx->tess_input_info;
+ vtx.dst_sel_x = 0;
+ vtx.dst_sel_y = 1;
+ vtx.dst_sel_z = 2;
+ vtx.dst_sel_w = 3;
+ vtx.src_gpr = temp_val;
+ vtx.src_sel_x = 0;
+
+ r = r600_bytecode_add_vtx(ctx->bc, &vtx);
+ if (r)
+ return r;
+ }
+
+ /* used by TCS/TES */
+ if (ctx->tess_output_info) {
+ /* fetch tcs output values into resv space */
+ memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
+ vtx.op = FETCH_OP_VFETCH;
+ vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
+ vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
+ vtx.mega_fetch_count = 16;
+ vtx.data_format = FMT_32_32_32_32;
+ vtx.num_format_all = 2;
+ vtx.format_comp_all = 1;
+ vtx.use_const_fields = 0;
+ vtx.endian = r600_endian_swap(32);
+ vtx.srf_mode_all = 1;
+ vtx.offset = 16;
+ vtx.dst_gpr = ctx->tess_output_info;
+ vtx.dst_sel_x = 0;
+ vtx.dst_sel_y = 1;
+ vtx.dst_sel_z = 2;
+ vtx.dst_sel_w = 3;
+ vtx.src_gpr = temp_val;
+ vtx.src_sel_x = 0;
+
+ r = r600_bytecode_add_vtx(ctx->bc, &vtx);
+ if (r)
+ return r;
+ }
+ return 0;
+}
+
static int r600_shader_from_tgsi(struct r600_context *rctx,
struct r600_pipe_shader *pipeshader,
union r600_shader_key key)
@@ -2157,7 +2231,15 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
- if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
+ if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) {
+ ctx.tess_input_info = ctx.bc->ar_reg + 3;
+ ctx.tess_output_info = ctx.bc->ar_reg + 4;
+ ctx.temp_reg = ctx.bc->ar_reg + 5;
+ } else if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) {
+ ctx.tess_input_info = 0;
+ ctx.tess_output_info = ctx.bc->ar_reg + 3;
+ ctx.temp_reg = ctx.bc->ar_reg + 4;
+ } else if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
@@ -2195,6 +2277,9 @@ static int r600_shader
[Mesa-dev] [PATCH 41/53] r600/shader: emit tessellation factors to GDS at end of TCS.
From: Dave Airlie
When we are finished the shader, we read back all the tess factors
from LDS and write them to special global memory storage using
GDS instructions.
This also handles adding NOP when GDS or ENDLOOP end the TCS.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 173 -
1 file changed, 172 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index f199055..b306c6e 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2534,6 +2534,174 @@ static int r600_store_tcs_output(struct r600_shader_ctx
*ctx)
return 0;
}
+static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
+int output_idx)
+{
+ int param;
+ unsigned temp_reg = r600_get_temp(ctx);
+ unsigned name = ctx->shader->output[output_idx].name;
+ int dreg = ctx->shader->output[output_idx].gpr;
+ int r;
+
+ param = r600_get_lds_unique_index(name, 0);
+ r = get_lds_offset0(ctx, 1, temp_reg, true);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, 0,
+ temp_reg, 0,
+ V_SQ_ALU_SRC_LITERAL, param * 16);
+ if (r)
+ return r;
+
+ do_lds_fetch_values(ctx, temp_reg, dreg);
+ return 0;
+}
+
+static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
+{
+ int i;
+ int stride, outer_comps, inner_comps;
+ int tessinner_idx = -1, tessouter_idx = -1;
+ int r;
+ int temp_reg = r600_get_temp(ctx);
+ int treg[3] = {-1, -1, -1};
+ struct r600_bytecode_alu alu;
+ struct r600_bytecode_cf *cf_jump, *cf_pop;
+
+ /* only execute factor emission for invocation 0 */
+ /* PRED_SETE_INT __, R0.x, 0 */
+ memset(&alu, 0, sizeof(alu));
+ alu.op = ALU_OP2_PRED_SETE_INT;
+ alu.src[0].chan = 2;
+ alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+ alu.execute_mask = 1;
+ alu.update_pred = 1;
+ alu.last = 1;
+ r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
+
+ r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
+ cf_jump = ctx->bc->cf_last;
+
+ treg[0] = r600_get_temp(ctx);
+ switch (ctx->shader->tcs_prim_mode) {
+ case PIPE_PRIM_LINES:
+ stride = 8; /* 2 dwords, 1 vec2 store */
+ outer_comps = 2;
+ inner_comps = 0;
+ break;
+ case PIPE_PRIM_TRIANGLES:
+ stride = 16; /* 4 dwords, 1 vec4 store */
+ outer_comps = 3;
+ inner_comps = 1;
+ treg[1] = r600_get_temp(ctx);
+ break;
+ case PIPE_PRIM_QUADS:
+ stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
+ outer_comps = 4;
+ inner_comps = 2;
+ treg[1] = r600_get_temp(ctx);
+ treg[2] = r600_get_temp(ctx);
+ break;
+ default:
+ assert(0);
+ return -1;
+ }
+
+ /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
+ /* TF_WRITE takes index in R.x, value in R.y */
+ for (i = 0; i < ctx->shader->noutput; i++) {
+ if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
+ tessinner_idx = i;
+ if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
+ tessouter_idx = i;
+ }
+
+ if (tessouter_idx == -1)
+ return -1;
+
+ if (tessinner_idx == -1 && inner_comps)
+ return -1;
+
+ if (tessouter_idx != -1) {
+ r = r600_tess_factor_read(ctx, tessouter_idx);
+ if (r)
+ return r;
+ }
+
+ if (tessinner_idx != -1) {
+ r = r600_tess_factor_read(ctx, tessinner_idx);
+ if (r)
+ return r;
+ }
+
+ /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
+ /* r.x = relpatchid(r0.y) * tf_stride */
+
+ /* multiply incoming r0.y * stride - t.x = r0.y * stride */
+ r = single_alu_op2(ctx, ALU_OP2_MULLO_INT,
+ temp_reg, 0,
+ 0, 1,
+ V_SQ_ALU_SRC_LITERAL, stride);
+ if (r)
+ return r;
+
+ /* add incoming r0.w to it: t.x = t.x + r0.w */
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, 0,
+ temp_reg, 0,
+ 0, 3);
+ if (r)
+ return r;
+
+ for (i = 0; i < outer_comps + inner_comps; i++) {
+ int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
+ int out_comp = i >= outer_comps ? i - outer_comps : i;
+
+
[Mesa-dev] [PATCH 39/53] r600/shader: handle VS shader writing to the LDS outputs.
From: Dave Airlie
This writes the VS shaders outputs to the LDS memory in
the correct places.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 76 +-
1 file changed, 75 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 69675b2..ee83114 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2385,6 +2385,71 @@ static int r600_fetch_tess_io_info(struct
r600_shader_ctx *ctx)
return 0;
}
+static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
+{
+ int i, j, r;
+ int temp_reg;
+
+ /* fetch tcs input values into input_vals */
+ ctx->tess_input_info = r600_get_temp(ctx);
+ ctx->tess_output_info = 0;
+ r = r600_fetch_tess_io_info(ctx);
+ if (r)
+ return r;
+
+ temp_reg = r600_get_temp(ctx);
+ /* dst reg contains LDS address stride * idx */
+ /* MUL vertexID, vertex_dw_stride */
+ r = single_alu_op2(ctx, ALU_OP2_MULLO_INT,
+ temp_reg, 0,
+ ctx->tess_input_info, 1,
+ 0, 1); /* rel id in r0.y? */
+ if (r)
+ return r;
+
+ for (i = 0; i < ctx->shader->noutput; i++) {
+ struct r600_bytecode_alu alu;
+ int param =
r600_get_lds_unique_index(ctx->shader->output[i].name,
ctx->shader->output[i].sid);
+
+ if (param) {
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, 1,
+ temp_reg, 0,
+ V_SQ_ALU_SRC_LITERAL, param * 16);
+ if (r)
+ return r;
+ }
+
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, 2,
+ temp_reg, param ? 1 : 0,
+ V_SQ_ALU_SRC_LITERAL, 8);
+ if (r)
+ return r;
+
+
+ for (j = 0; j < 2; j++) {
+ int chan = (j == 1) ? 2 : (param ? 1 : 0);
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = LDS_OP3_LDS_WRITE_REL;
+ alu.src[0].sel = temp_reg;
+ alu.src[0].chan = chan;
+ alu.src[1].sel = ctx->shader->output[i].gpr;
+ alu.src[1].chan = j * 2;
+ alu.src[2].sel = ctx->shader->output[i].gpr;
+ alu.src[2].chan = (j * 2) + 1;
+ alu.last = 1;
+ alu.dst.chan = 0;
+ alu.lds_idx = 1;
+ alu.is_lds_idx_op = true;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+ return 0;
+}
+
static int r600_shader_from_tgsi(struct r600_context *rctx,
struct r600_pipe_shader *pipeshader,
union r600_shader_key key)
@@ -2405,6 +2470,7 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
bool use_llvm = false;
bool indirect_gprs;
bool ring_outputs = false;
+ bool lds_outputs = false;
bool lds_inputs = false;
bool pos_emitted = false;
@@ -2437,12 +2503,15 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
shader->vs_as_ls = key.vs.as_ls;
if (shader->vs_as_es)
ring_outputs = true;
+ if (shader->vs_as_ls)
+ lds_outputs = true;
break;
case TGSI_PROCESSOR_GEOMETRY:
ring_outputs = true;
break;
case TGSI_PROCESSOR_TESS_CTRL:
shader->tcs_prim_mode = key.tcs.prim_mode;
+ lds_outputs = true;
lds_inputs = true;
break;
case TGSI_PROCESSOR_TESS_EVAL:
@@ -2882,7 +2951,12 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
pipeshader->enabled_stream_buffers_mask =
ctx.enabled_stream_buffers_mask;
convert_edgeflag_to_int(&ctx);
- if (ring_outputs) {
+ if (lds_outputs) {
+ if (ctx.type == TGSI_PROCESSOR_VERTEX) {
+ if (ctx.shader->noutput)
+ emit_lds_vs_writes(&ctx);
+ }
+ } else if (ring_outputs) {
if (shader->vs_as_es || shader->tes_as_es) {
ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
ctx.gs_export_gpr_tregs[1] = -1;
--
2.5.0
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[Mesa-dev] [PATCH 38/53] r600/shader: handle fetching tcs/tes inputs and tcs outputs
From: Dave Airlie
This handles the logic for doing fetches from LDS for
TCS and TES. For TCS we need to fetch both inputs and outputs,
for TES only inputs need to be fetched.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 298 -
1 file changed, 297 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index a5fb80d..69675b2 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1386,6 +1386,295 @@ static int tgsi_split_gs_inputs(struct r600_shader_ctx
*ctx)
return 0;
}
+
+/* Tessellation shaders pass outputs to the next shader using LDS.
+ *
+ * LS outputs = TCS(HS) inputs
+ * TCS(HS) outputs = TES(DS) inputs
+ *
+ * The LDS layout is:
+ * - TCS inputs for patch 0
+ * - TCS inputs for patch 1
+ * - TCS inputs for patch 2= get_tcs_in_current_patch_offset (if
RelPatchID==2)
+ * - ...
+ * - TCS outputs for patch 0= get_tcs_out_patch0_offset
+ * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
+ * - TCS outputs for patch 1
+ * - Per-patch TCS outputs for patch 1
+ * - TCS outputs for patch 2= get_tcs_out_current_patch_offset (if
RelPatchID==2)
+ * - Per-patch TCS outputs for patch 2 =
get_tcs_out_current_patch_data_offset (if RelPatchID==2)
+ * - ...
+ *
+ * All three shaders VS(LS), TCS, TES share the same LDS space.
+ */
+/* this will return with the dw address in temp_reg.x */
+static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
+const struct tgsi_full_dst_register *dst,
+const struct tgsi_full_src_register *src,
+int stride_bytes_reg, int stride_bytes_chan)
+{
+ struct tgsi_full_dst_register reg;
+ ubyte *name, *index, *array_first;
+ int r;
+ int param;
+ struct tgsi_shader_info *info = &ctx->info;
+ /* Set the register description. The address computation is the same
+* for sources and destinations. */
+ if (src) {
+ reg.Register.File = src->Register.File;
+ reg.Register.Index = src->Register.Index;
+ reg.Register.Indirect = src->Register.Indirect;
+ reg.Register.Dimension = src->Register.Dimension;
+ reg.Indirect = src->Indirect;
+ reg.Dimension = src->Dimension;
+ reg.DimIndirect = src->DimIndirect;
+ } else
+ reg = *dst;
+
+ /* If the register is 2-dimensional (e.g. an array of vertices
+* in a primitive), calculate the base address of the vertex. */
+ if (reg.Register.Dimension) {
+ int sel, chan;
+ if (reg.Dimension.Indirect) {
+ unsigned addr_reg;
+ assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
+
+ addr_reg = get_address_file_reg(ctx,
reg.DimIndirect.Index);
+ /* pull the value from index_reg */
+ sel = addr_reg;
+ chan = 0;
+ } else {
+ sel = V_SQ_ALU_SRC_LITERAL;
+ chan = reg.Dimension.Index;
+ }
+ r = single_alu_op2(ctx, ALU_OP2_MULLO_INT,
+ temp_reg, 1,
+ stride_bytes_reg, stride_bytes_chan,
+ sel, chan);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, 0,
+ temp_reg, 0,
+ temp_reg, 1);
+ if (r)
+ return r;
+ }
+
+ if (reg.Register.File == TGSI_FILE_INPUT) {
+ name = info->input_semantic_name;
+ index = info->input_semantic_index;
+ array_first = info->input_array_first;
+ } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
+ name = info->output_semantic_name;
+ index = info->output_semantic_index;
+ array_first = info->output_array_first;
+ } else {
+ assert(0);
+ return -1;
+ }
+ if (reg.Register.Indirect) {
+ int addr_reg;
+ int first;
+ /* Add the relative address of the element. */
+ if (reg.Indirect.ArrayID)
+ first = array_first[reg.Indirect.ArrayID];
+ else
+ first = reg.Register.Index;
+
+ addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
+ /* pull the value from index_reg */
+ r = single_alu_op2(ctx, ALU_OP2_MULLO_INT,
+ temp_reg, 1,
+
[Mesa-dev] [PATCH 20/53] r600/sb: add LS/HS hw shader types.
From: Dave Airlie
This just adds printing for the hw shader types, and hooks it up.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc.h | 2 ++
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 6 --
src/gallium/drivers/r600/sb/sb_shader.cpp| 4 +++-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc.h
b/src/gallium/drivers/r600/sb/sb_bc.h
index d2e8da0..34e1e58 100644
--- a/src/gallium/drivers/r600/sb/sb_bc.h
+++ b/src/gallium/drivers/r600/sb/sb_bc.h
@@ -174,6 +174,8 @@ enum shader_target
TARGET_GS_COPY,
TARGET_COMPUTE,
TARGET_FETCH,
+ TARGET_HS,
+ TARGET_LS,
TARGET_NUM
};
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index 28ebfa2..65aa801 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
@@ -58,10 +58,12 @@ int bc_parser::decode() {
switch (bc->type) {
case TGSI_PROCESSOR_FRAGMENT: t = TARGET_PS; break;
case TGSI_PROCESSOR_VERTEX:
- t = pshader->vs_as_es ? TARGET_ES : TARGET_VS;
+ t = pshader->vs_as_ls ? TARGET_LS : (pshader->vs_as_es
? TARGET_ES : TARGET_VS);
break;
case TGSI_PROCESSOR_GEOMETRY: t = TARGET_GS; break;
case TGSI_PROCESSOR_COMPUTE: t = TARGET_COMPUTE; break;
+ case TGSI_PROCESSOR_TESS_CTRL: t = TARGET_HS; break;
+ case TGSI_PROCESSOR_TESS_EVAL: t = pshader->tes_as_es ?
TARGET_ES : TARGET_VS; break;
default: assert(!"unknown shader target"); return -1; break;
}
} else {
@@ -146,7 +148,7 @@ int bc_parser::parse_decls() {
}
}
- if (sh->target == TARGET_VS || sh->target == TARGET_ES)
+ if (sh->target == TARGET_VS || sh->target == TARGET_ES || sh->target ==
TARGET_HS)
sh->add_input(0, 1, 0x0F);
else if (sh->target == TARGET_GS) {
sh->add_input(0, 1, 0x0F);
diff --git a/src/gallium/drivers/r600/sb/sb_shader.cpp
b/src/gallium/drivers/r600/sb/sb_shader.cpp
index 87e28e9..8c7b39b 100644
--- a/src/gallium/drivers/r600/sb/sb_shader.cpp
+++ b/src/gallium/drivers/r600/sb/sb_shader.cpp
@@ -215,7 +215,7 @@ void shader::init() {
void shader::init_call_fs(cf_node* cf) {
unsigned gpr = 0;
- assert(target == TARGET_VS || target == TARGET_ES);
+ assert(target == TARGET_LS || target == TARGET_VS || target ==
TARGET_ES);
for(inputs_vec::const_iterator I = inputs.begin(),
E = inputs.end(); I != E; ++I, ++gpr) {
@@ -436,6 +436,8 @@ const char* shader::get_shader_target_name() {
case TARGET_ES: return "ES";
case TARGET_PS: return "PS";
case TARGET_GS: return "GS";
+ case TARGET_HS: return "HS";
+ case TARGET_LS: return "LS";
case TARGET_COMPUTE: return "COMPUTE";
case TARGET_FETCH: return "FETCH";
default:
--
2.5.0
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[Mesa-dev] [PATCH 37/53] r600/shader: add get_lds_offset0 helper
From: Dave Airlie
This retrievs the offset into the LDS for a patch or
non-patch variable, it takes the RelPatch channel
and a temporary register.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 28
1 file changed, 28 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 950bbf9..a5fb80d 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -724,6 +724,34 @@ static int single_alu_op2(struct r600_shader_ctx *ctx, int
op,
return 0;
}
+/* put it in temp_reg.x */
+static int get_lds_offset0(struct r600_shader_ctx *ctx,
+ int rel_patch_chan,
+ int temp_reg, bool is_patch_var)
+{
+ int r;
+
+ /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
+ r = single_alu_op2(ctx, ALU_OP2_MULLO_INT,
+ temp_reg, 0,
+ ctx->tess_output_info, 0,
+ 0, rel_patch_chan);
+ if (r)
+ return r;
+
+ /* ADD temp.x, temp.x,
+ Dimension - patch0_offset (input_vals.z),
+ Non-dim - patch0_data_offset (input_vals.w)
+ */
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, 0,
+ temp_reg, 0,
+ ctx->tess_output_info, is_patch_var ? 3 : 2);
+ if (r)
+ return r;
+ return 0;
+}
+
static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
{
return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
--
2.5.0
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[Mesa-dev] [PATCH 43/53] r600/shader: allow multi-dimension arrays for tcs/tes inputs/outputs.
From: Dave Airlie
This just allows multi-dim arrays to be processed.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index d2cc927..cb86601 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -393,10 +393,16 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
case TGSI_FILE_CONSTANT:
break;
case TGSI_FILE_INPUT:
- if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
+ if (ctx->type == TGSI_PROCESSOR_GEOMETRY ||
+ ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
+ ctx->type == TGSI_PROCESSOR_TESS_EVAL)
+ break;
+ case TGSI_FILE_OUTPUT:
+ if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
break;
default:
- R600_ERR("unsupported src %d (dimension %d)\n", j,
+ R600_ERR("unsupported src %d (file %d, dimension
%d)\n", j,
+ i->Src[j].Register.File,
i->Src[j].Register.Dimension);
return -EINVAL;
}
@@ -404,6 +410,8 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
}
for (j = 0; j < i->Instruction.NumDstRegs; j++) {
if (i->Dst[j].Register.Dimension) {
+ if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
+ continue;
R600_ERR("unsupported dst (dimension)\n");
return -EINVAL;
}
--
2.5.0
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[Mesa-dev] [PATCH 40/53] r600/shader: handle TCS output writing.
From: Dave Airlie
TCS outputs whenever they are written in the shader,
need to be written to LDS not temporaries, this handles
this case. It also fixes up the case where the output
is a relative addressed output, so we don't try to apply
the relative address at the wrong time.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 100 -
1 file changed, 98 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index ee83114..f199055 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2450,6 +2450,90 @@ static int emit_lds_vs_writes(struct r600_shader_ctx
*ctx)
return 0;
}
+static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst =
&ctx->parse.FullToken.FullInstruction;
+ const struct tgsi_full_dst_register *dst = &inst->Dst[0];
+ int i, r, lasti;
+ int temp_reg = r600_get_temp(ctx);
+ struct r600_bytecode_alu alu;
+ unsigned write_mask = dst->Register.WriteMask;
+
+ if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
+ return 0;
+
+ r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false :
true);
+ if (r)
+ return r;
+
+ /* the base address is now in temp.x */
+ r = r600_get_byte_address(ctx, temp_reg,
+ &inst->Dst[0], NULL, ctx->tess_output_info,
1);
+ if (r)
+ return r;
+
+ /* LDS write */
+ lasti = tgsi_last_instruction(write_mask);
+ for (i = 1; i <= lasti; i++) {
+
+ if (!(write_mask & (1 << i)))
+ continue;
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, i,
+ temp_reg, 0,
+ V_SQ_ALU_SRC_LITERAL, 4 * i);
+ if (r)
+ return r;
+ }
+
+ for (i = 0; i <= lasti; i++) {
+ if (!(write_mask & (1 << i)))
+ continue;
+
+ if ((i == 0 && ((write_mask & 3) == 3)) ||
+ (i == 2 && ((write_mask & 0xc) == 0xc))) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = LDS_OP3_LDS_WRITE_REL;
+ alu.src[0].sel = temp_reg;
+ alu.src[0].chan = i;
+
+ alu.src[1].sel = dst->Register.Index;
+ alu.src[1].sel += ctx->file_offset[dst->Register.File];
+ alu.src[1].chan = i;
+
+ alu.src[2].sel = dst->Register.Index;
+ alu.src[2].sel += ctx->file_offset[dst->Register.File];
+ alu.src[2].chan = i + 1;
+ alu.lds_idx = 1;
+ alu.dst.chan = 0;
+ alu.last = 1;
+ alu.is_lds_idx_op = true;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ i += 1;
+ continue;
+ }
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = LDS_OP2_LDS_WRITE;
+ alu.src[0].sel = temp_reg;
+ alu.src[0].chan = i;
+
+ alu.src[1].sel = dst->Register.Index;
+ alu.src[1].sel += ctx->file_offset[dst->Register.File];
+ alu.src[1].chan = i;
+
+ alu.src[2].sel = V_SQ_ALU_SRC_0;
+ alu.dst.chan = 0;
+ alu.last = 1;
+ alu.is_lds_idx_op = true;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ return 0;
+}
+
static int r600_shader_from_tgsi(struct r600_context *rctx,
struct r600_pipe_shader *pipeshader,
union r600_shader_key key)
@@ -2881,6 +2965,12 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
r = ctx.inst_info->process(&ctx);
if (r)
goto out_err;
+
+ if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) {
+ r = r600_store_tcs_output(&ctx);
+ if (r)
+ goto out_err;
+ }
break;
default:
break;
@@ -3295,11 +3385,17 @@ static void tgsi_dst(struct r600_shader_ctx *ctx,
r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
r600_dst->chan = swizzle;
[Mesa-dev] [PATCH 21/53] r600: add create/bind/delete shader hooks for tessellation
From: Dave Airlie
This hooks up the gallium API for the tessellation shaders.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state_common.c | 59
1 file changed, 59 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index f245cf3..48ecd7d 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -893,6 +893,18 @@ static void *r600_create_gs_state(struct pipe_context *ctx,
return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
}
+static void *r600_create_tcs_state(struct pipe_context *ctx,
+const struct pipe_shader_state *state)
+{
+ return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
+}
+
+static void *r600_create_tes_state(struct pipe_context *ctx,
+const struct pipe_shader_state *state)
+{
+ return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
+}
+
static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
@@ -925,6 +937,24 @@ static void r600_bind_gs_state(struct pipe_context *ctx,
void *state)
rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
}
+static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
+}
+
+static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
+
+ if (!state)
+ return;
+ rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
+}
+
static void r600_delete_shader_selector(struct pipe_context *ctx,
struct r600_pipe_shader_selector *sel)
{
@@ -978,6 +1008,29 @@ static void r600_delete_gs_state(struct pipe_context
*ctx, void *state)
r600_delete_shader_selector(ctx, sel);
}
+static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_pipe_shader_selector *sel = (struct
r600_pipe_shader_selector *)state;
+
+ if (rctx->tcs_shader == sel) {
+ rctx->tcs_shader = NULL;
+ }
+
+ r600_delete_shader_selector(ctx, sel);
+}
+
+static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_pipe_shader_selector *sel = (struct
r600_pipe_shader_selector *)state;
+
+ if (rctx->tes_shader == sel) {
+ rctx->tes_shader = NULL;
+ }
+
+ r600_delete_shader_selector(ctx, sel);
+}
void r600_constant_buffers_dirty(struct r600_context *rctx, struct
r600_constbuf_state *state)
{
@@ -2656,6 +2709,8 @@ void r600_init_common_state_functions(struct r600_context
*rctx)
rctx->b.b.create_fs_state = r600_create_ps_state;
rctx->b.b.create_vs_state = r600_create_vs_state;
rctx->b.b.create_gs_state = r600_create_gs_state;
+ rctx->b.b.create_tcs_state = r600_create_tcs_state;
+ rctx->b.b.create_tes_state = r600_create_tes_state;
rctx->b.b.create_vertex_elements_state =
r600_create_vertex_fetch_shader;
rctx->b.b.bind_blend_state = r600_bind_blend_state;
rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
@@ -2665,6 +2720,8 @@ void r600_init_common_state_functions(struct r600_context
*rctx)
rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
rctx->b.b.bind_vs_state = r600_bind_vs_state;
rctx->b.b.bind_gs_state = r600_bind_gs_state;
+ rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
+ rctx->b.b.bind_tes_state = r600_bind_tes_state;
rctx->b.b.delete_blend_state = r600_delete_blend_state;
rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
rctx->b.b.delete_fs_state = r600_delete_ps_state;
@@ -2673,6 +2730,8 @@ void r600_init_common_state_functions(struct r600_context
*rctx)
rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
rctx->b.b.delete_vs_state = r600_delete_vs_state;
rctx->b.b.delete_gs_state = r600_delete_gs_state;
+ rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
+ rctx->b.b.delete_tes_state = r600_delete_tes_state;
rctx->b.b.set_blend_color = r600_set_blend_color;
rctx->b.b.set_clip_state = r600_set_clip_state;
rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
--
2.5.0
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[Mesa-dev] [PATCH 33/53] r600/shader: move get_temp and last_instruction helpers up
From: Dave Airlie
These are required for tess to be used earlier.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 36 --
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 8e50cc3..4f204c9 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -354,6 +354,18 @@ static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src,
const struct r600_shader_src *shader_src,
unsigned chan);
+static int tgsi_last_instruction(unsigned writemask)
+{
+ int i, lasti = 0;
+
+ for (i = 0; i < 4; i++) {
+ if (writemask & (1 << i)) {
+ lasti = i;
+ }
+ }
+ return lasti;
+}
+
static int tgsi_is_supported(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
@@ -659,6 +671,11 @@ static inline int get_address_file_reg(struct
r600_shader_ctx *ctx, int index)
return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
}
+static int r600_get_temp(struct r600_shader_ctx *ctx)
+{
+ return ctx->temp_reg + ctx->max_driver_temp_used++;
+}
+
static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
{
int i;
@@ -826,11 +843,6 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
return 0;
}
-static int r600_get_temp(struct r600_shader_ctx *ctx)
-{
- return ctx->temp_reg + ctx->max_driver_temp_used++;
-}
-
static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int
gpr_offset)
{
struct tgsi_parse_context parse;
@@ -2747,20 +2759,6 @@ static void tgsi_dst(struct r600_shader_ctx *ctx,
}
}
-static int tgsi_last_instruction(unsigned writemask)
-{
- int i, lasti = 0;
-
- for (i = 0; i < 4; i++) {
- if (writemask & (1 << i)) {
- lasti = i;
- }
- }
- return lasti;
-}
-
-
-
static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest,
bool swap)
{
struct tgsi_full_instruction *inst =
&ctx->parse.FullToken.FullInstruction;
--
2.5.0
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[Mesa-dev] [PATCH 14/53] r600: add functions to update ls/hs state.
From: Dave Airlie
This just adds the two functions, these will get hooked up
later in the shader code.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_state.c | 25 +
src/gallium/drivers/r600/r600_pipe.h | 2 ++
2 files changed, 27 insertions(+)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index fd4c8b5..7467925 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3186,6 +3186,31 @@ void evergreen_update_vs_state(struct pipe_context *ctx,
struct r600_pipe_shader
S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
}
+void evergreen_update_hs_state(struct pipe_context *ctx, struct
r600_pipe_shader *shader)
+{
+ struct r600_command_buffer *cb = &shader->command_buffer;
+ struct r600_shader *rshader = &shader->shader;
+
+ r600_init_command_buffer(cb, 32);
+ r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
+ S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
+ S_0288BC_STACK_SIZE(rshader->bc.nstack));
+ r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
+ shader->bo->gpu_address >> 8);
+}
+
+void evergreen_update_ls_state(struct pipe_context *ctx, struct
r600_pipe_shader *shader)
+{
+ struct r600_command_buffer *cb = &shader->command_buffer;
+ struct r600_shader *rshader = &shader->shader;
+
+ r600_init_command_buffer(cb, 32);
+ r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
+ S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
+ S_0288D4_STACK_SIZE(rshader->bc.nstack));
+ r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
+ shader->bo->gpu_address >> 8);
+}
void *evergreen_create_resolve_blend(struct r600_context *rctx)
{
struct pipe_blend_state blend;
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 0ca4052..f351996 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -603,6 +603,8 @@ void evergreen_update_ps_state(struct pipe_context *ctx,
struct r600_pipe_shader
void evergreen_update_es_state(struct pipe_context *ctx, struct
r600_pipe_shader *shader);
void evergreen_update_gs_state(struct pipe_context *ctx, struct
r600_pipe_shader *shader);
void evergreen_update_vs_state(struct pipe_context *ctx, struct
r600_pipe_shader *shader);
+void evergreen_update_ls_state(struct pipe_context *ctx, struct
r600_pipe_shader *shader);
+void evergreen_update_hs_state(struct pipe_context *ctx, struct
r600_pipe_shader *shader);
void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
void *evergreen_create_resolve_blend(struct r600_context *rctx);
void *evergreen_create_decompress_blend(struct r600_context *rctx);
--
2.5.0
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[Mesa-dev] [PATCH 32/53] r600: bind geometry shader ring to the correct place
From: Dave Airlie
When tess/gs are enabled, the geom shader ring needs
to bind to the tess eval not the vertex shader.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state_common.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 84d85fb..ab3313f 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1354,13 +1354,20 @@ static void update_gs_block_state(struct r600_context
*rctx, unsigned enable)
if (enable) {
r600_set_constant_buffer(&rctx->b.b,
PIPE_SHADER_GEOMETRY,
R600_GS_RING_CONST_BUFFER,
&rctx->gs_rings.esgs_ring);
- r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
- R600_GS_RING_CONST_BUFFER,
&rctx->gs_rings.gsvs_ring);
+ if (rctx->tes_shader) {
+ r600_set_constant_buffer(&rctx->b.b,
PIPE_SHADER_TESS_EVAL,
+
R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
+ } else {
+ r600_set_constant_buffer(&rctx->b.b,
PIPE_SHADER_VERTEX,
+
R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
+ }
} else {
r600_set_constant_buffer(&rctx->b.b,
PIPE_SHADER_GEOMETRY,
R600_GS_RING_CONST_BUFFER, NULL);
r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
R600_GS_RING_CONST_BUFFER, NULL);
+ r600_set_constant_buffer(&rctx->b.b,
PIPE_SHADER_TESS_EVAL,
+ R600_GS_RING_CONST_BUFFER, NULL);
}
}
}
--
2.5.0
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[Mesa-dev] [PATCH 35/53] r600/shader: add a utility function to do single slot arithmatic
From: Dave Airlie
This utility is to be used to do things like integer adds and
multiplies to be used in calculating the LDS offsets etc.
It handles CAYMAN MULLO differences as well.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 56 ++
1 file changed, 56 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 4f204c9..e335d29 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -666,6 +666,62 @@ static int select_twoside_color(struct r600_shader_ctx
*ctx, int front, int back
return 0;
}
+/* execute a single slot ALU calculation */
+static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
+ int dst_sel, int dst_chan,
+ int src0_sel, unsigned src0_chan_val,
+ int src1_sel, unsigned src1_chan_val)
+{
+ struct r600_bytecode_alu alu;
+ int r, i;
+
+ if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
+ for (i = 0; i < 4; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = op;
+ alu.src[0].sel = src0_sel;
+ if (src0_sel == V_SQ_ALU_SRC_LITERAL)
+ alu.src[0].value = src0_chan_val;
+ else
+ alu.src[0].chan = src0_chan_val;
+ alu.src[1].sel = src1_sel;
+ if (src1_sel == V_SQ_ALU_SRC_LITERAL)
+ alu.src[1].value = src1_chan_val;
+ else
+ alu.src[1].chan = src1_chan_val;
+ alu.dst.sel = dst_sel;
+ alu.dst.chan = i;
+ alu.dst.write = i == dst_chan;
+ alu.last = (i == 3);
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ return 0;
+ }
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = op;
+ alu.src[0].sel = src0_sel;
+ if (src0_sel == V_SQ_ALU_SRC_LITERAL)
+ alu.src[0].value = src0_chan_val;
+ else
+ alu.src[0].chan = src0_chan_val;
+ alu.src[1].sel = src1_sel;
+ if (src1_sel == V_SQ_ALU_SRC_LITERAL)
+ alu.src[1].value = src1_chan_val;
+ else
+ alu.src[1].chan = src1_chan_val;
+ alu.dst.sel = dst_sel;
+ alu.dst.chan = dst_chan;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ return 0;
+}
+
static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
{
return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
--
2.5.0
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[Mesa-dev] [PATCH 30/53] r600: create LDS info constants buffer and write LDS registers.
From: Dave Airlie
This creates a constant buffer with the information about
the layout of the LDS memory that is given to the vertex, tess
control and tess evaluation shaders.
This also programs the LDS size and the LS_HS_CONFIG registers,
on evergreen only.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_state.c | 128 +++
src/gallium/drivers/r600/r600_pipe.h | 24 -
src/gallium/drivers/r600/r600_state_common.c | 13 +++
3 files changed, 162 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index c01e8e3..edc6f28 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3763,3 +3763,131 @@ void evergreen_init_state_functions(struct r600_context
*rctx)
evergreen_init_compute_state_functions(rctx);
}
+
+/**
+ * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
+ *
+ * The information about LDS and other non-compile-time parameters is then
+ * written to the const buffer.
+
+ * const buffer contains -
+ * uint32_t input_patch_size
+ * uint32_t input_vertex_size
+ * uint32_t num_tcs_input_cp
+ * uint32_t num_tcs_output_cp;
+ * uint32_t output_patch_size
+ * uint32_t output_vertex_size
+ * uint32_t output_patch0_offset
+ * uint32_t perpatch_output_offset
+ * and the same constbuf is bound to LS/HS/VS(ES).
+ */
+void evergreen_setup_tess_constants(struct r600_context *rctx, const struct
pipe_draw_info *info, unsigned *num_patches, uint32_t *lds_alloc)
+{
+ struct pipe_constant_buffer constbuf = {0};
+ struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ?
rctx->tcs_shader : rctx->tes_shader;
+ struct r600_pipe_shader_selector *ls = rctx->vs_shader;
+ unsigned num_tcs_input_cp = info->vertices_per_patch;
+ unsigned num_tcs_outputs;
+ unsigned num_tcs_output_cp;
+ unsigned num_tcs_patch_outputs;
+ unsigned num_tcs_inputs;
+ unsigned input_vertex_size, output_vertex_size;
+ unsigned input_patch_size, pervertex_output_patch_size,
output_patch_size;
+ unsigned output_patch0_offset, perpatch_output_offset, lds_size;
+ uint32_t values[16];
+ uint32_t tmp;
+
+ if (!rctx->tes_shader)
+ return;
+
+ *num_patches = 1;
+
+ num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
+
+ if (rctx->tcs_shader) {
+ num_tcs_outputs =
util_last_bit64(tcs->lds_outputs_written_mask);
+ num_tcs_output_cp =
tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
+ num_tcs_patch_outputs =
util_last_bit64(tcs->lds_patch_outputs_written_mask);
+ } else {
+ num_tcs_outputs = num_tcs_inputs;
+ num_tcs_output_cp = num_tcs_input_cp;
+ num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
+ }
+
+ /* size in bytes */
+ input_vertex_size = num_tcs_inputs * 16;
+ output_vertex_size = num_tcs_outputs * 16;
+
+ input_patch_size = num_tcs_input_cp * input_vertex_size;
+
+ pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
+ output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs
* 16;
+
+ output_patch0_offset = rctx->tcs_shader ? input_patch_size *
*num_patches : 0;
+ perpatch_output_offset = output_patch0_offset +
pervertex_output_patch_size;
+
+ lds_size = output_patch0_offset + output_patch_size * *num_patches;
+
+ values[0] = input_patch_size;
+ values[1] = input_vertex_size;
+ values[2] = num_tcs_input_cp;
+ values[3] = num_tcs_output_cp;
+
+ values[4] = output_patch_size;
+ values[5] = output_vertex_size;
+ values[6] = output_patch0_offset;
+ values[7] = perpatch_output_offset;
+
+ /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
+ LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
+ tmp = (lds_size | (1 << 14)); /* TODO */
+
+ *lds_alloc = tmp;
+
+ memcpy(&values[8], rctx->tess_state, 6 * sizeof(float));
+ values[14] = 0;
+ values[15] = 0;
+
+ constbuf.user_buffer = values;
+ constbuf.buffer_size = 16 * 4;
+
+ rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
+ R600_LDS_INFO_CONST_BUFFER, &constbuf);
+ rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
+ R600_LDS_INFO_CONST_BUFFER, &constbuf);
+ rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
+ R600_LDS_INFO_CONST_BUFFER, &constbuf);
+ pipe_resource_reference(&constbuf.buffer, NULL);
+}
+
+uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
+ const struct pipe_draw_info *info,
+ unsi
[Mesa-dev] [PATCH 31/53] r600: create fixed function tess control shader fallback.
From: Dave Airlie
If we have no tess control shader, then we have to use a fallback
one that just writes the tessellation factors.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_pipe.c | 3 ++
src/gallium/drivers/r600/r600_pipe.h | 2 ++
src/gallium/drivers/r600/r600_state_common.c | 42 +++-
3 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index bd00dcb..64f5fc6 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -76,6 +76,9 @@ static void r600_destroy_context(struct pipe_context *context)
pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask,
NULL);
pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask,
NULL);
+ if (rctx->fixed_func_tcs_shader)
+ rctx->b.b.delete_tcs_state(&rctx->b.b,
rctx->fixed_func_tcs_shader);
+
if (rctx->dummy_pixel_shader) {
rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
}
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index dfb5f46..78f3a59 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -512,6 +512,8 @@ struct r600_context {
struct r600_pipe_shader_selector *tcs_shader;
struct r600_pipe_shader_selector *tes_shader;
+ struct r600_pipe_shader_selector *fixed_func_tcs_shader;
+
struct r600_rasterizer_state*rasterizer;
boolalpha_to_one;
boolforce_blend_disable;
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index d9152d7..84d85fb 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -35,6 +35,7 @@
#include "util/u_math.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_scan.h"
+#include "tgsi/tgsi_ureg.h"
void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
{
@@ -1376,6 +1377,35 @@ static void r600_update_clip_state(struct r600_context
*rctx,
r600_mark_atom_dirty(rctx,
&rctx->clip_misc_state.atom);
}
}
+
+static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
+{
+ struct ureg_src const0, const1;
+ struct ureg_dst tessouter, tessinner;
+ struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
+
+ if (!ureg)
+ return; /* if we get here, we're screwed */
+
+ assert(!rctx->fixed_func_tcs_shader);
+
+ ureg_DECL_constant2D(ureg, 0, 3, R600_LDS_INFO_CONST_BUFFER);
+ const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 2),
+ R600_LDS_INFO_CONST_BUFFER);
+ const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 3),
+ R600_LDS_INFO_CONST_BUFFER);
+
+ tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
+ tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
+
+ ureg_MOV(ureg, tessouter, const0);
+ ureg_MOV(ureg, tessinner, const1);
+ ureg_END(ureg);
+
+ rctx->fixed_func_tcs_shader =
+ ureg_create_shader_and_destroy(ureg, &rctx->b.b);
+}
+
#define SELECT_SHADER_OR_FAIL(x) do { \
r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
if (unlikely(!rctx->x##_shader))\
@@ -1411,7 +1441,7 @@ static bool r600_update_derived_state(struct r600_context
*rctx)
{
struct pipe_context * ctx = (struct pipe_context*)rctx;
bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
- bool tcs_dirty = false, tes_dirty = false;
+ bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
bool blend_disable;
bool need_buf_const;
struct r600_pipe_shader *clip_so_current = NULL;
@@ -1445,6 +1475,16 @@ static bool r600_update_derived_state(struct
r600_context *rctx)
SELECT_SHADER_OR_FAIL(tcs);
UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
+ } else if (rctx->tes_shader) {
+ if (!rctx->fixed_func_tcs_shader) {
+ r600_generate_fixed_func_tcs(rctx);
+ if (!rctx->fixed_func_tcs_shader)
+ return false;
+
+ }
+ SELECT_SHADER_OR_FAIL(fixed_func_tcs);
+
+ UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
} else
SET_NULL_SHADER(EG_HW_STAGE_HS);
--
2.5.0
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[Mesa-dev] [PATCH 46/53] r600/shader: increase number of inputs/outputs to 64.
From: Dave Airlie
Tessellation exceeds these sometimes, so increase them for now.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.h
b/src/gallium/drivers/r600/r600_shader.h
index f5b1c4b..cfdb020 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -62,8 +62,8 @@ struct r600_shader {
unsignedninput;
unsignednoutput;
unsignednlds;
- struct r600_shader_io input[40];
- struct r600_shader_io output[40];
+ struct r600_shader_io input[64];
+ struct r600_shader_io output[64];
boolean uses_kill;
boolean fs_write_all;
boolean two_side;
--
2.5.0
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[Mesa-dev] [PATCH 29/53] r600/eg: update shader stage emission/tf param for tess.
From: Dave Airlie
This update the setting of the shader stages register
when tess is enabled and add the setting of the VGT_TF_PARAM
register from the tess shader properties.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_state.c | 74 --
1 file changed, 69 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 4d448d1..c01e8e3 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2230,7 +2230,7 @@ static void evergreen_emit_shader_stages(struct
r600_context *rctx, struct r600_
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
struct r600_shader_stages_state *state = (struct
r600_shader_stages_state*)a;
- uint32_t v = 0, v2 = 0, primid = 0;
+ uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
if (rctx->vs_shader->current->shader.vs_as_gs_a) {
v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
@@ -2248,9 +2248,11 @@ static void evergreen_emit_shader_stages(struct
r600_context *rctx, struct r600_
cut_val = V_028A40_GS_CUT_512;
else
cut_val = V_028A40_GS_CUT_1024;
- v = S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
- S_028B54_GS_EN(1) |
- S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
+
+ v = S_028B54_GS_EN(1) |
+ S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
+ if (!rctx->tes_shader)
+ v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
S_028A40_CUT_MODE(cut_val);
@@ -2259,9 +2261,71 @@ static void evergreen_emit_shader_stages(struct
r600_context *rctx, struct r600_
primid = 1;
}
+ if (rctx->tes_shader) {
+ uint32_t type, partitioning, topology;
+ struct tgsi_shader_info *info =
&rctx->tes_shader->current->selector->info;
+ unsigned tes_prim_mode =
info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
+ unsigned tes_spacing =
info->properties[TGSI_PROPERTY_TES_SPACING];
+ bool tes_vertex_order_cw =
info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
+ bool tes_point_mode =
info->properties[TGSI_PROPERTY_TES_POINT_MODE];
+ switch (tes_prim_mode) {
+ case PIPE_PRIM_LINES:
+ type = V_028B6C_TESS_ISOLINE;
+ break;
+ case PIPE_PRIM_TRIANGLES:
+ type = V_028B6C_TESS_TRIANGLE;
+ break;
+ case PIPE_PRIM_QUADS:
+ type = V_028B6C_TESS_QUAD;
+ break;
+ default:
+ assert(0);
+ return;
+ }
+
+ switch (tes_spacing) {
+ case PIPE_TESS_SPACING_FRACTIONAL_ODD:
+ partitioning = V_028B6C_PART_FRAC_ODD;
+ break;
+ case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
+ partitioning = V_028B6C_PART_FRAC_EVEN;
+ break;
+ case PIPE_TESS_SPACING_EQUAL:
+ partitioning = V_028B6C_PART_INTEGER;
+ break;
+ default:
+ assert(0);
+ return;
+ }
+
+ if (tes_point_mode)
+ topology = V_028B6C_OUTPUT_POINT;
+ else if (tes_prim_mode == PIPE_PRIM_LINES)
+ topology = V_028B6C_OUTPUT_LINE;
+ else if (tes_vertex_order_cw)
+ /* XXX follow radeonsi and invert */
+ topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
+ else
+ topology = V_028B6C_OUTPUT_TRIANGLE_CW;
+
+ tf_param = S_028B6C_TYPE(type) |
+ S_028B6C_PARTITIONING(partitioning) |
+ S_028B6C_TOPOLOGY(topology);
+ }
+
+ if (rctx->tes_shader) {
+ v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
+S_028B54_HS_EN(1);
+ if (!state->geom_enable)
+ v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
+ else
+ v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
+ }
+
radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
+ radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
}
static void evergreen_emit_gs_rings(struct r600_context *rctx, struct
r600_atom *a)
@@ -3678,7 +3742,7 @@ void evergreen_init_state_functions(
[Mesa-dev] [PATCH 18/53] r600: disable SB for now on tess related shaders.
From: Dave Airlie
Note we have to disable on vertex shaders when we are
operating in tes mode.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index d13d2d7..b7d21fb 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -161,6 +161,13 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
R600_ERR("translation from TGSI failed !\n");
goto error;
}
+ if (shader->shader.processor_type == TGSI_PROCESSOR_VERTEX) {
+ /* only disable for vertex shaders in tess paths */
+ if (key.vs.as_ls)
+ use_sb = 0;
+ }
+ use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_CTRL);
+ use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_EVAL);
/* disable SB for shaders using doubles */
use_sb &= !shader->shader.uses_doubles;
--
2.5.0
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[Mesa-dev] [PATCH 45/53] r600: handle barrier opcode.
From: Edward O'Callaghan
This handles the barrier opcode for EG/CM.
Signed-off-by: Edward O'Callaghan
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 1701016..1edcec1 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -807,6 +807,22 @@ static int vs_add_primid_output(struct r600_shader_ctx
*ctx, int prim_id_sid)
return 0;
}
+static int tgsi_barrier(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst =
&ctx->parse.FullToken.FullInstruction;
+ struct r600_bytecode_alu alu;
+ int r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ctx->inst_info->op;
+ alu.last = 1;
+
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ return 0;
+}
+
static int tgsi_declaration(struct r600_shader_ctx *ctx)
{
struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
@@ -9242,7 +9258,7 @@ static const struct r600_shader_tgsi_instruction
eg_shader_tgsi_instruction[] =
[TGSI_OPCODE_MFENCE]= { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_LFENCE]= { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_SFENCE]= { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
+ [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
[TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
@@ -9464,7 +9480,7 @@ static const struct r600_shader_tgsi_instruction
cm_shader_tgsi_instruction[] =
[TGSI_OPCODE_MFENCE]= { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_LFENCE]= { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_SFENCE]= { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
+ [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
[TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
--
2.5.0
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[Mesa-dev] [PATCH 44/53] r600/shader: handle tess related system-values.
From: Dave Airlie
This adds handling for TESSINNER/TESSOUTER in the TES
where they need to be fetched from LDS,
and TESSCOORD which comes in via r0.
It also handle primitive ID and invocation ID.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 150 -
1 file changed, 148 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index cb86601..1701016 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -60,12 +60,33 @@ issued in the w slot as well.
The compiler must issue the source argument to slots z, y, and x
*/
+/* Contents of r0 on entry to various shaders
+
+ VS - .x = VertexID
+ .y = RelVertexID (??)
+ .w = InstanceID
+
+ GS - r0.xyw, r1.xyz = per-vertex offsets
+ r0.z = PrimitiveID
+
+ TCS - .x = PatchID
+ .y = RelPatchID (??)
+ .z = InvocationID
+ .w = tess factor base.
+
+ TES - .x = TessCoord.x
+ - .y = TessCoord.y
+ - .z = RelPatchID (??)
+ - .w = PrimitiveID
+
+ PS - face_gpr.z = SampleMask
+ face_gpr.w = SampleID
+*/
#define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
static int r600_shader_from_tgsi(struct r600_context *rctx,
struct r600_pipe_shader *pipeshader,
union r600_shader_key key);
-
static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
int size, unsigned comp_mask) {
@@ -355,6 +376,8 @@ static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
const struct r600_shader_src *shader_src,
unsigned chan);
+static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
+ unsigned dst_reg);
static int tgsi_last_instruction(unsigned writemask)
{
@@ -931,6 +954,73 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
break;
else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
break;
+ else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
+d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
+ int param = r600_get_lds_unique_index(d->Semantic.Name,
0);
+ int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER
? 3 : 2;
+ unsigned temp_reg = r600_get_temp(ctx);
+
+ r = get_lds_offset0(ctx, 2, temp_reg, true);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, 0,
+ temp_reg, 0,
+ V_SQ_ALU_SRC_LITERAL, param * 16);
+ if (r)
+ return r;
+
+ do_lds_fetch_values(ctx, temp_reg, dreg);
+ }
+ else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
+ /* MOV r1.x, r0.x;
+ MOV r1.y, r0.y;
+ */
+ for (i = 0; i < 2; i++) {
+ struct r600_bytecode_alu alu;
+ memset(&alu, 0, sizeof(struct
r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.src[0].sel = 0;
+ alu.src[0].chan = 0 + i;
+ alu.dst.sel = 1;
+ alu.dst.chan = 0 + i;
+ alu.dst.write = 1;
+ alu.last = (i == 1) ? 1 : 0;
+ if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
+ return r;
+ }
+ /* ADD r1.z, 1.0f, -r0.x */
+ struct r600_bytecode_alu alu;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_ADD;
+ alu.src[0].sel = V_SQ_ALU_SRC_1;
+ alu.src[1].sel = 1;
+ alu.src[1].chan = 0;
+ alu.src[1].neg = 1;
+ alu.dst.sel = 1;
+ alu.dst.chan = 2;
+ alu.dst.write = 1;
+ alu.last = 1;
+ if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
+ return r;
+
+ /* ADD r1.z, r1.z, -r1.y */
+ alu.op = ALU_OP2_ADD;
+ alu.src[0].sel = 1;
+ alu.src[0].chan = 2;
+
[Mesa-dev] [PATCH 47/53] r600: handle SIMD allocation issue with HS/LS
From: Dave Airlie At least one SIMD must be kept away from the HS/LS stages in order to avoid a hw issue on evergreen/cayman. This patch implements this workaround. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/evergreen_state.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index b3109c7..c1c8f22 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -2861,6 +2861,11 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT, S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000)); + r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3); + r600_store_value(cb, 0x); + r600_store_value(cb, 0x); + r600_store_value(cb, 0xfffe); + r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0); r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4)); -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 52/53] r600/asm: enable nstack check for tess ctrl/eval shaders.
From: Dave Airlie
This just makes sure they register at least one stack
usage frame like vertex shaders.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_asm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 88e35bc..c3a565e 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -1690,7 +1690,7 @@ int r600_bytecode_build(struct r600_bytecode *bc)
if (!bc->nstack) // If not 0, Stack_size already provided by llvm
bc->nstack = bc->stack.max_entries;
- if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
+ if ((bc->type == TGSI_PROCESSOR_VERTEX || bc->type ==
TGSI_PROCESSOR_TESS_EVAL || bc->type == TGSI_PROCESSOR_TESS_CTRL) &&
!bc->nstack) {
bc->nstack = 1;
}
--
2.5.0
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[Mesa-dev] [PATCH 49/53] r600: move VGT_VTX_CNT_EN into shader stages atom.
From: Dave Airlie This should be enabled for tessellation shaders as well. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/evergreen_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index c1c8f22..ae7539c 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -2349,6 +2349,7 @@ static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_ v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS); } + radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 ); radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v); radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2); radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid); @@ -3220,7 +3221,6 @@ void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader /* VGT_GS_MODE is written by evergreen_emit_shader_stages */ - r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1); r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT, S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices)); @@ -3742,7 +3742,7 @@ void evergreen_init_state_functions(struct r600_context *rctx) r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++); for (i = 0; i < EG_NUM_HW_STAGES; i++) r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0); - r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 12); + r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15); r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26); rctx->b.b.create_blend_state = evergreen_create_blend_state; -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 48/53] r600: enable tcs/tes dumping for R600_DUMP_SHADERS.
From: Dave Airlie
Trivial patch just to enable dumping more.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_pipe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 64f5fc6..78af44d 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -583,7 +583,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys
*ws)
if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
rscreen->b.debug_flags |= DBG_COMPUTE;
if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
- rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS |
DBG_CS;
+ rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS |
DBG_CS | DBG_TCS | DBG_TES;
if (!debug_get_bool_option("R600_HYPERZ", TRUE))
rscreen->b.debug_flags |= DBG_NO_HYPERZ;
if (debug_get_bool_option("R600_LLVM", FALSE))
--
2.5.0
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[Mesa-dev] [PATCH 53/53] r600: enable tessellation for evergreen/cayman
From: Dave Airlie This enables tessellation for evergreen/cayman, This will need changes before committing depending on what hw works etc. Currently known broken are SUMO/CAICOS working are CAYMAN/REDWOOD/BARTS/TURKS. --- src/gallium/drivers/r600/r600_pipe.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 78af44d..a5af72a 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -343,7 +343,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_USER_VERTEX_BUFFERS: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: case PIPE_CAP_VERTEXID_NOBASE: - case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: case PIPE_CAP_DEPTH_BOUNDS_TEST: case PIPE_CAP_FORCE_PERSAMPLE_INTERP: case PIPE_CAP_SHAREABLE_SHADERS: @@ -351,6 +350,8 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_CLEAR_TEXTURE: return 0; + case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: + return 30; /* Stream output. */ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: return rscreen->b.has_streamout ? 4 : 0; @@ -440,6 +441,8 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e case PIPE_SHADER_COMPUTE: break; case PIPE_SHADER_GEOMETRY: + case PIPE_SHADER_TESS_CTRL: + case PIPE_SHADER_TESS_EVAL: if (rscreen->b.family >= CHIP_CEDAR) break; /* pre-evergreen geom shaders need newer kernel */ -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 51/53] r600/asm: handle lds read operations.
From: Dave Airlie
Reads from the queue shouldn't be merged for now read operations.
Reads from the queue shouldn't be merged for now, or put in
T slots.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_asm.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 89a34c4..88e35bc 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -268,6 +268,24 @@ static int alu_uses_rel(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
return 0;
}
+static int is_lds_read(int sel)
+{
+ return sel == EG_V_SQ_ALU_SRC_LDS_OQ_A_POP || sel ==
EG_V_SQ_ALU_SRC_LDS_OQ_B_POP;
+}
+
+static int alu_uses_lds(struct r600_bytecode *bc, struct r600_bytecode_alu
*alu)
+{
+ unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
+ unsigned src;
+
+ for (src = 0; src < num_src; ++src) {
+ if (is_lds_read(alu->src[src].sel)) {
+ return 1;
+ }
+ }
+ return 0;
+}
+
static int is_alu_64bit_inst(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
{
const struct alu_op_info *op = r600_isa_alu(alu->op);
@@ -787,6 +805,8 @@ static int merge_inst_groups(struct r600_bytecode *bc,
struct r600_bytecode_alu
}
have_rel = 1;
}
+ if (alu_uses_lds(bc, prev[i]))
+ return 0;
num_once_inst += is_alu_once_inst(bc, prev[i]);
}
@@ -800,7 +820,7 @@ static int merge_inst_groups(struct r600_bytecode *bc,
struct r600_bytecode_alu
} else if (prev[i] && slots[i]) {
if (max_slots == 5 && result[4] == NULL && prev[4] ==
NULL && slots[4] == NULL) {
/* Trans unit is still free try to use it. */
- if (is_alu_any_unit_inst(bc, slots[i])) {
+ if (is_alu_any_unit_inst(bc, slots[i]) &&
!alu_uses_lds(bc, slots[i])) {
result[i] = prev[i];
result[4] = slots[i];
} else if (is_alu_any_unit_inst(bc, prev[i])) {
--
2.5.0
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[Mesa-dev] [PATCH 50/53] r600/asm: add LDS ops and barrier to the once per group restriction.
From: Dave Airlie
LDS ops must be scheduled in X slot, and barrier should be on its
own in a group.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_asm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 29515f2..89a34c4 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -237,7 +237,7 @@ int r600_bytecode_add_output(struct r600_bytecode *bc,
/* alu instructions that can ony exits once per group */
static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu
*alu)
{
- return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED);
+ return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED) ||
alu->is_lds_idx_op || alu->op == ALU_OP0_GROUP_BARRIER;
}
static int is_alu_reduction_inst(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
--
2.5.0
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Re: [Mesa-dev] [PATCH] glsl/dead_builin_varyings: Fix gl_FragData array lowering
Hi;
On 11/27/2015 02:14 PM, Iago Toral Quiroga wrote:
The current implementation looks for array dereferences on gl_FragData and
immediately then proceeds to lower them, however this is not enough because
we can have array access on vector variables too, like in this code:
out vec4 color;
void main()
{
int i;
for (i = 0; i < 4; i++)
color[i] = 1.0;
}
Fix it by making sure that the actual variable being dereferenced is an array.
Fixes a crash in:
spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-ldexp-dvec4.shader_test
Instead of asserting in IR validation now we assert in backend because
array 'should have been lowered' .. is there some other patches that
should be bundled together with this to make it work?
---
src/glsl/opt_dead_builtin_varyings.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/opt_dead_builtin_varyings.cpp
b/src/glsl/opt_dead_builtin_varyings.cpp
index 68b70ee..5387113 100644
--- a/src/glsl/opt_dead_builtin_varyings.cpp
+++ b/src/glsl/opt_dead_builtin_varyings.cpp
@@ -85,7 +85,7 @@ public:
{
ir_variable *var = ir->variable_referenced();
- if (!var || var->data.mode != this->mode)
+ if (!var || var->data.mode != this->mode || !var->type->is_array())
return visit_continue;
if (this->find_frag_outputs && var->data.location == FRAG_RESULT_DATA0)
{
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