[llvm-commits] [llvm] r44676 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2007-12-05-VectorShuffle.ll test/CodeGen/X86/vec_shuffle-12.ll
Author: evancheng
Date: Fri Dec 7 02:07:39 2007
New Revision: 44676
URL: http://llvm.org/viewvc/llvm-project?rev=44676&view=rev
Log:
Much improved v8i16 shuffles. (Step 1).
Added:
llvm/trunk/test/CodeGen/X86/vec_shuffle-12.ll
Removed:
llvm/trunk/test/CodeGen/X86/2007-12-05-VectorShuffle.ll
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=44676&r1=44675&r2=44676&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Dec 7 02:07:39 2007
@@ -2754,10 +2754,33 @@
}
std::swap(V1, V2);
- Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
}
+static
+SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
+ MVT::ValueType MaskVT = Mask.getValueType();
+ MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
+ unsigned NumElems = Mask.getNumOperands();
+ SmallVector MaskVec;
+ for (unsigned i = 0; i != NumElems; ++i) {
+SDOperand Arg = Mask.getOperand(i);
+if (Arg.getOpcode() == ISD::UNDEF) {
+ MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
+ continue;
+}
+assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!");
+unsigned Val = cast(Arg)->getValue();
+if (Val < NumElems)
+ MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
+else
+ MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
+ }
+ return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
+}
+
+
/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
/// match movhlps. The lower half elements should come from upper half of
/// V1 (and in order), and the upper half elements should come from the upper
@@ -3282,6 +3305,102 @@
return SDOperand();
}
+static
+SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
+ SDOperand PermMask, SelectionDAG &DAG,
+ TargetLowering &TLI) {
+ MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8);
+ MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
+ if (isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
+// Handle v8i16 shuffle high / low shuffle node pair.
+SmallVector MaskVec;
+for (unsigned i = 0; i != 4; ++i)
+ MaskVec.push_back(PermMask.getOperand(i));
+for (unsigned i = 4; i != 8; ++i)
+ MaskVec.push_back(DAG.getConstant(i, MaskEVT));
+SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
+V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V2, Mask);
+MaskVec.clear();
+for (unsigned i = 0; i != 4; ++i)
+ MaskVec.push_back(DAG.getConstant(i, MaskEVT));
+for (unsigned i = 4; i != 8; ++i)
+ MaskVec.push_back(PermMask.getOperand(i));
+Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
+return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V2, Mask);
+ }
+
+ // Lower than into extracts and inserts but try to do as few as possible.
+ // First, let's find out how many elements are already in the right order.
+ unsigned V1InOrder = 0;
+ unsigned V1FromV1 = 0;
+ unsigned V2InOrder = 0;
+ unsigned V2FromV2 = 0;
+ SmallVector V1Elts;
+ SmallVector V2Elts;
+ for (unsigned i = 0; i < 8; ++i) {
+SDOperand Elt = PermMask.getOperand(i);
+if (Elt.getOpcode() == ISD::UNDEF) {
+ V1Elts.push_back(i);
+ V2Elts.push_back(i);
+ ++V1InOrder;
+ ++V2InOrder;
+} else {
+ unsigned EltIdx = cast(Elt)->getValue();
+ if (EltIdx == i) {
+V1Elts.push_back(i);
+V2Elts.push_back(i+8);
+++V1InOrder;
+ } else if (EltIdx == i+8) {
+V1Elts.push_back(i+8);
+V2Elts.push_back(i);
+++V2InOrder;
+ } else {
+V1Elts.push_back(EltIdx);
+V2Elts.push_back(EltIdx);
+if (EltIdx < 8)
+ ++V1FromV1;
+else
+ ++V2FromV2;
+ }
+}
+ }
+
+ if (V2InOrder > V1InOrder) {
+PermMask = CommuteVectorShuffleMask(PermMask, DAG);
+std::swap(V1, V2);
+std::swap(V1Elts, V2Elts);
+std::swap(V1FromV1, V2FromV2);
+ }
+
+ MVT::ValueType PtrVT = TLI.getPointerTy();
+ if (V1FromV1) {
+// If there are elements that are from V1 but out of place,
+// then first sort them in place
+SmallVector MaskVec;
+for (unsigned i = 0; i < 8; ++i) {
+ unsigned EltIdx = V1Elts[i];
+ if (EltIdx >= 8)
+MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
+ else
+MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
+}
+SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8
Re: [llvm-commits] [llvm] r44676 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2007-12-05-VectorShuffle.ll test/CodeGen/X86/vec_shuffle-12.ll
Hey Evan,
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Dec 7
> 02:07:39 2007
> @@ -2754,10 +2754,33 @@
>}
>
>std::swap(V1, V2);
> - Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],
> MaskVec.size());
> + Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],
> NumElems);
>return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
> }
>
> +static
> +SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG
> &DAG) {
Please add a comment over this that gives an example of what it
does. I kept misreading the name as "compute..." and couldn't figure
out what it did :)
> +static
> +SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
> + SDOperand PermMask,
> SelectionDAG &DAG,
> + TargetLowering &TLI) {
Does this cause any pessimizations for v8i16 shuffles that could be
done as v4i32?
-Chris
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[llvm-commits] [poolalloc] r44677 - /poolalloc/trunk/include/poolalloc/PoolAllocate.h
Author: criswell Date: Fri Dec 7 12:05:12 2007 New Revision: 44677 URL: http://llvm.org/viewvc/llvm-project?rev=44677&view=rev Log: Do not use an absolute path to find the header file from SAFECode. The configure script now sets up -I options to the compiler to help us find it. Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc/PoolAllocate.h?rev=44677&r1=44676&r2=44677&view=diff == --- poolalloc/trunk/include/poolalloc/PoolAllocate.h (original) +++ poolalloc/trunk/include/poolalloc/PoolAllocate.h Fri Dec 7 12:05:12 2007 @@ -26,8 +26,7 @@ #include "poolalloc/Config/config.h" #ifdef SAFECODE -//FIXME : make this use some configuration options -#include "/home/vadve/criswell/src/latestllvm/projects/safecode/include/ConvertUnsafeAllocas.h" +#include "ConvertUnsafeAllocas.h" #endif ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [poolalloc] r44679 - /poolalloc/trunk/lib/DSA/DataStructure.cpp
Author: criswell
Date: Fri Dec 7 12:06:47 2007
New Revision: 44679
URL: http://llvm.org/viewvc/llvm-project?rev=44679&view=rev
Log:
Implement the isPointerType() method found in the DS namespace.
Modified:
poolalloc/trunk/lib/DSA/DataStructure.cpp
Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp
URL:
http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=44679&r1=44678&r2=44679&view=diff
==
--- poolalloc/trunk/lib/DSA/DataStructure.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructure.cpp Fri Dec 7 12:06:47 2007
@@ -14,6 +14,7 @@
#include "dsa/DSGraphTraits.h"
#include "dsa/DataStructure.h"
#include "dsa/DSGraph.h"
+#include "dsa/DSSupport.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/GlobalVariable.h"
@@ -60,6 +61,16 @@
using namespace DS;
+//
+// Function: DS::isPointerType()
+//
+// Description:
+// This returns whether the given type is a pointer.
+//
+bool DS::isPointerType(const Type *Ty) {
+ return isa(Ty);
+}
+
/// isForwarding - Return true if this NodeHandle is forwarding to another
/// one.
bool DSNodeHandle::isForwarding() const {
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[llvm-commits] [poolalloc] r44678 - /poolalloc/trunk/include/dsa/DataStructure.h
Author: criswell Date: Fri Dec 7 12:06:17 2007 New Revision: 44678 URL: http://llvm.org/viewvc/llvm-project?rev=44678&view=rev Log: Comment out the declarations of deleteValue() and copyValue() for the TDDataStructure pass. These methods are never defined and are uneeded. Need review from Andrew Lenharth to see whether these should be removed permanently. Modified: poolalloc/trunk/include/dsa/DataStructure.h Modified: poolalloc/trunk/include/dsa/DataStructure.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DataStructure.h?rev=44678&r1=44677&r2=44678&view=diff == --- poolalloc/trunk/include/dsa/DataStructure.h (original) +++ poolalloc/trunk/include/dsa/DataStructure.h Fri Dec 7 12:06:17 2007 @@ -272,10 +272,12 @@ virtual bool runOnModule(Module &M); +#if 0 /// deleteValue/copyValue - Interfaces to update the DSGraphs in the program. /// These correspond to the interfaces defined in the AliasAnalysis class. void deleteValue(Value *V); void copyValue(Value *From, Value *To); +#endif /// print - Print out the analysis results... /// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r44687 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/MachineLICM.cpp lib/Target/PowerPC/PPCInstrInfo.td
On Dec 7, 2007 4:42 PM, Evan Cheng <[EMAIL PROTECTED]> wrote:
>
> Nicely done!
>
Thx! :-)
> > +// Map the def of a virtual register to the machine instruction.
> > +std::map VRegDefs;
>
> Consider using IndexedMap.
>
Okay.
> > +bool CanHoistInst(MachineInstr &I) const {
> > + const TargetInstrDescriptor *TID = I.getInstrDescriptor();
> > + MachineOpCode Opcode = TID->Opcode;
> > +
> > + return TII->isTriviallyReMaterializable(&I) &&
> > +// FIXME: Below necessary?
> > +!(TII->isReturn(Opcode) ||
> > + TII->isTerminatorInstr(Opcode) ||
> > + TII->isBranch(Opcode) ||
> > + TII->isIndirectBranch(Opcode) ||
> > + TII->isBarrier(Opcode) ||
> > + TII->isCall(Opcode) ||
> > + TII->isLoad(Opcode) || // TODO: Do loads and stores.
> > + TII->isStore(Opcode));
> > +}
>
> Since you are touching this... When you have a chance, please rename
> it to something like hasNoSideEffect().
>
Okay. I'll do it in a future patch.
> > +void MoveInstToBlock(MachineBasicBlock *MBB, MachineInstr *MI) {
> > + MachineBasicBlock::iterator Iter = MBB->getFirstTerminator();
> > + MBB->insert(Iter, MI);
> > +}
>
> Poorly named. :-) MoveInstToEndOfBlock?
>
Sounds good.
> > +// Visit all of the instructions of the loop. We want to visit
> > the subloops
> > +// first, though, so that we can hoist their invariants first
> > into their
> > +// containing loop before we process that loop.
> > +SmallVector Loops;
> > +GatherAllLoops(L, Loops);
>
> Seems to me this can be smarter. When you are gathering the loops, put
> loops of greater depth in the front of the queue then HoistRegion
> won't have to check if the BB is in the current loop level?
>
> > +for (MachineBasicBlock::const_iterator
> > + II = MBB.begin(), IE = MBB.end(); II != IE; ++II) {
> > + const MachineInstr &MI = *II;
> > +
> > + if (MI.getNumOperands() > 0) {
> > +const MachineOperand &MO = MI.getOperand(0);
>
> This is not right. You are assuming only one def and it must be the
> first operand. Neither is necessarily true.
>
Okay.
> > + // If this subregion is not in the top level loop at all, exit.
> > + if (!CurLoop->contains(BB)) return;
> > +
> > + // Only need to process the contents of this block if it is not
> > part of a
> > + // subloop (which would already have been processed).
> > + if (!isInSubLoop(BB))
>
> Like I said earlier, I think this check can be eliminated if we visit
> the inner most loops first (and perhaps keep track which BB has been
> processed?)
>
I'm not sure I understand. I was under the impression that
MachineDomTreeNode would give blocks from the loop and its subloops.
If we keep track of those visited, I suppose we could simplify this
check...
> > + // Try hoisting the instruction out of the loop. We can only
> > do this if
> > + // all of the operands of the instruction are loop invariant
> > and if it is
> > + // safe to hoist the instruction.
> > + if (Hoist(MI))
> > +// Hoisting was successful! Remove bothersome instruction
> > now.
> > +MI.getParent()->remove(&MI);
>
> Why not have Hoist remove the MI?
>
I had a bug earlier where I was invalidating an iterator. I think it's
no longer the case, so this can be moved to Hoist instead.
> > + // Don't hoist if this instruction implicitly reads physical
> > registers or
> > + // doesn't take any operands.
> > + if (TID->ImplicitUses || !I.getNumOperands()) return false;
>
> The comment is wrong. It's ok to lift something that has no uses but
> produces result(s), right? "doesn't take any operands" to me means
> something that doesn't have any uses.
>
I was thinking about things like "emms" which don't seem to use
anything, but have definite side effects. Or will this be picked up in
the earlier check isTriviallyReMaterializable?
> > + if (!CanHoistInst(I)) return false;
>
> Perhaps fold the earlier check into CanHoistInst()?
>
Okay.
> > +// If the loop contains the definition of an operand, then the
> > instruction
> > +// isn't loop invariant.
> > +if (CurLoop->contains(VRegDefs[Reg]->getParent()))
> > + return false;
>
> Hmmm. I am not sure about this. What if the definition is in the
> preheader? Does contains() returns true? Chris, Owen?
>
The preheader wouldn't be part of the loop, so it should be okay.
> Also, I fear this might be slow. When you are creating the VReg -> MI
> map, perhaps you should create a VReg -> loop map as well?
>
I'll see if a map will help things along.
> > +bool MachineLICM::Hoist(MachineInstr &MI) {
> > + if (!isLoopInvariantInst(MI)) return false;
> > +
> > + std::vector Preds;
> > +
> > + // Non-back-edge predecessors.
> > + FindPredecessors(Preds);
>
> Consider caching some of these info?
>
Okay.
> > +// FIXME: We are assuming at first that the basic blocks coming
> > into this
> > +// loop have only one
[llvm-commits] [llvm] r44700 - in /llvm/trunk: lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.h lib/Target/PowerPC/PPCMachineFunctionInfo.h lib/Target/PowerPC/PPCRegisterInf
Author: lattner
Date: Sat Dec 8 00:59:59 2007
New Revision: 44700
URL: http://llvm.org/viewvc/llvm-project?rev=44700&view=rev
Log:
implement __builtin_return_addr(0) on ppc.
Added:
llvm/trunk/test/CodeGen/PowerPC/retaddr.ll
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/lib/Target/PowerPC/README.txt
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=44700&r1=44699&r2=44700&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sat Dec 8 00:59:59 2007
@@ -3036,8 +3036,8 @@
case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
case ISD::MUL:return LowerMUL(Op, DAG);
- // Frame & Return address. Currently unimplemented
- case ISD::RETURNADDR: break;
+ // Frame & Return address.
+ case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
}
return SDOperand();
@@ -3576,8 +3576,36 @@
return false;
}
-SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)
-{
+SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
+ // Depths > 0 not supported yet!
+ if (cast(Op.getOperand(0))->getValue() > 0)
+return SDOperand();
+
+ MachineFunction &MF = DAG.getMachineFunction();
+ PPCFunctionInfo *FuncInfo = MF.getInfo();
+ int RAIdx = FuncInfo->getReturnAddrSaveIndex();
+ if (RAIdx == 0) {
+bool isPPC64 = PPCSubTarget.isPPC64();
+int Offset =
+ PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI());
+
+// Set up a frame object for the return address.
+RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset);
+
+// Remember it for next time.
+FuncInfo->setReturnAddrSaveIndex(RAIdx);
+
+// Make sure the function really does not optimize away the store of the RA
+// to the stack.
+FuncInfo->setLRStoreRequired();
+ }
+
+ // Just load the return address off the stack.
+ SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy());
+ return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
+}
+
+SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
// Depths > 0 not supported yet!
if (cast(Op.getOperand(0))->getValue() > 0)
return SDOperand();
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=44700&r1=44699&r2=44700&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Sat Dec 8 00:59:59 2007
@@ -288,6 +288,7 @@
/// the offset of the target addressing mode.
virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
+SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
};
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h?rev=44700&r1=44699&r2=44700&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h Sat Dec 8 00:59:59
2007
@@ -27,18 +27,29 @@
/// when using frame pointers (dyna_add, dyna_sub.)
int FramePointerSaveIndex;
- /// UsesLR - Indicates whether LR is used in the current function.
+ /// ReturnAddrSaveIndex - Frame index of where the return address is stored.
///
+ int ReturnAddrSaveIndex;
+
+ /// UsesLR - Indicates whether LR is used in the current function. This is
+ /// only valid after the initial scan of the function by PEI.
bool UsesLR;
+ /// LRStoreRequired - The bool indicates whether there is some explicit use
of
+ /// the LR/LR8 stack slot that is not obvious from scanning the code. This
+ /// requires that the code generator produce a store of LR to the stack on
+ /// entry, even though LR may otherwise apparently not be used.
+ bool LRStoreRequired;
public:
- PPCFunctionInfo(MachineFunction& MF)
- : FramePointerSaveIndex(0)
- {}
+ PPCFunctionInfo(MachineFunction &MF)
+: FramePointerSaveIndex(0), ReturnAddrSaveIndex(0),
LRStoreRequired(false){}
int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
void setFramePointerSaveIndex(int Idx) { Frame
[llvm-commits] [llvm] r44703 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Author: lattner
Date: Sat Dec 8 01:22:58 2007
New Revision: 44703
URL: http://llvm.org/viewvc/llvm-project?rev=44703&view=rev
Log:
aesthetic changes, no functionality change. Evan, it's not clear
what 'Available' is, please add a comment near it and rename it
if appropriate.
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=44703&r1=44702&r2=44703&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Dec 8 01:22:58 2007
@@ -562,7 +562,7 @@
/// MatchAddress - Add the specified node to the specified addressing mode,
/// returning true if it cannot be done. This just pattern matches for the
-/// addressing mode
+/// addressing mode.
bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
bool isRoot, unsigned Depth) {
// Limit recursion.
@@ -653,33 +653,35 @@
break;
case ISD::SHL:
-if (!Available && AM.IndexReg.Val == 0 && AM.Scale == 1)
- if (ConstantSDNode *CN = dyn_cast(N.Val->getOperand(1)))
{
-unsigned Val = CN->getValue();
-if (Val == 1 || Val == 2 || Val == 3) {
- AM.Scale = 1 << Val;
- SDOperand ShVal = N.Val->getOperand(0);
-
- // Okay, we know that we have a scale by now. However, if the scaled
- // value is an add of something and a constant, we can fold the
- // constant into the disp field here.
- if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
- isa(ShVal.Val->getOperand(1))) {
-AM.IndexReg = ShVal.Val->getOperand(0);
-ConstantSDNode *AddVal =
- cast(ShVal.Val->getOperand(1));
-uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
-if (isInt32(Disp))
- AM.Disp = Disp;
-else
- AM.IndexReg = ShVal;
- } else {
+if (Available || AM.IndexReg.Val != 0 || AM.Scale != 1)
+ break;
+
+if (ConstantSDNode *CN = dyn_cast(N.Val->getOperand(1))) {
+ unsigned Val = CN->getValue();
+ if (Val == 1 || Val == 2 || Val == 3) {
+AM.Scale = 1 << Val;
+SDOperand ShVal = N.Val->getOperand(0);
+
+// Okay, we know that we have a scale by now. However, if the scaled
+// value is an add of something and a constant, we can fold the
+// constant into the disp field here.
+if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
+isa(ShVal.Val->getOperand(1))) {
+ AM.IndexReg = ShVal.Val->getOperand(0);
+ ConstantSDNode *AddVal =
+cast(ShVal.Val->getOperand(1));
+ uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
+ if (isInt32(Disp))
+AM.Disp = Disp;
+ else
AM.IndexReg = ShVal;
- }
- return false;
+} else {
+ AM.IndexReg = ShVal;
}
+return false;
}
break;
+}
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI:
@@ -738,22 +740,22 @@
case ISD::OR:
// Handle "X | C" as "X + C" iff X is known to have C bits clear.
-if (!Available) {
- if (ConstantSDNode *CN = dyn_cast(N.getOperand(1))) {
-X86ISelAddressMode Backup = AM;
-// Start with the LHS as an addr mode.
-if (!MatchAddress(N.getOperand(0), AM, false) &&
-// Address could not have picked a GV address for the displacement.
-AM.GV == NULL &&
-// On x86-64, the resultant disp must fit in 32-bits.
-isInt32(AM.Disp + CN->getSignExtended()) &&
-// Check to see if the LHS & C is zero.
-CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getValue())) {
- AM.Disp += CN->getValue();
- return false;
-}
-AM = Backup;
+if (Available) break;
+
+if (ConstantSDNode *CN = dyn_cast(N.getOperand(1))) {
+ X86ISelAddressMode Backup = AM;
+ // Start with the LHS as an addr mode.
+ if (!MatchAddress(N.getOperand(0), AM, false) &&
+ // Address could not have picked a GV address for the displacement.
+ AM.GV == NULL &&
+ // On x86-64, the resultant disp must fit in 32-bits.
+ isInt32(AM.Disp + CN->getSignExtended()) &&
+ // Check to see if the LHS & C is zero.
+ CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getValue())) {
+AM.Disp += CN->getValue();
+return false;
}
+ AM = Backup;
}
break;
}
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[llvm-commits] [llvm] r44701 - in /llvm/trunk: lib/Target/PowerPC/PPCRegisterInfo.cpp test/CodeGen/PowerPC/retaddr.ll
Author: lattner
Date: Sat Dec 8 01:04:58 2007
New Revision: 44701
URL: http://llvm.org/viewvc/llvm-project?rev=44701&view=rev
Log:
Fix a significant code quality regression I introduced on PPC64 quite
a while ago. We now produce:
_foo:
mflr r0
std r0, 16(r1)
ld r2, 16(r1)
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
instead of:
_foo:
mflr r0
std r0, 16(r1)
lis r0, 0
ori r0, r0, 16
ldx r2, r1, r0
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
for:
void foo(void **X) {
*X = __builtin_return_address(0);
}
on ppc64.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/test/CodeGen/PowerPC/retaddr.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=44701&r1=44700&r2=44701&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Sat Dec 8 01:04:58 2007
@@ -817,7 +817,7 @@
// clear can be encoded. This is extremely uncommon, because normally you
// only "std" to a stack slot that is at least 4-byte aligned, but it can
// happen in invalid code.
- if (isInt16(Offset) && (!isIXAddr || (isIXAddr & 3) == 0)) {
+ if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
if (isIXAddr)
Offset >>= 2;// The actual encoded value has the low two bits zero.
MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
Modified: llvm/trunk/test/CodeGen/PowerPC/retaddr.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/retaddr.ll?rev=44701&r1=44700&r2=44701&view=diff
==
--- llvm/trunk/test/CodeGen/PowerPC/retaddr.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/retaddr.ll Sat Dec 8 01:04:58 2007
@@ -1,5 +1,6 @@
; RUN: llvm-as < %s | llc -march=ppc32 | grep mflr
; RUN: llvm-as < %s | llc -march=ppc32 | grep lwz
+; RUN: llvm-as < %s | llc -march=ppc64 | grep {ld r., 16(r1)}
target triple = "powerpc-apple-darwin8"
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[llvm-commits] [llvm] r44699 - in /llvm/trunk/lib/Target/PowerPC: PPCMachineFunctionInfo.h PPCRegisterInfo.cpp PPCRegisterInfo.h
Author: lattner
Date: Sat Dec 8 00:39:11 2007
New Revision: 44699
URL: http://llvm.org/viewvc/llvm-project?rev=44699&view=rev
Log:
refactor some code to avoid overloading the name 'usesLR' in
different places to mean different things. Document what the
one in PPCFunctionInfo means and when it is valid.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
Modified: llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h?rev=44699&r1=44698&r2=44699&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h Sat Dec 8 00:39:11
2007
@@ -39,8 +39,12 @@
int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
+ /// UsesLR - This is set when the prolog/epilog inserter does its initial
scan
+ /// of the function, it is true if the LR/LR8 register is ever explicitly
+ /// accessed/clobbered in the machine function (e.g. by calls and movpctolr,
+ /// which is used in PIC generation).
void setUsesLR(bool U) { UsesLR = U; }
- bool usesLR() { return UsesLR; }
+ bool usesLR() const{ return UsesLR; }
};
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=44699&r1=44698&r2=44699&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Sat Dec 8 00:39:11 2007
@@ -645,11 +645,13 @@
return MFI->getStackSize() && needsFP(MF);
}
-/// usesLR - Returns if the link registers (LR) has been used in the function.
-///
-bool PPCRegisterInfo::usesLR(MachineFunction &MF) const {
- PPCFunctionInfo *FI = MF.getInfo();
- return FI->usesLR();
+/// MustSaveLR - Return true if this function requires that we save the LR
+/// register onto the stack in the prolog and restore it in the epilog of the
function.
+static bool MustSaveLR(const MachineFunction &MF) {
+ return MF.getInfo()->usesLR() ||
+ // FIXME: Anything that has a call should clobber the LR register,
+ // isn't this redundant??
+ MF.getFrameInfo()->hasCalls();
}
void PPCRegisterInfo::
@@ -1062,7 +1064,7 @@
// Get operating system
bool IsMachoABI = Subtarget.isMachoABI();
// Check if the link register (LR) has been used.
- bool UsesLR = MFI->hasCalls() || usesLR(MF);
+ bool UsesLR = MustSaveLR(MF);
// Do we have a frame pointer for this function?
bool HasFP = hasFP(MF) && FrameSize;
@@ -1226,7 +1228,7 @@
// Get operating system
bool IsMachoABI = Subtarget.isMachoABI();
// Check if the link register (LR) has been used.
- bool UsesLR = MFI->hasCalls() || usesLR(MF);
+ bool UsesLR = MustSaveLR(MF);
// Do we have a frame pointer for this function?
bool HasFP = hasFP(MF) && FrameSize;
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=44699&r1=44698&r2=44699&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Sat Dec 8 00:39:11 2007
@@ -96,10 +96,6 @@
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
- /// usesLR - Returns if the link registers (LR) has been used in the
function.
- ///
- bool usesLR(MachineFunction &MF) const;
-
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, RegScavenger *RS = NULL) const;
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[llvm-commits] [test-suite] r44698 - /test-suite/trunk/Makefile.programs
Author: lattner Date: Fri Dec 7 23:00:57 2007 New Revision: 44698 URL: http://llvm.org/viewvc/llvm-project?rev=44698&view=rev Log: Enable machine-licm for ppc beta. Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=44698&r1=44697&r2=44698&view=diff == --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Fri Dec 7 23:00:57 2007 @@ -209,7 +209,7 @@ endif#DISABLE_DIFFS ifeq ($(ARCH),PowerPC) -LLCBETAOPTION := -new-coalescer-heuristic=true +LLCBETAOPTION := -machine-licm #--enable-tail-merge #--enable-ppc-preinc #-regalloc=local -fast ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r44697 - /llvm/trunk/include/llvm/InstrTypes.h
Author: lattner
Date: Fri Dec 7 22:37:52 2007
New Revision: 44697
URL: http://llvm.org/viewvc/llvm-project?rev=44697&view=rev
Log:
Implement correct isa, problem reported by "ST".
Modified:
llvm/trunk/include/llvm/InstrTypes.h
Modified: llvm/trunk/include/llvm/InstrTypes.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InstrTypes.h?rev=44697&r1=44696&r2=44697&view=diff
==
--- llvm/trunk/include/llvm/InstrTypes.h (original)
+++ llvm/trunk/include/llvm/InstrTypes.h Fri Dec 7 22:37:52 2007
@@ -108,6 +108,20 @@
Op = Val;
}
unsigned getNumOperands() const { return 1; }
+
+ // Methods for support type inquiry through isa, cast, and dyn_cast:
+ static inline bool classof(const UnaryInstruction *) { return true; }
+ static inline bool classof(const Instruction *I) {
+return I->getOpcode() == Instruction::Malloc ||
+ I->getOpcode() == Instruction::Alloca ||
+ I->getOpcode() == Instruction::Free ||
+ I->getOpcode() == Instruction::Load ||
+ I->getOpcode() == Instruction::VAArg ||
+ (I->getOpcode() >= CastOpsBegin && I->getOpcode() < CastOpsEnd);
+ }
+ static inline bool classof(const Value *V) {
+return isa(V) && classof(cast(V));
+ }
};
//===--===//
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[llvm-commits] [llvm] r44696 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp
Author: void
Date: Fri Dec 7 19:47:01 2007
New Revision: 44696
URL: http://llvm.org/viewvc/llvm-project?rev=44696&view=rev
Log:
Incorporated comments from Evan and Chris:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20071203/056043.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20071203/056048.html
Modified:
llvm/trunk/lib/CodeGen/MachineLICM.cpp
Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=44696&r1=44695&r2=44696&view=diff
==
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Fri Dec 7 19:47:01 2007
@@ -13,6 +13,7 @@
//===--===//
#define DEBUG_TYPE "machine-licm"
+#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -27,7 +28,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include
using namespace llvm;
@@ -35,9 +35,12 @@
// Hidden options to help debugging
cl::opt
PerformLICM("machine-licm",
- cl::init(false), cl::Hidden);
+ cl::init(false), cl::Hidden,
+ cl::desc("Perform loop-invariant code motion on machine code"));
}
+STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loop");
+
namespace {
class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass {
// Various analyses that we use...
@@ -51,7 +54,7 @@
MachineLoop *CurLoop; // The current loop we are working on.
// Map the def of a virtual register to the machine instruction.
-std::map VRegDefs;
+IndexedMap VRegDefs;
public:
static char ID; // Pass identification, replacement for typeid
MachineLICM() : MachineFunctionPass((intptr_t)&ID) {}
@@ -66,16 +69,23 @@
AU.addRequired();
}
private:
-/// GatherAllLoops - Get all loops in depth first order.
+/// VisitAllLoops - Visit all of the loops in depth first order and try to
+/// hoist invariant instructions from them.
///
-void GatherAllLoops(MachineLoop *L, SmallVectorImpl &Loops) {
+void VisitAllLoops(MachineLoop *L) {
const std::vector &SubLoops = L->getSubLoops();
for (MachineLoop::iterator
- I = SubLoops.begin(), E = SubLoops.end(); I != E; ++I)
-GatherAllLoops(*I, Loops);
+ I = SubLoops.begin(), E = SubLoops.end(); I != E; ++I) {
+MachineLoop *ML = *I;
+
+// Traverse the body of the loop in depth first order on the dominator
+// tree so that we are guaranteed to see definitions before we see
uses.
+VisitAllLoops(ML);
+HoistRegion(DT->getNode(ML->getHeader()));
+ }
- Loops.push_back(L);
+ HoistRegion(DT->getNode(L->getHeader()));
}
/// MapVirtualRegisterDefs - Create a map of which machine instruction
@@ -104,8 +114,12 @@
///
bool CanHoistInst(MachineInstr &I) const {
const TargetInstrDescriptor *TID = I.getInstrDescriptor();
- MachineOpCode Opcode = TID->Opcode;
+ // Don't hoist if this instruction implicitly reads physical registers or
+ // doesn't take any operands.
+ if (TID->ImplicitUses || !I.getNumOperands()) return false;
+
+ MachineOpCode Opcode = TID->Opcode;
return TII->isTriviallyReMaterializable(&I) &&
// FIXME: Below necessary?
!(TII->isReturn(Opcode) ||
@@ -137,12 +151,13 @@
Preds.push_back(*I);
}
-/// MoveInstToBlock - Moves the machine instruction to the bottom of the
-/// predecessor basic block (but before the terminator instructions).
+/// MoveInstToEndOfBlock - Moves the machine instruction to the bottom of
+/// the predecessor basic block (but before the terminator instructions).
///
-void MoveInstToBlock(MachineBasicBlock *MBB, MachineInstr *MI) {
+void MoveInstToEndOfBlock(MachineBasicBlock *MBB, MachineInstr *MI) {
MachineBasicBlock::iterator Iter = MBB->getFirstTerminator();
MBB->insert(Iter, MI);
+ ++NumHoisted;
}
/// HoistRegion - Walk the specified region of the CFG (defined by all
@@ -156,7 +171,7 @@
/// Hoist - When an instruction is found to only use loop invariant
operands
/// that is safe to hoist, this instruction is called to do the dirty work.
///
-bool Hoist(MachineInstr &MI);
+void Hoist(MachineInstr &MI);
};
char MachineLICM::ID = 0;
@@ -188,17 +203,7 @@
// Visit all of the instructions of the loop. We want to visit the subloops
// first, though, so that we can hoist their invariants first into their
// containing loop before we process that loop.
-SmallVector Loops;
-GatherAllLoops(L, Loops);
[llvm-commits] [llvm] r44695 - in /llvm/trunk: include/llvm/Analysis/MemoryDependenceAnalysis.h lib/Analysis/MemoryDependenceAnalysis.cpp lib/Transforms/Scalar/GVN.cpp
Author: resistor
Date: Fri Dec 7 19:37:09 2007
New Revision: 44695
URL: http://llvm.org/viewvc/llvm-project?rev=44695&view=rev
Log:
Fix several cache coherence bugs in MemDep/GVN that were found. Also add some
(disabled) debugging code
to make such problems easier to diagnose in the future, written by Duncan Sands.
Modified:
llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h?rev=44695&r1=44694&r2=44695&view=diff
==
--- llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Fri Dec 7
19:37:09 2007
@@ -52,6 +52,8 @@
reverseDepMapType reverseDepNonLocal;
public:
+void ping(Instruction* D);
+
// Special marker indicating that the query has no dependency
// in the specified block.
static Instruction* const NonLocal;
Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=44695&r1=44694&r2=44695&view=diff
==
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Fri Dec 7 19:37:09
2007
@@ -40,6 +40,31 @@
static RegisterPass X("memdep",
"Memory Dependence Analysis");
+void MemoryDependenceAnalysis::ping(Instruction *D) {
+ for (depMapType::iterator I = depGraphLocal.begin(), E = depGraphLocal.end();
+ I != E; ++I) {
+assert(I->first != D);
+assert(I->second.first != D);
+ }
+
+ for (nonLocalDepMapType::iterator I = depGraphNonLocal.begin(), E =
depGraphNonLocal.end();
+ I != E; ++I) {
+assert(I->first != D);
+ }
+
+ for (reverseDepMapType::iterator I = reverseDep.begin(), E =
reverseDep.end();
+ I != E; ++I)
+for (SmallPtrSet::iterator II = I->second.begin(), EE =
I->second.end();
+ II != EE; ++II)
+ assert(*II != D);
+
+ for (reverseDepMapType::iterator I = reverseDepNonLocal.begin(), E =
reverseDepNonLocal.end();
+ I != E; ++I)
+for (SmallPtrSet::iterator II = I->second.begin(), EE =
I->second.end();
+ II != EE; ++II)
+ assert(*II != D);
+}
+
/// getAnalysisUsage - Does not modify anything. It uses Alias Analysis.
///
void MemoryDependenceAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
@@ -54,6 +79,8 @@
Instruction* start,
BasicBlock* block)
{
+ std::pair& cachedResult =
+
depGraphLocal[C.getInstruction()];
AliasAnalysis& AA = getAnalysis();
TargetData& TD = getAnalysis();
BasicBlock::iterator blockBegin = C.getInstruction()->getParent()->begin();
@@ -100,8 +127,8 @@
if (result != AliasAnalysis::DoesNotAccessMemory &&
result != AliasAnalysis::OnlyReadsMemory) {
if (!start && !block) {
- depGraphLocal.insert(std::make_pair(C.getInstruction(),
- std::make_pair(QI, true)));
+ cachedResult.first = QI;
+ cachedResult.second = true;
reverseDep[QI].insert(C.getInstruction());
}
return QI;
@@ -113,8 +140,8 @@
if (AA.getModRefInfo(C, pointer, pointerSize) != AliasAnalysis::NoModRef) {
if (!start && !block) {
-depGraphLocal.insert(std::make_pair(C.getInstruction(),
-std::make_pair(QI, true)));
+cachedResult.first = QI;
+cachedResult.second = true;
reverseDep[QI].insert(C.getInstruction());
}
return QI;
@@ -122,8 +149,8 @@
}
// No dependence found
- depGraphLocal.insert(std::make_pair(C.getInstruction(),
- std::make_pair(NonLocal, true)));
+ cachedResult.first = NonLocal;
+ cachedResult.second = true;
reverseDep[NonLocal].insert(C.getInstruction());
return NonLocal;
}
@@ -265,13 +292,15 @@
BasicBlock::iterator QI = query;
// Check for a cached result
- std::pair cachedResult = depGraphLocal[query];
+ std::pair& cachedResult = depGraphLocal[query];
// If we have a _confirmed_ cached entry, return it
- if (cachedResult.second)
-return cachedResult.first;
- else if (cachedResult.first && cachedResult.first != NonLocal)
- // If we have an unconfirmed cached entry, we can start our search from there
-QI = cachedResult.first;
+ if (!block && !start) {
+if (cachedR
Re: [llvm-commits] [llvm] r44687 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/MachineLICM.cpp lib/Target/PowerPC/PPCInstrInfo.td
>> +// Visit all of the instructions of the loop. We want to visit >> the subloops >> +// first, though, so that we can hoist their invariants first >> into their >> +// containing loop before we process that loop. >> +SmallVector Loops; >> +GatherAllLoops(L, Loops); > > Seems to me this can be smarter. When you are gathering the loops, put > loops of greater depth in the front of the queue then HoistRegion > won't have to check if the BB is in the current loop level? This should do a simple postorder traversal of the loop nest, there is no need to make a vector of the loops. This ensures you visit inner loops before outer loops etc. >> +// If the loop contains the definition of an operand, then the >> instruction >> +// isn't loop invariant. >> +if (CurLoop->contains(VRegDefs[Reg]->getParent())) >> + return false; > > Hmmm. I am not sure about this. What if the definition is in the > preheader? Does contains() returns true? Chris, Owen? a preheader is outside the loop. The header is the "top" of the loop. >> +// FIXME: We are assuming at first that the basic blocks coming >> into this >> +// loop have only one successor each. This isn't the case in >> general because >> +// we haven't broken critical edges or added preheaders. >> +if (MBB->succ_size() != 1) return false; >> +assert(*MBB->succ_begin() == CurLoop->getHeader() && >> + "The predecessor doesn't feed directly into the loop >> header!"); >> + } > > Are we going to create a preheader to hoist LICM to? Then we won't > need to do all these checking? I am entirely sure about it. Someone > please chime in. Step #0 is to only work with simple loop forms. Going forward, bill will generalize this to handle more cases. >> >> + >> + // Now move the instructions to the predecessors. >> + for (std::vector::iterator >> + I = Preds.begin(), E = Preds.end(); I != E; ++I) >> +MoveInstToBlock(*I, MI.clone()); > > This will create multiple copies, it seems bad. Again, this should be > fixable with a loop preheader? Furthermore, this won't work, you'd have to insert phi nodes etc. You really really really don't want to do this bill. Only handle loops that have a header with one predecessor that is outside the loop plz, Very nice bill! -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r44694 - /llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
Author: evancheng
Date: Fri Dec 7 19:01:07 2007
New Revision: 44694
URL: http://llvm.org/viewvc/llvm-project?rev=44694&view=rev
Log:
Doh
Modified:
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=44694&r1=44693&r2=44694&view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Fri Dec 7 19:01:07 2007
@@ -429,7 +429,7 @@
bool ARMRegisterInfo::canFoldMemoryOperand(MachineInstr *MI,
SmallVectorImpl &Ops) const
{
- if (Ops.size() != 1) return 0;
+ if (Ops.size() != 1) return false;
unsigned OpNum = Ops[0];
unsigned Opc = MI->getOpcode();
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Re: [llvm-commits] [llvm] r44687 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/MachineLICM.cpp lib/Target/PowerPC/PPCInstrInfo.td
On Dec 7, 2007, at 1:42 PM, Bill Wendling wrote: > Author: void > Date: Fri Dec 7 15:42:31 2007 > New Revision: 44687 > > URL: http://llvm.org/viewvc/llvm-project?rev=44687&view=rev > Log: > Initial commit of the machine code LICM pass. It successfully > hoists this: > > _foo: > li r2, 0 > LBB1_1: ; bb > li r5, 0 > stw r5, 0(r3) > addi r2, r2, 1 > addi r3, r3, 4 > cmplw cr0, r2, r4 > bne cr0, LBB1_1 ; bb > LBB1_2: ; return > blr > > to: > > _foo: > li r2, 0 > li r5, 0 > LBB1_1: ; bb > stw r5, 0(r3) > addi r2, r2, 1 > addi r3, r3, 4 > cmplw cr0, r2, r4 > bne cr0, LBB1_1 ; bb > LBB1_2: ; return > blr > > ZOMG!! :-) I know you're kidding, but have you benchmarked this on the G5? In this specific case, "foo" is probably MUCH faster because the loop is one dispatch group instead of two (I think). :) -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r44687 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/MachineLICM.cpp lib/Target/PowerPC/PPCInstrInfo.td
Author: void
Date: Fri Dec 7 15:42:31 2007
New Revision: 44687
URL: http://llvm.org/viewvc/llvm-project?rev=44687&view=rev
Log:
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
Added:
llvm/trunk/lib/CodeGen/MachineLICM.cpp
Modified:
llvm/trunk/include/llvm/CodeGen/Passes.h
llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
Modified: llvm/trunk/include/llvm/CodeGen/Passes.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=44687&r1=44686&r2=44687&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/Passes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/Passes.h Fri Dec 7 15:42:31 2007
@@ -135,6 +135,10 @@
/// for the Sparc.
FunctionPass *getRegisterAllocator(TargetMachine &T);
+ /// createMachineLICMPass - This pass performs LICM on machine instructions.
+ ///
+ FunctionPass *createMachineLICMPass();
+
} // End llvm namespace
#endif
Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=44687&r1=44686&r2=44687&view=diff
==
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Fri Dec 7 15:42:31 2007
@@ -66,7 +66,9 @@
// Print the instruction selected machine code...
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
-
+
+ PM.add(createMachineLICMPass());
+
// Perform register allocation to convert to a concrete x86 representation
PM.add(createRegisterAllocator());
@@ -92,7 +94,7 @@
// Branch folding must be run after regalloc and prolog/epilog insertion.
if (!Fast)
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
-
+
// Fold redundant debug labels.
PM.add(createDebugLabelFoldingPass());
@@ -175,7 +177,9 @@
// Print the instruction selected machine code...
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
-
+
+ PM.add(createMachineLICMPass());
+
// Perform register allocation to convert to a concrete x86 representation
PM.add(createRegisterAllocator());
@@ -204,7 +208,7 @@
// Branch folding must be run after regalloc and prolog/epilog insertion.
if (!Fast)
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
-
+
if (addPreEmitPass(PM, Fast) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
Added: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=44687&view=auto
==
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (added)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Fri Dec 7 15:42:31 2007
@@ -0,0 +1,336 @@
+//===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass
-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by Bill Wendling and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This pass performs loop invariant code motion on machine instructions. We
+// attempt to remove as much code from the body of a loop as possible.
+//
+//===--===//
+
+#define DEBUG_TYPE "machine-licm"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/CFG.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include
+
+using namespace llvm;
+
+namespace {
+ // Hidden options to help debugging
+ cl::opt
+ PerformLICM("machine-licm",
+ cl::init(false), cl::Hidden);
+}
+
+namespace {
+ class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass {
+// Various analyses that we use...
+MachineLoopInfo *LI; // Current Ma
[llvm-commits] [poolalloc] r44683 - /poolalloc/trunk/include/dsa/DataStructure.h
Author: criswell Date: Fri Dec 7 15:05:23 2007 New Revision: 44683 URL: http://llvm.org/viewvc/llvm-project?rev=44683&view=rev Log: Removed deleteValue() and copyValue() from TDDataStructure; these methods should be implemented by the base class. Modified: poolalloc/trunk/include/dsa/DataStructure.h Modified: poolalloc/trunk/include/dsa/DataStructure.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DataStructure.h?rev=44683&r1=44682&r2=44683&view=diff == --- poolalloc/trunk/include/dsa/DataStructure.h (original) +++ poolalloc/trunk/include/dsa/DataStructure.h Fri Dec 7 15:05:23 2007 @@ -272,13 +272,6 @@ virtual bool runOnModule(Module &M); -#if 0 - /// deleteValue/copyValue - Interfaces to update the DSGraphs in the program. - /// These correspond to the interfaces defined in the AliasAnalysis class. - void deleteValue(Value *V); - void copyValue(Value *From, Value *To); -#endif - /// print - Print out the analysis results... /// void print(std::ostream &O, const Module *M) const; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [poolalloc] r44680 - in /poolalloc/trunk/lib: DSA/Makefile PoolAllocate/Makefile
Author: criswell Date: Fri Dec 7 12:07:27 2007 New Revision: 44680 URL: http://llvm.org/viewvc/llvm-project?rev=44680&view=rev Log: Build relinked libraries for the SAFECode tool. Modified: poolalloc/trunk/lib/DSA/Makefile poolalloc/trunk/lib/PoolAllocate/Makefile Modified: poolalloc/trunk/lib/DSA/Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Makefile?rev=44680&r1=44679&r2=44680&view=diff == --- poolalloc/trunk/lib/DSA/Makefile (original) +++ poolalloc/trunk/lib/DSA/Makefile Fri Dec 7 12:07:27 2007 @@ -9,8 +9,6 @@ LEVEL = ../.. SHARED_LIBRARY=1 -LOADABLE_MODULE = 1 -DONT_BUILD_RELINKED=1 LIBRARYNAME = LLVMDataStructure include $(LEVEL)/Makefile.common Modified: poolalloc/trunk/lib/PoolAllocate/Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/Makefile?rev=44680&r1=44679&r2=44680&view=diff == --- poolalloc/trunk/lib/PoolAllocate/Makefile (original) +++ poolalloc/trunk/lib/PoolAllocate/Makefile Fri Dec 7 12:07:27 2007 @@ -7,8 +7,6 @@ # Give the name of a library. This will build a dynamic version. # SHARED_LIBRARY=1 -LOADABLE_MODULE = 1 -DONT_BUILD_RELINKED=1 LIBRARYNAME=poolalloc # ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r44687 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/MachineLICM.cpp lib/Target/PowerPC/PPCInstrInfo.td
On Dec 7, 2007 5:01 PM, Chris Lattner <[EMAIL PROTECTED]> wrote: > >> +// Visit all of the instructions of the loop. We want to visit > >> the subloops > >> +// first, though, so that we can hoist their invariants first > >> into their > >> +// containing loop before we process that loop. > >> +SmallVector Loops; > >> +GatherAllLoops(L, Loops); > > > > Seems to me this can be smarter. When you are gathering the loops, put > > loops of greater depth in the front of the queue then HoistRegion > > won't have to check if the BB is in the current loop level? > > This should do a simple postorder traversal of the loop nest, there > is no need to make a vector of the loops. This ensures you visit > inner loops before outer loops etc. > Doh! Yeah, it's easier to just do it without the vector. > >> + // Now move the instructions to the predecessors. > >> + for (std::vector::iterator > >> + I = Preds.begin(), E = Preds.end(); I != E; ++I) > >> +MoveInstToBlock(*I, MI.clone()); > > > > This will create multiple copies, it seems bad. Again, this should be > > fixable with a loop preheader? > > Furthermore, this won't work, you'd have to insert phi nodes etc. > You really really really don't want to do this bill. Only handle > loops that have a header with one predecessor that is outside the > loop plz, > Ah! Good point. When there's pre-headers, I'll be able to handle this much nicer. In the meantime, I'll make sure that there's only one predecessor. -bw ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r44687 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/MachineLICM.cpp lib/Target/PowerPC/PPCInstrInfo.td
> But when I set the alignment of the loop in main to 8, it got > slightly faster: > > $ time ./t.new > > real 0m15.090s > user 0m15.079s > sys 0m0.010s > > So there's some type of alignment thing that's getting in the way, but > it's encouraging for an initial pass that moved 3 instructions total. > :-) Ah right, to get stable performance and measure just the instruction change, you should align the loop top to 16 for each (just for measurment purposes) -chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r44692 - /llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
Author: evancheng
Date: Fri Dec 7 19:00:31 2007
New Revision: 44692
URL: http://llvm.org/viewvc/llvm-project?rev=44692&view=rev
Log:
Fix a compilation warning.
Modified:
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=44692&r1=44691&r2=44692&view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Fri Dec 7 19:00:31 2007
@@ -429,7 +429,7 @@
bool ARMRegisterInfo::canFoldMemoryOperand(MachineInstr *MI,
SmallVectorImpl &Ops) const
{
- if (Ops.size() != 1) return NULL;
+ if (Ops.size() != 1) return 0;
unsigned OpNum = Ops[0];
unsigned Opc = MI->getOpcode();
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[llvm-commits] [llvm-gcc-4.0] r44689 - /llvm-gcc-4.0/trunk/build_gcc
Author: void Date: Fri Dec 7 18:39:04 2007 New Revision: 44689 URL: http://llvm.org/viewvc/llvm-project?rev=44689&view=rev Log: Backport driver-driver linkage hack from 4.2 Modified: llvm-gcc-4.0/trunk/build_gcc Modified: llvm-gcc-4.0/trunk/build_gcc URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.0/trunk/build_gcc?rev=44689&r1=44688&r2=44689&view=diff == --- llvm-gcc-4.0/trunk/build_gcc (original) +++ llvm-gcc-4.0/trunk/build_gcc Fri Dec 7 18:39:04 2007 @@ -511,11 +511,17 @@ ln -s -f ../../../$DEST_ROOT/bin/llvm-gcc-$MAJ_VERS llvm-gcc-$MAJ_VERS || exit 1 ln -s -f ../../../$DEST_ROOT/bin/llvm-g++-$MAJ_VERS llvm-g++-$MAJ_VERS || exit 1 - # Copy one of the libllvmgcc.dylib's up to libexec/gcc. +# FIXME: This is a hack to get things working. +for h in $HOSTS ; do +ln -s -f ../../../$DEST_ROOT/bin/$h-apple-darwin$DARWIN_VERS-llvm-gcc-$MAJ_VERS $h-apple-darwin$DARWIN_VERS-llvm-gcc-$MAJ_VERS || exit 1 +ln -s -f ../../../$DEST_ROOT/bin/$h-apple-darwin$DARWIN_VERS-llvm-g++-$MAJ_VERS $h-apple-darwin$DARWIN_VERS-llvm-g++-$MAJ_VERS || exit 1 +done + +# Copy one of the libllvmgcc.dylib's up to libexec/gcc. cp $DEST_DIR/$DEST_ROOT/libexec/gcc/$BUILD-apple-darwin$DARWIN_VERS/$VERS/libllvmgcc.dylib \ $DEST_DIR/$DEST_ROOT/libexec/gcc/ - # Replace the installed ones with symlinks to the common one. +# Replace the installed ones with symlinks to the common one. for t in $TARGETS ; do cd $DEST_DIR/$DEST_ROOT/libexec/gcc/$t-apple-darwin$DARWIN_VERS/$VERS/ rm libllvmgcc.dylib ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r44686 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Author: evancheng
Date: Fri Dec 7 15:30:01 2007
New Revision: 44686
URL: http://llvm.org/viewvc/llvm-project?rev=44686&view=rev
Log:
Add comment.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=44686&r1=44685&r2=44686&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Dec 7 15:30:01 2007
@@ -2758,6 +2758,8 @@
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
}
+/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
+/// the two vector operands have swapped position.
static
SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
MVT::ValueType MaskVT = Mask.getValueType();
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[llvm-commits] [llvm] r44702 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/MachineLICM.cpp lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86
Author: void
Date: Sat Dec 8 01:17:56 2007
New Revision: 44702
URL: http://llvm.org/viewvc/llvm-project?rev=44702&view=rev
Log:
Renaming:
isTriviallyReMaterializable -> hasNoSideEffects
isReallyTriviallyReMaterializable -> isTriviallyReMaterializable
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/MachineLICM.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=44702&r1=44701&r2=44702&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sat Dec 8 01:17:56 2007
@@ -288,24 +288,24 @@
return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
}
- /// isTriviallyReMaterializable - Return true if the instruction is trivially
+ /// hasNoSideEffects - Return true if the instruction is trivially
/// rematerializable, meaning it has no side effects and requires no operands
/// that aren't always available.
- bool isTriviallyReMaterializable(MachineInstr *MI) const {
+ bool hasNoSideEffects(MachineInstr *MI) const {
return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) &&
- isReallyTriviallyReMaterializable(MI);
+ isTriviallyReMaterializable(MI);
}
protected:
- /// isReallyTriviallyReMaterializable - For instructions with opcodes for
- /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
- /// instruction itself is actually trivially rematerializable, considering
- /// its operands. This is used for targets that have instructions that are
- /// only trivially rematerializable for specific uses. This predicate must
- /// return false if the instruction has any side effects other than
- /// producing a value, or if it requres any address registers that are not
- /// always available.
- virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
+ /// isTriviallyReMaterializable - For instructions with opcodes for which the
+ /// M_REMATERIALIZABLE flag is set, this function tests whether the
+ /// instruction itself is actually trivially rematerializable, considering
its
+ /// operands. This is used for targets that have instructions that are only
+ /// trivially rematerializable for specific uses. This predicate must return
+ /// false if the instruction has any side effects other than producing a
+ /// value, or if it requres any address registers that are not always
+ /// available.
+ virtual bool isTriviallyReMaterializable(MachineInstr *MI) const {
return true;
}
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=44702&r1=44701&r2=44702&view=diff
==
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Sat Dec 8 01:17:56 2007
@@ -613,7 +613,7 @@
return false;
isLoad = false;
- if (tii_->isTriviallyReMaterializable(MI)) {
+ if (tii_->hasNoSideEffects(MI)) {
isLoad = MI->getInstrDescriptor()->Flags & M_LOAD_FLAG;
return true;
}
Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=44702&r1=44701&r2=44702&view=diff
==
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Sat Dec 8 01:17:56 2007
@@ -120,7 +120,7 @@
if (TID->ImplicitUses || !I.getNumOperands()) return false;
MachineOpCode Opcode = TID->Opcode;
- return TII->isTriviallyReMaterializable(&I) &&
+ return TII->hasNoSideEffects(&I) &&
// FIXME: Below necessary?
!(TII->isReturn(Opcode) ||
TII->isTerminatorInstr(Opcode) ||
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=44702&r1=44701&r2=44702&view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Dec 8 01:17:56 2007
@@ -116,7 +116,7 @@
}
-bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
+bool X86InstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: break;
case X86::MOV8rm:
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev
[llvm-commits] [llvm] r44690 - /llvm/trunk/win32/CodeGen/CodeGen.vcproj
Author: cfr Date: Fri Dec 7 18:53:13 2007 New Revision: 44690 URL: http://llvm.org/viewvc/llvm-project?rev=44690&view=rev Log: Adding MachineLoopInfo.h,.cpp and MachineLICP.cpp to VStudio build Modified: llvm/trunk/win32/CodeGen/CodeGen.vcproj Modified: llvm/trunk/win32/CodeGen/CodeGen.vcproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/CodeGen/CodeGen.vcproj?rev=44690&r1=44689&r2=44690&view=diff == --- llvm/trunk/win32/CodeGen/CodeGen.vcproj (original) +++ llvm/trunk/win32/CodeGen/CodeGen.vcproj Fri Dec 7 18:53:13 2007 @@ -377,6 +377,14 @@ > + + + + @@ -603,6 +611,10 @@ > + + ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r44691 - /llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
Author: evancheng
Date: Fri Dec 7 19:00:21 2007
New Revision: 44691
URL: http://llvm.org/viewvc/llvm-project?rev=44691&view=rev
Log:
Fix a compilation warning.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=44691&r1=44690&r2=44691&view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri Dec 7 19:00:21 2007
@@ -615,7 +615,7 @@
bool PPCRegisterInfo::canFoldMemoryOperand(MachineInstr *MI,
SmallVectorImpl &Ops) const
{
- if (Ops.size() != 1) return NULL;
+ if (Ops.size() != 1) return false;
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
// it takes more than one instruction to store it.
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Re: [llvm-commits] [llvm] r44687 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/MachineLICM.cpp lib/Target/PowerPC/PPCInstrInfo.td
On Dec 7, 2007 2:24 PM, Chris Lattner <[EMAIL PROTECTED]> wrote:
>
> I know you're kidding, but have you benchmarked this on the G5? In
> this specific case, "foo" is probably MUCH faster because the loop is
> one dispatch group instead of two (I think). :)
>
It made this program slower:
$ cat t.c
#include
#define SIZE 10
int arr[SIZE];
__attribute__((noinline)) void foo(int *arr, unsigned size) {
unsigned i = 0;
do {
arr[i++] = 0;
} while (i < size);
}
int main() {
int i;
for (i = 0; i < SIZE; ++i)
foo(arr, SIZE);
return 0;
}
$ time ./t.old
real0m15.107s
user0m15.095s
sys 0m0.012s
$ time ./t.new
real0m20.088s
user0m20.075s
sys 0m0.013s
But when I set the alignment of the loop in main to 8, it got slightly faster:
$ time ./t.new
real0m15.090s
user0m15.079s
sys 0m0.010s
So there's some type of alignment thing that's getting in the way, but
it's encouraging for an initial pass that moved 3 instructions total.
:-)
-bw
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Re: [llvm-commits] [llvm] r44676 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2007-12-05-VectorShuffle.ll test/CodeGen/X86/vec_shuffle-12.ll
On Dec 7, 2007, at 8:13 AM, Chris Lattner wrote:
> Hey Evan,
>
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Dec 7
>> 02:07:39 2007
>> @@ -2754,10 +2754,33 @@
>> }
>>
>> std::swap(V1, V2);
>> - Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],
>> MaskVec.size());
>> + Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],
>> NumElems);
>> return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
>> }
>>
>> +static
>> +SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG
>> &DAG) {
>
> Please add a comment over this that gives an example of what it
> does. I kept misreading the name as "compute..." and couldn't figure
> out what it did :)
Ok.
>
>
>> +static
>> +SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
>> + SDOperand PermMask,
>> SelectionDAG &DAG,
>> + TargetLowering &TLI) {
>
> Does this cause any pessimizations for v8i16 shuffles that could be
> done as v4i32?
No. Because the lowering before this patch is even worse. :-) I plan
on improving this further.
Evan
>
>
> -Chris
>
>
>
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Re: [llvm-commits] [llvm] r44687 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/MachineLICM.cpp lib/Target/PowerPC/PPCInstrInfo.td
On Dec 7, 2007, at 1:42 PM, Bill Wendling wrote:
>
>
> _foo:
>li r2, 0
> LBB1_1: ; bb
>li r5, 0
>stw r5, 0(r3)
>addi r2, r2, 1
>addi r3, r3, 4
>cmplw cr0, r2, r4
>bne cr0, LBB1_1 ; bb
> LBB1_2: ; return
>blr
>
> to:
>
> _foo:
>li r2, 0
>li r5, 0
> LBB1_1: ; bb
>stw r5, 0(r3)
>addi r2, r2, 1
>addi r3, r3, 4
>cmplw cr0, r2, r4
>bne cr0, LBB1_1 ; bb
> LBB1_2: ; return
>blr
>
> ZOMG!! :-)
Nicely done!
>
> +
> +#define DEBUG_TYPE "machine-licm"
> +#include "llvm/ADT/SmallVector.h"
> +#include "llvm/ADT/Statistic.h"
> +#include "llvm/CodeGen/MachineBasicBlock.h"
> +#include "llvm/CodeGen/MachineDominators.h"
> +#include "llvm/CodeGen/MachineInstr.h"
> +#include "llvm/CodeGen/MachineLoopInfo.h"
> +#include "llvm/CodeGen/Passes.h"
> +#include "llvm/Target/TargetInstrInfo.h"
> +#include "llvm/Support/CFG.h"
> +#include "llvm/Support/CommandLine.h"
> +#include "llvm/Support/Compiler.h"
> +#include "llvm/Support/Debug.h"
> +#include "llvm/Target/MRegisterInfo.h"
> +#include "llvm/Target/TargetMachine.h"
> +#include
> +
> +using namespace llvm;
> +
> +namespace {
> + // Hidden options to help debugging
> + cl::opt
> + PerformLICM("machine-licm",
> + cl::init(false), cl::Hidden);
> +}
> +
> +namespace {
> + class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass {
> +// Various analyses that we use...
> +MachineLoopInfo *LI; // Current MachineLoopInfo
> +MachineDominatorTree *DT; // Machine dominator tree for the
> current Loop
> +
> +const TargetInstrInfo *TII;
> +
> +// State that is updated as we process loops
> +bool Changed; // True if a loop is changed.
> +MachineLoop *CurLoop; // The current loop we are working
> on.
> +
> +// Map the def of a virtual register to the machine instruction.
> +std::map VRegDefs;
Consider using IndexedMap.
>
> + public:
> +static char ID; // Pass identification, replacement for typeid
> +MachineLICM() : MachineFunctionPass((intptr_t)&ID) {}
> +
> +virtual bool runOnMachineFunction(MachineFunction &MF);
> +
> +/// FIXME: Loop preheaders?
> +///
> +virtual void getAnalysisUsage(AnalysisUsage &AU) const {
> + AU.setPreservesCFG();
> + AU.addRequired();
> + AU.addRequired();
> +}
> + private:
> +/// GatherAllLoops - Get all loops in depth first order.
> +///
> +void GatherAllLoops(MachineLoop *L,
> SmallVectorImpl &Loops) {
> + const std::vector &SubLoops = L->getSubLoops();
> +
> + for (MachineLoop::iterator
> + I = SubLoops.begin(), E = SubLoops.end(); I != E; ++I)
> +GatherAllLoops(*I, Loops);
> +
> + Loops.push_back(L);
> +}
> +
> +/// MapVirtualRegisterDefs - Create a map of which machine
> instruction
> +/// defines a virtual register.
> +///
> +void MapVirtualRegisterDefs(const MachineFunction &MF);
> +
> +/// isInSubLoop - A little predicate that returns true if the
> specified
> +/// basic block is in a subloop of the current one, not the
> current one
> +/// itself.
> +///
> +bool isInSubLoop(MachineBasicBlock *BB) {
> + assert(CurLoop->contains(BB) && "Only valid if BB is IN the
> loop");
> +
> + for (MachineLoop::iterator
> + I = CurLoop->begin(), E = CurLoop->end(); I != E; ++I)
> +if ((*I)->contains(BB))
> + return true; // A subloop actually contains this block!
> +
> + return false;
> +}
> +
> +/// CanHoistInst - Checks that this instructions is one that
> can be hoisted
> +/// out of the loop. I.e., it has no side effects, isn't a
> control flow
> +/// instr, etc.
> +///
> +bool CanHoistInst(MachineInstr &I) const {
> + const TargetInstrDescriptor *TID = I.getInstrDescriptor();
> + MachineOpCode Opcode = TID->Opcode;
> +
> + return TII->isTriviallyReMaterializable(&I) &&
> +// FIXME: Below necessary?
> +!(TII->isReturn(Opcode) ||
> + TII->isTerminatorInstr(Opcode) ||
> + TII->isBranch(Opcode) ||
> + TII->isIndirectBranch(Opcode) ||
> + TII->isBarrier(Opcode) ||
> + TII->isCall(Opcode) ||
> + TII->isLoad(Opcode) || // TODO: Do loads and stores.
> + TII->isStore(Opcode));
> +}
Since you are touching this... When you have a chance, please rename
it to something like hasNoSideEffect().
>
> +
> +/// isLoopInvariantInst - Returns true if the instruction is loop
> +/// invariant. I.e., all virtual register operands are defined
> outside of
> +/// the loop, physical registers aren't accessed (explicitly or
> implicitly),
> +/// and the instruction is hoistable.
> +///
> +bool isLoopInvariantInst(MachineInstr &I);
> +
> +/// FindPredecessors - Get all of the predecessors of the loop
> that are not
> +///
