[llvm-commits] [llvm] r40965 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Author: johannes
Date: Thu Aug 9 12:27:48 2007
New Revision: 40965
URL: http://llvm.org/viewvc/llvm-project?rev=40965&view=rev
Log:
Update per review comments.
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=40965&r1=40964&r2=40965&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Aug 9 12:27:48 2007
@@ -333,8 +333,8 @@
/// for it.
LegalizeAction
getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
-if (MVT::isExtendedVT(ToVT) || MVT::isExtendedVT(FromVT))
- return Expand;
+assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 &&
+ "Table isn't big enough!");
return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=40965&r1=40964&r2=40965&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Aug 9 12:27:48 2007
@@ -3194,51 +3194,36 @@
}
break;
- case ISD::FP_EXTEND: {
- MVT::ValueType newVT = Op.getValueType();
- MVT::ValueType oldVT = Op.getOperand(0).getValueType();
- if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
-// The only way we can lower this is to turn it into a STORE,
-// EXTLOAD pair, targetting a temporary location (a stack slot).
-
-// NOTE: there is a choice here between constantly creating new stack
-// slots and always reusing the same one. We currently always create
-// new ones, as reuse may inhibit scheduling.
-const Type *Ty = MVT::getTypeForValueType(oldVT);
-uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
-unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
-MachineFunction &MF = DAG.getMachineFunction();
-int SSFI =
- MF.getFrameInfo()->CreateStackObject(TySize, Align);
-SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
-Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
- StackSlot, NULL, 0);
-Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
- Result, StackSlot, NULL, 0, oldVT);
-break;
- }
-}
-// FALL THROUGH (to ANY_EXTEND case)
+ case ISD::FP_EXTEND:
case ISD::FP_ROUND: {
MVT::ValueType newVT = Op.getValueType();
MVT::ValueType oldVT = Op.getOperand(0).getValueType();
if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
-// The only way we can lower this is to turn it into a TRUNCSTORE,
+// The only way we can lower this is to turn it into a STORE,
// LOAD pair, targetting a temporary location (a stack slot).
// NOTE: there is a choice here between constantly creating new stack
// slots and always reusing the same one. We currently always create
// new ones, as reuse may inhibit scheduling.
-const Type *Ty = MVT::getTypeForValueType(newVT);
+MVT::ValueType slotVT =
+(Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
+const Type *Ty = MVT::getTypeForValueType(slotVT);
uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
MachineFunction &MF = DAG.getMachineFunction();
int SSFI =
MF.getFrameInfo()->CreateStackObject(TySize, Align);
SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
-Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
- StackSlot, NULL, 0, newVT);
-Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT);
+if (Node->getOpcode() == ISD::FP_EXTEND) {
+ Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
+ StackSlot, NULL, 0);
+ Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
+ Result, StackSlot, NULL, 0, oldVT);
+} else {
+ Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
+ StackSlot, NULL, 0, newVT);
+ Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT);
+}
break;
}
}
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[llvm-commits] [llvm] r40970 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Author: evancheng
Date: Thu Aug 9 13:05:17 2007
New Revision: 40970
URL: http://llvm.org/viewvc/llvm-project?rev=40970&view=rev
Log:
GR16_ sub-register class should be GR8_, not GR8. That is, it should only be
8-bit registers in 32-bit mode. Ditto for GR32_.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=40970&r1=40969&r2=40970&view=diff
==
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Thu Aug 9 13:05:17 2007
@@ -417,13 +417,14 @@
}
-// GR16, GR32 subclasses which contain registers that have R8 sub-registers.
+// GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
// These should only be used for 32-bit mode.
+def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL, AH, CH, DH, BH]>;
def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
- let SubRegClassList = [GR8];
+ let SubRegClassList = [GR8_];
}
def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
- let SubRegClassList = [GR8, GR16];
+ let SubRegClassList = [GR8_, GR16_];
}
// Scalar SSE2 floating point registers.
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[llvm-commits] [llvm] r40971 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/align-inc.ll
Author: lattner
Date: Thu Aug 9 14:05:49 2007
New Revision: 40971
URL: http://llvm.org/viewvc/llvm-project?rev=40971&view=rev
Log:
when we see a unaligned load from an insufficiently aligned global or
alloca, increase the alignment of the load, turning it into an aligned load.
This allows us to compile:
#include
__m128i foo(__m128i x){
static const unsigned int c_0[4] = { 0, 0, 0, 0 };
__m128i v_Zero = _mm_loadu_si128((__m128i*)c_0);
x = _mm_unpacklo_epi8(x, v_Zero);
return x;
}
into:
_foo:
punpcklbw _c_0.5944, %xmm0
ret
.data
.lcomm _c_0.5944,16,4 # c_0.5944
instead of:
_foo:
movdqu _c_0.5944, %xmm1
punpcklbw %xmm1, %xmm0
ret
.data
.lcomm _c_0.5944,16,2 # c_0.5944
Added:
llvm/trunk/test/Transforms/InstCombine/align-inc.ll
Modified:
llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=40971&r1=40970&r2=40971&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Thu Aug 9
14:05:49 2007
@@ -7492,13 +7492,23 @@
return 0;
}
-/// GetKnownAlignment - If the specified pointer has an alignment that we can
-/// determine, return it, otherwise return 0.
-static unsigned GetKnownAlignment(Value *V, TargetData *TD) {
+/// GetOrEnforceKnownAlignment - If the specified pointer has an alignment that
+/// we can determine, return it, otherwise return 0. If PrefAlign is
specified,
+/// and it is more than the alignment of the ultimate object, see if we can
+/// increase the alignment of the ultimate object, making this check succeed.
+static unsigned GetOrEnforceKnownAlignment(Value *V, TargetData *TD,
+ unsigned PrefAlign = 0) {
if (GlobalVariable *GV = dyn_cast(V)) {
unsigned Align = GV->getAlignment();
if (Align == 0 && TD)
Align = TD->getPrefTypeAlignment(GV->getType()->getElementType());
+
+// If there is a large requested alignment and we can, bump up the
alignment
+// of the global.
+if (PrefAlign > Align && GV->hasInitializer()) {
+ GV->setAlignment(PrefAlign);
+ Align = PrefAlign;
+}
return Align;
} else if (AllocationInst *AI = dyn_cast(V)) {
unsigned Align = AI->getAlignment();
@@ -7516,18 +7526,20 @@
(unsigned)TD->getABITypeAlignment(Type::Int64Ty));
}
}
+
+// If there is a requested alignment and if this is an alloca, round up.
We
+// don't do this for malloc, because some systems can't respect the
request.
+if (PrefAlign > Align && isa(AI)) {
+ AI->setAlignment(PrefAlign);
+ Align = PrefAlign;
+}
return Align;
} else if (isa(V) ||
(isa(V) &&
cast(V)->getOpcode() == Instruction::BitCast)) {
-User *CI = cast(V);
-if (isa(CI->getOperand(0)->getType()))
- return GetKnownAlignment(CI->getOperand(0), TD);
-return 0;
+return GetOrEnforceKnownAlignment(cast(V)->getOperand(0),
+ TD, PrefAlign);
} else if (User *GEPI = dyn_castGetElementPtr(V)) {
-unsigned BaseAlignment = GetKnownAlignment(GEPI->getOperand(0), TD);
-if (BaseAlignment == 0) return 0;
-
// If all indexes are zero, it is just the alignment of the base pointer.
bool AllZeroOperands = true;
for (unsigned i = 1, e = GEPI->getNumOperands(); i != e; ++i)
@@ -7536,9 +7548,15 @@
AllZeroOperands = false;
break;
}
-if (AllZeroOperands)
- return BaseAlignment;
-
+
+if (AllZeroOperands) {
+ // Treat this like a bitcast.
+ return GetOrEnforceKnownAlignment(GEPI->getOperand(0), TD, PrefAlign);
+}
+
+unsigned BaseAlignment =
GetOrEnforceKnownAlignment(GEPI->getOperand(0),TD);
+if (BaseAlignment == 0) return 0;
+
// Otherwise, if the base alignment is >= the alignment we expect for the
// base pointer type, then we know that the resultant pointer is aligned at
// least as much as its type requires.
@@ -7608,15 +7626,15 @@
// If we can determine a pointer alignment that is bigger than currently
// set, update the alignment.
if (isa(MI) || isa(MI)) {
- unsigned Alignment1 = GetKnownAlignment(MI->getOperand(1), TD);
- unsigned Alignment2 = GetKnownAlignment(MI->getOperand(2), TD);
+ unsigned Alignment1 = GetOrEnforceKnownAlignment(MI->getOperand(1), TD);
+ unsigned Alignment2 = GetOrEnforceKnownAlignment(MI->getOperand(2), TD);
unsigned Align = std::min(Alignment1, Alignment2);
if (MI->getAlignment()->getZExtValue() < Align) {
MI->setAlignment(ConstantInt::ge
Re: [llvm-commits] [llvm] r40970 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Evan,
I don't think that this change is working quite correctly, and may
not be needed, given the way that the subreg code uses those values.
This is currently causing regressions in dejagnu.
The register classes in the SubRegClassList are used when new subreg
vregs are created. The key is that the register class be valid for
the register-register mappings in the SubRegSet of the corresponding
index, that is that the all the subregs of the class must be members
of the SubRegClass, not that the sets must be equal.
Every subreg of GR16_ is a member of GR8, and every subreg of GR32_
is properly a member of GR8 or GR16.
--
Chris
On Aug 9, 2007, at 11:05 AM, Evan Cheng wrote:
Author: evancheng
Date: Thu Aug 9 13:05:17 2007
New Revision: 40970
URL: http://llvm.org/viewvc/llvm-project?rev=40970&view=rev
Log:
GR16_ sub-register class should be GR8_, not GR8. That is, it
should only be 8-bit registers in 32-bit mode. Ditto for GR32_.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/
X86RegisterInfo.td?rev=40970&r1=40969&r2=40970&view=diff
==
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Thu Aug 9
13:05:17 2007
@@ -417,13 +417,14 @@
}
-// GR16, GR32 subclasses which contain registers that have R8 sub-
registers.
+// GR16, GR32 subclasses which contain registers that have GR8 sub-
registers.
// These should only be used for 32-bit mode.
+def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL, AH, CH,
DH, BH]>;
def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
- let SubRegClassList = [GR8];
+ let SubRegClassList = [GR8_];
}
def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
- let SubRegClassList = [GR8, GR16];
+ let SubRegClassList = [GR8_, GR16_];
}
// Scalar SSE2 floating point registers.
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[llvm-commits] [llvm] r40972 - in /llvm/trunk/lib/Target/X86: README-X86-64.txt X86ISelDAGToDAG.cpp
Author: evancheng
Date: Thu Aug 9 16:59:35 2007
New Revision: 40972
URL: http://llvm.org/viewvc/llvm-project?rev=40972&view=rev
Log:
divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the
instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift
right by 8 on AX and then truncate it to 8 bits instead.
Modified:
llvm/trunk/lib/Target/X86/README-X86-64.txt
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/README-X86-64.txt
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-X86-64.txt?rev=40972&r1=40971&r2=40972&view=diff
==
--- llvm/trunk/lib/Target/X86/README-X86-64.txt (original)
+++ llvm/trunk/lib/Target/X86/README-X86-64.txt Thu Aug 9 16:59:35 2007
@@ -221,3 +221,16 @@
instruction. We should probably introduce something like AbsoluteAddress to
distinguish it from GlobalAddress so the asm printer and JIT code emitter can
do the right thing.
+
+//===-===//
+
+It's not possible to reference AH, BH, CH, and DH registers in an instruction
+requiring REX prefix. However, divb and mulb both produce results in AH. If
isel
+emits a CopyFromReg which gets turned into a movb and that can be allocated a
+r8b - r15b.
+
+To get around this, isel emits a CopyFromReg from AX and then right shift it
+down by 8 and truncate it. It's not pretty but it works. We need some register
+allocation magic to make the hack go away (e.g. putting additional constraints
+on the result of the movb).
+
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=40972&r1=40971&r2=40972&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Aug 9 16:59:35 2007
@@ -1159,7 +1159,21 @@
SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
- SDOperand Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
+ SDOperand Result;
+ if (HiReg == X86::AH && Subtarget->is64Bit()) {
+// Prevent use of AH in a REX instruction by referencing AX instead.
+// Shift it down 8 bits.
+Result = CurDAG->getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
+Chain = Result.getValue(1);
+Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16,
Result,
+ CurDAG->getTargetConstant(8, MVT::i8)),
0);
+// Then truncate it down to i8.
+SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet
1
+Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
+ MVT::i8, Result, SRIdx), 0);
+ } else {
+Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
+ }
ReplaceUses(N.getValue(0), Result);
if (foldedLoad)
ReplaceUses(N1.getValue(1), Result.getValue(1));
@@ -1286,11 +1300,26 @@
SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
- SDOperand Result =
-CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg, NVT, InFlag);
+ unsigned Reg = isDiv ? LoReg : HiReg;
+ SDOperand Result;
+ if (Reg == X86::AH && Subtarget->is64Bit()) {
+// Prevent use of AH in a REX instruction by referencing AX instead.
+// Shift it down 8 bits.
+Result = CurDAG->getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
+Chain = Result.getValue(1);
+Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16,
Result,
+ CurDAG->getTargetConstant(8, MVT::i8)),
0);
+// Then truncate it down to i8.
+SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet
1
+Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
+ MVT::i8, Result, SRIdx), 0);
+ } else {
+Result = CurDAG->getCopyFromReg(Chain, Reg, NVT, InFlag);
+Chain = Result.getValue(1);
+ }
ReplaceUses(N.getValue(0), Result);
if (foldedLoad)
-ReplaceUses(N1.getValue(1), Result.getValue(1));
+ReplaceUses(N1.getValue(1), Chain);
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
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Re: [llvm-commits] [llvm] r40970 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td
On Aug 9, 2007, at 2:45 PM, Christopher Lamb wrote:
Evan,
I don't think that this change is working quite correctly, and may
not be needed, given the way that the subreg code uses those values.
This is currently causing regressions in dejagnu.
The register classes in the SubRegClassList are used when new subreg
vregs are created. The key is that the register class be valid for
the register-register mappings in the SubRegSet of the corresponding
index, that is that the all the subregs of the class must be members
of the SubRegClass, not that the sets must be equal.
Every subreg of GR16_ is a member of GR8, and every subreg of GR32_
is properly a member of GR8 or GR16.
Hi Chris,
Sorry, I am not following. Given GR16_ contains only AX, CX, DX, and
BX. How can its subregister class contains GR8 (which includes
register like R8B, SIL) that have no relationship with AX, etc.
I am ok with backing out the patch for now. But something else seems
wrong.
Evan
--
Chris
On Aug 9, 2007, at 11:05 AM, Evan Cheng wrote:
Author: evancheng
Date: Thu Aug 9 13:05:17 2007
New Revision: 40970
URL: http://llvm.org/viewvc/llvm-project?rev=40970&view=rev
Log:
GR16_ sub-register class should be GR8_, not GR8. That is, it
should only be 8-bit registers in 32-bit mode. Ditto for GR32_.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=40970&r1=40969&r2=40970&view=diff
=
=
=
=
=
=
=
=
=
=
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Thu Aug 9
13:05:17 2007
@@ -417,13 +417,14 @@
}
-// GR16, GR32 subclasses which contain registers that have R8 sub-
registers.
+// GR16, GR32 subclasses which contain registers that have GR8 sub-
registers.
// These should only be used for 32-bit mode.
+def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL, AH, CH,
DH, BH]>;
def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
- let SubRegClassList = [GR8];
+ let SubRegClassList = [GR8_];
}
def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
- let SubRegClassList = [GR8, GR16];
+ let SubRegClassList = [GR8_, GR16_];
}
// Scalar SSE2 floating point registers.
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[llvm-commits] [llvm] r40973 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Author: evancheng
Date: Thu Aug 9 17:25:35 2007
New Revision: 40973
URL: http://llvm.org/viewvc/llvm-project?rev=40973&view=rev
Log:
Temporarily backing out this change until we know why some dejagnu tests are
failing.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=40973&r1=40972&r2=40973&view=diff
==
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Thu Aug 9 17:25:35 2007
@@ -419,12 +419,11 @@
// GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
// These should only be used for 32-bit mode.
-def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL, AH, CH, DH, BH]>;
def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
- let SubRegClassList = [GR8_];
+ let SubRegClassList = [GR8];
}
def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
- let SubRegClassList = [GR8_, GR16_];
+ let SubRegClassList = [GR8, GR16];
}
// Scalar SSE2 floating point registers.
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Re: [llvm-commits] [llvm] r40970 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td
On Aug 9, 2007, at 3:20 PM, Evan Cheng wrote:
On Aug 9, 2007, at 2:45 PM, Christopher Lamb wrote:
Evan,
I don't think that this change is working quite correctly, and may
not be needed, given the way that the subreg code uses those
values. This is currently causing regressions in dejagnu.
The register classes in the SubRegClassList are used when new
subreg vregs are created. The key is that the register class be
valid for the register-register mappings in the SubRegSet of the
corresponding index, that is that the all the subregs of the class
must be members of the SubRegClass, not that the sets must be equal.
Every subreg of GR16_ is a member of GR8, and every subreg of
GR32_ is properly a member of GR8 or GR16.
Hi Chris,
Sorry, I am not following. Given GR16_ contains only AX, CX, DX,
and BX. How can its subregister class contains GR8 (which includes
register like R8B, SIL) that have no relationship with AX, etc.
GR16_ contains only [AX, CX, DX, BX], this means that only valid
SubRegSets (1) are [AL, CL, DL, BL] which are all members of GR8.
Constraining the superreg to GR16_ is necessary, but constraining the
subreg in a new class other than GR8 is not.
I am ok with backing out the patch for now. But something else
seems wrong.
EXTRACT_SUBREG needs to know what register class to use to create new
vregs during ScheduleDAG. If the register class that EXTRACT_SUBREG
produces doesn't match the input register class of the consuming
instruction then you get the errors that your patch created. You have
EXTRACT_SUBREG producing GR8_ vregs and target instructions expecting
to use a GR8. To get around this you could have a MOVGR#_toGR#
instruction placed after every use of EXTRACT_SUBREG, but that'd be
moving from a subclass to a superclass which can always be eliminated
(i.e MOV GR8_ -> GR8 is not necessary because all of GR8_ are already
in GR8).
Hope that helps explain it.
--
Chris
On Aug 9, 2007, at 11:05 AM, Evan Cheng wrote:
Author: evancheng
Date: Thu Aug 9 13:05:17 2007
New Revision: 40970
URL: http://llvm.org/viewvc/llvm-project?rev=40970&view=rev
Log:
GR16_ sub-register class should be GR8_, not GR8. That is, it
should only be 8-bit registers in 32-bit mode. Ditto for GR32_.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
X86/X86RegisterInfo.td?rev=40970&r1=40969&r2=40970&view=diff
==
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Thu Aug 9
13:05:17 2007
@@ -417,13 +417,14 @@
}
-// GR16, GR32 subclasses which contain registers that have R8
sub-registers.
+// GR16, GR32 subclasses which contain registers that have GR8
sub-registers.
// These should only be used for 32-bit mode.
+def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL, AH,
CH, DH, BH]>;
def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
- let SubRegClassList = [GR8];
+ let SubRegClassList = [GR8_];
}
def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
- let SubRegClassList = [GR8, GR16];
+ let SubRegClassList = [GR8_, GR16_];
}
// Scalar SSE2 floating point registers.
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--
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[llvm-commits] [llvm] r40974 - in /llvm/trunk/lib: Bitcode/Reader/BitcodeReader.cpp Bitcode/Writer/BitcodeWriter.cpp VMCore/Constants.cpp
Author: johannes
Date: Thu Aug 9 17:51:36 2007
New Revision: 40974
URL: http://llvm.org/viewvc/llvm-project?rev=40974&view=rev
Log:
Patch 10 for long double. Doing constants right needs expanding ConstantFP
to handle values bigger than double. If we assume host==target and host
long double works correctly, this is not too bad, but we don't want to
have that limitation longterm. I could implement accepting double
constants as long double or something like that, which would lead to
incorrect codegen with no errors; the more I think about that the worse
it seems. Rather than do such a hack that would be backed out later,
I'm settling for giving reasonable error messages, for now.
Modified:
llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/trunk/lib/VMCore/Constants.cpp
Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=40974&r1=40973&r2=40974&view=diff
==
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Thu Aug 9 17:51:36 2007
@@ -629,6 +629,10 @@
V = ConstantFP::get(CurTy, BitsToFloat(Record[0]));
else if (CurTy == Type::DoubleTy)
V = ConstantFP::get(CurTy, BitsToDouble(Record[0]));
+ // FIXME: Make long double constants work.
+ else if (CurTy == Type::X86_FP80Ty ||
+ CurTy == Type::FP128Ty || CurTy == Type::PPC_FP128Ty)
+assert(0 && "Long double constants not handled yet.");
else
V = UndefValue::get(CurTy);
break;
Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=40974&r1=40973&r2=40974&view=diff
==
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Thu Aug 9 17:51:36 2007
@@ -525,11 +525,17 @@
}
} else if (const ConstantFP *CFP = dyn_cast(C)) {
Code = bitc::CST_CODE_FLOAT;
- if (CFP->getType() == Type::FloatTy) {
+ const Type *Ty = CFP->getType();
+ if (Ty == Type::FloatTy) {
Record.push_back(FloatToBits((float)CFP->getValue()));
- } else {
-assert (CFP->getType() == Type::DoubleTy && "Unknown FP type!");
+ } else if (Ty == Type::DoubleTy) {
Record.push_back(DoubleToBits((double)CFP->getValue()));
+ // FIXME: make long double constants work.
+ } else if (Ty == Type::X86_FP80Ty ||
+ Ty == Type::FP128Ty || Ty == Type::PPC_FP128Ty) {
+assert (0 && "Long double constants not handled yet.");
+ } else {
+assert (0 && "Unknown FP type!");
}
} else if (isa(C) && cast(C)->isString()) {
// Emit constant strings specially.
Modified: llvm/trunk/lib/VMCore/Constants.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=40974&r1=40973&r2=40974&view=diff
==
--- llvm/trunk/lib/VMCore/Constants.cpp (original)
+++ llvm/trunk/lib/VMCore/Constants.cpp Thu Aug 9 17:51:36 2007
@@ -108,6 +108,9 @@
return ConstantInt::get(Ty, 0);
case Type::FloatTyID:
case Type::DoubleTyID:
+ case Type::X86_FP80TyID:
+ case Type::PPC_FP128TyID:
+ case Type::FP128TyID:
return ConstantFP::get(Ty, 0.0);
case Type::PointerTyID:
return ConstantPointerNull::get(cast(Ty));
@@ -288,12 +291,17 @@
ConstantFP *&Slot = (*FloatConstants)[std::make_pair(IntVal, Ty)];
if (Slot) return Slot;
return Slot = new ConstantFP(Ty, (float)V);
- } else {
-assert(Ty == Type::DoubleTy);
+ } else if (Ty == Type::DoubleTy) {
uint64_t IntVal = DoubleToBits(V);
ConstantFP *&Slot = (*DoubleConstants)[std::make_pair(IntVal, Ty)];
if (Slot) return Slot;
return Slot = new ConstantFP(Ty, V);
+ // FIXME: Make long double constants work.
+ } else if (Ty == Type::X86_FP80Ty ||
+ Ty == Type::PPC_FP128Ty || Ty == Type::FP128Ty) {
+assert(0 && "Long double constants not handled yet.");
+ } else {
+assert(0 && "Unknown FP Type!");
}
}
@@ -696,10 +704,13 @@
default:
return false; // These can't be represented as floating point!
-// TODO: Figure out how to test if a double can be cast to a float!
+// TODO: Figure out how to test if we can use a shorter type instead!
case Type::FloatTyID:
case Type::DoubleTyID:
-return true; // This is the largest type...
+ case Type::X86_FP80TyID:
+ case Type::PPC_FP128TyID:
+ case Type::FP128TyID:
+return true;
}
}
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Re: [llvm-commits] [llvm] r40974 - in /llvm/trunk/lib: Bitcode/Reader/BitcodeReader.cpp Bitcode/Writer/BitcodeWriter.cpp VMCore/Constants.cpp
> Patch 10 for long double. Doing constants right needs expanding
> ConstantFP
> to handle values bigger than double. If we assume host==target and
> host
> long double works correctly, this is not too bad, but we don't want to
> have that limitation longterm. I could implement accepting double
> constants as long double or something like that, which would lead to
> incorrect codegen with no errors; the more I think about that the
> worse
> it seems. Rather than do such a hack that would be backed out later,
> I'm settling for giving reasonable error messages, for now.
Using host long double is an acceptable hack for now. Alternatively:
> ==
>
> --- llvm/trunk/lib/VMCore/Constants.cpp (original)
> +++ llvm/trunk/lib/VMCore/Constants.cpp Thu Aug 9 17:51:36 2007
> @@ -288,12 +291,17 @@
> ConstantFP *&Slot = (*FloatConstants)[std::make_pair(IntVal,
> Ty)];
> if (Slot) return Slot;
> return Slot = new ConstantFP(Ty, (float)V);
> + } else if (Ty == Type::DoubleTy) {
> uint64_t IntVal = DoubleToBits(V);
> ConstantFP *&Slot = (*DoubleConstants)[std::make_pair(IntVal,
> Ty)];
> if (Slot) return Slot;
> return Slot = new ConstantFP(Ty, V);
> + // FIXME: Make long double constants work.
> + } else if (Ty == Type::X86_FP80Ty ||
> + Ty == Type::PPC_FP128Ty || Ty == Type::FP128Ty) {
> +assert(0 && "Long double constants not handled yet.");
You could just treat these like doubles for now:
> uint64_t IntVal = DoubleToBits(V);
> ConstantFP *&Slot = (*DoubleConstants)[std::make_pair(IntVal,
> Ty)];
> if (Slot) return Slot;
> return Slot = new ConstantFP(Ty, V);
This gives you the correct value, but loses the long double
precision. Seems a better short term hack than just asserting :)
-Chris
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[llvm-commits] [llvm] r40975 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Author: evancheng Date: Thu Aug 9 18:14:39 2007 New Revision: 40975 URL: http://llvm.org/viewvc/llvm-project?rev=40975&view=rev Log: Bug fix. ~1U marks the val# dead. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=40975&r1=40974&r2=40975&view=diff == --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Aug 9 18:14:39 2007 @@ -645,7 +645,7 @@ // Otherwise, use the specified value #. LHSValNoAssignments[VN] = RHSValID; if (VN != (unsigned)RHSValID) -ValueNumberInfo[VN].def = RHSValNoInfo.def; +ValueNumberInfo[VN]->def = ~1U; // Now this val# is dead. else ValueNumberInfo[VN] = RHSValNoInfo; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r40975 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
> -ValueNumberInfo[VN].def = RHSValNoInfo.def; > +ValueNumberInfo[VN]->def = ~1U; // Now this val# is > dead. Is .def equivalent to ->def here, or is this another change? ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r40975 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Something else changed. But not checked in. :-) Will fix. Thx. Evan On Aug 9, 2007, at 4:19 PM, Dale Johannesen wrote: > >> -ValueNumberInfo[VN].def = RHSValNoInfo.def; >> +ValueNumberInfo[VN]->def = ~1U; // Now this val# is >> dead. > > Is .def equivalent to ->def here, or is this another change? > > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40976 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Author: lattner Date: Thu Aug 9 18:55:17 2007 New Revision: 40976 URL: http://llvm.org/viewvc/llvm-project?rev=40976&view=rev Log: unbreak the build Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=40976&r1=40975&r2=40976&view=diff == --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Aug 9 18:55:17 2007 @@ -645,7 +645,7 @@ // Otherwise, use the specified value #. LHSValNoAssignments[VN] = RHSValID; if (VN != (unsigned)RHSValID) -ValueNumberInfo[VN]->def = ~1U; // Now this val# is dead. +ValueNumberInfo[VN].def = ~1U; // Now this val# is dead. else ValueNumberInfo[VN] = RHSValNoInfo; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r40974 - in /llvm/trunk/lib: Bitcode/Reader/BitcodeReader.cpp Bitcode/Writer/BitcodeWriter.cpp VMCore/Constants.cpp
On Aug 9, 2007, at 4:58 PM, Chris Lattner wrote: > Using host long double is an acceptable hack for now. Alternatively: OK, I'll do that. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40979 - /llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
Author: dpatel
Date: Thu Aug 9 19:59:03 2007
New Revision: 40979
URL: http://llvm.org/viewvc/llvm-project?rev=40979&view=rev
Log:
Remove unncessary duplication.
Modified:
llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=40979&r1=40978&r2=40979&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Thu Aug 9 19:59:03 2007
@@ -379,19 +379,6 @@
if (SD.SplitCondition->getParent() != Header)
return false;
- // If one of the Header block's successor is not an exit block then this
- // loop is not a suitable candidate.
- BasicBlock *ExitBlock = NULL;
- for (succ_iterator SI = succ_begin(Header), E = succ_end(Header); SI != E;
++SI) {
-if (L->isLoopExit(*SI)) {
- ExitBlock = *SI;
- break;
-}
- }
-
- if (!ExitBlock)
-return false;
-
// If loop header includes loop variant instruction operands then
// this loop may not be eliminated.
if (!safeHeader(SD, Header))
@@ -399,7 +386,7 @@
// If Exit block includes loop variant instructions then this
// loop may not be eliminated.
- if (!safeExitBlock(SD, ExitBlock))
+ if (!safeExitBlock(SD, ExitCondition->getParent()))
return false;
// Update CFG.
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[llvm-commits] [llvm] r40977 - /llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
Author: dpatel
Date: Thu Aug 9 19:33:50 2007
New Revision: 40977
URL: http://llvm.org/viewvc/llvm-project?rev=40977&view=rev
Log:
ExitCondition and Induction variable are loop constraints
not split condition constraints.
Modified:
llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=40977&r1=40976&r2=40977&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Thu Aug 9 19:33:50 2007
@@ -53,46 +53,32 @@
class SplitInfo {
public:
- SplitInfo() : IndVar(NULL), SplitValue(NULL), ExitValue(NULL),
-SplitCondition(NULL), ExitCondition(NULL),
-IndVarIncrement(NULL) {}
+ SplitInfo() : SplitValue(NULL), SplitCondition(NULL) {}
- // Induction variable whose range is being split by this transformation.
- PHINode *IndVar;
-
// Induction variable's range is split at this value.
Value *SplitValue;
- // Induction variable's final loop exit value.
- Value *ExitValue;
-
// This compare instruction compares IndVar against SplitValue.
ICmpInst *SplitCondition;
- // Loop exit condition.
- ICmpInst *ExitCondition;
-
- Instruction *IndVarIncrement;
-
// Clear split info.
void clear() {
-IndVar = NULL;
SplitValue = NULL;
-ExitValue = NULL;
SplitCondition = NULL;
-ExitCondition = NULL;
-IndVarIncrement = NULL;
}
- /// Return true if V is a induction variable or induction variable's
- /// increment for loop L.
- bool findIndVar(Value *V, Loop *L);
};
-
+
private:
/// Find condition inside a loop that is suitable candidate for index
split.
void findSplitCondition();
+/// Find loop's exit condition.
+void findLoopConditionals();
+
+/// Return induction variable associated with value V.
+void findIndVar(Value *V, Loop *L);
+
/// processOneIterationLoop - Current loop L contains compare instruction
/// that compares induction variable, IndVar, agains loop invariant. If
/// entire (i.e. meaningful) loop body is dominated by this compare
@@ -112,6 +98,13 @@
unsigned findSplitCost(Loop *L, SplitInfo &SD);
bool splitLoop(SplitInfo &SD);
+void initialize() {
+ IndVar = NULL;
+ IndVarIncrement = NULL;
+ ExitCondition = NULL;
+ StartValue = ExitValue = NULL;
+}
+
private:
// Current Loop.
@@ -119,6 +112,19 @@
ScalarEvolution *SE;
DominatorTree *DT;
SmallVector SplitData;
+
+// Induction variable whose range is being split by this transformation.
+PHINode *IndVar;
+Instruction *IndVarIncrement;
+
+// Loop exit condition.
+ICmpInst *ExitCondition;
+
+// Induction variable's initial value.
+Value *StartValue;
+
+// Induction variable's final loop exit value.
+Value *ExitValue;
};
char LoopIndexSplit::ID = 0;
@@ -137,6 +143,13 @@
SE = &getAnalysis();
DT = &getAnalysis();
+ initialize();
+
+ findLoopConditionals();
+
+ if (!ExitCondition)
+return false;
+
findSplitCondition();
if (SplitData.empty())
@@ -183,24 +196,24 @@
/// Return true if V is a induction variable or induction variable's
/// increment for loop L.
-bool LoopIndexSplit::SplitInfo::findIndVar(Value *V, Loop *L) {
+void LoopIndexSplit::findIndVar(Value *V, Loop *L) {
Instruction *I = dyn_cast(V);
if (!I)
-return false;
+return;
// Check if I is a phi node from loop header or not.
if (PHINode *PN = dyn_cast(V)) {
if (PN->getParent() == L->getHeader()) {
-IndVar = PN;
-return true;
+ IndVar = PN;
+ return;
}
}
// Check if I is a add instruction whose one operand is
// phi node from loop header and second operand is constant.
if (I->getOpcode() != Instruction::Add)
-return false;
+return;
Value *Op0 = I->getOperand(0);
Value *Op1 = I->getOperand(1);
@@ -210,7 +223,7 @@
&& isa(Op1)) {
IndVar = PN;
IndVarIncrement = I;
- return true;
+ return;
}
}
@@ -219,11 +232,66 @@
&& isa(Op0)) {
IndVar = PN;
IndVarIncrement = I;
- return true;
+ return;
}
}
- return false;
+ return;
+}
+
+// Find loop's exit condition and associated induction variable.
+void LoopIndexSplit::findLoopConditionals() {
+
+ BasicBlock *ExitBlock = NULL;
+
+ for (Loop::block_iterator I = L->block_begin(), E = L->block_end();
+ I != E; ++I) {
+BasicBlock *BB = *I;
+if (!L->isLoopExit(BB))
+ continue;
+if (ExitBlock)
+ return;
+ExitBlock = BB;
+ }
+
[llvm-commits] [llvm] r40978 - /llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
Author: dpatel
Date: Thu Aug 9 19:53:35 2007
New Revision: 40978
URL: http://llvm.org/viewvc/llvm-project?rev=40978&view=rev
Log:
Calculate exit and start value of true loop and false loop respectively.
Modified:
llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=40978&r1=40977&r2=40978&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Thu Aug 9 19:53:35 2007
@@ -587,11 +587,37 @@
}
bool LoopIndexSplit::splitLoop(SplitInfo &SD) {
+
+ BasicBlock *Preheader = L->getLoopPreheader();
+
// True loop is original loop. False loop is cloned loop.
+
+ bool SignedPredicate = ExitCondition->isSignedPredicate();
//[*] Calculate True loop's new Exit Value in loop preheader.
- // NewExitValue = min(SplitValue, ExitValue)
+ // TLExitValue = min(SplitValue, ExitValue)
//[*] Calculate False loop's new Start Value in loop preheader.
- // NewStartValue = min(SplitValue, TrueLoop.StartValue)
+ // FLStartValue = min(SplitValue, TrueLoop.StartValue)
+ Value *TLExitValue = NULL;
+ Value *FLStartValue = NULL;
+ if (isa(SD.SplitValue)) {
+TLExitValue = SD.SplitValue;
+FLStartValue = SD.SplitValue;
+ }
+ else {
+Value *C1 = new ICmpInst(SignedPredicate ?
+ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT,
+SD.SplitValue, ExitValue, "lsplit.ev",
+Preheader->getTerminator());
+TLExitValue = new SelectInst(C1, SD.SplitValue, ExitValue,
+ "lsplit.ev", Preheader->getTerminator());
+
+Value *C2 = new ICmpInst(SignedPredicate ?
+ ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT,
+ SD.SplitValue, StartValue, "lsplit.sv",
+ Preheader->getTerminator());
+FLStartValue = new SelectInst(C2, SD.SplitValue, StartValue,
+ "lsplit.sv", Preheader->getTerminator());
+ }
//[*] Split Exit Edge.
//[*] Clone loop. Avoid true destination of split condition and
//the blocks dominated by true destination.
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[llvm-commits] [llvm] r40982 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrSSE.td
Author: void
Date: Fri Aug 10 01:22:27 2007
New Revision: 40982
URL: http://llvm.org/viewvc/llvm-project?rev=40982&view=rev
Log:
Adding SSSE3 intrinsics.
Modified:
llvm/trunk/include/llvm/IntrinsicsX86.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=40982&r1=40981&r2=40982&view=diff
==
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Fri Aug 10 01:22:27 2007
@@ -553,11 +553,125 @@
//===--===//
// SSSE3
-// FP arithmetic ops
+// Horizontal arithmetic ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
- def int_x86_ssse3_pmulhrsw_128 : GCCBuiltin<"__builtin_ia32_pmulhrsw128">,
+ def int_x86_ssse3_phadd_w : GCCBuiltin<"__builtin_ia32_phaddw">,
+ Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem]>;
+ def int_x86_ssse3_phadd_w_128 : GCCBuiltin<"__builtin_ia32_phaddw128">,
+ Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
+ llvm_v8i16_ty], [IntrNoMem]>;
+
+ def int_x86_ssse3_phadd_d : GCCBuiltin<"__builtin_ia32_phaddd">,
+ Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
+ llvm_v2i32_ty], [IntrNoMem]>;
+ def int_x86_ssse3_phadd_d_128 : GCCBuiltin<"__builtin_ia32_phaddd128">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
+ llvm_v4i32_ty], [IntrNoMem]>;
+
+ def int_x86_ssse3_phadd_sw: GCCBuiltin<"__builtin_ia32_phaddsw">,
+ Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem]>;
+ def int_x86_ssse3_phadd_sw_128: GCCBuiltin<"__builtin_ia32_phaddsw128">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
+ llvm_v4i32_ty], [IntrNoMem]>;
+
+ def int_x86_ssse3_phsub_w : GCCBuiltin<"__builtin_ia32_phsubw">,
+ Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem]>;
+ def int_x86_ssse3_phsub_w_128 : GCCBuiltin<"__builtin_ia32_phsubw128">,
+ Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
+ llvm_v8i16_ty], [IntrNoMem]>;
+
+ def int_x86_ssse3_phsub_d : GCCBuiltin<"__builtin_ia32_phsubd">,
+ Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
+ llvm_v2i32_ty], [IntrNoMem]>;
+ def int_x86_ssse3_phsub_d_128 : GCCBuiltin<"__builtin_ia32_phsubd128">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
+ llvm_v4i32_ty], [IntrNoMem]>;
+
+ def int_x86_ssse3_phsub_sw: GCCBuiltin<"__builtin_ia32_phsubsw">,
+ Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem]>;
+ def int_x86_ssse3_phsub_sw_128: GCCBuiltin<"__builtin_ia32_phsubsw128">,
Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem]>;
+
+ def int_x86_ssse3_pmadd_ub_sw : GCCBuiltin<"__builtin_ia32_pmaddubsw">,
+ Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem]>;
+ def int_x86_ssse3_pmadd_ub_sw_128 :
GCCBuiltin<"__builtin_ia32_pmaddubsw128">,
+ Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
+ llvm_v8i16_ty], [IntrNoMem]>;
+
+ def int_x86_ssse3_pmul_hr_sw : GCCBuiltin<"__builtin_ia32_pmulhrsw">,
+ Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
+ llvm_v4i16_ty], [IntrNoMem]>;
+ def int_x86_ssse3_pmul_hr_sw_128 : GCCBuiltin<"__builtin_ia32_pmulhrsw128">,
+ Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
+ llvm_v8i16_ty], [IntrNoMem]>;
+}
+
+// Shuffle ops
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_ssse3_pshuf_b : GCCBuiltin<"__builtin_ia32_pshufb">,
+ Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v8i8_ty], [IntrNoMem]>;
+ def int_x86_ssse3_pshuf_b_128 : GCCBuiltin<"__builtin_ia32_pshufb128">,
+ Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty,
+ llvm_v16i8_ty], [IntrNoMem]>;
+}
+
+// Sign ops
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_ssse3_psign_b : GCCBuiltin<"__builtin_ia32_psignb">,
+ Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty,
+ llvm_v8i8_ty], [IntrNoMem]>;
+ def int_x86_ssse3_psign_b_128 : GCCBuiltin<"__builtin_ia32_psignb128">,
+ Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty,
+ llvm_v16i8_ty], [IntrNoMem]>;
+
+ def int_x86_ssse3_psign_w : G
[llvm-commits] [llvm] r40981 - /llvm/trunk/lib/VMCore/PassManager.cpp
Author: lattner
Date: Fri Aug 10 01:22:25 2007
New Revision: 40981
URL: http://llvm.org/viewvc/llvm-project?rev=40981&view=rev
Log:
minor simplifications.
Modified:
llvm/trunk/lib/VMCore/PassManager.cpp
Modified: llvm/trunk/lib/VMCore/PassManager.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=40981&r1=40980&r2=40981&view=diff
==
--- llvm/trunk/lib/VMCore/PassManager.cpp (original)
+++ llvm/trunk/lib/VMCore/PassManager.cpp Fri Aug 10 01:22:25 2007
@@ -961,7 +961,7 @@
AnalysisUsage AnUsage;
BP->getAnalysisUsage(AnUsage);
- dumpPassInfo(BP, EXECUTION_MSG, ON_BASICBLOCK_MSG, (*I).getName());
+ dumpPassInfo(BP, EXECUTION_MSG, ON_BASICBLOCK_MSG, I->getName());
dumpAnalysisSetInfo("Required", BP, AnUsage.getRequiredSet());
initializeAnalysisImpl(BP);
@@ -971,15 +971,15 @@
if (TheTimeInfo) TheTimeInfo->passEnded(BP);
if (Changed)
-dumpPassInfo(BP, MODIFICATION_MSG, ON_BASICBLOCK_MSG, (*I).getName());
+dumpPassInfo(BP, MODIFICATION_MSG, ON_BASICBLOCK_MSG, I->getName());
dumpAnalysisSetInfo("Preserved", BP, AnUsage.getPreservedSet());
verifyPreservedAnalysis(BP);
removeNotPreservedAnalysis(BP);
recordAvailableAnalysis(BP);
- removeDeadPasses(BP, (*I).getName(), ON_BASICBLOCK_MSG);
-
+ removeDeadPasses(BP, I->getName(), ON_BASICBLOCK_MSG);
}
+
return Changed |= doFinalization(F);
}
@@ -1238,8 +1238,7 @@
if (TheTimeInfo) TheTimeInfo->passEnded(MP);
if (Changed)
- dumpPassInfo(MP, MODIFICATION_MSG, ON_MODULE_MSG,
- M.getModuleIdentifier());
+ dumpPassInfo(MP, MODIFICATION_MSG, ON_MODULE_MSG,
M.getModuleIdentifier());
dumpAnalysisSetInfo("Preserved", MP, AnUsage.getPreservedSet());
verifyPreservedAnalysis(MP);
@@ -1418,10 +1417,10 @@
for(std::deque::iterator I = S.begin(),
E = S.end(); I != E; ++I) {
Pass *P = dynamic_cast(*I);
-printf ("%s ", P->getPassName());
+printf("%s ", P->getPassName());
}
if (!S.empty())
-printf ("\n");
+printf("\n");
}
/// Find appropriate Module Pass Manager in the PM Stack and
@@ -1497,9 +1496,8 @@
// Basic Pass Manager is a leaf pass manager. It does not handle
// any other pass manager.
- if (!PMS.empty()) {
+ if (!PMS.empty())
BBP = dynamic_cast(PMS.top());
- }
// If leaf manager is not Basic Block Pass manager then create new
// basic Block Pass manager.
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[llvm-commits] [llvm] r40983 - /llvm/trunk/include/llvm/ADT/SmallVector.h
Author: lattner
Date: Fri Aug 10 01:54:38 2007
New Revision: 40983
URL: http://llvm.org/viewvc/llvm-project?rev=40983&view=rev
Log:
small speedup in the case where a smallvector is default ctor'd from
an empty vector. This speeds up llc slightly.
Modified:
llvm/trunk/include/llvm/ADT/SmallVector.h
Modified: llvm/trunk/include/llvm/ADT/SmallVector.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallVector.h?rev=40983&r1=40982&r2=40983&view=diff
==
--- llvm/trunk/include/llvm/ADT/SmallVector.h (original)
+++ llvm/trunk/include/llvm/ADT/SmallVector.h Fri Aug 10 01:54:38 2007
@@ -455,7 +455,8 @@
}
SmallVector(const SmallVector &RHS) : SmallVectorImpl(NumTsAvailable) {
-operator=(RHS);
+if (!RHS.empty())
+ operator=(RHS);
}
const SmallVector &operator=(const SmallVector &RHS) {
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[llvm-commits] [llvm] r40980 - in /llvm/trunk: include/llvm/PassManagers.h lib/VMCore/PassManager.cpp
Author: lattner
Date: Fri Aug 10 01:17:04 2007
New Revision: 40980
URL: http://llvm.org/viewvc/llvm-project?rev=40980&view=rev
Log:
avoid copying strings.
Modified:
llvm/trunk/include/llvm/PassManagers.h
llvm/trunk/lib/VMCore/PassManager.cpp
Modified: llvm/trunk/include/llvm/PassManagers.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassManagers.h?rev=40980&r1=40979&r2=40980&view=diff
==
--- llvm/trunk/include/llvm/PassManagers.h (original)
+++ llvm/trunk/include/llvm/PassManagers.h Fri Aug 10 01:17:04 2007
@@ -218,7 +218,8 @@
void removeNotPreservedAnalysis(Pass *P);
/// Remove dead passes
- void removeDeadPasses(Pass *P, std::string Msg, enum PassDebuggingString);
+ void removeDeadPasses(Pass *P, const std::string &Msg,
+enum PassDebuggingString);
/// Add pass P into the PassVector. Update
/// AvailableAnalysis appropriately if ProcessAnalysis is true.
@@ -273,7 +274,7 @@
void dumpLastUses(Pass *P, unsigned Offset) const;
void dumpPassArguments() const;
void dumpPassInfo(Pass *P, enum PassDebuggingString S1,
-enum PassDebuggingString S2, std::string Msg);
+enum PassDebuggingString S2, const std::string &Msg);
void dumpAnalysisSetInfo(const char *Msg, Pass *P,
const std::vector &Set) const;
Modified: llvm/trunk/lib/VMCore/PassManager.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=40980&r1=40979&r2=40980&view=diff
==
--- llvm/trunk/lib/VMCore/PassManager.cpp (original)
+++ llvm/trunk/lib/VMCore/PassManager.cpp Fri Aug 10 01:17:04 2007
@@ -650,7 +650,7 @@
}
/// Remove analysis passes that are not used any longer
-void PMDataManager::removeDeadPasses(Pass *P, std::string Msg,
+void PMDataManager::removeDeadPasses(Pass *P, const std::string &Msg,
enum PassDebuggingString DBG_STR) {
SmallVector DeadPasses;
@@ -854,9 +854,9 @@
}
}
-void PMDataManager:: dumpPassInfo(Pass *P, enum PassDebuggingString S1,
- enum PassDebuggingString S2,
- std::string Msg) {
+void PMDataManager::dumpPassInfo(Pass *P, enum PassDebuggingString S1,
+ enum PassDebuggingString S2,
+ const std::string &Msg) {
if (PassDebugging < Executions)
return;
cerr << (void*)this << std::string(getDepth()*2+1, ' ');
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