[llvm-commits] Patch for X86 to use subregs
This patch changes the X86 back end to use the new subreg operations for appropriate truncate and extend operations. This should allow regression testing of the subreg feature going forward, as it's now used in a public target.The patch passed DejaGnu and all of SingleSource on my x86 machine, but there are changes for x86-64 as well which I haven't been able to test. Output assembly for x86-64 appears sane, but I'd appreciate someone giving the patch a try on their x86-64 system. Other 32-bit x86 testing is also appreciated.Thanks --Christopher Lamb x86_subregs.patch Description: Binary data ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] Patch for X86 to use subregs
Very cool! I need to read it more carefully. But I see you are lowering zext to a single insert_subreg. Is that right? It won't zero out the top part, no? Evan Sent from my iPhone On Jul 28, 2007, at 12:17 AM, Christopher Lamb <[EMAIL PROTECTED] > wrote: This patch changes the X86 back end to use the new subreg operations for appropriate truncate and extend operations. This should allow regression testing of the subreg feature going forward, as it's now used in a public target. The patch passed DejaGnu and all of SingleSource on my x86 machine, but there are changes for x86-64 as well which I haven't been able to test. Output assembly for x86-64 appears sane, but I'd appreciate someone giving the patch a try on their x86-64 system. Other 32-bit x86 testing is also appreciated. Thanks -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] Patch for X86 to use subregs
On Jul 28, 2007, at 12:17 AM, Christopher Lamb wrote: This patch changes the X86 back end to use the new subreg operations for appropriate truncate and extend operations. This should allow regression testing of the subreg feature going forward, as it's now used in a public target. The patch passed DejaGnu and all of SingleSource on my x86 machine, but there are changes for x86-64 as well which I BTW, please make sure all of MultiSource pass. Also, if it is possible, can you split out the x86-64 as a follow on patch? Thanks, Evan haven't been able to test. Output assembly for x86-64 appears sane, but I'd appreciate someone giving the patch a try on their x86-64 system. Other 32-bit x86 testing is also appreciated. Thanks -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40569 - /llvm/trunk/test/CFrontend/2007-06-18-SextAttrAggregate.c
Author: nicholas
Date: Sat Jul 28 11:43:10 2007
New Revision: 40569
URL: http://llvm.org/viewvc/llvm-project?rev=40569&view=rev
Log:
Make this explictly signed. Fixes PR1571.
Modified:
llvm/trunk/test/CFrontend/2007-06-18-SextAttrAggregate.c
Modified: llvm/trunk/test/CFrontend/2007-06-18-SextAttrAggregate.c
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CFrontend/2007-06-18-SextAttrAggregate.c?rev=40569&r1=40568&r2=40569&view=diff
==
--- llvm/trunk/test/CFrontend/2007-06-18-SextAttrAggregate.c (original)
+++ llvm/trunk/test/CFrontend/2007-06-18-SextAttrAggregate.c Sat Jul 28
11:43:10 2007
@@ -6,6 +6,6 @@
long b;
};
-void f(struct s a, char *b, char C) {
+void f(struct s a, char *b, signed char C) {
}
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Re: [llvm-commits] ScalarEvolution fix for treeadd
Dan Gohman wrote: >>I'm not sure why, but it doesn't seem as promising as the previous test >>I had. Could it be that when comparing the PDF I should ignore blocks >>that are not part of the loop? > > If there are branches from outside the loop to blocks inside the loop > other than the loop header, then the exit branch may not be executed the > same number of times as the loop header. > > Can you identify a testcase that doesn't involve an infinite loop where > the PDF test rejects a loop that the one of the other tests accepts? No, it turns out that the previous test I had was Just Plain Buggy. Dan, we should move this discussion over to PR817. I'll attach the patch there. Nick ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r40570 - in /llvm-gcc-4.2/trunk: ModuleInfo.txt build-for-llvm-top.sh
Author: reid Date: Sat Jul 28 12:30:57 2007 New Revision: 40570 URL: http://llvm.org/viewvc/llvm-project?rev=40570&view=rev Log: Make it possible to build from llvm-top. Added: llvm-gcc-4.2/trunk/ModuleInfo.txt llvm-gcc-4.2/trunk/build-for-llvm-top.sh (with props) Added: llvm-gcc-4.2/trunk/ModuleInfo.txt URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/ModuleInfo.txt?rev=40570&view=auto == --- llvm-gcc-4.2/trunk/ModuleInfo.txt (added) +++ llvm-gcc-4.2/trunk/ModuleInfo.txt Sat Jul 28 12:30:57 2007 @@ -0,0 +1,4 @@ +DepModule: llvm +BuildCmd: ./build-for-llvm-top.sh +CleanCmd: cd ../build.llvm-gcc-4.0 ; make clean +InstallCmd: cd ../build.llvm-gcc-4.0 ; make install Added: llvm-gcc-4.2/trunk/build-for-llvm-top.sh URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build-for-llvm-top.sh?rev=40570&view=auto == --- llvm-gcc-4.2/trunk/build-for-llvm-top.sh (added) +++ llvm-gcc-4.2/trunk/build-for-llvm-top.sh Sat Jul 28 12:30:57 2007 @@ -0,0 +1,43 @@ +#!/bin/sh +# build script for llvm-gcc-4.0 +# +# This file was developed by Reid Spencer and is distributed under the +# University of Illinois Open Source License. See LICENSE.TXT for details. +# +#======# +# + +# Get the llvm-top library +. ../library.sh + +# Process the arguments +process_arguments "$@" + +# First, see if the build directory is there. If not, create it. +build_dir="$LLVM_TOP/build.llvm-gcc-4.0" +if test ! -d "$build_dir" ; then + mkdir -p "$build_dir" +fi + +# Next, see if we have previously been configured by sensing the presense +# of the config.status scripts +config_status="$build_dir/config.status" +if test ! -d "$config_status" -o "$config_status" -ot "$0" ; then + # We must configure so build a list of configure options + config_options="--prefix=$PREFIX --enable-llvm=$LLVM_TOP/llvm " + config_options="$config_options --program-prefix=llvm-" + config_options="$config_options --enable-languages=c,c++" + if test "$OPTIMIZED" -eq 0 ; then +config_options="$config_options --enable-checking --enable-libstdcxx-debug" + fi + host=`./config.guess` + if test ! -z `echo "$host" | grep 'linux'` ; then +config_options="$config_options --disable-shared" + fi + config_options="$config_options $config_opts" + src_dir=`pwd` + cd "$build_dir" + echo $src_dir/configure $config_options + $src_dir/configure $config_options +fi +make Propchange: llvm-gcc-4.2/trunk/build-for-llvm-top.sh -- svn:executable = * ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r40571 - in /llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp toplev.c
Author: asl Date: Sat Jul 28 13:28:30 2007 New Revision: 40571 URL: http://llvm.org/viewvc/llvm-project?rev=40571&view=rev Log: Minor PCH-related fixes (will be propagated to 4.0 soon): 1. Don't call finish_aliases_2(), when PCH are written 2. Properly initialize LLVM machinery, when PCHs are used to produce another PCHs :) Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp llvm-gcc-4.2/trunk/gcc/toplev.c Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=40571&r1=40570&r2=40571&view=diff == --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Sat Jul 28 13:28:30 2007 @@ -234,7 +234,11 @@ delete PerModulePasses; delete CodeGenPasses; -createOptimizationPasses(); +// Don't run codegen, when we should output PCH +if (!flag_pch_file) + createOptimizationPasses(); +else + llvm_pch_write_init(); } // Read LLVM Types string table Modified: llvm-gcc-4.2/trunk/gcc/toplev.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/toplev.c?rev=40571&r1=40570&r2=40571&view=diff == --- llvm-gcc-4.2/trunk/gcc/toplev.c (original) +++ llvm-gcc-4.2/trunk/gcc/toplev.c Sat Jul 28 13:28:30 2007 @@ -1146,8 +1146,16 @@ lang_hooks.decls.final_write_globals (); cgraph_varpool_assemble_pending_decls (); + + /* LLVM LOCAL begin */ +#ifdef ENABLE_LLVM + if (!flag_pch_file) +finish_aliases_2 (); +#else finish_aliases_2 (); - +#endif + /* LLVM LOCAL end */ + /* This must occur after the loop to output deferred functions. Else the coverage initializer would not be emitted if all the functions in this compilation unit were deferred. */ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] Patch for X86 to use subregs
On Jul 28, 2007, at 1:48 AM, Evan Cheng wrote: Very cool! I need to read it more carefully. But I see you are lowering zext to a single insert_subreg. Is that right? It won't zero out the top part, no? It's only lowering (zext i32 to i64) to an insert_subreg on x86-64 where all writes to 32-bit registers implicitly zero-extend into the upper 32-bits. -- Chris Sent from my iPhone On Jul 28, 2007, at 12:17 AM, Christopher Lamb <[EMAIL PROTECTED]> wrote: This patch changes the X86 back end to use the new subreg operations for appropriate truncate and extend operations. This should allow regression testing of the subreg feature going forward, as it's now used in a public target. The patch passed DejaGnu and all of SingleSource on my x86 machine, but there are changes for x86-64 as well which I haven't been able to test. Output assembly for x86-64 appears sane, but I'd appreciate someone giving the patch a try on their x86-64 system. Other 32-bit x86 testing is also appreciated. Thanks -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] Patch for X86 to use subregs
On Jul 28, 2007, at 2:08 AM, Evan Cheng wrote: On Jul 28, 2007, at 12:17 AM, Christopher Lamb wrote: This patch changes the X86 back end to use the new subreg operations for appropriate truncate and extend operations. This should allow regression testing of the subreg feature going forward, as it's now used in a public target. The patch passed DejaGnu and all of SingleSource on my x86 machine, but there are changes for x86-64 as well which I BTW, please make sure all of MultiSource pass. Ok. Also, if it is possible, can you split out the x86-64 as a follow on patch? It's a bit more work, but I think it'd be possible. Evan haven't been able to test. Output assembly for x86-64 appears sane, but I'd appreciate someone giving the patch a try on their x86-64 system. Other 32-bit x86 testing is also appreciated. Thanks -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40572 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Author: clamb
Date: Sat Jul 28 14:03:30 2007
New Revision: 40572
URL: http://llvm.org/viewvc/llvm-project?rev=40572&view=rev
Log:
Add register info needed to use subreg sets on X86.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=40572&r1=40571&r2=40572&view=diff
==
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Sat Jul 28 14:03:30 2007
@@ -163,6 +163,48 @@
def ST7 : Register<"ST(7)">, DwarfRegNum<18>;
}
+
+//===--===//
+// Subregister Set Definitions... now that we have all of the pieces, define
the
+// sub registers for each register.
+//
+
+def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
+R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+// It's unclear if this subreg set is safe, given that not all registers
+// in the class have an 'H' subreg.
+// def : SubRegSet<2, [AX, CX, DX, BX],
+//[AH, CH, DH, BH]>;
+
+def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def : SubRegSet<2, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
+ [AX, CX, DX, BX, SP, BP, SI, DI,
+R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
+
+
+def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+R8, R9, R10, R11, R12, R13, R14, R15],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def : SubRegSet<2, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+R8, R9, R10, R11, R12, R13, R14, R15],
+ [AX, CX, DX, BX, SP, BP, SI, DI,
+R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
+
+def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+R8, R9, R10, R11, R12, R13, R14, R15],
+ [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
+
//===--===//
// Register Class Definitions... now that we have all of the pieces, define the
// top-level register classes. The order specified in the register list is
@@ -229,6 +271,7 @@
def GR16 : RegisterClass<"X86", [i16], 16,
[AX, CX, DX, SI, DI, BX, BP, SP,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
+ let SubRegClassList = [GR8];
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
@@ -292,6 +335,7 @@
def GR32 : RegisterClass<"X86", [i32], 32,
[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
+ let SubRegClassList = [GR8, GR16];
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
@@ -355,6 +399,7 @@
def GR64 : RegisterClass<"X86", [i64], 64,
[RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
RBX, R14, R15, R12, R13, RBP, RSP]> {
+ let SubRegClassList = [GR8, GR16, GR32];
let MethodProtos = [{
iterator allocation_order_end(const MachineFunction &MF) const;
}];
@@ -374,8 +419,12 @@
// GR16, GR32 subclasses which contain registers that have R8 sub-registers.
// These should only be used for 32-bit mode.
-def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]>;
-def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]>;
+def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
+ let SubRegClassList = [GR8];
+}
+def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
+ let SubRegClassList = [GR8, GR16];
+}
// Scalar SSE2 floating point registers.
def FR32 : RegisterClass<"X86", [f32], 32,
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Re: [llvm-commits] Patch for X86 to use subregs
On Jul 28, 2007, at 11:55 AM, Christopher Lamb wrote: On Jul 28, 2007, at 2:08 AM, Evan Cheng wrote: On Jul 28, 2007, at 12:17 AM, Christopher Lamb wrote: This patch changes the X86 back end to use the new subreg operations for appropriate truncate and extend operations. This should allow regression testing of the subreg feature going forward, as it's now used in a public target. The patch passed DejaGnu and all of SingleSource on my x86 machine, but there are changes for x86-64 as well which I BTW, please make sure all of MultiSource pass. Ok. Also, if it is possible, can you split out the x86-64 as a follow on patch? It's a bit more work, but I think it'd be possible. So, the truncate code is shared between x86 and x86-64 to an extent that I think it'd be bad to try to separate out the patches for those. But I can certainly separate out the patch for PsMOVZX64rr32 on x86-64. Evan haven't been able to test. Output assembly for x86-64 appears sane, but I'd appreciate someone giving the patch a try on their x86-64 system. Other 32-bit x86 testing is also appreciated. Thanks -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r40573 - /llvm-gcc-4.2/trunk/build-for-llvm-top.sh
Author: reid Date: Sat Jul 28 14:44:03 2007 New Revision: 40573 URL: http://llvm.org/viewvc/llvm-project?rev=40573&view=rev Log: Make the build directory be build.llvm-gcc-4.2 instead of build.llvm-gcc-4.0 so it doesn't collide with the llvm-gcc-4.0 build. Modified: llvm-gcc-4.2/trunk/build-for-llvm-top.sh Modified: llvm-gcc-4.2/trunk/build-for-llvm-top.sh URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build-for-llvm-top.sh?rev=40573&r1=40572&r2=40573&view=diff == --- llvm-gcc-4.2/trunk/build-for-llvm-top.sh (original) +++ llvm-gcc-4.2/trunk/build-for-llvm-top.sh Sat Jul 28 14:44:03 2007 @@ -1,5 +1,5 @@ #!/bin/sh -# build script for llvm-gcc-4.0 +# build script for llvm-gcc-4.2 # # This file was developed by Reid Spencer and is distributed under the # University of Illinois Open Source License. See LICENSE.TXT for details. @@ -14,7 +14,7 @@ process_arguments "$@" # First, see if the build directory is there. If not, create it. -build_dir="$LLVM_TOP/build.llvm-gcc-4.0" +build_dir="$LLVM_TOP/build.llvm-gcc-4.2" if test ! -d "$build_dir" ; then mkdir -p "$build_dir" fi @@ -27,8 +27,10 @@ config_options="--prefix=$PREFIX --enable-llvm=$LLVM_TOP/llvm " config_options="$config_options --program-prefix=llvm-" config_options="$config_options --enable-languages=c,c++" + config_options="$config_options --disable-bootstrap" + config_options="$config_options --with-gxx-include-dir=/proj/install/include/c++/4.2.1" if test "$OPTIMIZED" -eq 0 ; then -config_options="$config_options --enable-checking --enable-libstdcxx-debug" +config_options="$config_options --enable-checking" fi host=`./config.guess` if test ! -z `echo "$host" | grep 'linux'` ; then ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r40574 - /llvm-gcc-4.2/trunk/ModuleInfo.txt
Author: reid Date: Sat Jul 28 14:46:50 2007 New Revision: 40574 URL: http://llvm.org/viewvc/llvm-project?rev=40574&view=rev Log: Use 4.2 build directory instead of 4.0 Modified: llvm-gcc-4.2/trunk/ModuleInfo.txt Modified: llvm-gcc-4.2/trunk/ModuleInfo.txt URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/ModuleInfo.txt?rev=40574&r1=40573&r2=40574&view=diff == --- llvm-gcc-4.2/trunk/ModuleInfo.txt (original) +++ llvm-gcc-4.2/trunk/ModuleInfo.txt Sat Jul 28 14:46:50 2007 @@ -1,4 +1,4 @@ DepModule: llvm BuildCmd: ./build-for-llvm-top.sh -CleanCmd: cd ../build.llvm-gcc-4.0 ; make clean -InstallCmd: cd ../build.llvm-gcc-4.0 ; make install +CleanCmd: cd ../build.llvm-gcc-4.2 ; make clean +InstallCmd: cd ../build.llvm-gcc-4.2 ; make install ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r40575 - in /llvm-gcc-4.2/trunk/libstdc++-v3/libsupc++: eh_personality.cc unwind-cxx.h
Author: asl
Date: Sat Jul 28 15:15:55 2007
New Revision: 40575
URL: http://llvm.org/viewvc/llvm-project?rev=40575&view=rev
Log:
Recover from bad merge
Modified:
llvm-gcc-4.2/trunk/libstdc++-v3/libsupc++/eh_personality.cc
llvm-gcc-4.2/trunk/libstdc++-v3/libsupc++/unwind-cxx.h
Modified: llvm-gcc-4.2/trunk/libstdc++-v3/libsupc++/eh_personality.cc
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/libstdc%2B%2B-v3/libsupc%2B%2B/eh_personality.cc?rev=40575&r1=40574&r2=40575&view=diff
==
--- llvm-gcc-4.2/trunk/libstdc++-v3/libsupc++/eh_personality.cc (original)
+++ llvm-gcc-4.2/trunk/libstdc++-v3/libsupc++/eh_personality.cc Sat Jul 28
15:15:55 2007
@@ -38,12 +38,6 @@
#define NO_SIZE_OF_ENCODED_VALUE
#endif
-// LLVM LOCAL begin
-#ifdef __ARM_EABI_UNWINDER__
-#define NO_SIZE_OF_ENCODED_VALUE
-#endif
-// LLVM LOCAL end
-
#include "unwind-pe.h"
@@ -204,119 +198,6 @@
// Return an element from a type table.
-// LLVM LOCAL begin
-#ifdef __ARM_EABI_UNWINDER__
-
-// Return an element from a type table.
-
-static const std::type_info*
-get_ttype_entry(lsda_header_info* info, _Unwind_Word i)
-{
- _Unwind_Ptr ptr;
-
- ptr = (_Unwind_Ptr) (info->TType - (i * 4));
- ptr = _Unwind_decode_target2(ptr);
-
- return reinterpret_cast(ptr);
-}
-
-// The ABI provides a routine for matching exception object types.
-typedef _Unwind_Control_Block _throw_typet;
-#define get_adjusted_ptr(catch_type, throw_type, thrown_ptr_p) \
- (__cxa_type_match (throw_type, catch_type, false, thrown_ptr_p) \
- != ctm_failed)
-
-// Return true if THROW_TYPE matches one if the filter types.
-
-static bool
-check_exception_spec(lsda_header_info* info, _throw_typet* throw_type,
-void* thrown_ptr, _Unwind_Sword filter_value)
-{
- const _Unwind_Word* e = ((const _Unwind_Word*) info->TType)
- - filter_value - 1;
-
- while (1)
-{
- const std::type_info* catch_type;
- _Unwind_Word tmp;
-
- tmp = *e;
-
- // Zero signals the end of the list. If we've not found
- // a match by now, then we've failed the specification.
- if (tmp == 0)
-return false;
-
- tmp = _Unwind_decode_target2((_Unwind_Word) e);
-
- // Match a ttype entry.
- catch_type = reinterpret_cast(tmp);
-
- // ??? There is currently no way to ask the RTTI code about the
- // relationship between two types without reference to a specific
- // object. There should be; then we wouldn't need to mess with
- // thrown_ptr here.
- if (get_adjusted_ptr(catch_type, throw_type, &thrown_ptr))
- return true;
-
- // Advance to the next entry.
- e++;
-}
-}
-
-
-// Save stage1 handler information in the exception object
-
-static inline void
-save_caught_exception(struct _Unwind_Exception* ue_header,
- struct _Unwind_Context* context,
- void* thrown_ptr,
- int handler_switch_value,
- const unsigned char* language_specific_data,
- _Unwind_Ptr landing_pad,
- const unsigned char* action_record
- __attribute__((__unused__)))
-{
-ue_header->barrier_cache.sp = _Unwind_GetGR(context, 13);
-ue_header->barrier_cache.bitpattern[0] = (_uw) thrown_ptr;
-ue_header->barrier_cache.bitpattern[1]
- = (_uw) handler_switch_value;
-ue_header->barrier_cache.bitpattern[2]
- = (_uw) language_specific_data;
-ue_header->barrier_cache.bitpattern[3] = (_uw) landing_pad;
-}
-
-
-// Restore the catch handler data saved during phase1.
-
-static inline void
-restore_caught_exception(struct _Unwind_Exception* ue_header,
-int& handler_switch_value,
-const unsigned char*& language_specific_data,
-_Unwind_Ptr& landing_pad)
-{
- handler_switch_value = (int) ue_header->barrier_cache.bitpattern[1];
- language_specific_data =
-(const unsigned char*) ue_header->barrier_cache.bitpattern[2];
- landing_pad = (_Unwind_Ptr) ue_header->barrier_cache.bitpattern[3];
-}
-
-#define CONTINUE_UNWINDING \
- do \
-{ \
- if (__gnu_unwind_frame(ue_header, context) != _URC_OK) \
- return _URC_FAILURE;\
- return _URC_CONTINUE_UNWIND; \
-} \
- while (0)
-
-#else
-// LLVM LOCAL end
-typedef const std::type_info _throw_typet;
-
-
-// Return an element from a type table.
-
static const std::type_info *
get_ttype_entry (lsda_header_info *info, _Unwind_Word i)
{
@@ -433,52 +314,6 @@
#endif // !__ARM_EABI_UNWINDER__
-
-// LLVM LOCAL begin
-// Save stage1 handler information in the exception objec
[llvm-commits] [llvm-gcc-4.2] r40576 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-internal.h
Author: asl
Date: Sat Jul 28 15:17:33 2007
New Revision: 40576
URL: http://llvm.org/viewvc/llvm-project?rev=40576&view=rev
Log:
Add dummy placeholders for some EH GIMPLE trees
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
llvm-gcc-4.2/trunk/gcc/llvm-internal.h
Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=40576&r1=40575&r2=40576&view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sat Jul 28 15:17:33 2007
@@ -800,10 +800,21 @@
switch (TREE_CODE(exp)) {
default:
-std::cerr << "Unhandled expression!\n";
+std::cerr << "Unhandled expression!\n"
+ << "TREE_CODE: " << TREE_CODE(exp) << "\n";
debug_tree(exp);
abort();
-
+
+ // FIXME: EH handling trees. Blank right now
+ case FILTER_EXPR:
+ case RESX_EXPR:
+{
+ const Type *Ty = ConvertType(TREE_TYPE(exp));
+ if (Ty != Type::VoidTy)
+Result = Constant::getNullValue(Ty);
+}
+break;
+
// Basic lists and binding scopes
case BIND_EXPR: Result = EmitBIND_EXPR(exp, DestLoc); break;
case STATEMENT_LIST: Result = EmitSTATEMENT_LIST(exp, DestLoc); break;
@@ -1002,6 +1013,10 @@
case INDIRECT_REF:
// The lvalue is just the address.
return Emit(TREE_OPERAND(exp, 0), 0);
+
+ // EH stuff
+ case EXC_PTR_EXPR: return EmitLV_EXC_PTR_EXPR(exp);
+ case FILTER_EXPR: return EmitLV_FILTER_EXPR(exp);
}
}
@@ -5406,6 +5421,44 @@
return LV;
}
+/// EmitLV_EXC_PTR_EXPR - Handle EXC_PTR_EXPR as lvalue.
+///
+LValue TreeToLLVM::EmitLV_EXC_PTR_EXPR(tree exp) {
+ const Type *Ty = ConvertType(TREE_TYPE(exp));
+
+#ifdef ITANIUM_STYLE_EXCEPTIONS
+ // Create exception values.
+ CreateExceptionValues();
+ LValue LV = ExceptionValue;
+#else
+ Value* Tmp = CreateTemporary(PointerType::get(Ty));
+ Tmp->setName("dummy");
+ LValue LV = Tmp;
+#endif
+
+ LV.Ptr = BitCastToType(LV.Ptr, PointerType::get(Ty));
+ return LV;
+}
+
+/// EmitLV_FILTER_EXPR - Handle FILTER_EXPR as lvalue.
+///
+LValue TreeToLLVM::EmitLV_FILTER_EXPR(tree exp) {
+ const Type *Ty = ConvertType(TREE_TYPE(exp));
+
+#ifdef ITANIUM_STYLE_EXCEPTIONS
+ // Create exception values.
+ CreateExceptionValues();
+ LValue LV = ExceptionSelectorValue;
+#else
+ Value* Tmp = CreateTemporary(PointerType::get(Ty));
+ Tmp->setName("dummy");
+ LValue LV = Tmp;
+#endif
+
+ LV.Ptr = BitCastToType(LV.Ptr, PointerType::get(Ty));
+ return LV;
+}
+
//===--===//
// ... Constant Expressions ...
//===--===//
Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=40576&r1=40575&r2=40576&view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Sat Jul 28 15:17:33 2007
@@ -620,6 +620,8 @@
LValue EmitLV_BIT_FIELD_REF(tree_node *exp);
LValue EmitLV_PART_EXPR(tree_node *exp, unsigned Idx);
LValue EmitLV_VIEW_CONVERT_EXPR(tree_node *exp);
+ LValue EmitLV_EXC_PTR_EXPR(tree_node *exp);
+ LValue EmitLV_FILTER_EXPR(tree_node *exp);
// Constant Expressions.
Value *EmitINTEGER_CST(tree_node *exp);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] Patch for X86 to use subregs
On Jul 28, 2007, at 11:52 AM, Christopher Lamb <[EMAIL PROTECTED] > wrote: On Jul 28, 2007, at 1:48 AM, Evan Cheng wrote: Very cool! I need to read it more carefully. But I see you are lowering zext to a single insert_subreg. Is that right? It won't zero out the top part, no? It's only lowering (zext i32 to i64) to an insert_subreg on x86-64 where all writes to 32-bit registers implicitly zero-extend into the upper 32-bits. I know. But thy mismatch semantically. A insert_subreg to the lower part should not change the upper half. I think this is only legal for anyext. Evan -- Chris Sent from my iPhone On Jul 28, 2007, at 12:17 AM, Christopher Lamb <[EMAIL PROTECTED] > wrote: This patch changes the X86 back end to use the new subreg operations for appropriate truncate and extend operations. This should allow regression testing of the subreg feature going forward, as it's now used in a public target. The patch passed DejaGnu and all of SingleSource on my x86 machine, but there are changes for x86-64 as well which I haven't been able to test. Output assembly for x86-64 appears sane, but I'd appreciate someone giving the patch a try on their x86-64 system. Other 32-bit x86 testing is also appreciated. Thanks -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] Patch for X86 to use subregs
On Jul 28, 2007, at 11:55 AM, Christopher Lamb <[EMAIL PROTECTED] > wrote: On Jul 28, 2007, at 2:08 AM, Evan Cheng wrote: On Jul 28, 2007, at 12:17 AM, Christopher Lamb wrote: This patch changes the X86 back end to use the new subreg operations for appropriate truncate and extend operations. This should allow regression testing of the subreg feature going forward, as it's now used in a public target. The patch passed DejaGnu and all of SingleSource on my x86 machine, but there are changes for x86-64 as well which I BTW, please make sure all of MultiSource pass. Ok. Also, if it is possible, can you split out the x86-64 as a follow on patch? It's a bit more work, but I think it'd be possible. Thx. Evan Evan haven't been able to test. Output assembly for x86-64 appears sane, but I'd appreciate someone giving the patch a try on their x86-64 system. Other 32-bit x86 testing is also appreciated. Thanks -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] Patch for X86 to use subregs
On Jul 28, 2007, at 2:26 PM, Evan Cheng wrote: On Jul 28, 2007, at 11:52 AM, Christopher Lamb <[EMAIL PROTECTED]> wrote: On Jul 28, 2007, at 1:48 AM, Evan Cheng wrote: Very cool! I need to read it more carefully. But I see you are lowering zext to a single insert_subreg. Is that right? It won't zero out the top part, no? It's only lowering (zext i32 to i64) to an insert_subreg on x86-64 where all writes to 32-bit registers implicitly zero-extend into the upper 32-bits. I know. But thy mismatch semantically. A insert_subreg to the lower part should not change the upper half. I think this is only legal for anyext. On x86-64 the semantics of a 2 operand i32 insert_subreg is that the input super-value is implicitly zero. So in this sense the insert isn't changing the upper half, it's just that the upper half is being set to zero implicitly rather than explicitly. If you'll notice the insert_subreg is a two operand (implicit super value) not a three operand version. If the insert were the three operand version, and the super value as coming from an implicit def I'd agree with you, but it's not. Also the current behavior is to use a 32-bit mov instruction for both zeroext and for anyext, I don't see how this is any different. -- Chris Sent from my iPhone On Jul 28, 2007, at 12:17 AM, Christopher Lamb <[EMAIL PROTECTED]> wrote: This patch changes the X86 back end to use the new subreg operations for appropriate truncate and extend operations. This should allow regression testing of the subreg feature going forward, as it's now used in a public target. The patch passed DejaGnu and all of SingleSource on my x86 machine, but there are changes for x86-64 as well which I haven't been able to test. Output assembly for x86-64 appears sane, but I'd appreciate someone giving the patch a try on their x86-64 system. Other 32-bit x86 testing is also appreciated. Thanks -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40578 - in /llvm/trunk/lib/Target/X86: X86ATTAsmPrinter.cpp X86CodeEmitter.cpp X86ISelDAGToDAG.cpp X86InstrInfo.td X86InstrX86-64.td X86IntelAsmPrinter.cpp
Author: clamb
Date: Sat Jul 28 20:24:57 2007
New Revision: 40578
URL: http://llvm.org/viewvc/llvm-project?rev=40578&view=rev
Log:
Change the x86 backend to use extract_subreg for truncation operations. Passes
DejaGnu, SingleSource and MultiSource.
Modified:
llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrX86-64.td
llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp
Modified: llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp?rev=40578&r1=40577&r2=40578&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp Sat Jul 28 20:24:57 2007
@@ -580,29 +580,6 @@
// See if a truncate instruction can be turned into a nop.
switch (MI->getOpcode()) {
default: break;
- case X86::TRUNC_64to32:
- case X86::TRUNC_64to16:
- case X86::TRUNC_32to16:
- case X86::TRUNC_32to8:
- case X86::TRUNC_16to8:
- case X86::TRUNC_32_to8:
- case X86::TRUNC_16_to8: {
-const MachineOperand &MO0 = MI->getOperand(0);
-const MachineOperand &MO1 = MI->getOperand(1);
-unsigned Reg0 = MO0.getReg();
-unsigned Reg1 = MO1.getReg();
-unsigned Opc = MI->getOpcode();
-if (Opc == X86::TRUNC_64to32)
- Reg1 = getX86SubSuperRegister(Reg1, MVT::i32);
-else if (Opc == X86::TRUNC_32to16 || Opc == X86::TRUNC_64to16)
- Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
-else
- Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);
-O << TAI->getCommentString() << " TRUNCATE ";
-if (Reg0 != Reg1)
- O << "\n\t";
-break;
- }
case X86::PsMOVZX64rr32:
O << TAI->getCommentString() << " ZERO-EXTEND " << "\n\t";
break;
Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=40578&r1=40577&r2=40578&view=diff
==
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Sat Jul 28 20:24:57 2007
@@ -448,12 +448,6 @@
return false;
}
-inline static bool isX86_64TruncToByte(unsigned oc) {
- return (oc == X86::TRUNC_64to8 || oc == X86::TRUNC_32to8 ||
- oc == X86::TRUNC_16to8);
-}
-
-
inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
return (reg == X86::SPL || reg == X86::BPL ||
reg == X86::SIL || reg == X86::DIL);
@@ -465,7 +459,6 @@
unsigned Emitter::determineREX(const MachineInstr &MI) {
unsigned REX = 0;
const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
- unsigned Opcode = Desc->Opcode;
// Pseudo instructions do not need REX prefix byte.
if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
@@ -479,16 +472,11 @@
Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX
prefix.
-bool isTrunc8 = isX86_64TruncToByte(Opcode);
unsigned i = isTwoAddr ? 1 : 0;
for (unsigned e = NumOps; i != e; ++i) {
const MachineOperand& MO = MI.getOperand(i);
if (MO.isRegister()) {
unsigned Reg = MO.getReg();
-// Trunc to byte are actually movb. The real source operand is the low
-// byte of the register.
-if (isTrunc8 && i == 1)
- Reg = getX86SubSuperRegister(Reg, MVT::i8);
if (isX86_64NonExtLowByteReg(Reg))
REX |= 0x40;
}
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=40578&r1=40577&r2=40578&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Jul 28 20:24:57 2007
@@ -1258,39 +1258,51 @@
return NULL;
}
-
+
case ISD::TRUNCATE: {
- if (!Subtarget->is64Bit() && NVT == MVT::i8) {
-unsigned Opc2;
-MVT::ValueType VT;
-switch (Node->getOperand(0).getValueType()) {
-default: assert(0 && "Unknown truncate!");
-case MVT::i16:
- Opc = X86::MOV16to16_;
- VT = MVT::i16;
- Opc2 = X86::TRUNC_16_to8;
- break;
-case MVT::i32:
- Opc = X86::MOV32to32_;
- VT = MVT::i32;
- Opc2 = X86::TRUNC_32_to8;
- break;
+ SDOperand Tmp;
+ SDOperand Input = Node->getOperand(0);
+ AddToISelQueue(Node->getOperand(0));
+ switch (NVT) {
+ case MVT::i8:
+Tmp = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
+// Ensure that the source register h
[llvm-commits] X86-64 subreg patch
This patch causes anyext and zext to be code generated as insert_subreg on x86-64. It passes all tests on my system, but my system isn't x86-64. If someone would give it a run that'd be appreciated.Thanks --Christopher Lamb x86_64_zext_subreg.patch Description: Binary data ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
