[llvm-commits] [llvm] r40518 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/Target/Target.td utils/TableGen/CodeEmitterGen.cpp utils/TableGen/CodeGenTarget.cpp utils/TableGen/DAGISelEmitt
Author: clamb
Date: Thu Jul 26 02:48:21 2007
New Revision: 40518
URL: http://llvm.org/viewvc/llvm-project?rev=40518&view=rev
Log:
Add target independent MachineInstr's to represent subreg insert/extract in
MBB's. PR1350
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/Target/Target.td
llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
llvm/trunk/utils/TableGen/CodeGenTarget.cpp
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=40518&r1=40517&r2=40518&view=diff
==
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Thu Jul 26 02:48:21 2007
@@ -177,7 +177,9 @@
enum {
PHI = 0,
INLINEASM = 1,
-LABEL = 2
+LABEL = 2,
+EXTRACT_SUBREG = 3,
+INSERT_SUBREG = 4
};
unsigned getNumOpcodes() const { return NumOpcodes; }
Modified: llvm/trunk/lib/Target/Target.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=40518&r1=40517&r2=40518&view=diff
==
--- llvm/trunk/lib/Target/Target.td (original)
+++ llvm/trunk/lib/Target/Target.td Thu Jul 26 02:48:21 2007
@@ -321,6 +321,18 @@
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
}
+def EXTRACT_SUBREG : Instruction {
+let OutOperandList = (ops variable_ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+}
+def INSERT_SUBREG : Instruction {
+let OutOperandList = (ops variable_ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+}
//===--===//
// AsmWriter - This class can be implemented by targets that need to customize
Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=40518&r1=40517&r2=40518&view=diff
==
--- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Thu Jul 26 02:48:21 2007
@@ -26,7 +26,9 @@
Record *R = *I;
if (R->getName() == "PHI" ||
R->getName() == "INLINEASM" ||
-R->getName() == "LABEL") continue;
+R->getName() == "LABEL" ||
+R->getName() == "EXTRACT_SUBREG" ||
+R->getName() == "INSERT_SUBREG") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
@@ -97,7 +99,9 @@
if (R->getName() == "PHI" ||
R->getName() == "INLINEASM" ||
-R->getName() == "LABEL") {
+R->getName() == "LABEL" ||
+R->getName() == "EXTRACT_SUBREG" ||
+R->getName() == "INSERT_SUBREG") {
o << "0U";
continue;
}
@@ -127,7 +131,9 @@
if (InstName == "PHI" ||
InstName == "INLINEASM" ||
-InstName == "LABEL") continue;
+InstName == "LABEL"||
+InstName == "EXTRACT_SUBREG" ||
+InstName == "INSERT_SUBREG") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
const std::vector &Vals = R->getValues();
Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=40518&r1=40517&r2=40518&view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Thu Jul 26 02:48:21 2007
@@ -275,14 +275,28 @@
if (I == Instructions.end()) throw "Could not find 'LABEL' instruction!";
const CodeGenInstruction *LABEL = &I->second;
+ I = getInstructions().find("EXTRACT_SUBREG");
+ if (I == Instructions.end())
+throw "Could not find 'EXTRACT_SUBREG' instruction!";
+ const CodeGenInstruction *EXTRACT_SUBREG = &I->second;
+
+ I = getInstructions().find("INSERT_SUBREG");
+ if (I == Instructions.end())
+throw "Could not find 'INSERT_SUBREG' instruction!";
+ const CodeGenInstruction *INSERT_SUBREG = &I->second;
+
// Print out the rest of the instructions now.
NumberedInstructions.push_back(PHI);
NumberedInstructions.push_back(INLINEASM);
NumberedInstructions.push_back(LABEL);
+ NumberedInstructions.push_back(EXTRACT_SUBREG);
+ NumberedInstructions.push_back(INSERT_SUBREG);
for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
if (&II->second != PHI &&
&II->second != INLINEASM &&
-&II->second != LABEL)
+&II->second != LABEL &&
+&II->second != EXTRACT_SUBREG &&
+
[llvm-commits] [llvm] r40520 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Author: clamb
Date: Thu Jul 26 03:12:07 2007
New Revision: 40520
URL: http://llvm.org/viewvc/llvm-project?rev=40520&view=rev
Log:
Teach DAG scheduling how to properly emit subreg insert/extract machine
instructions. PR1350
Modified:
llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=40520&r1=40519&r2=40520&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Thu Jul 26 03:12:07 2007
@@ -255,6 +255,11 @@
virtual void Schedule() {}
private:
+/// EmitSubregNode - Generate machine code for subreg nodes.
+///
+void EmitSubregNode(SDNode *Node,
+DenseMap &VRBaseMap);
+
void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
const TargetInstrDescriptor *II,
DenseMap &VRBaseMap);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=40520&r1=40519&r2=40520&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Thu Jul 26 03:12:07 2007
@@ -429,6 +429,148 @@
return 0;
}
+// Returns the Register Class of a subregister
+static const TargetRegisterClass *getSubRegisterRegClass(
+const TargetRegisterClass *TRC,
+unsigned SubIdx) {
+ // Pick the register class of the subregister
+ MRegisterInfo::regclass_iterator I = TRC->subregclasses_begin() + SubIdx-1;
+ assert(I < TRC->subregclasses_end() &&
+ "Invalid subregister index for register class");
+ return *I;
+}
+
+static const TargetRegisterClass *getSuperregRegisterClass(
+const TargetRegisterClass *TRC,
+unsigned SubIdx,
+MVT::ValueType VT) {
+ // Pick the register class of the superegister for this type
+ for (MRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
+ E = TRC->superregclasses_end(); I != E; ++I)
+if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
+ return *I;
+ assert(false && "Couldn't find the register class");
+ return 0;
+}
+
+/// EmitSubregNode - Generate machine code for subreg nodes.
+///
+void ScheduleDAG::EmitSubregNode(SDNode *Node,
+ DenseMap &VRBaseMap) {
+ unsigned VRBase = 0;
+ unsigned Opc = Node->getTargetOpcode();
+ if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
+// If the node is only used by a CopyToReg and the dest reg is a vreg, use
+// the CopyToReg'd destination register instead of creating a new vreg.
+for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
+ UI != E; ++UI) {
+ SDNode *Use = *UI;
+ if (Use->getOpcode() == ISD::CopyToReg &&
+ Use->getOperand(2).Val == Node) {
+unsigned DestReg = cast(Use->getOperand(1))->getReg();
+if (MRegisterInfo::isVirtualRegister(DestReg)) {
+ VRBase = DestReg;
+ break;
+}
+ }
+}
+
+unsigned SubIdx = cast(Node->getOperand(1))->getValue();
+
+// TODO: If the node is a use of a CopyFromReg from a physical register
+// fold the extract into the copy now
+
+// TODO: Add tracking info to SSARegMap of which vregs are subregs
+// to allow coalescing in the allocator
+
+// Create the extract_subreg machine instruction.
+MachineInstr *MI =
+ new MachineInstr(BB, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
+
+// Figure out the register class to create for the destreg.
+unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
+const TargetRegisterClass *TRC = RegMap->getRegClass(VReg);
+const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
+
+if (VRBase) {
+ // Grab the destination register
+ const TargetRegisterClass *DRC = 0;
+ DRC = RegMap->getRegClass(VRBase);
+ assert(SRC == DRC &&
+ "Source subregister and destination must have the same class");
+} else {
+ // Create the reg
+ VRBase = RegMap->createVirtualRegister(SRC);
+}
+
+// Add def, source, and subreg index
+MI->addRegOperand(VRBase, true);
+AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
+MI->addImmOperand(SubIdx);
+
+ } else if (Opc == TargetInstrInfo::INSERT_SUBREG) {
+assert((Node->getNumOperands() == 2 || Node->getNumOperands() == 3) &&
+"Malformed insert_subreg node");
+bool isUndefInput = (Node->getNumOperands() == 2);
+unsigned SubReg = 0;
+unsigned SubIdx = 0;
+
+if (isUndefInput) {
+
[llvm-commits] [llvm] r40521 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/LowerSubregs.cpp
Author: clamb
Date: Thu Jul 26 03:18:32 2007
New Revision: 40521
URL: http://llvm.org/viewvc/llvm-project?rev=40521&view=rev
Log:
Add a MachineFunction pass, which runs post register allocation, that turns
subreg insert/extract instruction into register copies. This ensures correct
code gen if the coalescer isn't able to remove all subreg instructions.
Added:
llvm/trunk/lib/CodeGen/LowerSubregs.cpp
Modified:
llvm/trunk/include/llvm/CodeGen/Passes.h
llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
Modified: llvm/trunk/include/llvm/CodeGen/Passes.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=40521&r1=40520&r2=40521&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/Passes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/Passes.h Thu Jul 26 03:18:32 2007
@@ -88,6 +88,12 @@
/// and eliminates abstract frame references.
///
FunctionPass *createPrologEpilogCodeInserter();
+
+ /// LowerSubregs Pass - This pass lowers subregs to register-register copies
+ /// which yields suboptimial, but correct code if the register allocator
+ /// cannot coalesce all subreg operations during allocation.
+ ///
+ FunctionPass *createLowerSubregsPass();
/// createPostRAScheduler - under development.
FunctionPass *createPostRAScheduler();
Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=40521&r1=40520&r2=40521&view=diff
==
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul 26 03:18:32 2007
@@ -96,6 +96,8 @@
if (addPreEmitPass(PM, Fast) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
+
+ PM.add(createLowerSubregsPass());
switch (FileType) {
default:
@@ -197,6 +199,8 @@
if (addPreEmitPass(PM, Fast) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
+
+ PM.add(createLowerSubregsPass());
addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
Added: llvm/trunk/lib/CodeGen/LowerSubregs.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=40521&view=auto
==
--- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (added)
+++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Thu Jul 26 03:18:32 2007
@@ -0,0 +1,226 @@
+//===-- LowerSubregs.cpp - Subregister Lowering instruction pass
--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by Christopher Lamb and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===--===//
+
+#define DEBUG_TYPE "lowersubregs"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/Function.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/Compiler.h"
+using namespace llvm;
+
+namespace {
+ struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
+ : public MachineFunctionPass {
+static char ID; // Pass identification, replacement for typeid
+LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
+
+const char *getPassName() const {
+ return "Subregister lowering instruction pass";
+}
+
+/// runOnMachineFunction - pass entry point
+bool runOnMachineFunction(MachineFunction&);
+ };
+
+ char LowerSubregsInstructionPass::ID = 0;
+}
+
+FunctionPass *llvm::createLowerSubregsPass() {
+ return new LowerSubregsInstructionPass();
+}
+
+// Returns the Register Class of a physical register
+static const TargetRegisterClass *getPhysicalRegisterRegClass(
+const MRegisterInfo &MRI,
+unsigned reg) {
+ assert(MRegisterInfo::isPhysicalRegister(reg) &&
+ "reg must be a physical register");
+ // Pick the register class of the right type that contains this physreg.
+ for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
+ E = MRI.regclass_end(); I != E; ++I)
+if ((*I)->contains(reg))
+ return *I;
+ assert(false && "Couldn't find the register class");
+ return 0;
+}
+
+static bool isSubRegOf(const MRegisterInfo &MRI,
+ unsigned SubReg,
+ unsigned SupReg) {
+ const TargetRegisterDesc &RD = MRI[SubReg];
+ for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
+if (*reg == SupReg)
+ return true;
+
+ return false;
+}
+
+
+/// runOnMachineFunction - Reduce subregister inserts and extra
[llvm-commits] [llvm-gcc-4.2] r40522 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Author: asl Date: Thu Jul 26 05:31:52 2007 New Revision: 40522 URL: http://llvm.org/viewvc/llvm-project?rev=40522&view=rev Log: Fix float initializers emission (HOST_WORDS_BIG_ENDIAN is obsolete). We still need to verify stuff on big-endian targets and cross-compilation on targets with different endiannes. Also, make use of FLOAT_WORDS_BIG_ENDIAN, which seems to be important for ARM. This change allows most of SingleSource/Benchmark and some of MultiSource/Applications to pass! Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=40522&r1=40521&r2=40522&view=diff == --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jul 26 05:31:52 2007 @@ -5496,25 +5496,22 @@ // Here's how this works: // REAL_VALUE_TO_TARGET_DOUBLE() will generate the floating point number - // as an array of integers in the hosts's representation. Each integer + // as an array of integers in the target's representation. Each integer // in the array will hold 32 bits of the result REGARDLESS OF THE HOST'S - // INTEGER SIZE. + // INTEGER SIZE. // // This, then, makes the conversion pretty simple. The tricky part is // getting the byte ordering correct and make sure you don't print any // more than 32 bits per integer on platforms with ints > 32 bits. - // - bool HostBigEndian = false; -#ifdef WORDS_BIG_ENDIAN - HostBigEndian = true; -#endif - + UArr[0] = RealArr[0]; // Long -> int convert UArr[1] = RealArr[1]; - if (WORDS_BIG_ENDIAN != HostBigEndian) + // FIXME: verify on big-endian targets and cross from big- to little- endian + // targets + if (FLOAT_WORDS_BIG_ENDIAN) std::swap(UArr[0], UArr[1]); - + return ConstantFP::get(Ty, V); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40519 - in /llvm/trunk: include/llvm/Target/MRegisterInfo.h utils/TableGen/RegisterInfoEmitter.cpp
Author: clamb
Date: Thu Jul 26 03:01:58 2007
New Revision: 40519
URL: http://llvm.org/viewvc/llvm-project?rev=40519&view=rev
Log:
Have register info provide the inverse mapping of register->superregisters.
PR1350
Modified:
llvm/trunk/include/llvm/Target/MRegisterInfo.h
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/MRegisterInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/MRegisterInfo.h?rev=40519&r1=40518&r2=40519&view=diff
==
--- llvm/trunk/include/llvm/Target/MRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/MRegisterInfo.h Thu Jul 26 03:01:58 2007
@@ -68,6 +68,7 @@
const sc_iterator SubClasses;
const sc_iterator SuperClasses;
const sc_iterator SubRegClasses;
+ const sc_iterator SuperRegClasses;
const unsigned RegSize, Alignment;// Size & Alignment of register in
bytes
const iterator RegsBegin, RegsEnd;
public:
@@ -76,9 +77,10 @@
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *subregcs,
+ const TargetRegisterClass * const *superregcs,
unsigned RS, unsigned Al, iterator RB, iterator RE)
: ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
-SubRegClasses(subregcs),
+SubRegClasses(subregcs), SuperRegClasses(superregcs),
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
@@ -131,9 +133,9 @@
return I;
}
- /// hasSubRegClass - return true if the specified TargetRegisterClass is a
+ /// hasSubClass - return true if the specified TargetRegisterClass is a
/// sub-register class of this TargetRegisterClass.
- bool hasSubRegClass(const TargetRegisterClass *cs) const {
+ bool hasSubClass(const TargetRegisterClass *cs) const {
for (int i = 0; SubClasses[i] != NULL; ++i)
if (SubClasses[i] == cs)
return true;
@@ -152,9 +154,9 @@
return I;
}
- /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
+ /// hasSuperClass - return true if the specified TargetRegisterClass is a
/// super-register class of this TargetRegisterClass.
- bool hasSuperRegClass(const TargetRegisterClass *cs) const {
+ bool hasSuperClass(const TargetRegisterClass *cs) const {
for (int i = 0; SuperClasses[i] != NULL; ++i)
if (SuperClasses[i] == cs)
return true;
@@ -173,9 +175,9 @@
return I;
}
- /// hasSubRegForClass - return true if the specified TargetRegisterClass is a
+ /// hasSubRegClass - return true if the specified TargetRegisterClass is a
/// class of a sub-register class for this TargetRegisterClass.
- bool hasSubRegForClass(const TargetRegisterClass *cs) const {
+ bool hasSubRegClass(const TargetRegisterClass *cs) const {
for (int i = 0; SubRegClasses[i] != NULL; ++i)
if (SubRegClasses[i] == cs)
return true;
@@ -199,6 +201,7 @@
for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
if (i == SubReg)
return &SubRegClasses[i];
+assert(0 && "Invalid subregister index for register class");
return NULL;
}
@@ -214,6 +217,18 @@
return I;
}
+ /// superregclasses_begin / superregclasses_end - Loop over all of
+ /// the superregister classes of this register class.
+ sc_iterator superregclasses_begin() const {
+return SuperRegClasses;
+ }
+
+ sc_iterator superregclasses_end() const {
+sc_iterator I = SuperRegClasses;
+while (*I != NULL) ++I;
+return I;
+ }
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=40519&r1=40518&r2=40519&view=diff
==
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Thu Jul 26 03:01:58 2007
@@ -223,9 +223,9 @@
<< RegisterClasses[i].getName() << "RegClass;\n";
std::map > SuperClassMap;
+std::map > SuperRegClassMap;
OS << "\n";
-
// Emit the sub-register classes for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
@@ -246,9 +246,18 @@
for (; rc2 != e2; ++rc2) {
const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
-if
[llvm-commits] [llvm-gcc-4.2] r40524 - /llvm-gcc-4.2/trunk/gcc/gcc.c
Author: baldrick
Date: Thu Jul 26 07:52:29 2007
New Revision: 40524
URL: http://llvm.org/viewvc/llvm-project?rev=40524&view=rev
Log:
Tweak this uninitialized variable fix in a way that
minimizes the differences with mainline.
Modified:
llvm-gcc-4.2/trunk/gcc/gcc.c
Modified: llvm-gcc-4.2/trunk/gcc/gcc.c
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=40524&r1=40523&r2=40524&view=diff
==
--- llvm-gcc-4.2/trunk/gcc/gcc.c (original)
+++ llvm-gcc-4.2/trunk/gcc/gcc.c Thu Jul 26 07:52:29 2007
@@ -6460,8 +6460,7 @@
main (int argc, char **argv)
{
size_t i;
- /* APPLE LOCAL uninit warning */
- int value = 0;
+ int value;
int linker_was_run = 0;
int lang_n_infiles = 0;
int num_linker_inputs = 0;
@@ -6989,7 +6988,9 @@
infiles[i].incompiler = lookup_compiler (infiles[i].name,
strlen
(infiles[i].name),
infiles[i].language);
-
+
+ if (value < 0)
+ this_file_error = 1;
}
else if (traditional_cpp_flag)
{
@@ -7002,9 +7003,6 @@
}
}
- if (value < 0)
- this_file_error = 1;
-
if (this_file_error)
{
delete_failure_queue ();
___
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llvm-commits@cs.uiuc.edu
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[llvm-commits] [llvm-gcc-4.0] r40523 - /llvm-gcc-4.0/trunk/gcc/gcc.c
Author: baldrick
Date: Thu Jul 26 07:47:10 2007
New Revision: 40523
URL: http://llvm.org/viewvc/llvm-project?rev=40523&view=rev
Log:
This variable could be used uninitialized.
Modified:
llvm-gcc-4.0/trunk/gcc/gcc.c
Modified: llvm-gcc-4.0/trunk/gcc/gcc.c
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.0/trunk/gcc/gcc.c?rev=40523&r1=40522&r2=40523&view=diff
==
--- llvm-gcc-4.0/trunk/gcc/gcc.c (original)
+++ llvm-gcc-4.0/trunk/gcc/gcc.c Thu Jul 26 07:47:10 2007
@@ -6390,7 +6390,8 @@
main (int argc, const char **argv)
{
size_t i;
- int value;
+ /* APPLE LOCAL LLVM uninit warning */
+ int value = 0;
int linker_was_run = 0;
int lang_n_infiles = 0;
int num_linker_inputs = 0;
___
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[llvm-commits] [llvm] r40542 - in /llvm/trunk: lib/Analysis/MemoryDependenceAnalysis.cpp test/Transforms/GVN/2007-07-25-InfiniteLoop.ll test/Transforms/GVN/2007-07-26-NonRedundant.ll
Author: resistor
Date: Thu Jul 26 13:57:04 2007
New Revision: 40542
URL: http://llvm.org/viewvc/llvm-project?rev=40542&view=rev
Log:
Fix a bug introduced in my last commit.
Added:
llvm/trunk/test/Transforms/GVN/2007-07-26-NonRedundant.ll
Modified:
llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
llvm/trunk/test/Transforms/GVN/2007-07-25-InfiniteLoop.ll
Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=40542&r1=40541&r2=40542&view=diff
==
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Thu Jul 26 13:57:04
2007
@@ -117,12 +117,18 @@
visited.insert(block);
bool inserted = false;
+ bool predOnStack = false;
for (pred_iterator PI = pred_begin(block), PE = pred_end(block);
PI != PE; ++PI)
if (!visited.count(*PI))
inserted |= nonLocalHelper(query, *PI, resp, visited);
-
+else
+ predOnStack = true;
+
visited.erase(block);
+
+ if (!inserted && !predOnStack)
+resp.insert(std::make_pair(block, None));
return inserted;
}
Modified: llvm/trunk/test/Transforms/GVN/2007-07-25-InfiniteLoop.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2007-07-25-InfiniteLoop.ll?rev=40542&r1=40541&r2=40542&view=diff
==
--- llvm/trunk/test/Transforms/GVN/2007-07-25-InfiniteLoop.ll (original)
+++ llvm/trunk/test/Transforms/GVN/2007-07-25-InfiniteLoop.ll Thu Jul 26
13:57:04 2007
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -gvn | llvm-dis
+; RUN: llvm-as < %s | opt -gvn | llvm-dis | not grep {tmp10 =}
%struct.INT2 = type { i32, i32 }
@blkshifts = external global %struct.INT2* ; <%struct.INT2**>
[#uses=2]
Added: llvm/trunk/test/Transforms/GVN/2007-07-26-NonRedundant.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2007-07-26-NonRedundant.ll?rev=40542&view=auto
==
--- llvm/trunk/test/Transforms/GVN/2007-07-26-NonRedundant.ll (added)
+++ llvm/trunk/test/Transforms/GVN/2007-07-26-NonRedundant.ll Thu Jul 26
13:57:04 2007
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | opt -gvn | llvm-dis
+
[EMAIL PROTECTED] = external global i32 ; [#uses=2]
+
+define i32 @bsR(i32 %n) {
+entry:
+ br i1 false, label %cond_next, label %bb19
+
+cond_next: ; preds = %entry
+ store i32 0, i32* @bsLive, align 4
+ br label %bb19
+
+bb19: ; preds = %cond_next, %entry
+ %tmp29 = load i32* @bsLive, align 4 ; [#uses=0]
+ ret i32 0
+}
___
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[llvm-commits] [129934] Revert.
Revision: 129934 Author: echeng Date: 2007-07-26 12:08:11 -0700 (Thu, 26 Jul 2007) Log Message: --- Revert. Wrong repository. Modified Paths: -- apple-local/branches/llvm/gcc/Makefile.in Modified: apple-local/branches/llvm/gcc/Makefile.in === --- apple-local/branches/llvm/gcc/Makefile.in 2007-07-26 18:52:21 UTC (rev 129933) +++ apple-local/branches/llvm/gcc/Makefile.in 2007-07-26 19:08:11 UTC (rev 129934) @@ -218,6 +218,10 @@ @checkingenabled_flag@ LLVMOBJDIR = @LLVMBASEPATH@ +ifdef LLVM_VERSION_INFO +CPPFLAGS += -DLLVM_VERSION_INFO='"$(LLVM_VERSION_INFO)"' +endif + # Determine BUILDMODE from configure run (--enable-llvm) BUILDMODE := @LLVMBUILDMODE@ @@ -232,10 +236,6 @@ # srcdir != objdir builds. LLVMSRCDIR := $(shell $(LLVMBINPATH)/llvm-config --src-root) endif - -ifdef LLVM_VERSION_INFO -CPPFLAGS += -DLLVM_VERSION_INFO='"$(LLVM_VERSION_INFO)"' -endif # APPLE LOCAL end LLVM # These exists to be overridden by the x-* and t-* files, respectively. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40546 - /llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp
Author: dpatel Date: Thu Jul 26 15:21:42 2007 New Revision: 40546 URL: http://llvm.org/viewvc/llvm-project?rev=40546&view=rev Log: Fix thinko. Update return status appropriately. Modified: llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp?rev=40546&r1=40545&r2=40546&view=diff == --- llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CondPropagate.cpp Thu Jul 26 15:21:42 2007 @@ -65,7 +65,7 @@ MadeChange = false; for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) SimplifyBlock(BB); -EverMadeChange = MadeChange; +EverMadeChange = EverMadeChange || MadeChange; } while (MadeChange); return EverMadeChange; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.0] r40544 - /llvm-gcc-4.0/trunk/gcc/llvm-linker-hack.cpp
Author: evancheng Date: Thu Jul 26 14:49:30 2007 New Revision: 40544 URL: http://llvm.org/viewvc/llvm-project?rev=40544&view=rev Log: Unbreak Apple style build: createDeadStoreEliminationPass must be linked in until it's completely removed. Modified: llvm-gcc-4.0/trunk/gcc/llvm-linker-hack.cpp Modified: llvm-gcc-4.0/trunk/gcc/llvm-linker-hack.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.0/trunk/gcc/llvm-linker-hack.cpp?rev=40544&r1=40543&r2=40544&view=diff == --- llvm-gcc-4.0/trunk/gcc/llvm-linker-hack.cpp (original) +++ llvm-gcc-4.0/trunk/gcc/llvm-linker-hack.cpp Thu Jul 26 14:49:30 2007 @@ -77,6 +77,7 @@ llvm::createDeadArgEliminationPass(); llvm::createLoadValueNumberingPass(); llvm::createTailCallEliminationPass(); + llvm::createDeadStoreEliminationPass(); llvm::createFastDeadStoreEliminationPass(); llvm::createIPConstantPropagationPass(); llvm::createStripDeadPrototypesPass(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r40504 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle.ll
Hi Dan,
I am going to revert the patch for now. Please re-commit once you
fixed it.
Thanks,
Evan
On Jul 26, 2007, at 5:05 PM, Evan Cheng wrote:
> Hi Dan,
>
> This is breaking oggenc (at least on Mac OS X / x86). Can you look
> into it?
>
> Thanks,
>
> Evan
>
> On Jul 25, 2007, at 5:31 PM, Dan Gohman wrote:
>
>> Author: djg
>> Date: Wed Jul 25 19:31:09 2007
>> New Revision: 40504
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=40504&view=rev
>> Log:
>> Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code
>> from the
>> x86 target, replacing them with the new alignment attributes on
>> memory
>> references.
>>
>> Modified:
>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> llvm/trunk/lib/Target/X86/X86ISelLowering.h
>> llvm/trunk/lib/Target/X86/X86InstrSSE.td
>> llvm/trunk/test/CodeGen/X86/vec_shuffle.ll
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/
>> X86ISelLowering.cpp?rev=40504&r1=40503&r2=40504&view=diff
>>
>> =
>> =
>>
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 25
>> 19:31:09 2007
>> @@ -3367,14 +3367,10 @@
>> CV.push_back(C);
>> CV.push_back(C);
>>}
>> - Constant *CS = ConstantStruct::get(CV);
>> - SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
>> - SDVTList Tys = DAG.getVTList(VT, MVT::Other);
>> - SmallVector Ops;
>> - Ops.push_back(DAG.getEntryNode());
>> - Ops.push_back(CPIdx);
>> - Ops.push_back(DAG.getSrcValue(NULL));
>> - SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0],
>> Ops.size());
>> + Constant *C = ConstantVector::get(CV);
>> + SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
>> + SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
>> NULL, 0,
>> + false, 16);
>>return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
>> }
>>
>> @@ -3399,21 +3395,16 @@
>> CV.push_back(C);
>> CV.push_back(C);
>>}
>> - Constant *CS = ConstantStruct::get(CV);
>> - SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
>> + Constant *C = ConstantVector::get(CV);
>> + SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
>> + SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
>> NULL, 0,
>> + false, 16);
>>if (MVT::isVector(VT)) {
>> -SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
>> NULL, 0);
>> return DAG.getNode(ISD::BIT_CONVERT, VT,
>> DAG.getNode(ISD::XOR, MVT::v2i64,
>> DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
>> Op.getOperand(0)),
>> DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
>> Mask)));
>>} else {
>> -SDVTList Tys = DAG.getVTList(VT, MVT::Other);
>> -SmallVector Ops;
>> -Ops.push_back(DAG.getEntryNode());
>> -Ops.push_back(CPIdx);
>> -Ops.push_back(DAG.getSrcValue(NULL));
>> -SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0],
>> Ops.size());
>> return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
>>}
>> }
>> @@ -3442,14 +3433,10 @@
>> CV.push_back(ConstantFP::get(SrcTy, 0.0));
>> CV.push_back(ConstantFP::get(SrcTy, 0.0));
>>}
>> - Constant *CS = ConstantStruct::get(CV);
>> - SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
>> - SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other);
>> - SmallVector Ops;
>> - Ops.push_back(DAG.getEntryNode());
>> - Ops.push_back(CPIdx);
>> - Ops.push_back(DAG.getSrcValue(NULL));
>> - SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0],
>> Ops.size());
>> + Constant *C = ConstantVector::get(CV);
>> + SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
>> + SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
>> NULL, 0,
>> +false, 16);
>>SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
>>
>>// Shift sign bit right or left if the two operands have
>> different types.
>> @@ -3474,14 +3461,10 @@
>> CV.push_back(ConstantFP::get(SrcTy, 0.0));
>> CV.push_back(ConstantFP::get(SrcTy, 0.0));
>>}
>> - CS = ConstantStruct::get(CV);
>> - CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
>> - Tys = DAG.getVTList(VT, MVT::Other);
>> - Ops.clear();
>> - Ops.push_back(DAG.getEntryNode());
>> - Ops.push_back(CPIdx);
>> - Ops.push_back(DAG.getSrcValue(NULL));
>> - SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0],
>> Ops.size());
>> + C = ConstantVector::get(CV);
>> + CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
>> + SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
>> NULL, 0,
>> +false, 16);
>>SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
>>
>>// Or th
[llvm-commits] [llvm] r40547 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle.ll
Author: evancheng
Date: Thu Jul 26 20:37:47 2007
New Revision: 40547
URL: http://llvm.org/viewvc/llvm-project?rev=40547&view=rev
Log:
Reverting 40504 for now. It's breaking oggenc.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/CodeGen/X86/vec_shuffle.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=40547&r1=40546&r2=40547&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jul 26 20:37:47 2007
@@ -3367,10 +3367,14 @@
CV.push_back(C);
CV.push_back(C);
}
- Constant *C = ConstantVector::get(CV);
- SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
- false, 16);
+ Constant *CS = ConstantStruct::get(CV);
+ SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
+ SDVTList Tys = DAG.getVTList(VT, MVT::Other);
+ SmallVector Ops;
+ Ops.push_back(DAG.getEntryNode());
+ Ops.push_back(CPIdx);
+ Ops.push_back(DAG.getSrcValue(NULL));
+ SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
}
@@ -3395,16 +3399,21 @@
CV.push_back(C);
CV.push_back(C);
}
- Constant *C = ConstantVector::get(CV);
- SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
- false, 16);
+ Constant *CS = ConstantStruct::get(CV);
+ SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
if (MVT::isVector(VT)) {
+SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
return DAG.getNode(ISD::BIT_CONVERT, VT,
DAG.getNode(ISD::XOR, MVT::v2i64,
DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
Op.getOperand(0)),
DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
} else {
+SDVTList Tys = DAG.getVTList(VT, MVT::Other);
+SmallVector Ops;
+Ops.push_back(DAG.getEntryNode());
+Ops.push_back(CPIdx);
+Ops.push_back(DAG.getSrcValue(NULL));
+SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
}
}
@@ -3433,10 +3442,14 @@
CV.push_back(ConstantFP::get(SrcTy, 0.0));
CV.push_back(ConstantFP::get(SrcTy, 0.0));
}
- Constant *C = ConstantVector::get(CV);
- SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0,
-false, 16);
+ Constant *CS = ConstantStruct::get(CV);
+ SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
+ SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other);
+ SmallVector Ops;
+ Ops.push_back(DAG.getEntryNode());
+ Ops.push_back(CPIdx);
+ Ops.push_back(DAG.getSrcValue(NULL));
+ SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
// Shift sign bit right or left if the two operands have different types.
@@ -3461,10 +3474,14 @@
CV.push_back(ConstantFP::get(SrcTy, 0.0));
CV.push_back(ConstantFP::get(SrcTy, 0.0));
}
- C = ConstantVector::get(CV);
- CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
-false, 16);
+ CS = ConstantStruct::get(CV);
+ CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
+ Tys = DAG.getVTList(VT, MVT::Other);
+ Ops.clear();
+ Ops.push_back(DAG.getEntryNode());
+ Ops.push_back(CPIdx);
+ Ops.push_back(DAG.getSrcValue(NULL));
+ SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
// Or the value with the sign bit.
@@ -4340,6 +4357,8 @@
case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
+ case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
+ case X86ISD::LOAD_UA:return "X86ISD::LOAD_UA";
case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
case X86ISD::Wrapper:return "X86ISD::Wrapper";
case X86ISD::S2VEC: return "X86ISD::S2VEC";
@@ -4737,14 +4756,19 @@
}
bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
- LoadSDNode *LD = cast(Base);
if (isAlign16) {
+LoadSDNode *LD = cast(Base);
return DAG.getLoad(VT, LD->g
Re: [llvm-commits] Trampoline support (pointers nested funtions)
Hi Duncan,
Some nit picks.
1. Please don't use "Chain" for stand for function static chain. It
confuses backend guys like me. :-) "Chain" stands for control flow
dependency in the backend.
2. Purely a stylistic thing:
+SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
+ SelectionDAG &DAG) {
+ SDOperand Root = Op.getOperand(0);
+ SDOperand Trmp = Op.getOperand(1); // trampoline
+ SDOperand FPtr = Op.getOperand(2); // nested function
+ SDOperand SChn = Op.getOperand(3); // static chain
+
+ SrcValueSDNode *TrmpSV = cast(Op.getOperand(4));
+
+ if (Subtarget->is64Bit()) {
+return SDOperand(); // not yet supported
+ } else {
If you move the check is64Bit() to the beginning of function, there
is no need to nest the part that actually do the work in the "else"
clause.
3. In X86TargetLowering::LowerTRAMPOLINE():
+case CallingConv::X86_StdCall: {
+ Move = 0xb9; // Pass chain in ECX
I assume this is the ModR/M byte? Can you refactor ModRMByte() from
X86CodeEmitter.cpp (probably also getX86RegNum) and use that to
calculate this instead? Also, isn't the static chain register
described in X86CallingConv.td? Magic number is confusing. :-)
Looks great otherwise. Thanks!
Evan
On Jul 26, 2007, at 7:56 AM, Duncan Sands wrote:
> These patches add support for taking pointers to nested
> functions (a gcc extension). This is done by building
> and executing a small code stub on the stack, known as
> a trampoline. The LLVM part adds two new intrinsics,
> llvm.init.trampoline and llvm.adjust.trampoline. The
> adjust intrinsic is implemented for all architectures
> that are supported in gcc, while the init intrinsic is
> only implemented for X86. Furthermore, trampolines can
> interact badly with stack protection mechanisms which
> don't much like execution of code on the stack. GCC
> does various tricks to tell the OS that the trampoline
> is kosher. I didn't implement any of those tricks yet,
> because it works without them on my machine :)
>
> Enjoy!
>
> Duncan.
>
>
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Re: [llvm-commits] [llvm] r40520 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
On Jul 26, 2007, at 1:12 AM, Christopher Lamb wrote:
/// EmitNode - Generate machine code for an node and needed
dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
@@ -436,6 +578,14 @@
// If machine instruction
if (Node->isTargetOpcode()) {
unsigned Opc = Node->getTargetOpcode();
+
+// Handle subreg insert/extract specially
+if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
+Opc == TargetInstrInfo::INSERT_SUBREG) {
+ EmitSubregNode(Node, VRBaseMap);
+ return;
+}
+
Hi Chris,
Is this right? EXTRACT_SUBREG and INSERT_SUBREG are not target opcodes.
Evan___
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Re: [llvm-commits] [llvm] r40504 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle.ll
Hi Dan,
This is breaking oggenc (at least on Mac OS X / x86). Can you look
into it?
Thanks,
Evan
On Jul 25, 2007, at 5:31 PM, Dan Gohman wrote:
> Author: djg
> Date: Wed Jul 25 19:31:09 2007
> New Revision: 40504
>
> URL: http://llvm.org/viewvc/llvm-project?rev=40504&view=rev
> Log:
> Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code
> from the
> x86 target, replacing them with the new alignment attributes on memory
> references.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.h
> llvm/trunk/lib/Target/X86/X86InstrSSE.td
> llvm/trunk/test/CodeGen/X86/vec_shuffle.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/
> X86ISelLowering.cpp?rev=40504&r1=40503&r2=40504&view=diff
>
> ==
>
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 25
> 19:31:09 2007
> @@ -3367,14 +3367,10 @@
> CV.push_back(C);
> CV.push_back(C);
>}
> - Constant *CS = ConstantStruct::get(CV);
> - SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
> - SDVTList Tys = DAG.getVTList(VT, MVT::Other);
> - SmallVector Ops;
> - Ops.push_back(DAG.getEntryNode());
> - Ops.push_back(CPIdx);
> - Ops.push_back(DAG.getSrcValue(NULL));
> - SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0],
> Ops.size());
> + Constant *C = ConstantVector::get(CV);
> + SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
> + SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
> NULL, 0,
> + false, 16);
>return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
> }
>
> @@ -3399,21 +3395,16 @@
> CV.push_back(C);
> CV.push_back(C);
>}
> - Constant *CS = ConstantStruct::get(CV);
> - SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
> + Constant *C = ConstantVector::get(CV);
> + SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
> + SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
> NULL, 0,
> + false, 16);
>if (MVT::isVector(VT)) {
> -SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
> NULL, 0);
> return DAG.getNode(ISD::BIT_CONVERT, VT,
> DAG.getNode(ISD::XOR, MVT::v2i64,
> DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
> Op.getOperand(0)),
> DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
> Mask)));
>} else {
> -SDVTList Tys = DAG.getVTList(VT, MVT::Other);
> -SmallVector Ops;
> -Ops.push_back(DAG.getEntryNode());
> -Ops.push_back(CPIdx);
> -Ops.push_back(DAG.getSrcValue(NULL));
> -SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0],
> Ops.size());
> return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
>}
> }
> @@ -3442,14 +3433,10 @@
> CV.push_back(ConstantFP::get(SrcTy, 0.0));
> CV.push_back(ConstantFP::get(SrcTy, 0.0));
>}
> - Constant *CS = ConstantStruct::get(CV);
> - SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
> - SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other);
> - SmallVector Ops;
> - Ops.push_back(DAG.getEntryNode());
> - Ops.push_back(CPIdx);
> - Ops.push_back(DAG.getSrcValue(NULL));
> - SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0],
> Ops.size());
> + Constant *C = ConstantVector::get(CV);
> + SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
> + SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
> NULL, 0,
> +false, 16);
>SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
>
>// Shift sign bit right or left if the two operands have
> different types.
> @@ -3474,14 +3461,10 @@
> CV.push_back(ConstantFP::get(SrcTy, 0.0));
> CV.push_back(ConstantFP::get(SrcTy, 0.0));
>}
> - CS = ConstantStruct::get(CV);
> - CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
> - Tys = DAG.getVTList(VT, MVT::Other);
> - Ops.clear();
> - Ops.push_back(DAG.getEntryNode());
> - Ops.push_back(CPIdx);
> - Ops.push_back(DAG.getSrcValue(NULL));
> - SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0],
> Ops.size());
> + C = ConstantVector::get(CV);
> + CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
> + SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
> NULL, 0,
> +false, 16);
>SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
>
>// Or the value with the sign bit.
> @@ -4357,8 +4340,6 @@
>case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
>case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
>case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
> - case X86ISD::LOA
[llvm-commits] [poolalloc] r40545 - /poolalloc/branches/SVA/lib/DSA/Devirt.cpp
Author: alenhar2
Date: Thu Jul 26 15:07:56 2007
New Revision: 40545
URL: http://llvm.org/viewvc/llvm-project?rev=40545&view=rev
Log:
minor improvements
Modified:
poolalloc/branches/SVA/lib/DSA/Devirt.cpp
Modified: poolalloc/branches/SVA/lib/DSA/Devirt.cpp
URL:
http://llvm.org/viewvc/llvm-project/poolalloc/branches/SVA/lib/DSA/Devirt.cpp?rev=40545&r1=40544&r2=40545&view=diff
==
--- poolalloc/branches/SVA/lib/DSA/Devirt.cpp (original)
+++ poolalloc/branches/SVA/lib/DSA/Devirt.cpp Thu Jul 26 15:07:56 2007
@@ -95,11 +95,11 @@
public:
virtual bool runOnModule(Module &M) {
CallTargetFinder* CTF = &getAnalysis();
- bool changed = false;
Function* ams = M.getNamedFunction("llva_assert_match_sig");
std::set safecalls;
+ std::vector toDelete;
for (Value::use_iterator ii = ams->use_begin(), ee = ams->use_end();
ii != ee; ++ii) {
@@ -107,8 +107,9 @@
std::cerr << "Found safe call site in "
<< CI->getParent()->getParent()->getName() << "\n";
Value* V = CI->getOperand(1);
- CI->eraseFromParent();
+ toDelete.push_back(CI);
do {
+//V->dump();
safecalls.insert(V);
if (CastInst* CV = dyn_cast(V))
V = CV->getOperand(0);
@@ -117,13 +118,11 @@
}
}
- std::vector toDelete;
-
for(std::set::iterator i = safecalls.begin(), e =
safecalls.end();
i != e; ++i) {
-for (Value::use_iterator ii = (*i)->use_begin(), ie = (*i)->use_end();
- ii != ie; ++ii) {
- CallSite cs = CallSite::get(*ii);
+for (Value::use_iterator uii = (*i)->use_begin(), uie =
(*i)->use_end();
+ uii != uie; ++uii) {
+ CallSite cs = CallSite::get(*uii);
bool isSafeCall = cs.getInstruction() &&
safecalls.find(cs.getCalledValue()) != safecalls.end();
if (cs.getInstruction() && !cs.getCalledFunction() &&
@@ -135,9 +134,8 @@
Targets.push_back(*ii);
if (Targets.size() > 0) {
- std::cerr << "Target count: " << Targets.size() << "\n";
+ std::cerr << "Target count: " << Targets.size() << " in " <<
cs.getInstruction()->getParent()->getParent()->getName() << "\n";
Function* NF = buildBounce(cs, Targets, M);
- changed = true;
if (CallInst* ci = dyn_cast(cs.getInstruction())) {
++CSConvert;
std::vector Par(ci->op_begin(), ci->op_end());
@@ -155,13 +153,18 @@
ci->replaceAllUsesWith(cn);
toDelete.push_back(ci);
}
-}
+} else //Target size == 0
+ std::cerr << "Call site found, but no Targets\n";
}
}
}
+
+ bool changed = false;
for (std::vector::iterator ii = toDelete.begin(), ee =
toDelete.end();
- ii != ee; ++ii)
+ ii != ee; ++ii) {
+changed = true;
(*ii)->eraseFromParent();
+ }
return changed;
}
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[llvm-commits] [llvm] r40540 - in /llvm/trunk: lib/Analysis/MemoryDependenceAnalysis.cpp lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/2007-07-26-InterlockingLoops.ll test/Transforms/GVN/2007-07-2
Author: resistor
Date: Thu Jul 26 13:26:51 2007
New Revision: 40540
URL: http://llvm.org/viewvc/llvm-project?rev=40540&view=rev
Log:
Fix a couple more bugs in the phi construction by pulling in code that does
almost the same things from LCSSA.
Added:
llvm/trunk/test/Transforms/GVN/2007-07-26-InterlockingLoops.ll
llvm/trunk/test/Transforms/GVN/2007-07-26-PhiErasure.ll
Modified:
llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=40540&r1=40539&r2=40540&view=diff
==
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Thu Jul 26 13:26:51
2007
@@ -124,9 +124,6 @@
visited.erase(block);
- if (!inserted)
-resp.insert(std::make_pair(block, None));
-
return inserted;
}
Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=40540&r1=40539&r2=40540&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Thu Jul 26 13:26:51 2007
@@ -13,12 +13,14 @@
//===--===//
#define DEBUG_TYPE "gvn"
-#include "llvm/Value.h"
+
#include "llvm/Transforms/Scalar.h"
#include "llvm/BasicBlock.h"
-#include "llvm/Instructions.h"
-#include "llvm/Function.h"
+#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
+#include "llvm/Function.h"
+#include "llvm/Instructions.h"
+#include "llvm/Value.h"
#include "llvm/Analysis/Dominators.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
@@ -650,9 +652,8 @@
DenseMap& lastSeenLoad,
SmallVector& toErase);
bool processNonLocalLoad(LoadInst* L, SmallVector&
toErase);
-Value *performPHIConstruction(BasicBlock *BB, LoadInst* orig,
- DenseMap &Phis,
- SmallPtrSet& visited);
+Value *GetValueForBlock(BasicBlock *BB, LoadInst* orig,
+ DenseMap &Phis);
void dump(DenseMap& d);
};
@@ -706,59 +707,35 @@
}
-Value *GVN::performPHIConstruction(BasicBlock *BB, LoadInst* orig,
- DenseMap &Phis,
- SmallPtrSet& visited) {
- DenseMap::iterator DI = Phis.find(BB);
- if (DI != Phis.end())
-return DI->second;
-
- unsigned numPreds = std::distance(pred_begin(BB), pred_end(BB));
-
- if (numPreds == 1) {
-DenseMap::iterator DI = Phis.find(BB);
-if (DI != Phis.end()) {
- Phis.insert(std::make_pair(BB, DI->second));
- return DI->second;
-} else {
- visited.insert(BB);
- Value* domV = performPHIConstruction(*pred_begin(BB), orig, Phis,
visited);
- visited.erase(BB);
-
- Phis.insert(std::make_pair(BB, domV));
- return domV;
-}
- } else {
-PHINode *PN = new PHINode(orig->getType(), orig->getName()+".rle",
BB->begin());
-PN->reserveOperandSpace(numPreds);
-Phis[BB] = PN;
-
-visited.insert(BB);
-// Fill in the incoming values for the block.
-for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
- if (!visited.count(*PI))
-PN->addIncoming(performPHIConstruction(*PI, orig, Phis, visited), *PI);
- else {
-if (Phis[*PI])
- PN->addIncoming(Phis[*PI], *PI);
-else
- PN->addIncoming(PN, *PI);
- }
-visited.erase(BB);
-
-bool all_same = PN->getNumIncomingValues() != 1;
-Value* first = PN->getIncomingValue(0);
-for (unsigned i = 1; i < PN->getNumIncomingValues(); ++i)
- all_same &= (PN->getIncomingValue(i) == first);
-
-if (all_same) {
- PN->eraseFromParent();
- Phis[BB] = first;
- return first;
-} else {
- return PN;
-}
+/// GetValueForBlock - Get the value to use within the specified basic block.
+/// available values are in Phis.
+Value *GVN::GetValueForBlock(BasicBlock *BB, LoadInst* orig,
+ DenseMap &Phis) {
+ DominatorTree &DT = getAnalysis();
+
+ // If we have already computed this value, return the previously computed
val.
+ Value *&V = Phis[BB];
+ if (V) return V;
+
+ DomTreeNode *IDom = DT.getNode(BB)->getIDom();
+
+ if (IDom && Phis.count(IDom->getBlock())) {
+return V = GetValueForBlock(IDom->getBlock(), orig, Phis);
}
+
+
+
+ // Otherwise, the idom is the loop, so we need to insert a PHI node. Do so
+ // now, then get values to fill in the incoming values for t
[llvm-commits] [llvm] r40538 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Author: evancheng
Date: Thu Jul 26 12:45:41 2007
New Revision: 40538
URL: http://llvm.org/viewvc/llvm-project?rev=40538&view=rev
Log:
Make sure epilogue esp adjustment is placed before any terminator and pop
instructions.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=40538&r1=40537&r2=40538&view=diff
==
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Jul 26 12:45:41 2007
@@ -1372,8 +1372,9 @@
// Skip the callee-saved pop instructions.
while (MBBI != MBB.begin()) {
-MachineBasicBlock::iterator PI = prior(MBBI);
-if (PI->getOpcode() != X86::POP32r && PI->getOpcode() != X86::POP64r)
+MachineBasicBlock::iterator PI = prior(MBBI);
+unsigned Opc = PI->getOpcode();
+if (Opc != X86::POP32r && Opc != X86::POP64r &&
!TII.isTerminatorInstr(Opc))
break;
--MBBI;
}
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[llvm-commits] [llvm] r40535 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Author: evancheng
Date: Thu Jul 26 12:02:45 2007
New Revision: 40535
URL: http://llvm.org/viewvc/llvm-project?rev=40535&view=rev
Log:
Minor bug.
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=40535&r1=40534&r2=40535&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jul 26 12:02:45 2007
@@ -628,19 +628,19 @@
AM.CP = CP->getConstVal();
AM.Align = CP->getAlignment();
AM.Disp += CP->getOffset();
- AM.isRIPRel = !isStatic;
+ AM.isRIPRel = !isAbs32;
return false;
}
} else if (ExternalSymbolSDNode *S =dyn_cast(N0)) {
if (isAbs32 || isRoot) {
AM.ES = S->getSymbol();
- AM.isRIPRel = !isStatic;
+ AM.isRIPRel = !isAbs32;
return false;
}
} else if (JumpTableSDNode *J = dyn_cast(N0)) {
if (isAbs32 || isRoot) {
AM.JT = J->getIndex();
- AM.isRIPRel = !isStatic;
+ AM.isRIPRel = !isAbs32;
return false;
}
}
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[llvm-commits] [llvm] r40534 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Author: djg
Date: Thu Jul 26 11:14:06 2007
New Revision: 40534
URL: http://llvm.org/viewvc/llvm-project?rev=40534&view=rev
Log:
Fix the alias analysis query in DAGCombiner to not add in two
offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=40534&r1=40533&r2=40534&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jul 26 11:14:06 2007
@@ -4599,8 +4599,8 @@
if (CombinerGlobalAA) {
// Use alias analysis information.
-int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
-int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
+int Overlap1 = Size1 + SrcValueOffset1;
+int Overlap2 = Size2 + SrcValueOffset2;
AliasAnalysis::AliasResult AAResult =
AA.alias(SrcValue1, Overlap1, SrcValue2,
Overlap2);
if (AAResult == AliasAnalysis::NoAlias)
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[llvm-commits] [llvm] r40533 - in /llvm/trunk/lib: Transforms/Utils/Local.cpp VMCore/Instruction.cpp
Author: djg
Date: Thu Jul 26 11:06:08 2007
New Revision: 40533
URL: http://llvm.org/viewvc/llvm-project?rev=40533&view=rev
Log:
Move the GET_SIDE_EFFECT_INFO logic from isInstructionTriviallyDead
to Instruction::mayWriteToMemory, fixing a FIXME, and helping
various places that call mayWriteToMemory directly.
Modified:
llvm/trunk/lib/Transforms/Utils/Local.cpp
llvm/trunk/lib/VMCore/Instruction.cpp
Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=40533&r1=40532&r2=40533&view=diff
==
--- llvm/trunk/lib/Transforms/Utils/Local.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/Local.cpp Thu Jul 26 11:06:08 2007
@@ -175,13 +175,6 @@
if (!I->mayWriteToMemory()) return true;
- if (CallInst *CI = dyn_cast(I))
-if (Function *F = CI->getCalledFunction()) {
- unsigned IntrinsicID = F->getIntrinsicID();
-#define GET_SIDE_EFFECT_INFO
-#include "llvm/Intrinsics.gen"
-#undef GET_SIDE_EFFECT_INFO
-}
return false;
}
Modified: llvm/trunk/lib/VMCore/Instruction.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=40533&r1=40532&r2=40533&view=diff
==
--- llvm/trunk/lib/VMCore/Instruction.cpp (original)
+++ llvm/trunk/lib/VMCore/Instruction.cpp Thu Jul 26 11:06:08 2007
@@ -197,6 +197,15 @@
return true;
}
+// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
+// have any side-effects or if it only reads memory.
+static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
+#define GET_SIDE_EFFECT_INFO
+#include "llvm/Intrinsics.gen"
+#undef GET_SIDE_EFFECT_INFO
+ return false;
+}
+
/// mayWriteToMemory - Return true if this instruction may modify memory.
///
bool Instruction::mayWriteToMemory() const {
@@ -208,11 +217,10 @@
case Instruction::VAArg:
return true;
case Instruction::Call:
-//if (const IntrinsicInst *II = dyn_cast(this)) {
+if (const IntrinsicInst *II = dyn_cast(this)) {
// If the intrinsic doesn't write memory, it is safe.
- // FIXME: this is obviously supposed to determine which intrinsics
- // don't write to memory, but hasn't been implemented yet.
-//}
+ return !IntrinsicOnlyReadsMemory(II->getIntrinsicID());
+}
return true;
case Instruction::Load:
return cast(this)->isVolatile();
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[llvm-commits] [llvm] r40529 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td
Author: djg
Date: Thu Jul 26 10:24:15 2007
New Revision: 40529
URL: http://llvm.org/viewvc/llvm-project?rev=40529&view=rev
Log:
In the .loc directive, print the fields as "debug" fields, so they
don't get decorated as if for immediate fields for instructions.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=40529&r1=40528&r2=40529&view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jul 26 10:24:15 2007
@@ -2498,7 +2498,7 @@
def DWARF_LOC : I<0, Pseudo, (outs),
(ins i32imm:$line, i32imm:$col, i32imm:$file),
-"; .loc $file, $line, $col",
+"; .loc ${file:debug}, ${line:debug}, ${col:debug}",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
(i32 imm:$file))]>;
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[llvm-commits] [llvm] r40528 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td
Author: djg
Date: Thu Jul 26 10:11:50 2007
New Revision: 40528
URL: http://llvm.org/viewvc/llvm-project?rev=40528&view=rev
Log:
Fix a whitespace difference between CMPSSrr and CMPSDrr.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=40528&r1=40527&r2=40528&view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jul 26 10:11:50 2007
@@ -349,8 +349,7 @@
let isTwoAddress = 1 in {
def CMPSSrr : SSI<0xC2, MRMSrcReg,
(outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
-"cmp${cc}ss {$src, $dst|$dst, $src}",
-[]>;
+"cmp${cc}ss {$src, $dst|$dst, $src}", []>;
def CMPSSrm : SSI<0xC2, MRMSrcMem,
(outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
"cmp${cc}ss {$src, $dst|$dst, $src}", []>;
___
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[llvm-commits] [llvm] r40527 - /llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp
Author: djg Date: Thu Jul 26 10:11:00 2007 New Revision: 40527 URL: http://llvm.org/viewvc/llvm-project?rev=40527&view=rev Log: Fix a pasto in a comment. Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=40527&r1=40526&r2=40527&view=diff == --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Thu Jul 26 10:11:00 2007 @@ -309,7 +309,7 @@ break; } } - OS << "return true; // These intrinsics have no side effects.\n"; + OS << "return true; // These intrinsics do not reference memory.\n"; OS << " }\n"; OS << "#endif\n\n"; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] Trampoline support (pointers nested funtions)
These patches add support for taking pointers to nested
functions (a gcc extension). This is done by building
and executing a small code stub on the stack, known as
a trampoline. The LLVM part adds two new intrinsics,
llvm.init.trampoline and llvm.adjust.trampoline. The
adjust intrinsic is implemented for all architectures
that are supported in gcc, while the init intrinsic is
only implemented for X86. Furthermore, trampolines can
interact badly with stack protection mechanisms which
don't much like execution of code on the stack. GCC
does various tricks to tell the OS that the trampoline
is kosher. I didn't implement any of those tricks yet,
because it works without them on my machine :)
Enjoy!
Duncan.
Index: include/llvm/Target/TargetLowering.h
===
--- include/llvm/Target/TargetLowering.h (revision 40522)
+++ include/llvm/Target/TargetLowering.h (working copy)
@@ -812,8 +812,10 @@
bool isZExt;
bool isInReg;
bool isSRet;
+bool isChain;
-ArgListEntry():isSExt(false), isZExt(false), isInReg(false), isSRet(false) { };
+ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
+ isSRet(false), isChain(false) { };
};
typedef std::vector ArgListTy;
virtual std::pair
Index: include/llvm/ParameterAttributes.h
===
--- include/llvm/ParameterAttributes.h (revision 40522)
+++ include/llvm/ParameterAttributes.h (working copy)
@@ -30,14 +30,15 @@
/// @brief Function parameter attributes.
enum Attributes {
None = 0, ///< No attributes have been set
- ZExt = 1 << 0, ///< zero extended before/after call
- SExt = 1 << 1, ///< sign extended before/after call
- NoReturn = 1 << 2, ///< mark the function as not returning
- InReg = 1 << 3, ///< force argument to be passed in register
- StructRet = 1 << 4, ///< hidden pointer to structure to return
+ ZExt = 1 << 0, ///< Zero extended before/after call
+ SExt = 1 << 1, ///< Sign extended before/after call
+ NoReturn = 1 << 2, ///< Mark the function as not returning
+ InReg = 1 << 3, ///< Force argument to be passed in register
+ StructRet = 1 << 4, ///< Hidden pointer to structure to return
NoUnwind = 1 << 5, ///< Function doesn't unwind stack
- NoAlias= 1 << 6, ///< Considered to not alias after call.
- ByVal = 1 << 7 ///< Pass structure by value
+ NoAlias= 1 << 6, ///< Considered to not alias after call
+ ByVal = 1 << 7, ///< Pass structure by value
+ Chain = 1 << 8 ///< Nested function static chain
};
}
Index: include/llvm/Intrinsics.td
===
--- include/llvm/Intrinsics.td (revision 40522)
+++ include/llvm/Intrinsics.td (working copy)
@@ -247,6 +247,14 @@
llvm_ptr_ty, llvm_i32_ty],
[], "llvm.var.annotation">;
+//=== Trampoline Intrinsics ---===//
+//
+def int_init_trampoline : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty,
+ llvm_ptr_ty], []>,
+GCCBuiltin<"__builtin_init_trampoline">;
+def int_adjust_trampoline : Intrinsic<[llvm_ptr_ty, llvm_ptr_ty], [IntrNoMem]>,
+GCCBuiltin<"__builtin_adjust_trampoline">;
+
//===--===//
// Target-specific intrinsics
//===--===//
Index: include/llvm/CodeGen/SelectionDAGNodes.h
===
--- include/llvm/CodeGen/SelectionDAGNodes.h (revision 40522)
+++ include/llvm/CodeGen/SelectionDAGNodes.h (working copy)
@@ -66,6 +66,8 @@
StructReturnOffs = 3,
ByVal = 1<<4, ///< Struct passed by value
ByValOffs = 4,
+Chain = 1<<5, ///< Parameter is nested function static chain
+ChainOffs = 5,
OrigAlignment = 0x1F<<27,
OrigAlignmentOffs = 27
};
@@ -528,7 +530,19 @@
// number, then a column then a file id (provided by MachineModuleInfo.) It
// produces a token chain as output.
DEBUG_LOC,
-
+
+// ADJUST_TRAMP - This corresponds to the adjust_trampoline intrinsic.
+// It takes a value as input and returns a value as output.
+ADJUST_TRAMP,
+
+// TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
+// It takes as input a token chain, the pointer to the trampoline,
+// the pointer to the nested function, the static chain pointer, a
+// SRCVALUE for the trampoline and another for the nested function
+// (allowing targets to access the original Function*). It produces
+// a token chain as output.
+TRAMPOLINE,
+
// BUILTIN_OP_END - This must be the last en
[llvm-commits] [llvm] r40517 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Author: evancheng
Date: Thu Jul 26 02:35:15 2007
New Revision: 40517
URL: http://llvm.org/viewvc/llvm-project?rev=40517&view=rev
Log:
Same goes for constantpool, etc.
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=40517&r1=40516&r2=40517&view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jul 26 02:35:15 2007
@@ -613,10 +613,10 @@
if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
bool isStatic = TM.getRelocationModel() == Reloc::Static;
SDOperand N0 = N.getOperand(0);
+ // Mac OS X X86-64 lower 4G address is not available.
+ bool isAbs32 = !is64Bit || (isStatic && !Subtarget->isTargetDarwin());
if (GlobalAddressSDNode *G = dyn_cast(N0)) {
GlobalValue *GV = G->getGlobal();
-// Mac OS X X86-64 lower 4G address is not available.
-bool isAbs32 = !is64Bit || (isStatic && !Subtarget->isTargetDarwin());
if (isAbs32 || isRoot) {
AM.GV = GV;
AM.Disp += G->getOffset();
@@ -624,7 +624,7 @@
return false;
}
} else if (ConstantPoolSDNode *CP = dyn_cast(N0)) {
-if (!is64Bit || isStatic || isRoot) {
+if (isAbs32 || isRoot) {
AM.CP = CP->getConstVal();
AM.Align = CP->getAlignment();
AM.Disp += CP->getOffset();
@@ -632,13 +632,13 @@
return false;
}
} else if (ExternalSymbolSDNode *S =dyn_cast(N0)) {
-if (isStatic || isRoot) {
+if (isAbs32 || isRoot) {
AM.ES = S->getSymbol();
AM.isRIPRel = !isStatic;
return false;
}
} else if (JumpTableSDNode *J = dyn_cast(N0)) {
-if (isStatic || isRoot) {
+if (isAbs32 || isRoot) {
AM.JT = J->getIndex();
AM.isRIPRel = !isStatic;
return false;
___
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[llvm-commits] [llvm] r40514 - in /llvm/trunk: include/llvm/CodeGen/MachineInstr.h include/llvm/CodeGen/MachineInstrBuilder.h lib/CodeGen/MachineInstr.cpp
Author: clamb
Date: Thu Jul 26 02:00:46 2007
New Revision: 40514
URL: http://llvm.org/viewvc/llvm-project?rev=40514&view=rev
Log:
Remove subreg index from MachineInstr's and also keep vregs as unsigned when
adding operands.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
llvm/trunk/lib/CodeGen/MachineInstr.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=40514&r1=40513&r2=40514&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Thu Jul 26 02:00:46 2007
@@ -76,10 +76,6 @@
/// offset - Offset to address of global or external, only valid for
/// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
int offset;
-
-/// subReg - SubRegister number, only valid for MO_Register. A value of 0
-/// indicates the MO_Register has no subReg.
-unsigned subReg;
} auxInfo;
MachineOperand() {}
@@ -178,10 +174,6 @@
"Wrong MachineOperand accessor");
return auxInfo.offset;
}
- unsigned getSubReg() const {
-assert(isRegister() && "Wrong MachineOperand accessor");
-return auxInfo.subReg;
- }
const char *getSymbolName() const {
assert(isExternalSymbol() && "Wrong MachineOperand accessor");
return contents.SymbolName;
@@ -267,10 +259,6 @@
"Wrong MachineOperand accessor");
auxInfo.offset = Offset;
}
- void setSubReg(unsigned subReg) {
-assert(isRegister() && "Wrong MachineOperand accessor");
-auxInfo.subReg = subReg;
- }
void setConstantPoolIndex(unsigned Idx) {
assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
contents.immedVal = Idx;
@@ -459,7 +447,6 @@
Op.IsKill = IsKill;
Op.IsDead = IsDead;
Op.contents.RegNo = Reg;
-Op.auxInfo.subReg = 0;
}
/// addImmOperand - Add a zero extended constant argument to the
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=40514&r1=40513&r2=40514&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Thu Jul 26 02:00:46
2007
@@ -37,7 +37,7 @@
/// addReg - Add a new virtual register operand...
///
const
- MachineInstrBuilder &addReg(int RegNo, bool isDef = false, bool isImp =
false,
+ MachineInstrBuilder &addReg(unsigned RegNo, bool isDef = false, bool isImp =
false,
bool isKill = false, bool isDead = false) const {
MI->addRegOperand(RegNo, isDef, isImp, isKill, isDead);
return *this;
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=40514&r1=40513&r2=40514&view=diff
==
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Jul 26 02:00:46 2007
@@ -39,7 +39,6 @@
Op.IsKill = false;
Op.IsDead = false;
Op.contents.RegNo = *ImpDefs;
- Op.auxInfo.subReg = 0;
Operands.push_back(Op);
}
if (TID->ImplicitUses)
@@ -51,7 +50,6 @@
Op.IsKill = false;
Op.IsDead = false;
Op.contents.RegNo = *ImpUses;
- Op.auxInfo.subReg = 0;
Operands.push_back(Op);
}
}
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Re: [llvm-commits] [llvm] r40521 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/LowerSubregs.cpp
Should this be right after register allocation? Any reason to keep the pseudo instructions around after allocation? Evan On Jul 26, 2007, at 1:18 AM, Christopher Lamb wrote: if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + + PM.add(createLowerSubregsPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.0] r40543 - /llvm-gcc-4.0/trunk/gcc/Makefile.in
Author: evancheng Date: Thu Jul 26 14:08:44 2007 New Revision: 40543 URL: http://llvm.org/viewvc/llvm-project?rev=40543&view=rev Log: Restore llvm version info. Modified: llvm-gcc-4.0/trunk/gcc/Makefile.in Modified: llvm-gcc-4.0/trunk/gcc/Makefile.in URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.0/trunk/gcc/Makefile.in?rev=40543&r1=40542&r2=40543&view=diff == --- llvm-gcc-4.0/trunk/gcc/Makefile.in (original) +++ llvm-gcc-4.0/trunk/gcc/Makefile.in Thu Jul 26 14:08:44 2007 @@ -218,10 +218,6 @@ @checkingenabled_flag@ LLVMOBJDIR = @LLVMBASEPATH@ -ifdef LLVM_VERSION_INFO -CPPFLAGS += -DLLVM_VERSION_INFO='"$(LLVM_VERSION_INFO)"' -endif - # Determine BUILDMODE from configure run (--enable-llvm) BUILDMODE := @LLVMBUILDMODE@ @@ -236,6 +232,10 @@ # srcdir != objdir builds. LLVMSRCDIR := $(shell $(LLVMBINPATH)/llvm-config --src-root) endif + +ifdef LLVM_VERSION_INFO +CPPFLAGS += -DLLVM_VERSION_INFO='"$(LLVM_VERSION_INFO)"' +endif # APPLE LOCAL end LLVM # These exists to be overridden by the x-* and t-* files, respectively. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r40532 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Author: asl
Date: Thu Jul 26 10:47:14 2007
New Revision: 40532
URL: http://llvm.org/viewvc/llvm-project?rev=40532&view=rev
Log:
This correct way to handle with globals.
This makes MultiSource/{Applications,Benchmarks} and
SingleSource/{Applications,Benchmark} (C parts) to pass
being compiled with llvm-gcc-4.2!
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=40532&r1=40531&r2=40532&view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jul 26 10:47:14 2007
@@ -5048,7 +5048,7 @@
// If this is an aggregate, emit it to LLVM now. GCC happens to
// get this case right by forcing the initializer into memory.
if (TREE_CODE(exp) == CONST_DECL || TREE_CODE(exp) == VAR_DECL) {
- if (GV->isDeclaration()) {
+ if ((DECL_INITIAL(exp) || !TREE_PUBLIC(exp)) && GV->isDeclaration()) {
emit_global_to_llvm(exp);
Decl = DECL_LLVM(exp); // Decl could have change if it changed
type.
}
@@ -6124,11 +6124,11 @@
TREE_USED(exp) = 1;
Val = cast(DECL_LLVM(exp));
}
-
+
// If this is an aggregate, emit it to LLVM now. GCC happens to
// get this case right by forcing the initializer into memory.
if (TREE_CODE(exp) == CONST_DECL || TREE_CODE(exp) == VAR_DECL) {
-if (Val->isDeclaration()) {
+if ((DECL_INITIAL(exp) || !TREE_PUBLIC(exp)) && Val->isDeclaration()) {
emit_global_to_llvm(exp);
// Decl could have change if it changed type.
Val = cast(DECL_LLVM(exp));
___
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[llvm-commits] [llvm] r40539 - /llvm/trunk/test/CodeGen/X86/2007-07-25-EpilogueBug.ll
Author: evancheng
Date: Thu Jul 26 12:45:57 2007
New Revision: 40539
URL: http://llvm.org/viewvc/llvm-project?rev=40539&view=rev
Log:
Test case for PR1573.
Added:
llvm/trunk/test/CodeGen/X86/2007-07-25-EpilogueBug.ll
Added: llvm/trunk/test/CodeGen/X86/2007-07-25-EpilogueBug.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-07-25-EpilogueBug.ll?rev=40539&view=auto
==
--- llvm/trunk/test/CodeGen/X86/2007-07-25-EpilogueBug.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2007-07-25-EpilogueBug.ll Thu Jul 26 12:45:57
2007
@@ -0,0 +1,54 @@
+; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -mcpu=i386 | \
+; RUN: %prcontext ret 1 | grep FP_REG_KILL
+; PR1573
+
+ %struct.c34006f__TsB = type { i8, i32, i32,
%struct.c34006f__TsB___b___XVN }
+ %struct.c34006f__TsB___b___XVN = type {
%struct.c34006f__TsB___b___XVN___O }
+ %struct.c34006f__TsB___b___XVN___O = type { float }
+
+define fastcc i8 @c34006f__pkg__parentEQ.213(%struct.c34006f__TsB* %x,
%struct.c34006f__TsB* %y) zeroext {
+entry:
+ %tmp190 = icmp eq i8 0, 0 ; [#uses=1]
+ %tmp207 = icmp eq i32 0, 0 ; [#uses=1]
+ %bothcond = and i1 %tmp190, %tmp207 ; [#uses=1]
+ %tmp224 = icmp eq i32 0, 0 ; [#uses=1]
+ %bothcond1 = and i1 %bothcond, %tmp224 ; [#uses=1]
+ br i1 %bothcond1, label %cond_next229, label %UnifiedReturnBlock
+
+cond_next229: ; preds = %entry
+ %tmp234 = icmp eq i8 0, 0 ; [#uses=1]
+ br i1 %tmp234, label %cond_false391, label %cond_true237
+
+cond_true237: ; preds = %cond_next229
+ %tmp268 = icmp sgt i32 0, -1; [#uses=2]
+ %max269 = select i1 %tmp268, i32 0, i32 0 ;
[#uses=1]
+ %tmp305.op = add i32 0, -1 ; [#uses=1]
+ br i1 false, label %bb328, label %cond_next315
+
+cond_next315: ; preds = %cond_true237
+ ret i8 0
+
+bb328: ; preds = %cond_true237
+ %tmp337 = select i1 %tmp268, i32 %tmp305.op, i32 -1 ;
[#uses=1]
+ %tmp347 = icmp eq i32 %tmp337, 0; [#uses=1]
+ br i1 %tmp347, label %cond_next351, label %UnifiedReturnBlock
+
+cond_next351: ; preds = %bb328
+ %tmp354 = getelementptr %struct.c34006f__TsB* %y, i32 0, i32 3
; <%struct.c34006f__TsB___b___XVN*> [#uses=1]
+ %tmp354355 = bitcast %struct.c34006f__TsB___b___XVN* %tmp354 to i8*
; [#uses=1]
+ %tmp358 = getelementptr %struct.c34006f__TsB* %x, i32 0, i32 3
; <%struct.c34006f__TsB___b___XVN*> [#uses=1]
+ %tmp358359 = bitcast %struct.c34006f__TsB___b___XVN* %tmp358 to i8*
; [#uses=1]
+ %tmp360 = tail call i32 (i8*, i8*, i32, ...)* @memcmp( i8* %tmp358359,
i8* %tmp354355, i32 %max269 ); [#uses=0]
+ ret i8 0
+
+cond_false391: ; preds = %cond_next229
+ %tmp400 = fcmp une float 0.00e+00, 0.00e+00 ;
[#uses=1]
+ %not.tmp400 = xor i1 %tmp400, true ; [#uses=1]
+ %retval = zext i1 %not.tmp400 to i8 ; [#uses=1]
+ ret i8 %retval
+
+UnifiedReturnBlock:; preds = %bb328, %entry
+ ret i8 0
+}
+
+declare i32 @memcmp(i8*, i8*, i32, ...)
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[llvm-commits] [llvm] r40531 - /llvm/trunk/lib/Transforms/Scalar/CorrelatedExprs.cpp
Author: djg
Date: Thu Jul 26 10:29:35 2007
New Revision: 40531
URL: http://llvm.org/viewvc/llvm-project?rev=40531&view=rev
Log:
Remove a bogus return statement, what appears to have been a pasto
from Relation::contradicts in Relation::incorporate.
Modified:
llvm/trunk/lib/Transforms/Scalar/CorrelatedExprs.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedExprs.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CorrelatedExprs.cpp?rev=40531&r1=40530&r2=40531&view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/CorrelatedExprs.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CorrelatedExprs.cpp Thu Jul 26 10:29:35
2007
@@ -1321,7 +1321,6 @@
}
return false;
case FCmpInst::FCMP_OGE:
-return Op == FCmpInst::FCMP_OLT;
if (Op == FCmpInst::FCMP_OEQ || Op == FCmpInst::FCMP_OGT) {
Rel = Op;
return true;
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[llvm-commits] [llvm] r40530 - /llvm/trunk/lib/VMCore/BasicBlock.cpp
Author: djg
Date: Thu Jul 26 10:25:08 2007
New Revision: 40530
URL: http://llvm.org/viewvc/llvm-project?rev=40530&view=rev
Log:
DummyInst's member functions don't need to be virtual.
Modified:
llvm/trunk/lib/VMCore/BasicBlock.cpp
Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=40530&r1=40529&r2=40530&view=diff
==
--- llvm/trunk/lib/VMCore/BasicBlock.cpp (original)
+++ llvm/trunk/lib/VMCore/BasicBlock.cpp Thu Jul 26 10:25:08 2007
@@ -40,11 +40,11 @@
LeakDetector::removeGarbageObject(this);
}
-virtual Instruction *clone() const {
+Instruction *clone() const {
assert(0 && "Cannot clone EOL");abort();
return 0;
}
-virtual const char *getOpcodeName() const { return "*end-of-list-inst*"; }
+const char *getOpcodeName() const { return "*end-of-list-inst*"; }
// Methods for support type inquiry through isa, cast, and dyn_cast...
static inline bool classof(const DummyInst *) { return true; }
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[llvm-commits] [llvm] r40516 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/TargetSelectionDAG
Author: clamb
Date: Thu Jul 26 02:34:40 2007
New Revision: 40516
URL: http://llvm.org/viewvc/llvm-project?rev=40516&view=rev
Log:
Add selection DAG nodes for subreg insert/extract. PR1350
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/Target/TargetSelectionDAG.td
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=40516&r1=40515&r2=40516&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Jul 26 02:34:40 2007
@@ -289,6 +289,15 @@
/// elements of the vector are undefined.
SCALAR_TO_VECTOR,
+// EXTRACT_SUBREG - This node is used to extract a sub-register value.
+// This node takes a superreg and a constant sub-register index as
operands.
+EXTRACT_SUBREG,
+
+// INSERT_SUBREG - This node is used to insert a sub-register value.
+// This node takes a superreg, a subreg value, and a constant sub-register
+// index as operands.
+INSERT_SUBREG,
+
// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
producing
// an unsigned/signed value of type i[2*n], then return the top part.
MULHU, MULHS,
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=40516&r1=40515&r2=40516&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jul 26 02:34:40 2007
@@ -957,7 +957,23 @@
AddLegalizedOperand(SDOperand(Node, i), Tmp1);
}
return Tmp2;
-
+ case ISD::EXTRACT_SUBREG: {
+ Tmp1 = LegalizeOp(Node->getOperand(0));
+ ConstantSDNode *idx = dyn_cast(Node->getOperand(1));
+ assert(idx && "Operand must be a constant");
+ Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+}
+break;
+ case ISD::INSERT_SUBREG: {
+ Tmp1 = LegalizeOp(Node->getOperand(0));
+ Tmp2 = LegalizeOp(Node->getOperand(1));
+ ConstantSDNode *idx = dyn_cast(Node->getOperand(2));
+ assert(idx && "Operand must be a constant");
+ Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+}
+break;
case ISD::BUILD_VECTOR:
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=40516&r1=40515&r2=40516&view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jul 26 02:34:40
2007
@@ -3455,7 +3455,10 @@
case ISD::SHL_PARTS: return "shl_parts";
case ISD::SRA_PARTS: return "sra_parts";
case ISD::SRL_PARTS: return "srl_parts";
-
+
+ case ISD::EXTRACT_SUBREG: return "extract_subreg";
+ case ISD::INSERT_SUBREG: return "insert_subreg";
+
// Conversion operators.
case ISD::SIGN_EXTEND: return "sign_extend";
case ISD::ZERO_EXTEND: return "zero_extend";
Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=40516&r1=40515&r2=40516&view=diff
==
--- llvm/trunk/lib/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/lib/Target/TargetSelectionDAG.td Thu Jul 26 02:34:40 2007
@@ -317,6 +317,11 @@
SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
+
+def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
+SDTypeProfile<1, 2, []>>;
+def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
+SDTypeProfile<1, 3, []>>;
// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
// these internally. Don't reference these directly.
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[llvm-commits] [llvm] r40515 - /llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
Author: clamb
Date: Thu Jul 26 02:03:08 2007
New Revision: 40515
URL: http://llvm.org/viewvc/llvm-project?rev=40515&view=rev
Log:
Fix 80 col violation.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=40515&r1=40514&r2=40515&view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Thu Jul 26 02:03:08
2007
@@ -37,8 +37,9 @@
/// addReg - Add a new virtual register operand...
///
const
- MachineInstrBuilder &addReg(unsigned RegNo, bool isDef = false, bool isImp =
false,
- bool isKill = false, bool isDead = false) const {
+ MachineInstrBuilder &addReg(unsigned RegNo, bool isDef = false,
+ bool isImp = false, bool isKill = false,
+ bool isDead = false) const {
MI->addRegOperand(RegNo, isDef, isImp, isKill, isDead);
return *this;
}
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[llvm-commits] [llvm] r40537 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Author: evancheng
Date: Thu Jul 26 12:32:14 2007
New Revision: 40537
URL: http://llvm.org/viewvc/llvm-project?rev=40537&view=rev
Log:
Don't pollute the meaning of isUnpredicatedTerminator.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=40537&r1=40536&r2=40537&view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jul 26 12:32:14 2007
@@ -402,11 +402,7 @@
}
}
-// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
- if (MI->getOpcode() == X86::FP_REG_KILL)
-return false;
-
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if (TID->Flags & M_TERMINATOR_FLAG) {
// Conditional branch is a special case.
@@ -419,20 +415,28 @@
return false;
}
+// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
+static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
+ const X86InstrInfo &TII) {
+ if (MI->getOpcode() == X86::FP_REG_KILL)
+return false;
+ return TII.isUnpredicatedTerminator(MI);
+}
+
bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
std::vector &Cond) const {
// If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end();
- if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
+ if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
return false;
// Get the last instruction in the block.
MachineInstr *LastInst = I;
// If there is only one terminator instruction, process it.
- if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
+ if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
if (!isBranch(LastInst->getOpcode()))
return true;
@@ -457,7 +461,8 @@
MachineInstr *SecondLastInst = I;
// If there are three terminators, we don't know what sort of block this is.
- if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
+ if (SecondLastInst && I != MBB.begin() &&
+ isBrAnalysisUnpredicatedTerminator(--I, *this))
return true;
// If the block ends with X86::JMP and a conditional branch, handle it.
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[llvm-commits] [llvm-gcc-4.2] r40525 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Author: asl
Date: Thu Jul 26 08:18:48 2007
New Revision: 40525
URL: http://llvm.org/viewvc/llvm-project?rev=40525&view=rev
Log:
Emit globals to LLVM properly (when they appear as lvalue's)
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=40525&r1=40524&r2=40525&view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jul 26 08:18:48 2007
@@ -5048,7 +5048,7 @@
// If this is an aggregate, emit it to LLVM now. GCC happens to
// get this case right by forcing the initializer into memory.
if (TREE_CODE(exp) == CONST_DECL || TREE_CODE(exp) == VAR_DECL) {
- if (DECL_INITIAL(exp) && GV->isDeclaration()) {
+ if (GV->isDeclaration()) {
emit_global_to_llvm(exp);
Decl = DECL_LLVM(exp); // Decl could have change if it changed
type.
}
@@ -6128,7 +6128,7 @@
// If this is an aggregate, emit it to LLVM now. GCC happens to
// get this case right by forcing the initializer into memory.
if (TREE_CODE(exp) == CONST_DECL || TREE_CODE(exp) == VAR_DECL) {
-if (DECL_INITIAL(exp) && Val->isDeclaration()) {
+if (Val->isDeclaration()) {
emit_global_to_llvm(exp);
// Decl could have change if it changed type.
Val = cast(DECL_LLVM(exp));
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Re: [llvm-commits] [llvm] r40521 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/LowerSubregs.cpp
On Jul 26, 2007, at 6:30 PM, Evan Cheng wrote: Should this be right after register allocation? Any reason to keep the pseudo instructions around after allocation? It should probably be after prolog/epilog insertion. As for the post RA scheduler and branch folding, I'd think it'd be OK to put it before them. Thoughts? Evan On Jul 26, 2007, at 1:18 AM, Christopher Lamb wrote: if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + + PM.add(createLowerSubregsPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r40520 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
On Jul 26, 2007, at 6:27 PM, Evan Cheng wrote:
On Jul 26, 2007, at 1:12 AM, Christopher Lamb wrote:
/// EmitNode - Generate machine code for an node and needed
dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
@@ -436,6 +578,14 @@
// If machine instruction
if (Node->isTargetOpcode()) {
unsigned Opc = Node->getTargetOpcode();
+
+// Handle subreg insert/extract specially
+if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
+Opc == TargetInstrInfo::INSERT_SUBREG) {
+ EmitSubregNode(Node, VRBaseMap);
+ return;
+}
+
Hi Chris,
Is this right? EXTRACT_SUBREG and INSERT_SUBREG are not target
opcodes.
Actually, they are both DAG nodes and target opcodes. ISel lowers the
DAG nodes to target opcodes before schedule DAG sees them.
--
Christopher Lamb
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Re: [llvm-commits] Trampoline support (pointers nested funtions)
There was a small mistake in the X86 error checking: i64 inreg arguments should count as consuming two registers. Fix: -InRegCount++; +InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r40536 - /llvm/trunk/test/CodeGen/X86/test-pic-jtbl.ll
Author: evancheng
Date: Thu Jul 26 12:07:03 2007
New Revision: 40536
URL: http://llvm.org/viewvc/llvm-project?rev=40536&view=rev
Log:
Fix test.
Modified:
llvm/trunk/test/CodeGen/X86/test-pic-jtbl.ll
Modified: llvm/trunk/test/CodeGen/X86/test-pic-jtbl.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/test-pic-jtbl.ll?rev=40536&r1=40535&r2=40536&view=diff
==
--- llvm/trunk/test/CodeGen/X86/test-pic-jtbl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/test-pic-jtbl.ll Thu Jul 26 12:07:03 2007
@@ -3,8 +3,8 @@
; RUN: grep _GLOBAL_OFFSET_TABLE_ %t
; RUN: grep piclabel %t | wc -l | grep 3
; RUN: grep PLT %t | wc -l | grep 6
-; RUN: grep GOTOFF %t | wc -l | grep 1
-; RUN: grep JTI %t | wc -l | grep 8
+; RUN: grep GOTOFF %t | wc -l | grep 2
+; RUN: grep JTI %t | wc -l | grep 9
define void @bar(i32 %n.u) {
entry:
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[llvm-commits] [129933] Restore llvm version info.
Revision: 129933 Author: echeng Date: 2007-07-26 11:52:21 -0700 (Thu, 26 Jul 2007) Log Message: --- Restore llvm version info. Modified Paths: -- apple-local/branches/llvm/gcc/Makefile.in Modified: apple-local/branches/llvm/gcc/Makefile.in === --- apple-local/branches/llvm/gcc/Makefile.in 2007-07-26 18:36:42 UTC (rev 129932) +++ apple-local/branches/llvm/gcc/Makefile.in 2007-07-26 18:52:21 UTC (rev 129933) @@ -218,10 +218,6 @@ @checkingenabled_flag@ LLVMOBJDIR = @LLVMBASEPATH@ -ifdef LLVM_VERSION_INFO -CPPFLAGS += -DLLVM_VERSION_INFO='"$(LLVM_VERSION_INFO)"' -endif - # Determine BUILDMODE from configure run (--enable-llvm) BUILDMODE := @LLVMBUILDMODE@ @@ -236,6 +232,10 @@ # srcdir != objdir builds. LLVMSRCDIR := $(shell $(LLVMBINPATH)/llvm-config --src-root) endif + +ifdef LLVM_VERSION_INFO +CPPFLAGS += -DLLVM_VERSION_INFO='"$(LLVM_VERSION_INFO)"' +endif # APPLE LOCAL end LLVM # These exists to be overridden by the x-* and t-* files, respectively. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r40520 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
I don't think they are target opcodes. These are similar to phi,
copyfromreg, etc. Target opcodes are those that are target specific,
I.e. not shared between targets.
Evan
Sent from my iPhone
On Jul 26, 2007, at 8:36 PM, Christopher Lamb <[EMAIL PROTECTED]
> wrote:
On Jul 26, 2007, at 6:27 PM, Evan Cheng wrote:
On Jul 26, 2007, at 1:12 AM, Christopher Lamb wrote:
/// EmitNode - Generate machine code for an node and needed
dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
@@ -436,6 +578,14 @@
// If machine instruction
if (Node->isTargetOpcode()) {
unsigned Opc = Node->getTargetOpcode();
+
+// Handle subreg insert/extract specially
+if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
+Opc == TargetInstrInfo::INSERT_SUBREG) {
+ EmitSubregNode(Node, VRBaseMap);
+ return;
+}
+
Hi Chris,
Is this right? EXTRACT_SUBREG and INSERT_SUBREG are not target
opcodes.
Actually, they are both DAG nodes and target opcodes. ISel lowers
the DAG nodes to target opcodes before schedule DAG sees them.
--
Christopher Lamb
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Re: [llvm-commits] [llvm] r40521 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/LowerSubregs.cpp
Sent from my iPhone On Jul 26, 2007, at 8:41 PM, Christopher Lamb <[EMAIL PROTECTED] > wrote: On Jul 26, 2007, at 6:30 PM, Evan Cheng wrote: Should this be right after register allocation? Any reason to keep the pseudo instructions around after allocation? It should probably be after prolog/epilog insertion. As for the post RA scheduler and branch folding, I'd think it'd be OK to put it before them. Thoughts? Not sure. Why do you think it's necessary for it to be after PEI? It should definitely be run before post-ra scheduler,IMHO. Evan Evan On Jul 26, 2007, at 1:18 AM, Christopher Lamb wrote: if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + + PM.add(createLowerSubregsPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] [llvm] r40520 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
On Jul 26, 2007, at 10:28 PM, Evan Cheng wrote:
I don't think they are target opcodes.
Is that a suggestion? In the implementation they are:
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Thu Jul 26
02:48:21 2007
@@ -177,7 +177,9 @@
enum {
PHI = 0,
INLINEASM = 1,
-LABEL = 2
+LABEL = 2,
+EXTRACT_SUBREG = 3,
+INSERT_SUBREG = 4
};
These are similar to phi, copyfromreg, etc.
Not quite. The copyfrom/to reg and inlineasm nodes are ISD DAG nodes
and are actually ISel'd in ScheduleDAG to the TargetInstrInfo types.
Target opcodes are those that are target specific, I.e. not shared
between targets.
They're part of the low instruction numbers for all targets.
--
Chris
On Jul 26, 2007, at 8:36 PM, Christopher Lamb
<[EMAIL PROTECTED]> wrote:
On Jul 26, 2007, at 6:27 PM, Evan Cheng wrote:
On Jul 26, 2007, at 1:12 AM, Christopher Lamb wrote:
/// EmitNode - Generate machine code for an node and needed
dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
@@ -436,6 +578,14 @@
// If machine instruction
if (Node->isTargetOpcode()) {
unsigned Opc = Node->getTargetOpcode();
+
+// Handle subreg insert/extract specially
+if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
+Opc == TargetInstrInfo::INSERT_SUBREG) {
+ EmitSubregNode(Node, VRBaseMap);
+ return;
+}
+
Hi Chris,
Is this right? EXTRACT_SUBREG and INSERT_SUBREG are not target
opcodes.
Actually, they are both DAG nodes and target opcodes. ISel lowers
the DAG nodes to target opcodes before schedule DAG sees them.
--
Christopher Lamb
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Re: [llvm-commits] [llvm] r40521 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/LowerSubregs.cpp
On Jul 26, 2007, at 10:47 PM, Evan Cheng wrote: Sent from my iPhone On Jul 26, 2007, at 8:41 PM, Christopher Lamb <[EMAIL PROTECTED]> wrote: On Jul 26, 2007, at 6:30 PM, Evan Cheng wrote: Should this be right after register allocation? Any reason to keep the pseudo instructions around after allocation? It should probably be after prolog/epilog insertion. As for the post RA scheduler and branch folding, I'd think it'd be OK to put it before them. Thoughts? Not sure. Why do you think it's necessary for it to be after PEI? Now that I think on it, I don't think moving it before PEI would preclude any future operations. It should definitely be run before post-ra scheduler,IMHO. Sure. Easy change. -- Chris Evan Evan On Jul 26, 2007, at 1:18 AM, Christopher Lamb wrote: if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + + PM.add(createLowerSubregsPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
