date:20070330

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

2007-03-30 Thread Zhou Sheng



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.710 -> 1.711
---
Log message:

1. Make sure the use of ConstantInt::getZExtValue() for getting shift
   amount is safe.
2. Use new method on ConstantInt instead of (? :) operator.
3. Use new method uge() on ConstantInt to simplify codes.


---
Diffs of the changes:  (+25 -27)

 InstructionCombining.cpp |   52 ++-
 1 files changed, 25 insertions(+), 27 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.710 
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.711
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.710   Fri Mar 30 
00:45:18 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri Mar 30 04:29:48 2007
@@ -541,8 +541,7 @@
 if ((CST = dyn_cast(I->getOperand(1 {
   // The multiplier is really 1 << CST.
   uint32_t BitWidth = cast(V->getType())->getBitWidth();
-  uint32_t CSTVal = CST->getValue().getActiveBits() > 64 ?
-  BitWidth : CST->getZExtValue();
+  uint32_t CSTVal = CST->getLimitedValue(BitWidth);
   CST = ConstantInt::get(APInt(BitWidth, 1).shl(CSTVal));
   return I->getOperand(0);
 }
@@ -745,7 +744,7 @@
   case Instruction::Shl:
 // (shl X, C1) & C2 == 0   iff   (X & C2 >>u C1) == 0
 if (ConstantInt *SA = dyn_cast(I->getOperand(1))) {
-  uint64_t ShiftAmt = SA->getZExtValue();
+  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
   APInt Mask2(Mask.lshr(ShiftAmt));
   ComputeMaskedBits(I->getOperand(0), Mask2, KnownZero, KnownOne, Depth+1);
   assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 
@@ -759,7 +758,7 @@
 // (ushr X, C1) & C2 == 0   iff  (-1 >> C1) & C2 == 0
 if (ConstantInt *SA = dyn_cast(I->getOperand(1))) {
   // Compute the new bits that are at the top now.
-  uint64_t ShiftAmt = SA->getZExtValue();
+  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
   
   // Unsigned shift right.
   APInt Mask2(Mask.shl(ShiftAmt));
@@ -776,7 +775,7 @@
 // (ashr X, C1) & C2 == 0   iff  (-1 >> C1) & C2 == 0
 if (ConstantInt *SA = dyn_cast(I->getOperand(1))) {
   // Compute the new bits that are at the top now.
-  uint64_t ShiftAmt = SA->getZExtValue();
+  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
   
   // Signed shift right.
   APInt Mask2(Mask.shl(ShiftAmt));
@@ -1306,7 +1305,7 @@
 break;
   case Instruction::Shl:
 if (ConstantInt *SA = dyn_cast(I->getOperand(1))) {
-  uint64_t ShiftAmt = SA->getZExtValue();
+  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
   APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
   if (SimplifyDemandedBits(I->getOperand(0), DemandedMaskIn, 
RHSKnownZero, RHSKnownOne, Depth+1))
@@ -1323,7 +1322,7 @@
   case Instruction::LShr:
 // For a logical shift right
 if (ConstantInt *SA = dyn_cast(I->getOperand(1))) {
-  unsigned ShiftAmt = SA->getZExtValue();
+  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
   
   // Unsigned shift right.
   APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
@@ -2984,8 +2983,7 @@
 // the anded constant includes them, clear them now!
 //
 uint32_t BitWidth = AndRHS->getType()->getBitWidth();
-uint32_t OpRHSVal = OpRHS->getValue().getActiveBits() > 64 ?
-BitWidth : OpRHS->getZExtValue();
+uint32_t OpRHSVal = OpRHS->getLimitedValue(BitWidth);
 APInt ShlMask(APInt::getHighBitsSet(BitWidth, BitWidth-OpRHSVal));
 ConstantInt *CI = ConstantInt::get(AndRHS->getValue() & ShlMask);
 
@@ -3005,8 +3003,7 @@
 // unsigned shifts, because a signed shr may bring in set bits!
 //
 uint32_t BitWidth = AndRHS->getType()->getBitWidth();
-uint32_t OpRHSVal = OpRHS->getValue().getActiveBits() > 64 ?
-BitWidth : OpRHS->getZExtValue();
+uint32_t OpRHSVal = OpRHS->getLimitedValue(BitWidth);
 APInt ShrMask(APInt::getLowBitsSet(BitWidth, BitWidth - OpRHSVal));
 ConstantInt *CI = ConstantInt::get(AndRHS->getValue() & ShrMask);
 
@@ -3025,8 +3022,7 @@
 // with an and.
 if (Op->hasOneUse()) {
   uint32_t BitWidth = AndRHS->getType()->getBitWidth();
-  uint32_t OpRHSVal = OpRHS->getValue().getActiveBits() > 64 ?
-  BitWidth : OpRHS->getZExtValue();
+  uint32_t OpRHSVal = OpRHS->getLimitedValue(BitWidth);
   APInt ShrMask(APInt::getLowBitsSet(BitWidth, BitWidth - OpRHSVal));
   Constant *C = ConstantInt::get(AndRHS->getValue() & ShrMask);
   if (C == AndRHS) {  // Masking out bits shifted in.
@@ -3541,11 +3537,12 @@
 return CollectBSwapParts(I->getOperand(0), ByteValues) ||
CollectBSwapParts(I->getOperand(1), ByteValues);
   
+  uint32_t BitWidth =

[llvm-commits] CVS: llvm/docs/AliasAnalysis.html DeveloperPolicy.html ExceptionHandling.html GarbageCollection.html LangRef.html ProgrammersManual.html SystemLibrary.html

2007-03-30 Thread Duncan Sands



Changes in directory llvm/docs:

AliasAnalysis.html updated: 1.27 -> 1.28
DeveloperPolicy.html updated: 1.37 -> 1.38
ExceptionHandling.html updated: 1.1 -> 1.2
GarbageCollection.html updated: 1.8 -> 1.9
LangRef.html updated: 1.217 -> 1.218
ProgrammersManual.html updated: 1.130 -> 1.131
SystemLibrary.html updated: 1.10 -> 1.11
---
Log message:

Various hopefully correct easy fixes.


---
Diffs of the changes:  (+26 -27)

 AliasAnalysis.html |4 ++--
 DeveloperPolicy.html   |4 ++--
 ExceptionHandling.html |8 
 GarbageCollection.html |4 ++--
 LangRef.html   |   21 ++---
 ProgrammersManual.html |8 
 SystemLibrary.html |4 ++--
 7 files changed, 26 insertions(+), 27 deletions(-)


Index: llvm/docs/AliasAnalysis.html
diff -u llvm/docs/AliasAnalysis.html:1.27 llvm/docs/AliasAnalysis.html:1.28
--- llvm/docs/AliasAnalysis.html:1.27   Mon Mar 13 23:39:39 2006
+++ llvm/docs/AliasAnalysis.htmlFri Mar 30 07:22:09 2007
@@ -70,7 +70,7 @@
 different ways of classifying them: flow-sensitive vs flow-insensitive,
 context-sensitive vs context-insensitive, field-sensitive vs field-insensitive,
 unification-based vs subset-based, etc.  Traditionally, alias analyses respond
-to a query with a Must, May, or No alias response,
+to a query with a Must, May, or No alias response,
 indicating that two pointers always point to the same object, might point to 
the
 same object, or are known to never point to the same object.
 
@@ -952,7 +952,7 @@
 
   mailto:[EMAIL PROTECTED]">Chris Lattner
   http://llvm.org";>LLVM Compiler Infrastructure
-  Last modified: $Date: 2006/03/14 05:39:39 $
+  Last modified: $Date: 2007/03/30 12:22:09 $
 
 
 


Index: llvm/docs/DeveloperPolicy.html
diff -u llvm/docs/DeveloperPolicy.html:1.37 llvm/docs/DeveloperPolicy.html:1.38
--- llvm/docs/DeveloperPolicy.html:1.37 Thu Mar  1 20:57:34 2007
+++ llvm/docs/DeveloperPolicy.html  Fri Mar 30 07:22:09 2007
@@ -162,7 +162,7 @@
 bug being fixed or feature being implemented is in the llvm-gcc C++
 front-end, in which case it must be written in C++).
 Test cases, especially for regressions, should be reduced as much as 
-possible, by bugpoint or
+possible, by bugpoint or
 manually. It is unacceptable 
 to place an entire failing program into llvm/test as this creates
 a time-to-test burden on all developers. Please keep them 
short.
@@ -499,7 +499,7 @@
   Written by the 
   mailto:[EMAIL PROTECTED]">LLVM Oversight Group
   http://llvm.org";>The LLVM Compiler Infrastructure
-  Last modified: $Date: 2007/03/02 02:57:34 $
+  Last modified: $Date: 2007/03/30 12:22:09 $
 
 
 


Index: llvm/docs/ExceptionHandling.html
diff -u llvm/docs/ExceptionHandling.html:1.1 
llvm/docs/ExceptionHandling.html:1.2
--- llvm/docs/ExceptionHandling.html:1.1Wed Mar 14 14:29:42 2007
+++ llvm/docs/ExceptionHandling.htmlFri Mar 30 07:22:09 2007
@@ -22,10 +22,10 @@
   
 Throw
 Try/Catch
-Finallys
+Finallys
 Throw Filters
   
-  Exception Handling Intrinsics
+  Exception Handling Intrinsics
   
llvm.eh.exception
llvm.eh.selector
@@ -281,7 +281,7 @@
 
 
 
-  Exception Handling Intrinsics
+  Exception Handling Intrinsics
 
 
 
@@ -453,7 +453,7 @@
 
   mailto:[EMAIL PROTECTED]">Chris Lattner
   http://llvm.org";>LLVM Compiler Infrastructure
-  Last modified: $Date: 2007/03/14 19:29:42 $
+  Last modified: $Date: 2007/03/30 12:22:09 $
 
 
 


Index: llvm/docs/GarbageCollection.html
diff -u llvm/docs/GarbageCollection.html:1.8 
llvm/docs/GarbageCollection.html:1.9
--- llvm/docs/GarbageCollection.html:1.8Mon Mar 13 23:39:39 2006
+++ llvm/docs/GarbageCollection.htmlFri Mar 30 07:22:09 2007
@@ -387,7 +387,7 @@
 generator that iterates through all of the GC roots on the stack, calling the
 specified function pointer with each record.  For each GC root, the address of
 the pointer and the meta-data (from the llvm.gcroot intrinsic) are provided.
+href="#roots">llvm.gcroot intrinsic) are provided.
 
 
 
@@ -526,7 +526,7 @@
 
   mailto:[EMAIL PROTECTED]">Chris Lattner
   http://llvm.org";>LLVM Compiler Infrastructure
-  Last modified: $Date: 2006/03/14 05:39:39 $
+  Last modified: $Date: 2007/03/30 12:22:09 $
 
 
 


Index: llvm/docs/LangRef.html
diff -u llvm/docs/LangRef.html:1.217 llvm/docs/LangRef.html:1.218
--- llvm/docs/LangRef.html:1.217Tue Mar 27 21:46:29 2007
+++ llvm/docs/LangRef.html  Fri Mar 30 07:22:09 2007
@@ -27,7 +27,6 @@
   Parameter Attributes
   Module-Level Inline Assembly
   Data Layout
-  Check Points
 
   
   Type System
@@ -886,7 +885,7 @@
   
 
 TypeDescription
-voidNo value
+voidNo value
 i88-bit value
 i3232-bit value
 float32-bit floating point value
@@ -1714,7 +1713,7 @@
 
 
   
-The optional "cconv" marker indicates which calling
+The optional "cconv" marker indicates which calling
 convention the call sho

Re: [llvm-commits] CVS: llvm/docs/AliasAnalysis.html DeveloperPolicy.html ExceptionHandling.html GarbageCollection.html LangRef.html ProgrammersManual.html SystemLibrary.html

2007-03-30 Thread Reid Spencer

Duncan, 

A Couple notes ..

On Fri, 2007-03-30 at 07:22 -0500, Duncan Sands wrote:

> 
> Index: llvm/docs/DeveloperPolicy.html
> diff -u llvm/docs/DeveloperPolicy.html:1.37 
> llvm/docs/DeveloperPolicy.html:1.38
> --- llvm/docs/DeveloperPolicy.html:1.37   Thu Mar  1 20:57:34 2007
> +++ llvm/docs/DeveloperPolicy.htmlFri Mar 30 07:22:09 2007
> @@ -162,7 +162,7 @@
>  bug being fixed or feature being implemented is in the llvm-gcc C++
>  front-end, in which case it must be written in C++).
>  Test cases, especially for regressions, should be reduced as much as 
> -possible, by bugpoint or
> +possible, by bugpoint or

These aren't the same document. If the bugpoint.html document isn't
there its an artifact of not generating the HTML version from the POD
version.  This isn't a huge deal for the link, but do we have a larger
issue generating the command pages?
 

> 
> Index: llvm/docs/LangRef.html
> diff -u llvm/docs/LangRef.html:1.217 llvm/docs/LangRef.html:1.218
> --- llvm/docs/LangRef.html:1.217  Tue Mar 27 21:46:29 2007
> +++ llvm/docs/LangRef.htmlFri Mar 30 07:22:09 2007
> @@ -27,7 +27,6 @@
>Parameter Attributes
>Module-Level Inline Assembly
>Data Layout
> -  Check Points

Can you delete the CheckPoints section too? Its going away soon, when
PR1289 is closed.

Thx.

>  
>
>Type System
> @@ -886,7 +885,7 @@
>
>  
>  TypeDescription
> -voidNo value
> +voidNo value
>  i88-bit value
>  i3232-bit value
>  float32-bit floating point value

Why not put in links for the other types?


Thanks,

Reid.

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Re: [llvm-commits] CVS: llvm/docs/AliasAnalysis.html DeveloperPolicy.html ExceptionHandling.html GarbageCollection.html LangRef.html ProgrammersManual.html SystemLibrary.html

2007-03-30 Thread Duncan Sands

Hi Reid,

> > -possible, by bugpoint or
> > +possible, by bugpoint or
> 
> These aren't the same document. If the bugpoint.html document isn't
> there its an artifact of not generating the HTML version from the POD
> version.  This isn't a huge deal for the link, but do we have a larger
> issue generating the command pages?

I first changed this mistakenly, because I hadn't generated the html files,
but when I realized it was a mistake it struck me that it was better this way,
so I left it rather than changing it back.

> > -  Check Points
> 
> Can you delete the CheckPoints section too? Its going away soon, when
> PR1289 is closed.

There is no checkpoints section, there is only "Data Layout".  However
"Data Layout" talks only of checkpoints.  Would you like me to delete it?


  Data Layout


  At the top level, the keyword checkpoint may be used to force the
  assembler to check point the types and values it has defined so far. Any
  unresolved types or references will generate error messages. This is useful
  as an assertion point or for debugging.



> > -voidNo value
> > +voidNo 
> > value
> >  i88-bit value
> >  i3232-bit value
> >  float32-bit floating point 
> > value
> 
> Why not put in links for the other types?

Because they have their own sections with an anchor, eg t_integer refers to the
section on integers.  Void is the only type that doesn't have its own section.
Probably it should get one.

Ciao,

Duncan.
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Re: [llvm-commits] CVS: llvm/lib/System/Unix/MappedFile.inc

2007-03-30 Thread Jeff Cohen

Chris Lattner wrote:
>> Use the stat information in the Path object, if it is already  
>> obtained. This
>> avoids a call to ::fstat by MappedFile when the file size  
>> information was
>> already obtained by the Path object.
>> 
>
> Interesting approach.  The problem is that fstat is significantly  
> faster than stat.  How about a new Path::getFileStatusFromFD()  
> method, which takes an open file descriptor.  If the System supports  
> it, it can get status information faster by using it, otherwise it  
> falls back to getFileStatus (e.g. if win32 doesn't have fstat)?
>
> -Chris
>   

It does, but names it _fstat.  I'm not sure it's worth the bother to 
cache fstat either.  stat is slow because it has to look up the file path.
>   
>> ---
>> Diffs of the changes:  (+3 -4)
>>
>>  MappedFile.inc |7 +++
>>  1 files changed, 3 insertions(+), 4 deletions(-)
>>
>>
>> Index: llvm/lib/System/Unix/MappedFile.inc
>> diff -u llvm/lib/System/Unix/MappedFile.inc:1.18 llvm/lib/System/ 
>> Unix/MappedFile.inc:1.19
>> --- llvm/lib/System/Unix/MappedFile.inc:1.18 Fri Aug 25 16:37:17 2006
>> +++ llvm/lib/System/Unix/MappedFile.inc  Thu Mar 29 14:11:22 2007
>> @@ -54,15 +54,14 @@
>>  MakeErrMsg(ErrMsg, "can't open file '" + path_.toString() + "'");
>>  return true;
>>}
>> -  struct stat sbuf;
>> -  if(::fstat(FD, &sbuf) < 0) {
>> -MakeErrMsg(ErrMsg, "can't stat file '"+ path_.toString() + "'");
>> +  const FileStatus *Status = path_.getFileStatus(false, ErrMsg);
>> +  if (!Status) {
>>  ::close(FD);
>>  return true;
>>}
>>info_ = new MappedFileInfo;
>>info_->FD = FD;
>> -  info_->Size = sbuf.st_size;
>> +  info_->Size = Status->getSize();
>>return false;
>>  }
>>
>>
>>
>>
>> ___
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>> llvm-commits@cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>
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>
>
>   

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Re: [llvm-commits] CVS: llvm/docs/AliasAnalysis.html DeveloperPolicy.html ExceptionHandling.html GarbageCollection.html LangRef.html ProgrammersManual.html SystemLibrary.html

2007-03-30 Thread Reid Spencer

Hi Duncan,

On Fri, 2007-03-30 at 16:39 +0200, Duncan Sands wrote:
> Hi Reid,
> 
> > > -possible, by bugpoint 
> > > or
> > > +possible, by bugpoint or
> > 
> > These aren't the same document. If the bugpoint.html document isn't
> > there its an artifact of not generating the HTML version from the POD
> > version.  This isn't a huge deal for the link, but do we have a larger
> > issue generating the command pages?
> 
> I first changed this mistakenly, because I hadn't generated the html files,
> but when I realized it was a mistake it struck me that it was better this way,
> so I left it rather than changing it back.

Okay, that's fine.

> 
> > > -  Check Points
> > 
> > Can you delete the CheckPoints section too? Its going away soon, when
> > PR1289 is closed.
> 
> There is no checkpoints section, there is only "Data Layout".  However
> "Data Layout" talks only of checkpoints.  Would you like me to delete it?
> 
> 
>   Data Layout
> 
> 
>   At the top level, the keyword checkpoint may be used to force 
> the
>   assembler to check point the types and values it has defined so far. Any
>   unresolved types or references will generate error messages. This is useful
>   as an assertion point or for debugging.
> 

Yes, delete that whole  and the doc_subsection too
if that's the only paragraph in it. The checkpoint thing is not
supported any more.  I know this isn't your change, but since you're in
there ... :)

> 
> 
> > > -voidNo value
> > > +voidNo 
> > > value
> > >  i88-bit value
> > >  i3232-bit value
> > >  float32-bit floating point 
> > > value
> > 
> > Why not put in links for the other types?
> 
> Because they have their own sections with an anchor, eg t_integer refers to 
> the
> section on integers.  Void is the only type that doesn't have its own section.
> Probably it should get one.

Oh, yeah, sorry, thought that was an href="#t_void" you put in there. 

In this case, this link isn't good. We don't want a link coming to this
table because itw ill confuse the reader. Please add a section near
t_integer for t_void.  Then, make all of these table entries have links
to the type's section.

Thx,

Reid.

> 
> Ciao,
> 
> Duncan.

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[llvm-commits] CVS: llvm/docs/LangRef.html

2007-03-30 Thread Duncan Sands



Changes in directory llvm/docs:

LangRef.html updated: 1.218 -> 1.219
---
Log message:

Remove reference to checkpoint.


---
Diffs of the changes:  (+1 -11)

 LangRef.html |   12 +---
 1 files changed, 1 insertion(+), 11 deletions(-)


Index: llvm/docs/LangRef.html
diff -u llvm/docs/LangRef.html:1.218 llvm/docs/LangRef.html:1.219
--- llvm/docs/LangRef.html:1.218Fri Mar 30 07:22:09 2007
+++ llvm/docs/LangRef.html  Fri Mar 30 11:09:58 2007
@@ -846,16 +846,6 @@
   terms of 64 <2 x double>, for example.
 
 
-
-
-  Data Layout
-
-
-  At the top level, the keyword checkpoint may be used to force the
-  assembler to check point the types and values it has defined so far. Any
-  unresolved types or references will generate error messages. This is useful
-  as an assertion point or for debugging.
-
 
 
  Type System 
@@ -4610,7 +4600,7 @@
 
   mailto:[EMAIL PROTECTED]">Chris Lattner
   http://llvm.org";>The LLVM Compiler Infrastructure
-  Last modified: $Date: 2007/03/30 12:22:09 $
+  Last modified: $Date: 2007/03/30 16:09:58 $
 
 
 



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Re: [llvm-commits] CVS: llvm/docs/AliasAnalysis.html DeveloperPolicy.html ExceptionHandling.html GarbageCollection.html LangRef.html ProgrammersManual.html SystemLibrary.html

2007-03-30 Thread Duncan Sands

> > There is no checkpoints section, there is only "Data Layout".  However
> > "Data Layout" talks only of checkpoints.  Would you like me to delete it?
...
> Yes, delete that whole  and the doc_subsection too
> if that's the only paragraph in it. The checkpoint thing is not
> supported any more.  I know this isn't your change, but since you're in
> there ... :)

Done.

> > > > -voidNo value
> > > > +voidNo 
> > > > value
> > > >  i88-bit value
> > > >  i3232-bit value
> > > >  float32-bit floating point 
> > > > value
> > > 
> > > Why not put in links for the other types?
> > 
> > Because they have their own sections with an anchor, eg t_integer refers to 
> > the
> > section on integers.  Void is the only type that doesn't have its own 
> > section.
> > Probably it should get one.
> 
> Oh, yeah, sorry, thought that was an href="#t_void" you put in there. 
> 
> In this case, this link isn't good. We don't want a link coming to this
> table because itw ill confuse the reader. Please add a section near
> t_integer for t_void.  Then, make all of these table entries have links
> to the type's section.

Actually, the integer and floating point types don't have their own section.
#t_integer and #t_floating refer to the entries in the next table.  I don't
think leaving t_void anchor where it is will confuse anyone.

Ciao,

Duncan.
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[llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp

2007-03-30 Thread Reid Spencer



Changes in directory llvm/lib/ExecutionEngine/Interpreter:

ExternalFunctions.cpp updated: 1.96 -> 1.97
---
Log message:

For PR1293: http://llvm.org/PR1293 :
* Rename the FunctionType* parameter from M to FT on all the functions.
* Implement a fix for PR1293: http://llvm.org/PR1293  by just asserting that 
library functions that
  must return pointers should have pointer typed results. This just makes
  sure that we don't attempt to use an uninitialized integer or something
  later on.


---
Diffs of the changes:  (+67 -49)

 ExternalFunctions.cpp |  116 --
 1 files changed, 67 insertions(+), 49 deletions(-)


Index: llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
diff -u llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp:1.96 
llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp:1.97
--- llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp:1.96 Mon Mar 
 5 21:08:12 2007
+++ llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp  Fri Mar 30 
11:41:50 2007
@@ -113,25 +113,25 @@
 extern "C" {  // Don't add C++ manglings to llvm mangling :)
 
 // void putchar(sbyte)
-GenericValue lle_VB_putchar(FunctionType *M, const vector &Args) 
{
+GenericValue lle_VB_putchar(FunctionType *FT, const vector 
&Args){
   cout << ((char)Args[0].IntVal.getZExtValue());
   return GenericValue();
 }
 
 // int putchar(int)
-GenericValue lle_ii_putchar(FunctionType *M, const vector &Args) 
{
+GenericValue lle_ii_putchar(FunctionType *FT, const vector 
&Args){
   cout << ((char)Args[0].IntVal.getZExtValue()) << std::flush;
   return Args[0];
 }
 
 // void putchar(ubyte)
-GenericValue lle_Vb_putchar(FunctionType *M, const vector &Args) 
{
+GenericValue lle_Vb_putchar(FunctionType *FT, const vector 
&Args){
   cout << ((char)Args[0].IntVal.getZExtValue()) << std::flush;
   return Args[0];
 }
 
 // void atexit(Function*)
-GenericValue lle_X_atexit(FunctionType *M, const vector &Args) {
+GenericValue lle_X_atexit(FunctionType *FT, const vector &Args) {
   assert(Args.size() == 1);
   TheInterpreter->addAtExitHandler((Function*)GVTOP(Args[0]));
   GenericValue GV;
@@ -140,39 +140,48 @@
 }
 
 // void exit(int)
-GenericValue lle_X_exit(FunctionType *M, const vector &Args) {
+GenericValue lle_X_exit(FunctionType *FT, const vector &Args) {
   TheInterpreter->exitCalled(Args[0]);
   return GenericValue();
 }
 
 // void abort(void)
-GenericValue lle_X_abort(FunctionType *M, const vector &Args) {
+GenericValue lle_X_abort(FunctionType *FT, const vector &Args) {
   raise (SIGABRT);
   return GenericValue();
 }
 
 // void *malloc(uint)
-GenericValue lle_X_malloc(FunctionType *M, const vector &Args) {
+GenericValue lle_X_malloc(FunctionType *FT, const vector &Args) {
   assert(Args.size() == 1 && "Malloc expects one argument!");
+  assert(isa(FT->getReturnType()) && "malloc must return 
pointer");
   return PTOGV(malloc(Args[0].IntVal.getZExtValue()));
 }
 
 // void *calloc(uint, uint)
-GenericValue lle_X_calloc(FunctionType *M, const vector &Args) {
+GenericValue lle_X_calloc(FunctionType *FT, const vector &Args) {
   assert(Args.size() == 2 && "calloc expects two arguments!");
+  assert(isa(FT->getReturnType()) && "calloc must return 
pointer");
   return PTOGV(calloc(Args[0].IntVal.getZExtValue(), 
   Args[1].IntVal.getZExtValue()));
 }
 
+// void *calloc(uint, uint)
+GenericValue lle_X_realloc(FunctionType *FT, const vector &Args) 
{
+  assert(Args.size() == 2 && "calloc expects two arguments!");
+  assert(isa(FT->getReturnType()) &&"realloc must return 
pointer");
+  return PTOGV(realloc(GVTOP(Args[0]), Args[1].IntVal.getZExtValue()));
+}
+
 // void free(void *)
-GenericValue lle_X_free(FunctionType *M, const vector &Args) {
+GenericValue lle_X_free(FunctionType *FT, const vector &Args) {
   assert(Args.size() == 1);
   free(GVTOP(Args[0]));
   return GenericValue();
 }
 
 // int atoi(char *)
-GenericValue lle_X_atoi(FunctionType *M, const vector &Args) {
+GenericValue lle_X_atoi(FunctionType *FT, const vector &Args) {
   assert(Args.size() == 1);
   GenericValue GV;
   GV.IntVal = APInt(32, atoi((char*)GVTOP(Args[0])));
@@ -180,7 +189,7 @@
 }
 
 // double pow(double, double)
-GenericValue lle_X_pow(FunctionType *M, const vector &Args) {
+GenericValue lle_X_pow(FunctionType *FT, const vector &Args) {
   assert(Args.size() == 2);
   GenericValue GV;
   GV.DoubleVal = pow(Args[0].DoubleVal, Args[1].DoubleVal);
@@ -188,7 +197,7 @@
 }
 
 // double exp(double)
-GenericValue lle_X_exp(FunctionType *M, const vector &Args) {
+GenericValue lle_X_exp(FunctionType *FT, const vector &Args) {
   assert(Args.size() == 1);
   GenericValue GV;
   GV.DoubleVal = exp(Args[0].DoubleVal);
@@ -196,7 +205,7 @@
 }
 
 // double sqrt(double)
-GenericValue lle_X_sqrt(FunctionType *M, const vector &Args) {
+GenericValue lle_X_sqrt(FunctionType *FT, const vector &Args) {
   assert(Args.size() == 1);
   GenericValue GV;
   GV.DoubleVal = sqrt(Args[0].DoubleVal);

Re: [llvm-commits] CVS: llvm/lib/System/Unix/MappedFile.inc

2007-03-30 Thread Chris Lattner


On Mar 30, 2007, at 7:49 AM, Jeff Cohen wrote:

> Chris Lattner wrote:
>>> Use the stat information in the Path object, if it is already   
>>> obtained. This
>>> avoids a call to ::fstat by MappedFile when the file size   
>>> information was
>>> already obtained by the Path object.
>>>
>>
>> Interesting approach.  The problem is that fstat is significantly   
>> faster than stat.  How about a new Path::getFileStatusFromFD()   
>> method, which takes an open file descriptor.  If the System  
>> supports  it, it can get status information faster by using it,  
>> otherwise it  falls back to getFileStatus (e.g. if win32 doesn't  
>> have fstat)?
>>
>> -Chris
>>
>
> It does, but names it _fstat.  I'm not sure it's worth the bother  
> to cache fstat either.  stat is slow because it has to look up the  
> file path.

fstat is slow because it's a syscall, meaning you have to cross the  
userspace/kernel boundary.

-Chris
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[llvm-commits] CVS: llvm/include/llvm/Constants.h

2007-03-30 Thread Zhou Sheng



Changes in directory llvm/include/llvm:

Constants.h updated: 1.142 -> 1.143
---
Log message:

Make sure this method just return value equal or less than Limit.


---
Diffs of the changes:  (+2 -1)

 Constants.h |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Constants.h
diff -u llvm/include/llvm/Constants.h:1.142 llvm/include/llvm/Constants.h:1.143
--- llvm/include/llvm/Constants.h:1.142 Fri Mar 30 00:10:59 2007
+++ llvm/include/llvm/Constants.h   Fri Mar 30 11:50:28 2007
@@ -187,7 +187,8 @@
   /// not greater than 64, otherwise, just return the given uint64_t number.
   /// @brief Get the constant's value if possible.
   uint64_t getLimitedValue(uint64_t Limit) {
-return (Val.getActiveBits() > 64) ? Limit : Val.getZExtValue();
+return (Val.getActiveBits() > 64 || Val.getZExtValue() > Limit) ? 
+   Limit : Val.getZExtValue();
   }
 
   /// @returns the value for an integer constant of the given type that has all



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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

2007-03-30 Thread Zhou Sheng



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.711 -> 1.712
---
Log message:

Make sure the use of ConstantInt::getZExtValue() for shift amount safe.


---
Diffs of the changes:  (+20 -18)

 InstructionCombining.cpp |   38 --
 1 files changed, 20 insertions(+), 18 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.711 
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.712
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.711   Fri Mar 30 
04:29:48 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri Mar 30 12:20:39 2007
@@ -1354,7 +1354,7 @@
 }
 
 if (ConstantInt *SA = dyn_cast(I->getOperand(1))) {
-  unsigned ShiftAmt = SA->getZExtValue();
+  uint32_t ShiftAmt = SA->getLimitedValue(BitWidth);
   
   // Signed shift right.
   APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
@@ -2095,12 +2095,12 @@
 
 // -(X >>u 31) -> (X >>s 31)
 // -(X >>s 31) -> (X >>u 31)
-if (C->isNullValue()) {
+if (C->isZero()) {
   if (BinaryOperator *SI = dyn_cast(Op1))
 if (SI->getOpcode() == Instruction::LShr) {
   if (ConstantInt *CU = dyn_cast(SI->getOperand(1))) {
 // Check to see if we are shifting out everything but the sign bit.
-if (CU->getZExtValue() == 
+if (CU->getLimitedValue(SI->getType()->getPrimitiveSizeInBits()) ==
 SI->getType()->getPrimitiveSizeInBits()-1) {
   // Ok, the transformation is safe.  Insert AShr.
   return BinaryOperator::create(Instruction::AShr, 
@@ -2111,7 +2111,7 @@
 else if (SI->getOpcode() == Instruction::AShr) {
   if (ConstantInt *CU = dyn_cast(SI->getOperand(1))) {
 // Check to see if we are shifting out everything but the sign bit.
-if (CU->getZExtValue() == 
+if (CU->getLimitedValue(SI->getType()->getPrimitiveSizeInBits()) ==
 SI->getType()->getPrimitiveSizeInBits()-1) {
   // Ok, the transformation is safe.  Insert LShr. 
   return BinaryOperator::createLShr(
@@ -4789,7 +4789,8 @@
 if (!CanFold) {
   // To test for the bad case of the signed shr, see if any
   // of the bits shifted in could be tested after the mask.
-  int ShAmtVal = 
Ty->getPrimitiveSizeInBits()-ShAmt->getZExtValue();
+  uint32_t TyBits = Ty->getPrimitiveSizeInBits();
+  int ShAmtVal = TyBits - ShAmt->getLimitedValue(TyBits);
   if (ShAmtVal < 0) ShAmtVal = 0; // Out of range shift.
 
   uint32_t BitWidth = AndTy->getPrimitiveSizeInBits();
@@ -4883,7 +4884,7 @@
 
 if (LHSI->hasOneUse()) {
   // Otherwise strength reduce the shift into an and.
-  unsigned ShAmtVal = (unsigned)ShAmt->getZExtValue();
+  uint32_t ShAmtVal = (uint32_t)ShAmt->getLimitedValue(TypeBits);
   uint64_t Val = (1ULL << (TypeBits-ShAmtVal))-1;
   Constant *Mask = ConstantInt::get(CI->getType(), Val);
 
@@ -4926,7 +4927,7 @@
 }
 
 if (LHSI->hasOneUse() || CI->isNullValue()) {
-  unsigned ShAmtVal = (unsigned)ShAmt->getZExtValue();
+  uint32_t ShAmtVal = (uint32_t)ShAmt->getLimitedValue(TypeBits);
 
   // Otherwise strength reduce the shift into an and.
   APInt Val(APInt::getHighBitsSet(TypeBits, TypeBits - ShAmtVal));
@@ -5658,7 +5659,7 @@
   BinaryOperator::create(Op0BO->getOpcode(), YS, V1,
  Op0BO->getOperand(1)->getName());
 InsertNewInstBefore(X, I);  // (X + (Y << C))
-uint32_t Op1Val = Op1->getZExtValue();
+uint32_t Op1Val = Op1->getLimitedValue(TypeBits);
 return BinaryOperator::createAnd(X, ConstantInt::get(
APInt::getHighBitsSet(TypeBits, TypeBits-Op1Val)));
   }
@@ -5697,7 +5698,7 @@
   BinaryOperator::create(Op0BO->getOpcode(), V1, YS,
  Op0BO->getOperand(0)->getName());
 InsertNewInstBefore(X, I);  // (X + (Y << C))
-uint32_t Op1Val = Op1->getZExtValue();
+uint32_t Op1Val = Op1->getLimitedValue(TypeBits);
 return BinaryOperator::createAnd(X, ConstantInt::get(
APInt::getHighBitsSet(TypeBits, TypeBits-Op1Val)));
   }
@@ -6084,8 +6085,9 @@
 // If we are truncating the result of this SHL, and if it's a shift of a
 // constant amount, we can always perform a SHL in a smaller type.
 if (ConstantInt *CI = dyn_cast(I->getOperand(1))) {
-  if (Ty->getBitWidth() < OrigTy->getBitWidth() &&
-  CI->getZExtValue() < Ty->getBitWidth())
+  uint32_t BitWidth = Ty->getBitWidth();
+  if (BitWidth < OrigTy->getBitWidth()

[llvm-commits] Cleanups in ROTL/ROTR DAG combiner code

2007-03-30 Thread Scott Michel

The attached patch contains:

- Cleanups in the DAGCombiner.cpp ROTL/ROTR combine code, primarily
  helping me to fix 80col violations (benefiting the code as a whole).
  
- Detect sign/zext/any-extended versions of ROTL/ROTR patterns.

- Allow custom lowering for ROTL/ROTR (needed in the CellSPU's case
  for 8-bit rotates, when only 16-bit and 32-bit rotates are actually
  implemented in the instruction set.)


-scooter
Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp(.../trunk) (revision 2118)
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp(.../branches/llvm-spu) 
(revision 2118)
@@ -2683,10 +2683,24 @@
   case ISD::ROTR:
 Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
 Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
-
-assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
-   "Cannot handle this yet!");
 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
+default:
+  assert(0 && "ROTL/ROTR legalize operation not supported");
+  break;
+case TargetLowering::Legal:
+  break;
+case TargetLowering::Custom:
+  Tmp1 = TLI.LowerOperation(Result, DAG);
+  if (Tmp1.Val) Result = Tmp1;
+  break;
+case TargetLowering::Promote:
+  assert(0 && "Do not know how to promote ROTL/ROTR");
+  break;
+case TargetLowering::Expand:
+  assert(0 && "Do not know how to expand ROTL/ROTR");
+  break;
+}
 break;
 
   case ISD::BSWAP:
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp(.../trunk) (revision 2118)
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp(.../branches/llvm-spu) 
(revision 2118)
@@ -1488,23 +1488,24 @@
   }
 
   unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+  SDOperand LHSShiftArg = LHSShift.getOperand(0);
+  SDOperand LHSShiftAmt = LHSShift.getOperand(1);
+  SDOperand RHSShiftAmt = RHSShift.getOperand(1);
 
   // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
   // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
-  if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
-  RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
-uint64_t LShVal = cast(LHSShift.getOperand(1))->getValue();
-uint64_t RShVal = cast(RHSShift.getOperand(1))->getValue();
+  if (LHSShiftAmt.getOpcode() == ISD::Constant &&
+  RHSShiftAmt.getOpcode() == ISD::Constant) {
+uint64_t LShVal = cast(LHSShiftAmt)->getValue();
+uint64_t RShVal = cast(RHSShiftAmt)->getValue();
 if ((LShVal + RShVal) != OpSizeInBits)
   return 0;
 
 SDOperand Rot;
 if (HasROTL)
-  Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
-LHSShift.getOperand(1));
+  Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
 else
-  Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
-RHSShift.getOperand(1));
+  Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
 
 // If there is an AND of either shifted operand, apply it to the result.
 if (LHSMask.Val || RHSMask.Val) {
@@ -1532,35 +1533,71 @@
   
   // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
   // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
-  if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
-  LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
+  if (RHSShiftAmt.getOpcode() == ISD::SUB &&
+  LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
 if (ConstantSDNode *SUBC = 
-  dyn_cast(RHSShift.getOperand(1).getOperand(0))) {
+  dyn_cast(RHSShiftAmt.getOperand(0))) {
   if (SUBC->getValue() == OpSizeInBits)
 if (HasROTL)
-  return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+  return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
 else
-  return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+  return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, LHSShiftAmt).Val;
 }
   }
   
   // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
   // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
-  if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
-  RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
+  if (LHSShiftAmt.getOpcode() == ISD::SUB &&
+  RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
 if (ConstantSDNode *SUBC = 
-  dyn_cast(LHSShift.getOperand(1).getOperand(0))) {
+  dyn_cast(LHSShiftAmt.getOperand(0))) {
   if (SUBC->getValue() == OpSizeInBits)
 if (HasROTL)
-  return DAG.getNod

[llvm-commits] Patch resubmit: ROTL/ROTR cleanups

2007-03-30 Thread Scott Michel

Spotted what was probably a long-standing bug, since some of my cleanups
were simple substitutions.


-scooter
Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp(.../trunk) (revision 2119)
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp(.../branches/llvm-spu) 
(revision 2119)
@@ -2683,10 +2683,24 @@
   case ISD::ROTR:
 Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
 Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
-
-assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
-   "Cannot handle this yet!");
 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
+default:
+  assert(0 && "ROTL/ROTR legalize operation not supported");
+  break;
+case TargetLowering::Legal:
+  break;
+case TargetLowering::Custom:
+  Tmp1 = TLI.LowerOperation(Result, DAG);
+  if (Tmp1.Val) Result = Tmp1;
+  break;
+case TargetLowering::Promote:
+  assert(0 && "Do not know how to promote ROTL/ROTR");
+  break;
+case TargetLowering::Expand:
+  assert(0 && "Do not know how to expand ROTL/ROTR");
+  break;
+}
 break;
 
   case ISD::BSWAP:
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp(.../trunk) (revision 2119)
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp(.../branches/llvm-spu) 
(revision 2119)
@@ -1488,23 +1488,24 @@
   }
 
   unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+  SDOperand LHSShiftArg = LHSShift.getOperand(0);
+  SDOperand LHSShiftAmt = LHSShift.getOperand(1);
+  SDOperand RHSShiftAmt = RHSShift.getOperand(1);
 
   // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
   // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
-  if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
-  RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
-uint64_t LShVal = cast(LHSShift.getOperand(1))->getValue();
-uint64_t RShVal = cast(RHSShift.getOperand(1))->getValue();
+  if (LHSShiftAmt.getOpcode() == ISD::Constant &&
+  RHSShiftAmt.getOpcode() == ISD::Constant) {
+uint64_t LShVal = cast(LHSShiftAmt)->getValue();
+uint64_t RShVal = cast(RHSShiftAmt)->getValue();
 if ((LShVal + RShVal) != OpSizeInBits)
   return 0;
 
 SDOperand Rot;
 if (HasROTL)
-  Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
-LHSShift.getOperand(1));
+  Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
 else
-  Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
-RHSShift.getOperand(1));
+  Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
 
 // If there is an AND of either shifted operand, apply it to the result.
 if (LHSMask.Val || RHSMask.Val) {
@@ -1532,35 +1533,71 @@
   
   // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
   // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
-  if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
-  LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
+  if (RHSShiftAmt.getOpcode() == ISD::SUB &&
+  LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
 if (ConstantSDNode *SUBC = 
-  dyn_cast(RHSShift.getOperand(1).getOperand(0))) {
+  dyn_cast(RHSShiftAmt.getOperand(0))) {
   if (SUBC->getValue() == OpSizeInBits)
 if (HasROTL)
-  return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+  return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
 else
-  return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+  return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
 }
   }
   
   // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
   // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
-  if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
-  RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
+  if (LHSShiftAmt.getOpcode() == ISD::SUB &&
+  RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
 if (ConstantSDNode *SUBC = 
-  dyn_cast(LHSShift.getOperand(1).getOperand(0))) {
+  dyn_cast(LHSShiftAmt.getOperand(0))) {
   if (SUBC->getValue() == OpSizeInBits)
 if (HasROTL)
-  return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+  return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
 else
-  return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 
- RHSShift.getOperand(1)).

[llvm-commits] CVS: llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll

2007-03-30 Thread Evan Cheng



Changes in directory llvm/test/CodeGen/ARM:

2007-03-30-RegScavengerAssert.ll added (r1.1)
---
Log message:

Test case for PR1279: http://llvm.org/PR1279  (part 2).

---
Diffs of the changes:  (+101 -0)

 2007-03-30-RegScavengerAssert.ll |  101 +++
 1 files changed, 101 insertions(+)


Index: llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll
diff -c /dev/null llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll:1.1
*** /dev/null   Fri Mar 30 15:15:33 2007
--- llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll  Fri Mar 30 
15:15:22 2007
***
*** 0 
--- 1,101 
+ ; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi
+ ; PR1279
+ 
+   %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
+   %struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 }
+   %struct.eh_status = type opaque
+   %struct.emit_status = type { i32, i32, %struct.rtx_def*, 
%struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, 
%struct.rtx_def** }
+   %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, 
%struct.rtx_def*, %struct.rtx_def* }
+   %struct.function = type { %struct.eh_status*, %struct.expr_status*, 
%struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, 
%struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, 
i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, 
%struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, 
%struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, 
%struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, 
%struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, 
%struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, 
%struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, 
%struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, 
%struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
+   %struct.initial_value_struct = type opaque
+   %struct.lang_decl = type opaque
+   %struct.language_function = type opaque
+   %struct.location_t = type { i8*, i32 }
+   %struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, 
%struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] }
+   %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+   %struct.rtx_def = type { i16, i8, i8, %struct.u }
+   %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, 
%struct.sequence_stack* }
+   %struct.temp_slot = type opaque
+   %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, 
%union.tree_ann_d*, i8, i8, i8, i8, i8 }
+   %struct.tree_decl = type { %struct.tree_common, %struct.location_t, 
i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, 
%struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, 
%struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, 
%struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, 
%struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, 
%struct.tree_node*, i64, %struct.lang_decl* }
+   %struct.tree_decl_u1 = type { i64 }
+   %struct.tree_decl_u2 = type { %struct.function* }
+   %struct.tree_node = type { %struct.tree_decl }
+   %struct.u = type { [1 x i64] }
+   %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, 
%struct.var_refs_queue* }
+   %struct.varasm_status = type opaque
+   %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.u }
+   %union.tree_ann_d = type opaque
+ @str469 = external global [42 x i8]   ; <[42 x i8]*> [#uses=0]
+ @__FUNCTION__.24265 = external global [19 x i8]   ; <[19 x i8]*> 
[#uses=0]
+ 
+ declare void @fancy_abort()
+ 
+ define fastcc void @fold_builtin_bitop() {
+ entry:
+   br i1 false, label %cond_true105, label %UnifiedReturnBlock
+ 
+ cond_true105: ; preds = %entry
+   br i1 false, label %cond_true134, label %UnifiedReturnBlock
+ 
+ cond_true134: ; preds = %cond_true105
+   switch i32 0, label %bb479 [
+i32 378, label %bb313
+i32 380, label %bb313
+i32 381, label %bb313
+i32 383, label %bb366
+i32 385, label %bb366
+i32 386, label %bb366
+i32 403, label %bb250
+i32 405, label %bb250
+i32 406, label %bb250
+i32 434, label %bb464
+i32 436, label %bb464
+i32 437, label %bb464
+i32 438, label %bb441
+i32 440, label %bb441
+i32 441, label %bb441
+   ]
+ 
+ bb250:; preds = %cond_true134, %cond_true134, %cond_true134
+   ret void
+ 
+ bb313:; preds = %cond_true134, %cond_true134, %cond_true134
+   ret void
+

[llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp

2007-03-30 Thread Evan Cheng



Changes in directory llvm/lib/CodeGen:

LiveIntervalAnalysis.cpp updated: 1.230 -> 1.231
---
Log message:

Bug fix for PR1279: http://llvm.org/PR1279 . When isDead is propagate by copy 
coalescing, we keep length
of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.

---
Diffs of the changes:  (+10 -5)

 LiveIntervalAnalysis.cpp |   15 ++-
 1 files changed, 10 insertions(+), 5 deletions(-)


Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.230 
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.231
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.230 Wed Mar 28 03:26:40 2007
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp   Fri Mar 30 15:18:35 2007
@@ -915,6 +915,7 @@
 
   // Check if it is necessary to propagate "isDead" property before intervals
   // are joined.
+  MachineBasicBlock *CopyBB = CopyMI->getParent();
   MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
   bool isDead = mopd->isDead();
   bool isShorten = false;
@@ -941,9 +942,15 @@
 isShorten = true;
 RemoveStart = getDefIndex(getInstructionIndex(LastUse));
 RemoveEnd   = SrcEnd;
-  } else if (RemoveStart > 0)
-// A dead def should have a single cycle interval.
-++RemoveStart;
+  } else {
+MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
+if (SrcMI) {
+  MachineOperand *mops = SrcMI->findRegisterDefOperand(SrcReg);
+  if (mops)
+// A dead def should have a single cycle interval.
+++RemoveStart;
+}
+  }
 }
   }
 
@@ -959,7 +966,6 @@
 
 LiveVariables::VarInfo& dvi = lv_->getVarInfo(repDstReg);
 // Is the value used in the current BB or any immediate successroe BB?
-MachineBasicBlock *CopyBB = CopyMI->getParent();
 if (dvi.UsedBlocks[CopyBB->getNumber()])
   goto TryJoin;
 for (MachineBasicBlock::succ_iterator SI = CopyBB->succ_begin(),
@@ -1018,7 +1024,6 @@
 if (SrcMI) {
   MachineOperand *mops = SrcMI->findRegisterDefOperand(SrcReg);
   if (mops)
-// FIXME: mops == NULL means SrcMI defines a subregister?
 mops->setIsDead();
 }
   }



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[llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp

2007-03-30 Thread Evan Cheng



Changes in directory llvm/lib/CodeGen:

VirtRegMap.cpp updated: 1.107 -> 1.108
---
Log message:

Don't add the same MI to register reuse "last def/use" twice if it reads the
register more than once.

---
Diffs of the changes:  (+4 -1)

 VirtRegMap.cpp |5 -
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.107 
llvm/lib/CodeGen/VirtRegMap.cpp:1.108
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.107   Mon Mar 26 19:48:28 2007
+++ llvm/lib/CodeGen/VirtRegMap.cpp Fri Mar 30 15:21:35 2007
@@ -316,7 +316,9 @@
   assert(II != SpillSlotsAvailable.end() && "Slot not available!");
   unsigned Val = II->second.first;
   assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
-  II->second.second.push_back(Use);
+  // This can be true if there are multiple uses of the same register.
+  if (II->second.second.back() != Use)
+II->second.second.push_back(Use);
 }
   }
   
@@ -1117,6 +1119,7 @@
   if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
 ++NumDCE;
 DOUT << "Removing now-noop copy: " << MI;
+Spills.removeLastUse(Src, &MI);
 MBB.erase(&MI);
 VRM.RemoveFromFoldedVirtMap(&MI);
 goto ProcessNextInst;



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[llvm-commits] CVS: llvm-test/MultiSource/Benchmarks/MiBench/consumer-lame/lame.c

2007-03-30 Thread Chris Lattner



Changes in directory llvm-test/MultiSource/Benchmarks/MiBench/consumer-lame:

lame.c updated: 1.2 -> 1.3
---
Log message:

fix compilation on darwin


---
Diffs of the changes:  (+2 -0)

 lame.c |2 ++
 1 files changed, 2 insertions(+)


Index: llvm-test/MultiSource/Benchmarks/MiBench/consumer-lame/lame.c
diff -u llvm-test/MultiSource/Benchmarks/MiBench/consumer-lame/lame.c:1.2 
llvm-test/MultiSource/Benchmarks/MiBench/consumer-lame/lame.c:1.3
--- llvm-test/MultiSource/Benchmarks/MiBench/consumer-lame/lame.c:1.2   Thu Mar 
29 11:53:54 2007
+++ llvm-test/MultiSource/Benchmarks/MiBench/consumer-lame/lame.c   Fri Mar 
30 15:31:43 2007
@@ -1199,6 +1199,7 @@
   /*
*  Disable floating point exepctions
*/
+#ifdef __FreeBSD__
   {
   /* seet floating point mask to the Linux default */
   fp_except_t mask;
@@ -1207,6 +1208,7 @@
   fpsetmask(mask & ~(FP_X_INV|FP_X_DZ));
   /*  fprintf(stderr,"FreeBSD mask is 0x%x\n",mask); */
   }
+#endif
 #if defined(__riscos__) && !defined(ABORTFP)
   /* Disable FPE's under RISC OS */
   /* if bit is set, we disable trapping that error! */



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[llvm-commits] CVS: llvm/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll

2007-03-30 Thread Chris Lattner



Changes in directory llvm/test/CodeGen/X86:

2007-03-15-GEP-Idx-Sink.ll added (r1.1)
---
Log message:

add a testcase for x86


---
Diffs of the changes:  (+73 -0)

 2007-03-15-GEP-Idx-Sink.ll |   73 +
 1 files changed, 73 insertions(+)


Index: llvm/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll
diff -c /dev/null llvm/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll:1.1
*** /dev/null   Fri Mar 30 16:22:56 2007
--- llvm/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.llFri Mar 30 16:22:46 2007
***
*** 0 
--- 1,73 
+ ; RUN: llvm-as < %s | llc &&
+ ; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-darwin | grep 'addl $20, 
%esp'
+ 
+ define void @foo(i8** %buf, i32 %size, i32 %col, i8* %p) {
+ entry:
+   icmp sgt i32 %size, 0   ; :0 [#uses=1]
+   br i1 %0, label %bb.preheader, label %return
+ 
+ bb.preheader: ; preds = %entry
+   %tmp5.sum72 = add i32 %col, 7   ;  [#uses=1]
+   %tmp5.sum71 = add i32 %col, 5   ;  [#uses=1]
+   %tmp5.sum70 = add i32 %col, 3   ;  [#uses=1]
+   %tmp5.sum69 = add i32 %col, 2   ;  [#uses=1]
+   %tmp5.sum68 = add i32 %col, 1   ;  [#uses=1]
+   %tmp5.sum66 = add i32 %col, 4   ;  [#uses=1]
+   %tmp5.sum = add i32 %col, 6 ;  [#uses=1]
+   br label %bb
+ 
+ bb:   ; preds = %bb, %bb.preheader
+   %i.073.0 = phi i32 [ 0, %bb.preheader ], [ %indvar.next, %bb ]  
;  [#uses=3]
+   %p_addr.076.0.rec = mul i32 %i.073.0, 9 ;  [#uses=9]
+   %p_addr.076.0 = getelementptr i8* %p, i32 %p_addr.076.0.rec 
;  [#uses=1]
+   %tmp2 = getelementptr i8** %buf, i32 %i.073.0   ;  
[#uses=1]
+   %tmp3 = load i8** %tmp2 ;  [#uses=8]
+   %tmp5 = getelementptr i8* %tmp3, i32 %col   ;  
[#uses=1]
+   %tmp7 = load i8* %p_addr.076.0  ;  [#uses=1]
+   store i8 %tmp7, i8* %tmp5
+   %p_addr.076.0.sum93 = add i32 %p_addr.076.0.rec, 1  ;  
[#uses=1]
+   %tmp11 = getelementptr i8* %p, i32 %p_addr.076.0.sum93  ;  
[#uses=1]
+   %tmp13 = load i8* %tmp11;  [#uses=1]
+   %tmp15 = getelementptr i8* %tmp3, i32 %tmp5.sum72   ;  
[#uses=1]
+   store i8 %tmp13, i8* %tmp15
+   %p_addr.076.0.sum92 = add i32 %p_addr.076.0.rec, 2  ;  
[#uses=1]
+   %tmp17 = getelementptr i8* %p, i32 %p_addr.076.0.sum92  ;  
[#uses=1]
+   %tmp19 = load i8* %tmp17;  [#uses=1]
+   %tmp21 = getelementptr i8* %tmp3, i32 %tmp5.sum71   ;  
[#uses=1]
+   store i8 %tmp19, i8* %tmp21
+   %p_addr.076.0.sum91 = add i32 %p_addr.076.0.rec, 3  ;  
[#uses=1]
+   %tmp23 = getelementptr i8* %p, i32 %p_addr.076.0.sum91  ;  
[#uses=1]
+   %tmp25 = load i8* %tmp23;  [#uses=1]
+   %tmp27 = getelementptr i8* %tmp3, i32 %tmp5.sum70   ;  
[#uses=1]
+   store i8 %tmp25, i8* %tmp27
+   %p_addr.076.0.sum90 = add i32 %p_addr.076.0.rec, 4  ;  
[#uses=1]
+   %tmp29 = getelementptr i8* %p, i32 %p_addr.076.0.sum90  ;  
[#uses=1]
+   %tmp31 = load i8* %tmp29;  [#uses=1]
+   %tmp33 = getelementptr i8* %tmp3, i32 %tmp5.sum69   ;  
[#uses=2]
+   store i8 %tmp31, i8* %tmp33
+   %p_addr.076.0.sum89 = add i32 %p_addr.076.0.rec, 5  ;  
[#uses=1]
+   %tmp35 = getelementptr i8* %p, i32 %p_addr.076.0.sum89  ;  
[#uses=1]
+   %tmp37 = load i8* %tmp35;  [#uses=1]
+   %tmp39 = getelementptr i8* %tmp3, i32 %tmp5.sum68   ;  
[#uses=1]
+   store i8 %tmp37, i8* %tmp39
+   %p_addr.076.0.sum88 = add i32 %p_addr.076.0.rec, 6  ;  
[#uses=1]
+   %tmp41 = getelementptr i8* %p, i32 %p_addr.076.0.sum88  ;  
[#uses=1]
+   %tmp43 = load i8* %tmp41;  [#uses=1]
+   store i8 %tmp43, i8* %tmp33
+   %p_addr.076.0.sum87 = add i32 %p_addr.076.0.rec, 7  ;  
[#uses=1]
+   %tmp47 = getelementptr i8* %p, i32 %p_addr.076.0.sum87  ;  
[#uses=1]
+   %tmp49 = load i8* %tmp47;  [#uses=1]
+   %tmp51 = getelementptr i8* %tmp3, i32 %tmp5.sum66   ;  
[#uses=1]
+   store i8 %tmp49, i8* %tmp51
+   %p_addr.076.0.sum = add i32 %p_addr.076.0.rec, 8;  
[#uses=1]
+   %tmp53 = getelementptr i8* %p, i32 %p_addr.076.0.sum;  
[#uses=1]
+   %tmp55 = load i8* %tmp53;  [#uses=1]
+   %tmp57 = getelementptr i8* %tmp3, i32 %tmp5.sum ;  
[#uses=1]
+   store i8 %tmp55, i8* %tmp57
+   %indvar.next = add i32 %i.073.0, 1  ;  [#uses=2]
+   icmp eq i32 %indvar.next, %size ; :1 [#uses=1]
+   br i1 %1, label %return, label %bb
+ 
+ return:   ; preds = %bb, %entry
+   ret void
+ }

[llvm-commits] Correctly handle sret attributes

2007-03-30 Thread Anton Korobeynikov

Hello, Everyone.

Attached patch will correctly set "sret" attribute for functions like:
'struct foo bar(void)'  or 'struct foo bar()'. Testcase is attached.

-- 
With best regards, Anton Korobeynikov.

Faculty of Mathematics & Mechanics, Saint Petersburg State University.

diff -r e1f510b2fded gcc/llvm-types.cpp
--- a/gcc/llvm-types.cpp	Wed Mar 28 09:02:02 2007 +
+++ b/gcc/llvm-types.cpp	Sat Mar 31 01:19:01 2007 +0400
@@ -708,9 +708,10 @@ ConvertArgListToFnType(tree ReturnType, 
 
   FunctionType::ParamAttrsList ParamAttrs;
 
+  // Something for the return type.
+  ParamAttrs.push_back(FunctionType::NoAttributeSet);
+
   if (static_chain) {
-// Something for the return type.
-ParamAttrs.push_back(FunctionType::NoAttributeSet);
 // Pass the static chain in a register.
 ParamAttrs.push_back(FunctionType::InRegAttribute);
   }
@@ -797,9 +798,14 @@ const FunctionType *TypeConverter::Conve
 // Pass the static chain in a register.
 ParamAttrs.push_back(FunctionType::InRegAttribute);
 
-  for (tree Args = TYPE_ARG_TYPES(type);
-   Args && TREE_VALUE(Args) != void_type_node;
-   Args = TREE_CHAIN(Args)) {
+  Args = TYPE_ARG_TYPES(type);
+  // Handle struct return for things like 'struct foo dummy = bar()'
+  if (!Args || (TREE_VALUE(Args) == void_type_node)) {
+if (ABIConverter.isStructReturn())
+  ParamAttrs.push_back(FunctionType::StructRetAttribute);
+  }
+  
+  for (; Args && TREE_VALUE(Args) != void_type_node; Args = TREE_CHAIN(Args)) {
 unsigned Attributes = FunctionType::NoAttributeSet;
 tree Ty = TREE_VALUE(Args);
 
@@ -820,7 +826,6 @@ const FunctionType *TypeConverter::Conve
 if (isFirstArg) {
   if (ABIConverter.isStructReturn()) {
 Attributes |= FunctionType::StructRetAttribute;
-//printf("Struct return!\n");
   }
   isFirstArg = false;
 }
// RUN: %llvmgcc %s -S -emit-llvm -O0 -o - | grep 'sret' | wc -l | grep '5'

struct abc {
 int a;
 int b;
 int c;
};
 
struct abc foo1(void);
struct abc foo2();

void bar() {
  struct abc dummy1 = foo1();
  struct abc dummy2 = foo2();
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp

2007-03-30 Thread Dale Johannesen



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.283 -> 1.284
SelectionDAG.cpp updated: 1.393 -> 1.394
---
Log message:

Fix incorrect combination of different loads.  Reenable zext-over-truncate
combination.



---
Diffs of the changes:  (+71 -75)

 DAGCombiner.cpp  |4 -
 SelectionDAG.cpp |  142 +++
 2 files changed, 71 insertions(+), 75 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.283 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.284
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.283 Thu Mar 29 02:56:46 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp   Fri Mar 30 16:38:07 2007
@@ -2110,9 +2110,7 @@
 
   // fold (zext (truncate (load x))) -> (zext (smaller load x))
   // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
-  // FIXME: Temporarily disable this for big endian machines until llvm-gcc
-  // build issue has been resolved.
-  if (TLI.isLittleEndian() && N0.getOpcode() == ISD::TRUNCATE) {
+  if (N0.getOpcode() == ISD::TRUNCATE) {
 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
 if (NarrowLoad.Val) {
   if (NarrowLoad.Val != N0.Val)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.393 
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.394
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.393Sun Mar  4 
14:40:38 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp  Fri Mar 30 16:38:07 2007
@@ -285,78 +285,76 @@
   AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands());
 
   // Handle SDNode leafs with special info.
-  if (N->getNumOperands() == 0) {
-switch (N->getOpcode()) {
-default: break;  // Normal nodes don't need extra info.
-case ISD::TargetConstant:
-case ISD::Constant:
-  ID.AddInteger(cast(N)->getValue());
-  break;
-case ISD::TargetConstantFP:
-case ISD::ConstantFP:
-  ID.AddDouble(cast(N)->getValue());
-  break;
-case ISD::TargetGlobalAddress:
-case ISD::GlobalAddress: {
-  GlobalAddressSDNode *GA = cast(N);
-  ID.AddPointer(GA->getGlobal());
-  ID.AddInteger(GA->getOffset());
-  break;
-}
-case ISD::BasicBlock:
-  ID.AddPointer(cast(N)->getBasicBlock());
-  break;
-case ISD::Register:
-  ID.AddInteger(cast(N)->getReg());
-  break;
-case ISD::SRCVALUE: {
-  SrcValueSDNode *SV = cast(N);
-  ID.AddPointer(SV->getValue());
-  ID.AddInteger(SV->getOffset());
-  break;
-}
-case ISD::FrameIndex:
-case ISD::TargetFrameIndex:
-  ID.AddInteger(cast(N)->getIndex());
-  break;
-case ISD::JumpTable:
-case ISD::TargetJumpTable:
-  ID.AddInteger(cast(N)->getIndex());
-  break;
-case ISD::ConstantPool:
-case ISD::TargetConstantPool: {
-  ConstantPoolSDNode *CP = cast(N);
-  ID.AddInteger(CP->getAlignment());
-  ID.AddInteger(CP->getOffset());
-  if (CP->isMachineConstantPoolEntry())
-CP->getMachineCPVal()->AddSelectionDAGCSEId(ID);
-  else
-ID.AddPointer(CP->getConstVal());
-  break;
-}
-case ISD::LOAD: {
-  LoadSDNode *LD = cast(N);
-  ID.AddInteger(LD->getAddressingMode());
-  ID.AddInteger(LD->getExtensionType());
-  ID.AddInteger(LD->getLoadedVT());
-  ID.AddPointer(LD->getSrcValue());
-  ID.AddInteger(LD->getSrcValueOffset());
-  ID.AddInteger(LD->getAlignment());
-  ID.AddInteger(LD->isVolatile());
-  break;
-}
-case ISD::STORE: {
-  StoreSDNode *ST = cast(N);
-  ID.AddInteger(ST->getAddressingMode());
-  ID.AddInteger(ST->isTruncatingStore());
-  ID.AddInteger(ST->getStoredVT());
-  ID.AddPointer(ST->getSrcValue());
-  ID.AddInteger(ST->getSrcValueOffset());
-  ID.AddInteger(ST->getAlignment());
-  ID.AddInteger(ST->isVolatile());
-  break;
-}
-}
+  switch (N->getOpcode()) {
+  default: break;  // Normal nodes don't need extra info.
+  case ISD::TargetConstant:
+  case ISD::Constant:
+ID.AddInteger(cast(N)->getValue());
+break;
+  case ISD::TargetConstantFP:
+  case ISD::ConstantFP:
+ID.AddDouble(cast(N)->getValue());
+break;
+  case ISD::TargetGlobalAddress:
+  case ISD::GlobalAddress: {
+GlobalAddressSDNode *GA = cast(N);
+ID.AddPointer(GA->getGlobal());
+ID.AddInteger(GA->getOffset());
+break;
+  }
+  case ISD::BasicBlock:
+ID.AddPointer(cast(N)->getBasicBlock());
+break;
+  case ISD::Register:
+ID.AddInteger(cast(N)->getReg());
+break;
+  case ISD::SRCVALUE: {
+SrcValueSDNode *SV = cast(N);
+ID.AddPointer(SV->getValue());
+ID.AddInteger(SV->getOffset());
+break;
+  }
+  case ISD::FrameIndex:
+  case ISD::TargetFrameIndex:
+ID.AddInteger(cast(N)->getIndex());
+break;
+  case ISD::JumpTable:
+  case ISD::TargetJumpTable:
+ID.AddInt

Re: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp RegAllocLinearScan.cpp VirtRegMap.cpp VirtRegMap.h

2007-03-30 Thread Chris Lattner

> First cut trivial re-materialization support.

Woot!

>  unsigned reg = rep(mop.getReg());
>  mii->getOperand(i).setReg(reg);
>
> +// If the definition instruction is re-materializable,  
> its spill
> +// weight is zero.
>  LiveInterval &RegInt = getInterval(reg);
> -RegInt.weight +=
> -  (mop.isUse() + mop.isDef()) * pow(10.0F, (int) 
> loopDepth);
> +if (!RegInt.remat) {
> +  RegInt.weight +=
> +(mop.isUse() + mop.isDef()) * pow(10.0F, (int) 
> loopDepth);
> +}

Should it really be zero?  It should definitely be lower that a  
normal value, but zero seems low.  The loop depth should still be  
taken into consideration.

> @@ -497,6 +515,9 @@
>  }
>
>} else {
> +// Can't safely assume definition is rematierializable anymore.

typo in comment.

> @@ -53,14 +60,20 @@
>  /// read/written by this instruction.
>  MI2VirtMapTy MI2VirtMap;
>
> +/// ReMatMap - This is irtual register to re-materialized  
> instruction
typo

> +/// mapping. Each virtual register whose definition is going  
> to be
> +/// re-materialized has an entry in it.
> +std::map ReMatMap;

> +/// ReMatId - Instead of assigning a stack slot to a to be  
> rematerialized
> +/// virtaul register, an unique id is being assinged. This  
> keeps track of
2 x typo

> +/// the highest id used so far. Note, this starts at (1<<18)  
> to avoid
> +/// conflicts with stack slot numbers.
> +int ReMatId;

-Chris


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Re: [llvm-commits] CVS: llvm/test/CodeGen/ARM/trunc_ldr.ll

2007-03-30 Thread Chris Lattner

>
> Index: llvm/test/CodeGen/ARM/trunc_ldr.ll
> diff -u llvm/test/CodeGen/ARM/trunc_ldr.ll:1.1 llvm/test/CodeGen/ 
> ARM/trunc_ldr.ll:1.2
> --- llvm/test/CodeGen/ARM/trunc_ldr.ll:1.1Wed Mar 21 15:14:56 2007
> +++ llvm/test/CodeGen/ARM/trunc_ldr.llWed Mar 21 20:55:16 2007
> @@ -1,27 +1,25 @@
>  ; RUN: llvm-as < %s | llc -march=arm &&
> -; RUN: llvm-as < %s | llc -march=arm | grep "ldrb.*7"
> +; RUN: llvm-as < %s | llc -march=arm | grep "ldrb.*7" | wc -l |  
> grep 1
> +; RUN: llvm-as < %s | llc -march=arm | grep "ldrsb.*7" | wc -l |  
> grep 1

This is missing an &&

-Chris

>
>   %struct.A = type { i8, i8, i8, i8, i16, i8, i8, %struct.B** }
>   %struct.B = type { float, float, i32, i32, i32, [0 x i8] }
>
> -implementation   ; Functions:
> -
> -define i32 @f1(%struct.A* %d) {
> -entry:
> +define i8 @f1(%struct.A* %d) {
>   %tmp2 = getelementptr %struct.A* %d, i32 0, i32 4
>   %tmp23 = bitcast i16* %tmp2 to i32*
>   %tmp4 = load i32* %tmp23
>   %tmp512 = lshr i32 %tmp4, 24
>   %tmp56 = trunc i32 %tmp512 to i8
> - icmp eq i8 %tmp56, 0
> - br i1 %0, label %UnifiedReturnBlock, label %conArue
> -
> -conArue:
> - %tmp8 = tail call i32 @f( %struct.A* %d )
> - ret i32 %tmp8
> -
> -UnifiedReturnBlock:
> - ret i32 0
> + ret i8 %tmp56
>  }
>
> -declare i32 @f(%struct.A*)
> +define i32 @f2(%struct.A* %d) {
> + %tmp2 = getelementptr %struct.A* %d, i32 0, i32 4
> + %tmp23 = bitcast i16* %tmp2 to i32*
> + %tmp4 = load i32* %tmp23
> + %tmp512 = lshr i32 %tmp4, 24
> + %tmp56 = trunc i32 %tmp512 to i8
> +%tmp57 = sext i8 %tmp56 to i32
> + ret i32 %tmp57
> +}
>
>
>
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[llvm-commits] CVS: llvm/docs/GettingStartedVS.html

2007-03-30 Thread Jeff Cohen



Changes in directory llvm/docs:

GettingStartedVS.html updated: 1.9 -> 1.10
---
Log message:

This is working again.

---
Diffs of the changes:  (+2 -3)

 GettingStartedVS.html |5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)


Index: llvm/docs/GettingStartedVS.html
diff -u llvm/docs/GettingStartedVS.html:1.9 llvm/docs/GettingStartedVS.html:1.10
--- llvm/docs/GettingStartedVS.html:1.9 Wed Mar 28 15:27:51 2007
+++ llvm/docs/GettingStartedVS.html Fri Mar 30 17:02:18 2007
@@ -293,8 +293,7 @@
 
   Note: this will only work for trivial C programs.  Non-trivial 
programs
 (and any C++ program) will have dependencies on the GCC runtime that
-won't be satisfied by the Microsoft runtime libraries.  Currently, it
-doesn't even work for trivial C programs such as the one above.
+won't be satisfied by the Microsoft runtime libraries.
 
   Execute the native code program:
 
@@ -352,7 +351,7 @@
 
   mailto:[EMAIL PROTECTED]">Jeff Cohen
   http://llvm.org";>The LLVM Compiler Infrastructure
-  Last modified: $Date: 2007/03/28 20:27:51 $
+  Last modified: $Date: 2007/03/30 22:02:18 $
 
 
 



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Re: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp RegAllocLinearScan.cpp VirtRegMap.cpp VirtRegMap.h

2007-03-30 Thread Evan Cheng


On Mar 30, 2007, at 2:44 PM, Chris Lattner wrote:

>> First cut trivial re-materialization support.
>
> Woot!
>
>>  unsigned reg = rep(mop.getReg());
>>  mii->getOperand(i).setReg(reg);
>>
>> +// If the definition instruction is re- 
>> materializable, its spill
>> +// weight is zero.
>>  LiveInterval &RegInt = getInterval(reg);
>> -RegInt.weight +=
>> -  (mop.isUse() + mop.isDef()) * pow(10.0F, (int) 
>> loopDepth);
>> +if (!RegInt.remat) {
>> +  RegInt.weight +=
>> +(mop.isUse() + mop.isDef()) * pow(10.0F, (int) 
>> loopDepth);
>> +}
>
> Should it really be zero?  It should definitely be lower that a  
> normal value, but zero seems low.  The loop depth should still be  
> taken into consideration.

Funny you should mention this. I am re-evaluating this right now. My  
thinking is loads (load from constantpool or stack slots) would have  
the normal weight. The rest will have half the weight.

Evan

>
>> @@ -497,6 +515,9 @@
>>  }
>>
>>} else {
>> +// Can't safely assume definition is rematierializable anymore.
>
> typo in comment.
>
>> @@ -53,14 +60,20 @@
>>  /// read/written by this instruction.
>>  MI2VirtMapTy MI2VirtMap;
>>
>> +/// ReMatMap - This is irtual register to re-materialized  
>> instruction
> typo
>
>> +/// mapping. Each virtual register whose definition is going  
>> to be
>> +/// re-materialized has an entry in it.
>> +std::map ReMatMap;
>
>> +/// ReMatId - Instead of assigning a stack slot to a to be  
>> rematerialized
>> +/// virtaul register, an unique id is being assinged. This  
>> keeps track of
> 2 x typo
>
>> +/// the highest id used so far. Note, this starts at (1<<18)  
>> to avoid
>> +/// conflicts with stack slot numbers.
>> +int ReMatId;
>
> -Chris
>
>

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[llvm-commits] CVS: llvm/test/CodeGen/ARM/trunc_ldr.ll

2007-03-30 Thread Evan Cheng



Changes in directory llvm/test/CodeGen/ARM:

trunc_ldr.ll updated: 1.2 -> 1.3
---
Log message:

Missing '&&'


---
Diffs of the changes:  (+1 -1)

 trunc_ldr.ll |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/test/CodeGen/ARM/trunc_ldr.ll
diff -u llvm/test/CodeGen/ARM/trunc_ldr.ll:1.2 
llvm/test/CodeGen/ARM/trunc_ldr.ll:1.3
--- llvm/test/CodeGen/ARM/trunc_ldr.ll:1.2  Wed Mar 21 20:55:16 2007
+++ llvm/test/CodeGen/ARM/trunc_ldr.ll  Fri Mar 30 17:03:49 2007
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=arm &&
-; RUN: llvm-as < %s | llc -march=arm | grep "ldrb.*7" | wc -l | grep 1
+; RUN: llvm-as < %s | llc -march=arm | grep "ldrb.*7" | wc -l | grep 1 &&
 ; RUN: llvm-as < %s | llc -march=arm | grep "ldrsb.*7" | wc -l | grep 1
 
%struct.A = type { i8, i8, i8, i8, i16, i8, i8, %struct.B** }



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Re: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp RegAllocLinearScan.cpp VirtRegMap.cpp VirtRegMap.h

2007-03-30 Thread Chris Lattner


On Mar 30, 2007, at 3:03 PM, Evan Cheng wrote:

>>>  unsigned reg = rep(mop.getReg());
>>>  mii->getOperand(i).setReg(reg);
>>>
>>> +// If the definition instruction is re- 
>>> materializable, its spill
>>> +// weight is zero.
>>>  LiveInterval &RegInt = getInterval(reg);
>>> -RegInt.weight +=
>>> -  (mop.isUse() + mop.isDef()) * pow(10.0F, (int) 
>>> loopDepth);
>>> +if (!RegInt.remat) {
>>> +  RegInt.weight +=
>>> +(mop.isUse() + mop.isDef()) * pow(10.0F, (int) 
>>> loopDepth);
>>> +}
>>
>> Should it really be zero?  It should definitely be lower that a  
>> normal value, but zero seems low.  The loop depth should still be  
>> taken into consideration.
>
> Funny you should mention this. I am re-evaluating this right now.  
> My thinking is loads (load from constantpool or stack slots) would  
> have the normal weight. The rest will have half the weight.

Why not just make everything half weight?  What would be lost?

-Chris
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp RegAllocLinearScan.cpp VirtRegMap.cpp VirtRegMap.h

2007-03-30 Thread Evan Cheng


On Mar 30, 2007, at 3:09 PM, Chris Lattner wrote:

>
> On Mar 30, 2007, at 3:03 PM, Evan Cheng wrote:
>
  unsigned reg = rep(mop.getReg());
  mii->getOperand(i).setReg(reg);

 +// If the definition instruction is re- 
 materializable, its spill
 +// weight is zero.
  LiveInterval &RegInt = getInterval(reg);
 -RegInt.weight +=
 -  (mop.isUse() + mop.isDef()) * pow(10.0F, (int) 
 loopDepth);
 +if (!RegInt.remat) {
 +  RegInt.weight +=
 +(mop.isUse() + mop.isDef()) * pow(10.0F, (int) 
 loopDepth);
 +}
>>>
>>> Should it really be zero?  It should definitely be lower that a  
>>> normal value, but zero seems low.  The loop depth should still be  
>>> taken into consideration.
>>
>> Funny you should mention this. I am re-evaluating this right now.  
>> My thinking is loads (load from constantpool or stack slots) would  
>> have the normal weight. The rest will have half the weight.
>
> Why not just make everything half weight?  What would be lost?

To avoid a common problem. A value live-in to a function and is  
loaded from stack slot and used in a loop. You do not want to  
rematerialize this and end up issuing the load in the loop.

This is tricky to get right. I am not sure simple heuristics can  
cover all the cases.

Evan

>
> -Chris

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Re: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp RegAllocLinearScan.cpp VirtRegMap.cpp VirtRegMap.h

2007-03-30 Thread Chris Lattner

> -  (mop.isUse() + mop.isDef()) * pow(10.0F, (int) 
> loopDepth);
> +if (!RegInt.remat) {
> +  RegInt.weight +=
> +(mop.isUse() + mop.isDef()) * pow(10.0F, (int) 
> loopDepth);
> +}

 Should it really be zero?  It should definitely be lower that a  
 normal value, but zero seems low.  The loop depth should still  
 be taken into consideration.
>>>
>>> Funny you should mention this. I am re-evaluating this right now.  
>>> My thinking is loads (load from constantpool or stack slots)  
>>> would have the normal weight. The rest will have half the weight.
>>
>> Why not just make everything half weight?  What would be lost?
>
> To avoid a common problem. A value live-in to a function and is  
> loaded from stack slot and used in a loop. You do not want to  
> rematerialize this and end up issuing the load in the loop.
>
> This is tricky to get right. I am not sure simple heuristics can  
> cover all the cases.

Okay, so just look to see if the instr has the  TargetInstrInfo::LOAD  
flag on it?

-Chris
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/CodeGen/SelectionDAG:

TargetLowering.cpp updated: 1.103 -> 1.104
---
Log message:

add one addressing mode description hook to rule them all.


---
Diffs of the changes:  (+34 -0)

 TargetLowering.cpp |   34 ++
 1 files changed, 34 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.103 
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.104
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.103  Tue Mar 27 
20:51:02 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppFri Mar 30 18:14:50 2007
@@ -1940,6 +1940,40 @@
 //  Loop Strength Reduction hooks
 
//===--===//
 
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 
+   const Type *Ty) const {
+  // The default implementation of this implements a conservative RISCy, r+r 
and
+  // r+i addr mode.
+
+  // Allows a sign-extended 16-bit immediate field.
+  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
+return false;
+  
+  // No global is ever allowed as a base.
+  if (AM.BaseGV)
+return false;
+  
+  // Only support r+r, 
+  switch (AM.Scale) {
+  case 0:  // "r+i" or just "i", depending on HasBaseReg.
+break;
+  case 1:
+if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
+  return false;
+// Otherwise we have r+r or r+i.
+break;
+  case 2:
+if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
+  return false;
+// Allow 2*r as r+r.
+break;
+  }
+  
+  return true;
+}
+
 /// isLegalAddressImmediate - Return true if the integer value can be used as
 /// the offset of the target addressing mode for load / store of the given
 /// type.



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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

2007-03-30 Thread Chris Lattner



Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.117 -> 1.118
---
Log message:

add one addressing mode description hook to rule them all.


---
Diffs of the changes:  (+21 -1)

 TargetLowering.h |   22 +-
 1 files changed, 21 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.117 
llvm/include/llvm/Target/TargetLowering.h:1.118
--- llvm/include/llvm/Target/TargetLowering.h:1.117 Tue Mar 27 20:51:02 2007
+++ llvm/include/llvm/Target/TargetLowering.h   Fri Mar 30 18:14:50 2007
@@ -853,9 +853,29 @@
  MachineBasicBlock *MBB);
 
   
//======//
-  // Loop Strength Reduction hooks
+  // Addressing mode description hooks (used by LSR etc).
   //
 
+  /// AddrMode - This represents an addressing mode of:
+  ///BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
+  /// If BaseGV is null,  there is no BaseGV.
+  /// If BaseOffs is zero, there is no base offset.
+  /// If HasBaseReg is false, there is no base register.
+  /// If Scale is zero, there is no ScaleReg.  Scale of 1 indicates a reg with
+  /// no scale.
+  ///
+  struct AddrMode {
+GlobalValue *BaseGV;
+int64_t  BaseOffs;
+bool HasBaseReg;
+int64_t  Scale;
+  };
+  
+  /// isLegalAddressingMode - Return true if the addressing mode represented by
+  /// AM is legal for this target, for a load/store of the specified type.
+  /// TODO: Handle pre/postinc as well.
+  virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
+  
   /// isLegalAddressImmediate - Return true if the integer value can be used as
   /// the offset of the target addressing mode for load / store of the given
   /// type.



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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/Target/ARM:

ARMISelLowering.cpp updated: 1.32 -> 1.33
ARMISelLowering.h updated: 1.9 -> 1.10
---
Log message:

implement the new addressing mode description hook.


---
Diffs of the changes:  (+42 -0)

 ARMISelLowering.cpp |   38 ++
 ARMISelLowering.h   |4 
 2 files changed, 42 insertions(+)


Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.32 
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.33
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.32Tue Mar 27 20:53:55 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Mar 30 18:15:24 2007
@@ -1281,6 +1281,44 @@
 //   ARM Optimization Hooks
 
//===--===//
 
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 
+  const Type *Ty) const {
+  if (!isLegalAddressImmediate(AM.BaseOffs, Ty))
+return false;
+  
+  // Can never fold addr of global into load/store.
+  if (AM.BaseGV) 
+return false;
+  
+  switch (AM.Scale) {
+  case 0:  // no scale reg, must be "r+i" or "r", or "i".
+break;
+  case 1:
+if (Subtarget->isThumb())
+  return false;
+
+  default:
+// FIXME: verify.
+switch (getValueType(Ty)) {
+default: return false;
+case MVT::i1:
+case MVT::i8:
+// TODO: i16?  i64 should be i32, no?
+case MVT::i32:
+  // r + r
+  if (AM.Scale == 2)
+return true;
+  // r + r << imm
+  if (!isPowerOf2_32(AM.Scale & ~1))
+return false;
+}
+break;
+  }
+  return true;
+}
+
 /// isLegalAddressImmediate - Return true if the integer value can be used
 /// as the offset of the target addressing mode for load / store of the
 /// given type.


Index: llvm/lib/Target/ARM/ARMISelLowering.h
diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.9 
llvm/lib/Target/ARM/ARMISelLowering.h:1.10
--- llvm/lib/Target/ARM/ARMISelLowering.h:1.9   Tue Mar 27 20:52:29 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.h   Fri Mar 30 18:15:24 2007
@@ -80,6 +80,10 @@
 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
 
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+virtual bool isLegalAddressingMode(const AddrMode &AM, const Type 
*Ty)const;
+
 /// isLegalAddressImmediate - Return true if the integer value can be used
 /// as the offset of the target addressing mode for load / store of the
 /// given type.



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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.264 -> 1.265
PPCISelLowering.h updated: 1.63 -> 1.64
---
Log message:

implement the new addressing mode description hook.


---
Diffs of the changes:  (+38 -1)

 PPCISelLowering.cpp |   35 ++-
 PPCISelLowering.h   |4 
 2 files changed, 38 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.264 
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.265
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.264   Tue Mar 27 11:33:08 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Mar 30 18:15:24 2007
@@ -3199,6 +3199,39 @@
   return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
 }
 
+// isLegalAddressingMode - Return true if the addressing mode represented
+// by AM is legal for this target, for a load/store of the specified type.
+bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 
+  const Type *Ty) const {
+  // FIXME: PPC does not allow r+i addressing modes for vectors!
+  
+  // PPC allows a sign-extended 16-bit immediate field.
+  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
+return false;
+  
+  // No global is ever allowed as a base.
+  if (AM.BaseGV)
+return false;
+  
+  // PPC only support r+r, 
+  switch (AM.Scale) {
+  case 0:  // "r+i" or just "i", depending on HasBaseReg.
+break;
+  case 1:
+if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
+  return false;
+// Otherwise we have r+r or r+i.
+break;
+  case 2:
+if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
+  return false;
+// Allow 2*r as r+r.
+break;
+  }
+  
+  return true;
+}
+
 /// isLegalAddressImmediate - Return true if the integer value can be used
 /// as the offset of the target addressing mode for load / store of the
 /// given type.
@@ -3208,7 +3241,7 @@
 }
 
 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
-  return TargetLowering::isLegalAddressImmediate(GV); 
+  return false; 
 }
 
 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.63 
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.64
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.63  Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h   Fri Mar 30 18:15:24 2007
@@ -236,6 +236,10 @@
 SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
   SelectionDAG &DAG);
 
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+virtual bool isLegalAddressingMode(const AddrMode &AM, const Type 
*Ty)const;
+
 /// isLegalAddressImmediate - Return true if the integer value can be used
 /// as the offset of the target addressing mode for load / store of the
 /// given type.



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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.382 -> 1.383
X86ISelLowering.h updated: 1.94 -> 1.95
---
Log message:

implement the new addressing mode description hook.


---
Diffs of the changes:  (+49 -0)

 X86ISelLowering.cpp |   45 +
 X86ISelLowering.h   |4 
 2 files changed, 49 insertions(+)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.382 
llvm/lib/Target/X86/X86ISelLowering.cpp:1.383
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.382   Tue Mar 27 20:02:54 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 30 18:15:24 2007
@@ -4047,6 +4047,51 @@
   }
 }
 
+// isLegalAddressingMode - Return true if the addressing mode represented
+// by AM is legal for this target, for a load/store of the specified type.
+bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 
+  const Type *Ty) const {
+  // X86 supports extremely general addressing modes.
+  
+  // X86 allows a sign-extended 32-bit immediate field as a displacement.
+  if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
+return false;
+  
+  if (AM.BaseGV) {
+// X86-64 only supports addr of globals in small code model.
+if (Subtarget->is64Bit() &&
+getTargetMachine().getCodeModel() != CodeModel::Small)
+  return false;
+
+// We can only fold this if we don't need a load either.
+if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
+  return false;
+  }
+  
+  switch (AM.Scale) {
+  case 0:
+  case 1:
+  case 2:
+  case 4:
+  case 8:
+// These scales always work.
+break;
+  case 3:
+  case 5:
+  case 9:
+// These scales are formed with basereg+scalereg.  Only accept if there is
+// no basereg yet.
+if (AM.HasBaseReg)
+  return false;
+break;
+  default:  // Other stuff never works.
+return false;
+  }
+  
+  return true;
+}
+
+
 /// isLegalAddressImmediate - Return true if the integer value can be used
 /// as the offset of the target addressing mode for load / store of the
 /// given type.


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.94 
llvm/lib/Target/X86/X86ISelLowering.h:1.95
--- llvm/lib/Target/X86/X86ISelLowering.h:1.94  Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h   Fri Mar 30 18:15:24 2007
@@ -335,6 +335,10 @@
   getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
 
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+virtual bool isLegalAddressingMode(const AddrMode &AM, const Type 
*Ty)const;
+
 /// isLegalAddressImmediate - Return true if the integer value can be used
 /// as the offset of the target addressing mode for load / store of the
 /// given type.



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[llvm-commits] Correct handling of "sret" attribute - 2

2007-03-30 Thread Anton Korobeynikov

Hello, Everyone.

Please ignore my prev. patch, it's definitely wrong.

You might find attached new patch + testcase.

-- 
With best regards, Anton Korobeynikov.

Faculty of Mathematics & Mechanics, Saint Petersburg State University.

diff -r 6942c57f1ff9 gcc/llvm-types.cpp
--- a/gcc/llvm-types.cpp	Fri Mar 30 09:02:21 2007 +
+++ b/gcc/llvm-types.cpp	Sat Mar 31 01:51:42 2007 +0400
@@ -708,9 +708,10 @@ ConvertArgListToFnType(tree ReturnType, 
 
   FunctionType::ParamAttrsList ParamAttrs;
 
+  // Something for the return type.
+  ParamAttrs.push_back(FunctionType::NoAttributeSet);
+
   if (static_chain) {
-// Something for the return type.
-ParamAttrs.push_back(FunctionType::NoAttributeSet);
 // Pass the static chain in a register.
 ParamAttrs.push_back(FunctionType::InRegAttribute);
   }
@@ -796,10 +797,13 @@ const FunctionType *TypeConverter::Conve
   if (static_chain)
 // Pass the static chain in a register.
 ParamAttrs.push_back(FunctionType::InRegAttribute);
-
+  
+  // Handle struct return
+  if (ABIConverter.isStructReturn())
+ParamAttrs.push_back(FunctionType::StructRetAttribute);
+  
   for (tree Args = TYPE_ARG_TYPES(type);
-   Args && TREE_VALUE(Args) != void_type_node;
-   Args = TREE_CHAIN(Args)) {
+   Args && TREE_VALUE(Args) != void_type_node; Args = TREE_CHAIN(Args)) {
 unsigned Attributes = FunctionType::NoAttributeSet;
 tree Ty = TREE_VALUE(Args);
 
@@ -814,15 +818,6 @@ const FunctionType *TypeConverter::Conve
 else
   Attributes |= FunctionType::SExtAttribute;
   }
-}
-
-// Handle struct return
-if (isFirstArg) {
-  if (ABIConverter.isStructReturn()) {
-Attributes |= FunctionType::StructRetAttribute;
-//printf("Struct return!\n");
-  }
-  isFirstArg = false;
 }
 
 #ifdef LLVM_TARGET_ENABLE_REGPARM
// RUN: %llvmgcc %s -S -emit-llvm -O0 -o - | grep 'sret' | wc -l | grep '5'

struct abc {
 int a;
 int b;
 int c;
};
 
struct abc foo1(void);
struct abc foo2();

void bar() {
  struct abc dummy1 = foo1();
  struct abc dummy2 = foo2();
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[llvm-commits] CVS: llvm/lib/CodeGen/LLVMTargetMachine.cpp

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/CodeGen:

LLVMTargetMachine.cpp updated: 1.10 -> 1.11
---
Log message:

Add a -print-lsr-output option to LLC, to print the output of the LSR pass.


---
Diffs of the changes:  (+9 -1)

 LLVMTargetMachine.cpp |   10 +-
 1 files changed, 9 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/LLVMTargetMachine.cpp
diff -u llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.10 
llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.11
--- llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.10 Tue Mar  6 15:14:09 2007
+++ llvm/lib/CodeGen/LLVMTargetMachine.cpp  Fri Mar 30 19:24:43 2007
@@ -14,12 +14,16 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/PassManager.h"
 #include "llvm/Pass.h"
+#include "llvm/Assembly/PrintModulePass.h"
 #include "llvm/Analysis/LoopPass.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Transforms/Scalar.h"
+#include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
+static cl::opt PrintLSR("print-lsr-output");
+
 FileModel::Model
 LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
std::ostream &Out,
@@ -28,7 +32,11 @@
   // Standard LLVM-Level Passes.
   
   // Run loop strength reduction before anything else.
-  if (!Fast) PM.add(createLoopStrengthReducePass(getTargetLowering()));
+  if (!Fast) {
+PM.add(createLoopStrengthReducePass(getTargetLowering()));
+if (PrintLSR)
+  PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
+  }
   
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());



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[llvm-commits] CVS: llvm/lib/Target/X86/X86CallingConv.td

2007-03-30 Thread Bill Wendling



Changes in directory llvm/lib/Target/X86:

X86CallingConv.td updated: 1.11 -> 1.12
---
Log message:

Match GCC's MMX calling convention.


---
Diffs of the changes:  (+4 -0)

 X86CallingConv.td |4 
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/X86/X86CallingConv.td
diff -u llvm/lib/Target/X86/X86CallingConv.td:1.11 
llvm/lib/Target/X86/X86CallingConv.td:1.12
--- llvm/lib/Target/X86/X86CallingConv.td:1.11  Thu Mar 29 19:35:22 2007
+++ llvm/lib/Target/X86/X86CallingConv.td   Fri Mar 30 20:03:53 2007
@@ -101,6 +101,10 @@
   CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
   CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
 
+  // The first 8 MMX vector arguments are passed in MMX registers.
+  CCIfType<[v8i8, v4i16, v2i32, v1i64],
+  CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
+
   // Integer/FP values get stored in stack slots that are 8 bytes in size and
   // 8-byte aligned if there are no more registers to hold them.
   CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,



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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

2007-03-30 Thread Zhou Sheng



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.712 -> 1.713
---
Log message:

Use APInt operators to calculate the carry bits, remove this loop.


---
Diffs of the changes:  (+2 -16)

 InstructionCombining.cpp |   18 ++
 1 files changed, 2 insertions(+), 16 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.712 
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.713
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.712   Fri Mar 30 
12:20:39 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri Mar 30 21:38:39 2007
@@ -1243,22 +1243,8 @@
   // To compute this, we first compute the potential carry bits.  These are
   // the bits which may be modified.  I'm not aware of a better way to do
   // this scan.
-  APInt RHSVal(RHS->getValue());
-  
-  bool CarryIn = false;
-  APInt CarryBits(BitWidth, 0);
-  const uint64_t *LHSKnownZeroRawVal = LHSKnownZero.getRawData(),
- *RHSRawVal = RHSVal.getRawData();
-  for (uint32_t i = 0; i != RHSVal.getNumWords(); ++i) {
-uint64_t AddVal = ~LHSKnownZeroRawVal[i] + RHSRawVal[i],
- XorVal = ~LHSKnownZeroRawVal[i] ^ RHSRawVal[i];
-uint64_t WordCarryBits = AddVal ^ XorVal + CarryIn;
-if (AddVal < RHSRawVal[i])
-  CarryIn = true;
-else
-  CarryIn = false;
-CarryBits.setWordToValue(i, WordCarryBits);
-  }
+  const APInt& RHSVal = RHS->getValue();
+  APInt CarryBits((~LHSKnownZero + RHSVal) ^ (~LHSKnownZero ^ RHSVal));
   
   // Now that we know which bits have carries, compute the known-1/0 sets.
   



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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

2007-03-30 Thread Zhou Sheng



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.713 -> 1.714
---
Log message:

Delete dead code.


---
Diffs of the changes:  (+0 -1)

 InstructionCombining.cpp |1 -
 1 files changed, 1 deletion(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.713 
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.714
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.713   Fri Mar 30 
21:38:39 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri Mar 30 21:50:26 2007
@@ -4777,7 +4777,6 @@
   // of the bits shifted in could be tested after the mask.
   uint32_t TyBits = Ty->getPrimitiveSizeInBits();
   int ShAmtVal = TyBits - ShAmt->getLimitedValue(TyBits);
-  if (ShAmtVal < 0) ShAmtVal = 0; // Out of range shift.
 
   uint32_t BitWidth = AndTy->getPrimitiveSizeInBits();
   if ((APInt::getHighBitsSet(BitWidth, BitWidth-ShAmtVal) & 



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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86CallingConv.td

2007-03-30 Thread Chris Lattner


On Mar 30, 2007, at 6:04 PM, Bill Wendling wrote:

>
> +  // The first 8 MMX vector arguments are passed in MMX registers.
> +  CCIfType<[v8i8, v4i16, v2i32, v1i64],
> +  CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
> +

Please update the comment to match the code.

-Chris
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Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

2007-03-30 Thread Chris Lattner

> Use APInt operators to calculate the carry bits, remove this loop.

Nice :)

-Chris

>
>
> ---
> Diffs of the changes:  (+2 -16)
>
>  InstructionCombining.cpp |   18 ++
>  1 files changed, 2 insertions(+), 16 deletions(-)
>
>
> Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
> diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.712  
> llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.713
> --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.712 Fri  
> Mar 30 12:20:39 2007
> +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp   Fri Mar 30  
> 21:38:39 2007
> @@ -1243,22 +1243,8 @@
>// To compute this, we first compute the potential carry  
> bits.  These are
>// the bits which may be modified.  I'm not aware of a  
> better way to do
>// this scan.
> -  APInt RHSVal(RHS->getValue());
> -
> -  bool CarryIn = false;
> -  APInt CarryBits(BitWidth, 0);
> -  const uint64_t *LHSKnownZeroRawVal = LHSKnownZero.getRawData(),
> - *RHSRawVal = RHSVal.getRawData();
> -  for (uint32_t i = 0; i != RHSVal.getNumWords(); ++i) {
> -uint64_t AddVal = ~LHSKnownZeroRawVal[i] + RHSRawVal[i],
> - XorVal = ~LHSKnownZeroRawVal[i] ^ RHSRawVal[i];
> -uint64_t WordCarryBits = AddVal ^ XorVal + CarryIn;
> -if (AddVal < RHSRawVal[i])
> -  CarryIn = true;
> -else
> -  CarryIn = false;
> -CarryBits.setWordToValue(i, WordCarryBits);
> -  }
> +  const APInt& RHSVal = RHS->getValue();
> +  APInt CarryBits((~LHSKnownZero + RHSVal) ^ (~LHSKnownZero ^  
> RHSVal));
>
>// Now that we know which bits have carries, compute the  
> known-1/0 sets.
>
>
>
>
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[llvm-commits] CVS: llvm/lib/VMCore/ValueTypes.cpp

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/VMCore:

ValueTypes.cpp updated: 1.15 -> 1.16
---
Log message:

add a method to turn a type into a VT.


---
Diffs of the changes:  (+28 -0)

 ValueTypes.cpp |   28 
 1 files changed, 28 insertions(+)


Index: llvm/lib/VMCore/ValueTypes.cpp
diff -u llvm/lib/VMCore/ValueTypes.cpp:1.15 llvm/lib/VMCore/ValueTypes.cpp:1.16
--- llvm/lib/VMCore/ValueTypes.cpp:1.15 Sat Mar 24 12:36:26 2007
+++ llvm/lib/VMCore/ValueTypes.cpp  Fri Mar 30 23:03:02 2007
@@ -110,3 +110,31 @@
   case MVT::v2f64: return VectorType::get(Type::DoubleTy, 2);
   }
 }
+
+/// MVT::getValueType - Return the value type corresponding to the specified
+/// type.  This returns all vectors as MVT::Vector and all pointers as
+/// MVT::iPTR.
+MVT::ValueType MVT::getValueType(const Type *Ty) {
+  switch (Ty->getTypeID()) {
+  default: assert(0 && "Unknown type!");
+  case Type::VoidTyID:
+return MVT::isVoid;
+  case Type::IntegerTyID:
+switch (cast(Ty)->getBitWidth()) {
+default:
+  // FIXME: Return MVT::iANY.
+  assert(0 && "Invalid width for value type");
+case 1:return MVT::i1;
+case 8:return MVT::i8;
+case 16:   return MVT::i16;
+case 32:   return MVT::i32;
+case 64:   return MVT::i64;
+case 128:  return MVT::i128;
+}
+break;
+  case Type::FloatTyID:   return MVT::f32;
+  case Type::DoubleTyID:  return MVT::f64;
+  case Type::PointerTyID: return MVT::iPTR;
+  case Type::VectorTyID:  return MVT::Vector;
+  }
+}



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[llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h

2007-03-30 Thread Chris Lattner



Changes in directory llvm/include/llvm/CodeGen:

ValueTypes.h updated: 1.30 -> 1.31
---
Log message:

add a method to turn a type into a VT.


---
Diffs of the changes:  (+5 -0)

 ValueTypes.h |5 +
 1 files changed, 5 insertions(+)


Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.30 
llvm/include/llvm/CodeGen/ValueTypes.h:1.31
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.30 Sat Mar 24 12:36:26 2007
+++ llvm/include/llvm/CodeGen/ValueTypes.h  Fri Mar 30 23:03:02 2007
@@ -197,6 +197,11 @@
   /// to the specified ValueType.  For integer types, this returns an unsigned
   /// type.  Note that this will abort for types that cannot be represented.
   const Type *getTypeForValueType(ValueType VT);
+  
+  /// MVT::getValueType - Return the value type corresponding to the specified
+  /// type.  This returns all vectors as MVT::Vector and all pointers as
+  /// MVT::iPTR.
+  ValueType getValueType(const Type *Ty);
 }
 
 } // End llvm namespace



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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/CodeGen/SelectionDAG:

TargetLowering.cpp updated: 1.104 -> 1.105
---
Log message:

switch TL::getValueType to use MVT::getValueType.


---
Diffs of the changes:  (+0 -22)

 TargetLowering.cpp |   22 --
 1 files changed, 22 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.104 
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.105
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.104  Fri Mar 30 
18:14:50 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppFri Mar 30 23:05:24 2007
@@ -2273,25 +2273,3 @@
DAG.getConstant(magics.s-1, getShiftAmountTy()));
   }
 }
-
-MVT::ValueType TargetLowering::getValueType(const Type *Ty) const {
-  switch (Ty->getTypeID()) {
-  default: assert(0 && "Unknown type!");
-  case Type::VoidTyID:return MVT::isVoid;
-  case Type::IntegerTyID:
-switch (cast(Ty)->getBitWidth()) {
-  default: assert(0 && "Invalid width for value type");
-  case 1:return MVT::i1;
-  case 8:return MVT::i8;
-  case 16:   return MVT::i16;
-  case 32:   return MVT::i32;
-  case 64:   return MVT::i64;
-  case 128:  return MVT::i128;
-}
-break;
-  case Type::FloatTyID:   return MVT::f32;
-  case Type::DoubleTyID:  return MVT::f64;
-  case Type::PointerTyID: return PointerTy;
-  case Type::VectorTyID:  return MVT::Vector;
-  }
-}



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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

2007-03-30 Thread Chris Lattner



Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.118 -> 1.119
---
Log message:

switch TL::getValueType to use MVT::getValueType.


---
Diffs of the changes:  (+4 -1)

 TargetLowering.h |5 -
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.118 
llvm/include/llvm/Target/TargetLowering.h:1.119
--- llvm/include/llvm/Target/TargetLowering.h:1.118 Fri Mar 30 18:14:50 2007
+++ llvm/include/llvm/Target/TargetLowering.h   Fri Mar 30 23:05:24 2007
@@ -340,7 +340,10 @@
 
   /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
   /// This is fixed by the LLVM operations except for the pointer size.
-  MVT::ValueType getValueType(const Type *Ty) const;
+  MVT::ValueType getValueType(const Type *Ty) const {
+MVT::ValueType VT = MVT::getValueType(Ty);
+return VT == MVT::iPTR ? PointerTy : VT;
+  }
 
   /// getNumElements - Return the number of registers that this ValueType will
   /// eventually require.  This is one for any types promoted to live in larger



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[llvm-commits] CVS: llvm/include/llvm/Transforms/Scalar.h

2007-03-30 Thread Chris Lattner



Changes in directory llvm/include/llvm/Transforms:

Scalar.h updated: 1.77 -> 1.78
---
Log message:

Split the sdisel code munging stuff out into its own opt-pass, CodeGenPrepare.


---
Diffs of the changes:  (+7 -1)

 Scalar.h |8 +++-
 1 files changed, 7 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Transforms/Scalar.h
diff -u llvm/include/llvm/Transforms/Scalar.h:1.77 
llvm/include/llvm/Transforms/Scalar.h:1.78
--- llvm/include/llvm/Transforms/Scalar.h:1.77  Wed Mar  7 00:39:01 2007
+++ llvm/include/llvm/Transforms/Scalar.h   Fri Mar 30 23:06:36 2007
@@ -121,7 +121,7 @@
 // optional parameter used to consult the target machine whether certain
 // transformations are profitable.
 //
-LoopPass *createLoopStrengthReducePass(const TargetLowering *TLI = NULL);
+LoopPass *createLoopStrengthReducePass(const TargetLowering *TLI = 0);
 
 
//===--===//
 //
@@ -309,6 +309,12 @@
 //
 FunctionPass *createPredicateSimplifierPass();
 
+//===--===//
+//
+// CodeGenPrepare - This pass prepares a function for instruction selection.
+//
+FunctionPass *createCodeGenPreparePass(const TargetLowering *TLI = 0);
+
 } // End llvm namespace
 
 #endif



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[llvm-commits] CVS: llvm/include/llvm/LinkAllPasses.h

2007-03-30 Thread Chris Lattner



Changes in directory llvm/include/llvm:

LinkAllPasses.h updated: 1.10 -> 1.11
---
Log message:

Split the sdisel code munging stuff out into its own opt-pass, CodeGenPrepare.


---
Diffs of the changes:  (+1 -0)

 LinkAllPasses.h |1 +
 1 files changed, 1 insertion(+)


Index: llvm/include/llvm/LinkAllPasses.h
diff -u llvm/include/llvm/LinkAllPasses.h:1.10 
llvm/include/llvm/LinkAllPasses.h:1.11
--- llvm/include/llvm/LinkAllPasses.h:1.10  Mon Feb 19 23:31:04 2007
+++ llvm/include/llvm/LinkAllPasses.h   Fri Mar 30 23:06:36 2007
@@ -109,6 +109,7 @@
   (void) llvm::createIndMemRemPass();
   (void) llvm::createInstCountPass();
   (void) llvm::createPredicateSimplifierPass();
+  (void) llvm::createCodeGenPreparePass();
 
   (void)new llvm::IntervalPartition();
   (void)new llvm::ImmediateDominators();



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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/CodeGenPrepare.cpp

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/Transforms/Scalar:

CodeGenPrepare.cpp added (r1.1)
---
Log message:

Split the sdisel code munging stuff out into its own opt-pass, CodeGenPrepare.


---
Diffs of the changes:  (+548 -0)

 CodeGenPrepare.cpp |  548 +
 1 files changed, 548 insertions(+)


Index: llvm/lib/Transforms/Scalar/CodeGenPrepare.cpp
diff -c /dev/null llvm/lib/Transforms/Scalar/CodeGenPrepare.cpp:1.1
*** /dev/null   Fri Mar 30 23:06:46 2007
--- llvm/lib/Transforms/Scalar/CodeGenPrepare.cpp   Fri Mar 30 23:06:36 2007
***
*** 0 
--- 1,548 
+ //===- CodeGenPrepare.cpp - Prepare a function for code generation 
===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for 
details.
+ //
+ 
//===--===//
+ //
+ // This pass munges the code in the input function to better prepare it for
+ // SelectionDAG-based code generation.  This works around limitations in it's
+ // basic-block-at-a-time approach.  It should eventually be removed.
+ //
+ 
//===--===//
+ 
+ #define DEBUG_TYPE "codegenprepare"
+ #include "llvm/Transforms/Scalar.h"
+ #include "llvm/Constants.h"
+ #include "llvm/DerivedTypes.h"
+ #include "llvm/Function.h"
+ #include "llvm/Instructions.h"
+ #include "llvm/Pass.h"
+ #include "llvm/Support/Compiler.h"
+ #include "llvm/Target/TargetAsmInfo.h"
+ #include "llvm/Target/TargetData.h"
+ #include "llvm/Target/TargetLowering.h"
+ #include "llvm/Target/TargetMachine.h"
+ #include "llvm/Transforms/Utils/BasicBlockUtils.h"
+ #include "llvm/ADT/SmallSet.h"
+ using namespace llvm;
+ 
+ namespace {  
+   class VISIBILITY_HIDDEN CodeGenPrepare : public FunctionPass {
+ /// TLI - Keep a pointer of a TargetLowering to consult for determining
+ /// transformation profitability.
+ const TargetLowering *TLI;
+   public:
+ CodeGenPrepare(const TargetLowering *tli = 0) : TLI(tli) {}
+ bool runOnFunction(Function &F);
+ 
+   private:
+ bool OptimizeBlock(BasicBlock &BB);
+ bool OptimizeGEPExpression(GetElementPtrInst *GEPI);
+   };
+ }
+ static RegisterPass X("codegenprepare",
+   "Optimize for code generation");
+ 
+ FunctionPass *llvm::createCodeGenPreparePass(const TargetLowering *TLI) {
+   return new CodeGenPrepare(TLI);
+ }
+ 
+ 
+ bool CodeGenPrepare::runOnFunction(Function &F) {
+   bool MadeChange = true;
+   bool EverMadeChange = false;
+   while (MadeChange) {
+ MadeChange = false;
+ for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
+   MadeChange |= OptimizeBlock(*BB);
+ EverMadeChange |= MadeChange;
+   }
+   return EverMadeChange;
+ }
+ 
+ /// SplitEdgeNicely - Split the critical edge from TI to it's specified
+ /// successor if it will improve codegen.  We only do this if the successor 
has
+ /// phi nodes (otherwise critical edges are ok).  If there is already another
+ /// predecessor of the succ that is empty (and thus has no phi nodes), use it
+ /// instead of introducing a new block.
+ static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum, Pass *P) {
+   BasicBlock *TIBB = TI->getParent();
+   BasicBlock *Dest = TI->getSuccessor(SuccNum);
+   assert(isa(Dest->begin()) &&
+  "This should only be called if Dest has a PHI!");
+   
+   /// TIPHIValues - This array is lazily computed to determine the values of
+   /// PHIs in Dest that TI would provide.
+   std::vector TIPHIValues;
+   
+   // Check to see if Dest has any blocks that can be used as a split edge for
+   // this terminator.
+   for (pred_iterator PI = pred_begin(Dest), E = pred_end(Dest); PI != E; 
++PI) {
+ BasicBlock *Pred = *PI;
+ // To be usable, the pred has to end with an uncond branch to the dest.
+ BranchInst *PredBr = dyn_cast(Pred->getTerminator());
+ if (!PredBr || !PredBr->isUnconditional() ||
+ // Must be empty other than the branch.
+ &Pred->front() != PredBr)
+   continue;
+ 
+ // Finally, since we know that Dest has phi nodes in it, we have to make
+ // sure that jumping to Pred will have the same affect as going to Dest in
+ // terms of PHI values.
+ PHINode *PN;
+ unsigned PHINo = 0;
+ bool FoundMatch = true;
+ for (BasicBlock::iterator I = Dest->begin();
+  (PN = dyn_cast(I)); ++I, ++PHINo) {
+   if (PHINo == TIPHIValues.size())
+ TIPHIValues.push_back(PN->getIncomingValueForBlock(TIBB));
+   
+   // If the PHI entry doesn't work, we can't use this pred.
+   if (TIPHIValues[PHINo] != PN->getIncomingValueForBlock(Pred)) {
+ FoundMatch = false;
+ break;
+   }
+ }
+ 
+ // If we found a workable predecesso

[llvm-commits] CVS: llvm/lib/CodeGen/LLVMTargetMachine.cpp

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/CodeGen:

LLVMTargetMachine.cpp updated: 1.11 -> 1.12
---
Log message:

move a bunch of code out of the sdisel pass into its own opt pass 
"codegenprepare".


---
Diffs of the changes:  (+20 -2)

 LLVMTargetMachine.cpp |   22 --
 1 files changed, 20 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/LLVMTargetMachine.cpp
diff -u llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.11 
llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.12
--- llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.11 Fri Mar 30 19:24:43 2007
+++ llvm/lib/CodeGen/LLVMTargetMachine.cpp  Fri Mar 30 23:18:03 2007
@@ -23,7 +23,7 @@
 using namespace llvm;
 
 static cl::opt PrintLSR("print-lsr-output");
-
+static cl::opt PrintISelInput("print-isel-input");
 FileModel::Model
 LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
std::ostream &Out,
@@ -48,6 +48,13 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
+  if (!Fast)
+PM.add(createCodeGenPreparePass(getTargetLowering()));
+
+  if (PrintISelInput)
+PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** 
\n",
+ &cerr));
+  
   // Ask the target for an isel.
   if (addInstSelector(PM, Fast))
 return FileModel::Error;
@@ -126,7 +133,11 @@
   // Standard LLVM-Level Passes.
   
   // Run loop strength reduction before anything else.
-  if (!Fast) PM.add(createLoopStrengthReducePass(getTargetLowering()));
+  if (!Fast) {
+PM.add(createLoopStrengthReducePass(getTargetLowering()));
+if (PrintLSR)
+  PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
+  }
   
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
@@ -137,6 +148,13 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
+  if (!Fast)
+PM.add(createCodeGenPreparePass(getTargetLowering()));
+
+  if (PrintISelInput)
+PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** 
\n",
+ &cerr));
+
   // Ask the target for an isel.
   if (addInstSelector(PM, Fast))
 return true;



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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.399 -> 1.400
---
Log message:

move a bunch of code out of the sdisel pass into its own opt pass 
"codegenprepare".


---
Diffs of the changes:  (+1 -483)

 SelectionDAGISel.cpp |  484 ---
 1 files changed, 1 insertion(+), 483 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.399 
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.400
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.399Tue Mar 27 
20:55:52 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp  Fri Mar 30 23:18:03 2007
@@ -16,7 +16,6 @@
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CallingConv.h"
-#include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/Function.h"
 #include "llvm/GlobalVariable.h"
@@ -33,14 +32,12 @@
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/MRegisterInfo.h"
-#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
-#include "llvm/Transforms/Utils/BasicBlockUtils.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Compiler.h"
@@ -3830,496 +3827,17 @@
 }
 
 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
-  // FIXME: we only modify the CFG to split critical edges.  This
-  // updates dom and loop info.
   AU.addRequired();
+  AU.setPreservesAll();
 }
 
 
-/// OptimizeNoopCopyExpression - We have determined that the specified cast
-/// instruction is a noop copy (e.g. it's casting from one pointer type to
-/// another, int->uint, or int->sbyte on PPC.
-///
-/// Return true if any changes are made.
-static bool OptimizeNoopCopyExpression(CastInst *CI) {
-  BasicBlock *DefBB = CI->getParent();
-  
-  /// InsertedCasts - Only insert a cast in each block once.
-  std::map InsertedCasts;
-  
-  bool MadeChange = false;
-  for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end(); 
-   UI != E; ) {
-Use &TheUse = UI.getUse();
-Instruction *User = cast(*UI);
-
-// Figure out which BB this cast is used in.  For PHI's this is the
-// appropriate predecessor block.
-BasicBlock *UserBB = User->getParent();
-if (PHINode *PN = dyn_cast(User)) {
-  unsigned OpVal = UI.getOperandNo()/2;
-  UserBB = PN->getIncomingBlock(OpVal);
-}
-
-// Preincrement use iterator so we don't invalidate it.
-++UI;
-
-// If this user is in the same block as the cast, don't change the cast.
-if (UserBB == DefBB) continue;
-
-// If we have already inserted a cast into this block, use it.
-CastInst *&InsertedCast = InsertedCasts[UserBB];
-
-if (!InsertedCast) {
-  BasicBlock::iterator InsertPt = UserBB->begin();
-  while (isa(InsertPt)) ++InsertPt;
-  
-  InsertedCast = 
-CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(), 
"", 
- InsertPt);
-  MadeChange = true;
-}
-
-// Replace a use of the cast with a use of the new casat.
-TheUse = InsertedCast;
-  }
-  
-  // If we removed all uses, nuke the cast.
-  if (CI->use_empty())
-CI->eraseFromParent();
-  
-  return MadeChange;
-}
-
-/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
-/// casting to the type of GEPI.
-static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
- Instruction *GEPI, Value *Ptr,
- Value *PtrOffset) {
-  if (V) return V;   // Already computed.
-  
-  // Figure out the insertion point
-  BasicBlock::iterator InsertPt;
-  if (BB == GEPI->getParent()) {
-// If GEP is already inserted into BB, insert right after the GEP.
-InsertPt = GEPI;
-++InsertPt;
-  } else {
-// Otherwise, insert at the top of BB, after any PHI nodes
-InsertPt = BB->begin();
-while (isa(InsertPt)) ++InsertPt;
-  }
-  
-  // If Ptr is itself a cast, but in some other BB, emit a copy of the cast 
into
-  // BB so that there is only one value live across basic blocks (the cast 
-  // operand).
-  if (CastInst *CI = dyn_cast(Ptr))
-if (CI->getParent() != BB && 
isa(CI->getOperand(0)->getType()))
-  Ptr = CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(),
- "", InsertPt);
-  
-  // Add the offset, cast it to the right type.
-  Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
-  // Ptr is an integer type, GEPI is pointer type ==> IntToPtr
-  return V = CastInst::create(Instruction::IntToPtr, Ptr, GEPI

[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt

2007-03-30 Thread Chris Lattner



Changes in directory llvm/lib/Target/PowerPC:

README.txt updated: 1.113 -> 1.114
---
Log message:

add a note


---
Diffs of the changes:  (+23 -0)

 README.txt |   23 +++
 1 files changed, 23 insertions(+)


Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.113 
llvm/lib/Target/PowerPC/README.txt:1.114
--- llvm/lib/Target/PowerPC/README.txt:1.113Sun Mar 25 00:10:46 2007
+++ llvm/lib/Target/PowerPC/README.txt  Sat Mar 31 02:06:25 2007
@@ -639,3 +639,26 @@
 The dead or is a 'truncate' from 64- to 32-bits.
 
 ===-===
+
+We generate horrible ppc code for this:
+
+#define N  200
+double   a[N],c[N];
+void simpleloop() {
+   int j;
+   for (j=0; jhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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