[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/addSubConstant.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
addSubConstant.ll added (r1.1)
---
Log message:
Avoid creating invalid sub/add instructions on the prolog/epilog
patch by Lauro
---
Diffs of the changes: (+19 -0)
addSubConstant.ll | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/addSubConstant.ll
diff -c /dev/null llvm/test/Regression/CodeGen/ARM/addSubConstant.ll:1.1
*** /dev/null Thu Dec 14 07:31:37 2006
--- llvm/test/Regression/CodeGen/ARM/addSubConstant.ll Thu Dec 14 07:31:27 2006
***
*** 0
--- 1,19
+ ; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm &&
+ ; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | not grep "805306384"
+
+
+ int %main() {
+ entry:
+ %retval = alloca int, align 4 ; [#uses=2]
+ %tmp = alloca int, align 4 ; [#uses=2]
+ %a = alloca [805306369 x sbyte], align 16 ; <[805306369 x
sbyte]*> [#uses=0]
+ "alloca point" = bitcast int 0 to int ; [#uses=0]
+ store int 0, int* %tmp
+ %tmp = load int* %tmp ; [#uses=1]
+ store int %tmp, int* %retval
+ br label %return
+
+ return: ; preds = %entry
+ %retval = load int* %retval ; [#uses=1]
+ ret int %retval
+ }
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.28 -> 1.29
---
Log message:
Avoid creating invalid sub/add instructions on the prolog/epilog
patch by Lauro
---
Diffs of the changes: (+86 -10)
ARMRegisterInfo.cpp | 96 ++--
1 files changed, 86 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.28
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.29
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.28Thu Dec 7 16:21:48 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Thu Dec 14 07:31:27 2006
@@ -35,6 +35,80 @@
return NoFramePointerElim || MFI->hasVarSizedObjects();
}
+#define ROTATE32L(x, n) (((x) << (n)) | ((x) >> (32 - (n
+
+#define ROTATE32R(x, n) (((x) >> (n)) | ((x) << (32 - (n
+
+// finds the end position of largest sequence of zeros in binary representation
+// of 'immediate'.
+static int findLargestZeroSequence(unsigned immediate){
+ int max_zero_pos;
+ int max_zero_length = 0;
+ int zero_pos;
+ int zero_length;
+ int pos = 0;
+ int end_pos;
+
+ while ((immediate & 0x3) == 0) {
+immediate = ROTATE32R(immediate, 2);
+pos+=2;
+ }
+ end_pos = pos+32;
+
+ while (pos max_zero_length){
+ max_zero_length = zero_length;
+ max_zero_pos = zero_pos % 32;
+}
+
+ }
+
+ return (max_zero_pos + max_zero_length) % 32;
+}
+
+static void splitInstructionWithImmediate(MachineBasicBlock &BB,
+ MachineBasicBlock::iterator I,
+ const TargetInstrDescriptor &TID,
+ unsigned DestReg,
+ unsigned OrigReg,
+ unsigned immediate){
+
+ if (immediate == 0){
+BuildMI(BB, I, TID, DestReg).addReg(OrigReg).addImm(0)
+ .addImm(0).addImm(ARMShift::LSL);
+return;
+ }
+
+ int start_pos = findLargestZeroSequence(immediate);
+ unsigned immediate_tmp = ROTATE32R(immediate, start_pos);
+
+ int pos = 0;
+ while (pos < 32){
+while(((immediate_tmp&0x3) == 0)&&(pos<32)){
+ immediate_tmp = ROTATE32R(immediate_tmp,2);
+ pos+=2;
+}
+if (pos < 32){
+ BuildMI(BB, I, TID, DestReg).addReg(OrigReg)
+ .addImm(ROTATE32L(immediate_tmp&0xFF, (start_pos + pos) % 32 ))
+ .addImm(0).addImm(ARMShift::LSL);
+ immediate_tmp = ROTATE32R(immediate_tmp,8);
+ pos+=8;
+}
+ }
+
+}
+
ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii)
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii) {
@@ -110,13 +184,13 @@
if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
// sub sp, sp, amount
-BuildMI(MBB, I, TII.get(ARM::SUB),
ARM::R13).addReg(ARM::R13).addImm(Amount)
- .addImm(0).addImm(ARMShift::LSL);
+ splitInstructionWithImmediate(MBB, I, TII.get(ARM::SUB), ARM::R13,
+ ARM::R13, Amount);
} else {
// add sp, sp, amount
assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
-BuildMI(MBB, I, TII.get(ARM::ADD),
ARM::R13).addReg(ARM::R13).addImm(Amount)
- .addImm(0).addImm(ARMShift::LSL);
+ splitInstructionWithImmediate(MBB, I, TII.get(ARM::ADD), ARM::R13,
+ ARM::R13, Amount);
}
}
}
@@ -156,8 +230,8 @@
// Insert a set of r12 with the full address
// r12 = r13 + offset
MachineBasicBlock *MBB2 = MI.getParent();
-BuildMI(*MBB2, II, TII.get(ARM::ADD), ARM::R12).addReg(BaseRegister)
- .addImm(Offset).addImm(0).addImm(ARMShift::LSL);
+splitInstructionWithImmediate(*MBB2, II, TII.get(ARM::ADD), ARM::R12,
+ BaseRegister, Offset);
// Replace the FrameIndex with r12
MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
@@ -192,8 +266,9 @@
MFI->setStackSize(NumBytes);
//sub sp, sp, #NumBytes
- BuildMI(MBB, MBBI, TII.get(ARM::SUB),
ARM::R13).addReg(ARM::R13).addImm(NumBytes)
- .addImm(0).addImm(ARMShift::LSL);
+ splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::SUB), ARM::R13,
+ARM::R13, NumBytes);
+
if (HasFP) {
BuildMI(MBB, MBBI, TII.get(ARM::STR))
@@ -219,8 +294,9 @@
}
//add sp, sp, #NumBytes
- BuildMI(MBB, MBBI, TII.get(ARM::ADD),
ARM::R13).addReg(ARM::R13).addImm(NumBytes)
- .addImm(0).addImm(ARMShift::LSL);
+ splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::ADD), ARM::R13,
+ARM::R13, NumBytes);
+
}
unsigned ARMRegisterInfo::getRARegister() const {
___
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[llvm-commits] CVS: llvm/docs/CodeGenerator.html
Changes in directory llvm/docs: CodeGenerator.html updated: 1.42 -> 1.43 --- Log message: Start of PowerPC info. --- Diffs of the changes: (+223 -1) CodeGenerator.html | 224 - 1 files changed, 223 insertions(+), 1 deletion(-) Index: llvm/docs/CodeGenerator.html diff -u llvm/docs/CodeGenerator.html:1.42 llvm/docs/CodeGenerator.html:1.43 --- llvm/docs/CodeGenerator.html:1.42 Wed Oct 11 13:00:22 2006 +++ llvm/docs/CodeGenerator.htmlThu Dec 14 11:19:50 2006 @@ -84,6 +84,13 @@ Target-specific Implementation Notes The X86 backend +The PowerPC backend + + LLVM PowerPC ABI + Frame Layout + Prolog/Epilog + Dynamic Allocation + @@ -1723,6 +1730,221 @@ + + + The PowerPC backend + + + +The PowerPC code generator lives in the lib/Target/PowerPC directory. The +code generation is retargetable to several variations or subtargets of +the PowerPC ISA; including ppc32, ppc64 and altivec. + + + + + + LLVM PowerPC ABI + + + +LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC +relative (PIC) or static addressing for accessing global values, so no TOC (r2) +is used. Second, r31 is used as a frame pointer to allow dynamic growth of a +stack frame. LLVM takes advantage of having no TOC to provide space to save +the frame pointer in the PowerPC linkage area of the caller frame. Other +details of PowerPC ABI can be found at http://developer.apple.com/documentation/DeveloperTools/Conceptual/ +LowLevelABI/Articles/32bitPowerPC.html" target="_blank">PowerPC ABI. Note: +This link describes the 32 bit ABI. The 64 bit ABI is similar except space for +GPRs are 8 bytes wide (not 4) and r13 is reserved for system use. + + + + + Frame Layout + + + +The size of a PowerPC frame is usually fixed for the duration of a +function's invocation. Since the frame is fixed size, all references into +the frame can be accessed via fixed offsets from the stack pointer. The +exception to this is when dynamic alloca or variable sized arrays are present, +then a base pointer (r31) is used as a proxy for the stack pointer and stack +pointer is free to grow or shrink. A base pointer is also used if llvm-gcc is +not passed the -fomit-frame-pointer flag. The stack pointer is always aligned to +16 bytes, so that space allocated for altivec vectors will be properly +aligned. +An invocation frame is layed out as follows (low memory at top); + + + + + + Linkage + + + Parameter area + + + Dynamic area + + + Locals area + + + Saved registers area + + + + + + Previous Frame + + + + + +The linkage area is used by a callee to save special registers prior +to allocating its own frame. Only three entries are relevant to LLVM. The +first entry is the previous stack pointer (sp), aka link. This allows probing +tools like gdb or exception handlers to quickly scan the frames in the stack. A +function epilog can also use the link to pop the frame from the stack. The +third entry in the linkage area is used to save the return address from the lr +register. Finally, as mentioned above, the last entry is used to save the +previous frame pointer (r31.) The entries in the linkage area are the size of a +GPR, thus the linkage area is 24 bytes long in 32 bit mode and 48 bytes in 64 +bit mode. + + + +32 bit linkage area + + + 0 + Saved SP (r1) + + + 4 + Saved CR + + + 8 + Saved LR + + + 12 + Reserved + + + 16 + Reserved + + + 20 + Saved FP (r31) + + + + + +64 bit linkage area + + + 0 + Saved SP (r1) + + + 8 + Saved CR + + + 16 + Saved LR + + + 24 + Reserved + + + 32 + Reserved + + + 40 + Saved FP (r31) + + + + + +The parameter area is used to store arguments being passed to a callee +function. Following the PowerPC ABI, the first few arguments are actually +passed in registers, with the space in the parameter area unused. However, if +there are not enough registers or the callee is a thunk or vararg function, +these register arguments can be spilled into the parameter area. Thus, the +parameter area must be large enough to store all the parameters for the largest +call sequence made by the caller. The size must also be mimimally large enough +to spill registers r3-r10. This allows callees blind to the call signature,
[llvm-commits] CVS: llvm/lib/VMCore/PassManager.cpp
Changes in directory llvm/lib/VMCore:
PassManager.cpp updated: 1.101 -> 1.102
---
Log message:
random minor typographical changes
---
Diffs of the changes: (+9 -14)
PassManager.cpp | 23 +--
1 files changed, 9 insertions(+), 14 deletions(-)
Index: llvm/lib/VMCore/PassManager.cpp
diff -u llvm/lib/VMCore/PassManager.cpp:1.101
llvm/lib/VMCore/PassManager.cpp:1.102
--- llvm/lib/VMCore/PassManager.cpp:1.101 Wed Dec 13 18:59:42 2006
+++ llvm/lib/VMCore/PassManager.cpp Thu Dec 14 12:22:14 2006
@@ -33,12 +33,12 @@
// o If Analysis information is dirtied by a pass then regenerate Analysis
// information before it is consumed by another pass.
//
-// Pass Manager Infrastructure uses multipe pass managers. They are
PassManager,
-// FunctionPassManager, ModulePassManager, BasicBlockPassManager. This class
-// hierarcy uses multiple inheritance but pass managers do not derive from
-// another pass manager.
+// Pass Manager Infrastructure uses multiple pass managers. They are
+// PassManager, FunctionPassManager, ModulePassManager, BasicBlockPassManager.
+// This class hierarcy uses multiple inheritance but pass managers do not
derive
+// from another pass manager.
//
-// PassManager and FunctionPassManager are two top level pass manager that
+// PassManager and FunctionPassManager are two top-level pass manager that
// represents the external interface of this entire pass manager infrastucture.
//
// Important classes :
@@ -124,7 +124,6 @@
/// PMTopLevelManager manages LastUser info and collects common APIs used by
/// top level pass managers.
class PMTopLevelManager {
-
public:
inline std::vector::iterator passManagersBegin() {
@@ -160,7 +159,6 @@
}
virtual ~PMTopLevelManager() {
-
for (std::vector::iterator I = PassManagers.begin(),
E = PassManagers.end(); I != E; ++I)
delete *I;
@@ -219,9 +217,7 @@
/// PMDataManager provides the common place to manage the analysis data
/// used by pass managers.
class PMDataManager {
-
public:
-
PMDataManager(int D) : TPM(NULL), Depth(D) {
initializeAnalysisInfo();
}
@@ -250,7 +246,7 @@
/// Add pass P into the PassVector. Update
/// AvailableAnalysis appropriately if ProcessAnalysis is true.
- void addPassToManager (Pass *P, bool ProcessAnalysis = true);
+ void addPassToManager(Pass *P, bool ProcessAnalysis = true);
/// Initialize available analysis information.
void initializeAnalysisInfo() {
@@ -364,7 +360,7 @@
/// pass together and sequence them to process one basic block before
/// processing next basic block.
class BasicBlockPassManager : public PMDataManager,
- public FunctionPass {
+ public FunctionPass {
public:
BasicBlockPassManager(int D) : PMDataManager(D) { }
@@ -482,8 +478,7 @@
/// ModulePassManager manages ModulePasses and function pass managers.
/// It batches all Module passes passes and function pass managers together
and
/// sequence them to process one module.
-class ModulePassManager : public Pass,
- public PMDataManager {
+class ModulePassManager : public Pass, public PMDataManager {
public:
ModulePassManager(int D) : PMDataManager(D) {
@@ -965,7 +960,7 @@
if (!manageablePass(P))
return false;
- addPassToManager (BP);
+ addPassToManager(BP);
return true;
}
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.91 -> 1.92
---
Log message:
avoid using a constant table when a constant can be used inline
---
Diffs of the changes: (+82 -24)
ARMISelDAGToDAG.cpp | 106
1 files changed, 82 insertions(+), 24 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.91
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.92
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.91Tue Dec 12 11:10:13 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Dec 14 12:58:37 2006
@@ -660,14 +660,91 @@
return DAG.getConstant(DAGFPCCToARMCC(CC), MVT::i32);
}
+static bool isUInt8Immediate(uint32_t x) {
+ return x < (1 << 8);
+}
+
+static uint32_t rotateL(uint32_t x) {
+ uint32_t bit31 = (x & (1 << 31)) >> 31;
+ uint32_t t = x << 1;
+ return t | bit31;
+}
+
+static bool isRotInt8Immediate(uint32_t x) {
+ int r;
+ for (r = 0; r < 16; r++) {
+if (isUInt8Immediate(x))
+ return true;
+x = rotateL(rotateL(x));
+ }
+ return false;
+}
+
+static void LowerCMP(SDOperand &Cmp, SDOperand &ARMCC, SDOperand LHS,
+ SDOperand RHS, ISD::CondCode CC, SelectionDAG &DAG) {
+ MVT::ValueType vt = LHS.getValueType();
+ if (vt == MVT::i32) {
+assert(!isa(LHS));
+if (ConstantSDNode *SD_C = dyn_cast(RHS.Val)) {
+ uint32_t C = SD_C->getValue();
+
+ uint32_t NC;
+ switch(CC) {
+ default:
+NC = C; break;
+ case ISD::SETLT:
+ case ISD::SETULT:
+ case ISD::SETGE:
+ case ISD::SETUGE:
+NC = C - 1; break;
+ case ISD::SETLE:
+ case ISD::SETULE:
+ case ISD::SETGT:
+ case ISD::SETUGT:
+NC = C + 1; break;
+ }
+
+ ISD::CondCode NCC;
+ switch(CC) {
+ default:
+NCC = CC; break;
+ case ISD::SETLT:
+NCC = ISD::SETLE; break;
+ case ISD::SETULT:
+NCC = ISD::SETULE; break;
+ case ISD::SETGE:
+NCC = ISD::SETGT; break;
+ case ISD::SETUGE:
+NCC = ISD::SETUGT; break;
+ case ISD::SETLE:
+NCC = ISD::SETLT; break;
+ case ISD::SETULE:
+NCC = ISD::SETULT; break;
+ case ISD::SETGT:
+NCC = ISD::SETGE; break;
+ case ISD::SETUGT:
+NCC = ISD::SETUGE; break;
+ }
+
+ if (!isRotInt8Immediate(C) && isRotInt8Immediate(NC)) {
+RHS = DAG.getConstant(NC, MVT::i32);
+CC = NCC;
+ }
+}
+ }
+ Cmp = GetCMP(CC, LHS, RHS, DAG);
+ ARMCC = GetARMCC(CC, vt, DAG);
+}
+
static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
SDOperand LHS = Op.getOperand(0);
SDOperand RHS = Op.getOperand(1);
ISD::CondCode CC = cast(Op.getOperand(4))->get();
SDOperand TrueVal = Op.getOperand(2);
SDOperand FalseVal = Op.getOperand(3);
- SDOperand Cmp = GetCMP(CC, LHS, RHS, DAG);
- SDOperandARMCC = GetARMCC(CC, LHS.getValueType(), DAG);
+ SDOperand Cmp;
+ SDOperand ARMCC;
+ LowerCMP(Cmp, ARMCC, LHS, RHS, CC, DAG);
return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp);
}
@@ -677,8 +754,9 @@
SDOperandLHS = Op.getOperand(2);
SDOperandRHS = Op.getOperand(3);
SDOperand Dest = Op.getOperand(4);
- SDOperandCmp = GetCMP(CC, LHS, RHS, DAG);
- SDOperand ARMCC = GetARMCC(CC, LHS.getValueType(), DAG);
+ SDOperand Cmp;
+ SDOperand ARMCC;
+ LowerCMP(Cmp, ARMCC, LHS, RHS, CC, DAG);
return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
}
@@ -820,26 +898,6 @@
return isInt12Immediate(Op.Val, Imm);
}
-static uint32_t rotateL(uint32_t x) {
- uint32_t bit31 = (x & (1 << 31)) >> 31;
- uint32_t t = x << 1;
- return t | bit31;
-}
-
-static bool isUInt8Immediate(uint32_t x) {
- return x < (1 << 8);
-}
-
-static bool isRotInt8Immediate(uint32_t x) {
- int r;
- for (r = 0; r < 16; r++) {
-if (isUInt8Immediate(x))
- return true;
-x = rotateL(rotateL(x));
- }
- return false;
-}
-
bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand Op,
SDOperand N,
SDOperand &Arg,
___
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/constants.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
constants.ll updated: 1.5 -> 1.6
---
Log message:
avoid using a constant table when a constant can be used inline
---
Diffs of the changes: (+10 -0)
constants.ll | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/constants.ll
diff -u llvm/test/Regression/CodeGen/ARM/constants.ll:1.5
llvm/test/Regression/CodeGen/ARM/constants.ll:1.6
--- llvm/test/Regression/CodeGen/ARM/constants.ll:1.5 Sat Dec 9 20:53:14 2006
+++ llvm/test/Regression/CodeGen/ARM/constants.ll Thu Dec 14 12:58:37 2006
@@ -5,6 +5,7 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep ".word.*257" | wc
-l | grep 1 &&
; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "mov r0,
#-1073741761" | wc -l | grep 1 &&
; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "mov r0, #1008" |
wc -l | grep 1 &&
+; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "cmp r0, #65536" |
wc -l | grep 1 &&
; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "\.comm.*a,4,4" |
wc -l | grep 1
%a = internal global int 0
@@ -32,3 +33,12 @@
uint %f6() {
ret uint 1008
}
+
+void %f7(uint %a) {
+entry:
+ %b = setgt uint %a, 65536
+ br bool %b, label %r, label %r
+
+r:
+ ret void
+}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp AsmPrinter.cpp
Changes in directory llvm/lib/CodeGen:
MachineFunction.cpp updated: 1.105 -> 1.106
AsmPrinter.cpp updated: 1.124 -> 1.125
---
Log message:
1. Tidy up jump table info.
2. Allow the jit to handle PIC relocable jump tables.
---
Diffs of the changes: (+32 -37)
AsmPrinter.cpp | 51 +++
MachineFunction.cpp | 18 +-
2 files changed, 32 insertions(+), 37 deletions(-)
Index: llvm/lib/CodeGen/MachineFunction.cpp
diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.105
llvm/lib/CodeGen/MachineFunction.cpp:1.106
--- llvm/lib/CodeGen/MachineFunction.cpp:1.105 Thu Dec 7 14:28:15 2006
+++ llvm/lib/CodeGen/MachineFunction.cppThu Dec 14 13:17:33 2006
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Function.h"
@@ -117,7 +118,14 @@
MFInfo = 0;
FrameInfo = new MachineFrameInfo();
ConstantPool = new MachineConstantPool(TM.getTargetData());
- JumpTableInfo = new MachineJumpTableInfo(TM.getTargetData());
+
+ // Set up jump table.
+ const TargetData &TD = *TM.getTargetData();
+ bool IsPic = TM.getRelocationModel() == Reloc::PIC_;
+ unsigned EntrySize = IsPic ? 4 : TD.getPointerSize();
+ unsigned Alignment = IsPic ? TD.getIntAlignment() : TD.getPointerAlignment();
+ JumpTableInfo = new MachineJumpTableInfo(EntrySize, Alignment);
+
BasicBlocks.Parent = this;
}
@@ -380,14 +388,6 @@
}
}
-unsigned MachineJumpTableInfo::getEntrySize() const {
- return TD->getPointerSize();
-}
-
-unsigned MachineJumpTableInfo::getAlignment() const {
- return TD->getPointerAlignment();
-}
-
void MachineJumpTableInfo::dump() const { print(*cerr.stream()); }
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.124
llvm/lib/CodeGen/AsmPrinter.cpp:1.125
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.124 Mon Dec 11 23:18:19 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp Thu Dec 14 13:17:33 2006
@@ -188,36 +188,31 @@
MachineFunction &MF) {
const std::vector &JT = MJTI->getJumpTables();
if (JT.empty()) return;
- const TargetData *TD = TM.getTargetData();
+ bool IsPic = TM.getRelocationModel() == Reloc::PIC_;
- // JTEntryDirective is a string to print sizeof(ptr) for non-PIC jump tables,
- // and 32 bits for PIC since PIC jump table entries are differences, not
- // pointers to blocks.
- // Use the architecture specific relocation directive, if it is set
+ // Use JumpTableDirective otherwise honor the entry size from the jump table
+ // info.
const char *JTEntryDirective = TAI->getJumpTableDirective();
- if (!JTEntryDirective)
-JTEntryDirective = TAI->getData32bitsDirective();
+ bool HadJTEntryDirective = JTEntryDirective != NULL;
+ if (!HadJTEntryDirective) {
+JTEntryDirective = MJTI->getEntrySize() == 4 ?
+ TAI->getData32bitsDirective() : TAI->getData64bitsDirective();
+ }
// Pick the directive to use to print the jump table entries, and switch to
// the appropriate section.
- if (TM.getRelocationModel() == Reloc::PIC_) {
-TargetLowering *LoweringInfo = TM.getTargetLowering();
-if (LoweringInfo && LoweringInfo->usesGlobalOffsetTable()) {
- SwitchToDataSection(TAI->getJumpTableDataSection());
- if (TD->getPointerSize() == 8 && !JTEntryDirective)
-JTEntryDirective = TAI->getData64bitsDirective();
-} else {
- // In PIC mode, we need to emit the jump table to the same section as the
- // function body itself, otherwise the label differences won't make
sense.
- const Function *F = MF.getFunction();
- SwitchToTextSection(getSectionForFunction(*F).c_str(), F);
-}
+ TargetLowering *LoweringInfo = TM.getTargetLowering();
+
+ if (IsPic && !(LoweringInfo && LoweringInfo->usesGlobalOffsetTable())) {
+// In PIC mode, we need to emit the jump table to the same section as the
+// function body itself, otherwise the label differences won't make sense.
+const Function *F = MF.getFunction();
+SwitchToTextSection(getSectionForFunction(*F).c_str(), F);
} else {
SwitchToDataSection(TAI->getJumpTableDataSection());
-if (TD->getPointerSize() == 8)
- JTEntryDirective = TAI->getData64bitsDirective();
}
- EmitAlignment(Log2_32(TD->getPointerAlignment()));
+
+ EmitAlignment(Log2_32(MJTI->getAlignment()));
for (unsigned i = 0, e = JT.size(); i != e; ++i) {
const std::vector &JTBBs = JT[i].MBBs;
@@ -229,7 +224,7 @@
// the number of relocations the assembler will generate for the jump
table.
// Set directives are all printed before the jump table itself.
std::set EmittedSets;
-if (TAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_)
+if (TAI->getSetDirective() && IsPic)
[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineJumpTableInfo.h
Changes in directory llvm/include/llvm/CodeGen:
MachineJumpTableInfo.h updated: 1.8 -> 1.9
---
Log message:
1. Tidy up jump table info.
2. Allow the jit to handle PIC relocable jump tables.
---
Diffs of the changes: (+6 -3)
MachineJumpTableInfo.h |9 ++---
1 files changed, 6 insertions(+), 3 deletions(-)
Index: llvm/include/llvm/CodeGen/MachineJumpTableInfo.h
diff -u llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.8
llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.9
--- llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.8Sat Oct 28
13:21:51 2006
+++ llvm/include/llvm/CodeGen/MachineJumpTableInfo.hThu Dec 14 13:17:33 2006
@@ -39,9 +39,11 @@
class MachineJumpTableInfo {
const TargetData *TD;
+ unsigned EntrySize;
std::vector JumpTables;
public:
- MachineJumpTableInfo(const TargetData *td) : TD(td) {}
+ MachineJumpTableInfo(const TargetData *td, unsigned ES)
+ : TD(td), EntrySize(ES) {}
/// getJumpTableIndex - Create a new jump table or return an existing one.
///
@@ -77,8 +79,9 @@
return MadeChange;
}
- /// getEntrySize - returns the size of an individual field in a jump table
- unsigned getEntrySize() const;
+ /// getEntrySize - Returns the size of an individual field in a jump table.
+ ///
+ unsigned getEntrySize() const { return EntrySize; }
/// getAlignment - returns the target's preferred alignment for jump tables
unsigned getAlignment() const;
___
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[llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
Changes in directory llvm/lib/ExecutionEngine/JIT:
JITEmitter.cpp updated: 1.121 -> 1.122
---
Log message:
1. Tidy up jump table info.
2. Allow the jit to handle PIC relocable jump tables.
---
Diffs of the changes: (+36 -17)
JITEmitter.cpp | 53 -
1 files changed, 36 insertions(+), 17 deletions(-)
Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.121
llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.122
--- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.121 Thu Dec 7 14:04:42 2006
+++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Thu Dec 14 13:17:33 2006
@@ -25,6 +25,7 @@
#include "llvm/ExecutionEngine/GenericValue.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetJITInfo.h"
+#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MutexGuard.h"
#include "llvm/ADT/Statistic.h"
@@ -700,7 +701,7 @@
void emitConstantPool(MachineConstantPool *MCP);
void initJumpTableInfo(MachineJumpTableInfo *MJTI);
-void emitJumpTableInfo(MachineJumpTableInfo *MJTI);
+void emitJumpTableInfo(MachineJumpTableInfo *MJTI, Reloc::Model RM);
virtual void startFunctionStub(unsigned StubSize, unsigned Alignment = 1);
virtual void* finishFunctionStub(const Function *F);
@@ -791,7 +792,7 @@
abort();
}
- emitJumpTableInfo(F.getJumpTableInfo());
+ emitJumpTableInfo(F.getJumpTableInfo(), F.getTarget().getRelocationModel());
// FnStart is the start of the text, not the start of the constant pool and
// other per-function data.
@@ -821,7 +822,7 @@
MR.doesntNeedFunctionStub());
} else if (MR.isBasicBlock()) {
ResultPtr = (void*)getMachineBasicBlockAddress(MR.getBasicBlock());
- } else if (MR.isConstantPoolIndex()){
+ } else if (MR.isConstantPoolIndex()) {
ResultPtr=(void*)getConstantPoolEntryAddress(MR.getConstantPoolIndex());
} else {
assert(MR.isJumpTableIndex());
@@ -914,22 +915,38 @@
JumpTableBase = allocateSpace(NumEntries * EntrySize, MJTI->getAlignment());
}
-void JITEmitter::emitJumpTableInfo(MachineJumpTableInfo *MJTI) {
+void JITEmitter::emitJumpTableInfo(MachineJumpTableInfo *MJTI, Reloc::Model
RM){
const std::vector &JT = MJTI->getJumpTables();
if (JT.empty() || JumpTableBase == 0) return;
-
- assert(MJTI->getEntrySize() == sizeof(void*) && "Cross JIT'ing?");
- // For each jump table, map each target in the jump table to the address of
- // an emitted MachineBasicBlock.
- intptr_t *SlotPtr = (intptr_t*)JumpTableBase;
-
- for (unsigned i = 0, e = JT.size(); i != e; ++i) {
-const std::vector &MBBs = JT[i].MBBs;
-// Store the address of the basic block for this jump table slot in the
-// memory we allocated for the jump table in 'initJumpTableInfo'
-for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi)
- *SlotPtr++ = getMachineBasicBlockAddress(MBBs[mi]);
+ if (RM == Reloc::PIC_) {
+assert(MJTI->getEntrySize() == 4 && "Cross JIT'ing?");
+// For each jump table, place the offset from the beginning of the table
+// to the target address.
+int *SlotPtr = (int*)JumpTableBase;
+
+for (unsigned i = 0, e = JT.size(); i != e; ++i) {
+ const std::vector &MBBs = JT[i].MBBs;
+ // Store the offset of the basic block for this jump table slot in the
+ // memory we allocated for the jump table in 'initJumpTableInfo'
+ intptr_t Base = (intptr_t)SlotPtr;
+ for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi)
+*SlotPtr++ = (intptr_t)getMachineBasicBlockAddress(MBBs[mi]) - Base;
+}
+ } else {
+assert(MJTI->getEntrySize() == sizeof(void*) && "Cross JIT'ing?");
+
+// For each jump table, map each target in the jump table to the address
of
+// an emitted MachineBasicBlock.
+intptr_t *SlotPtr = (intptr_t*)JumpTableBase;
+
+for (unsigned i = 0, e = JT.size(); i != e; ++i) {
+ const std::vector &MBBs = JT[i].MBBs;
+ // Store the address of the basic block for this jump table slot in the
+ // memory we allocated for the jump table in 'initJumpTableInfo'
+ for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi)
+*SlotPtr++ = getMachineBasicBlockAddress(MBBs[mi]);
+}
}
}
@@ -972,7 +989,9 @@
unsigned EntrySize = JumpTable->getEntrySize();
for (unsigned i = 0; i < Index; ++i)
-Offset += JT[i].MBBs.size() * EntrySize;
+Offset += JT[i].MBBs.size();
+
+ Offset *= EntrySize;
return (intptr_t)((char *)JumpTableBase + Offset);
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.440 -> 1.441
---
Log message:
1. Tidy up jump table info.
2. Allow the jit to handle PIC relocable jump tables.
---
Diffs of the changes: (+12 -5)
LegalizeDAG.cpp | 17 -
1 files changed, 12 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.440
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.441
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.440 Wed Dec 13 14:57:08 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Dec 14 13:17:33 2006
@@ -14,6 +14,7 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
@@ -1275,13 +1276,19 @@
SDOperand Index = Result.getOperand(2);
MVT::ValueType PTy = TLI.getPointerTy();
- bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_;
- // PIC jump table entries are 32-bit values.
- unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8;
+ MachineFunction &MF = DAG.getMachineFunction();
+ unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize,
PTy));
SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
- SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
- if (isPIC) {
+
+ SDOperand LD;
+ switch (EntrySize) {
+ default: assert(0 && "Size of jump table not supported yet."); break;
+ case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
+ case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
+ }
+
+ if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
// For PIC, the sequence is:
// BRIND(load(Jumptable + index) + RelocBase)
// RelocBase is the JumpTable on PPC and X86, GOT on Alpha
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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.184 -> 1.185
---
Log message:
Added MOVSS2DIrr and MOVDI2SSrr to foldMemeoryOperand().
---
Diffs of the changes: (+2 -0)
X86RegisterInfo.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.184
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.185
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.184 Thu Dec 7 16:21:48 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Dec 14 13:44:45 2006
@@ -511,6 +511,7 @@
{ X86::MOVPQIto64rr,X86::MOVPQIto64mr },
{ X86::MOVPS2SSrr, X86::MOVPS2SSmr },
{ X86::MOVSDrr, X86::MOVSDmr },
+ { X86::MOVSS2DIrr, X86::MOVSS2DImr },
{ X86::MOVSSrr, X86::MOVSSmr },
{ X86::MOVUPDrr,X86::MOVUPDmr },
{ X86::MOVUPSrr,X86::MOVUPSmr },
@@ -612,6 +613,7 @@
{ X86::MOVAPSrr,X86::MOVAPSrm },
{ X86::MOVDDUPrr, X86::MOVDDUPrm },
{ X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
+ { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
{ X86::MOVSD2PDrr, X86::MOVSD2PDrm },
{ X86::MOVSDrr, X86::MOVSDrm },
{ X86::MOVSHDUPrr, X86::MOVSHDUPrm },
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.173 -> 1.174
---
Log message:
- Rename MOVDSS2DIrr to MOVSS2DIrr for consistency sake.
- Add MOVDI2SSrm and MOVSS2DImr to fold load / store for i32 <-> f32 bit_convert
patterns.
---
Diffs of the changes: (+9 -3)
X86InstrSSE.td | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.173
llvm/lib/Target/X86/X86InstrSSE.td:1.174
--- llvm/lib/Target/X86/X86InstrSSE.td:1.173Tue Dec 5 12:45:06 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Dec 14 13:43:11 2006
@@ -1687,6 +1687,9 @@
"movd {$src, $dst|$dst, $src}",
[(set FR32:$dst, (bitconvert GR32:$src))]>;
+def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
+ "movd {$src, $dst|$dst, $src}",
+ [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
// SSE2 instructions with XS prefix
def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
@@ -1729,9 +1732,12 @@
[(store (i32 (vector_extract (v4i32 VR128:$src),
(iPTR 0))), addr:$dst)]>;
-def MOVDSS2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, FR32:$src),
- "movd {$src, $dst|$dst, $src}",
- [(set GR32:$dst, (bitconvert FR32:$src))]>;
+def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, FR32:$src),
+ "movd {$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (bitconvert FR32:$src))]>;
+def MOVSS2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, FR32:$src),
+ "movd {$src, $dst|$dst, $src}",
+ [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
// Move to lower bits of a VR128, leaving upper bits alone.
___
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[llvm-commits] CVS: llvm/lib/Target/X86/README-SSE.txt
Changes in directory llvm/lib/Target/X86: README-SSE.txt updated: 1.12 -> 1.13 --- Log message: This is done. --- Diffs of the changes: (+0 -5) README-SSE.txt |5 - 1 files changed, 5 deletions(-) Index: llvm/lib/Target/X86/README-SSE.txt diff -u llvm/lib/Target/X86/README-SSE.txt:1.12 llvm/lib/Target/X86/README-SSE.txt:1.13 --- llvm/lib/Target/X86/README-SSE.txt:1.12 Wed Dec 13 14:59:43 2006 +++ llvm/lib/Target/X86/README-SSE.txt Thu Dec 14 13:45:32 2006 @@ -535,8 +535,3 @@ Floating point max / min are commutable when -enable-unsafe-fp-path is specified. We should turn int_x86_sse_max_ss and X86ISD::FMIN etc. into other nodes which are selected to max / min instructions that are marked commutable. - -//===-===// - -Add MOVDI2SSrr and MOVDSS2DIrr to X86RegisterInfo::foldMemoryOperand() once the -recent X86 JIT regressions have been identified and fixed. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrX86-64.td
Changes in directory llvm/lib/Target/X86:
X86InstrX86-64.td updated: 1.11 -> 1.12
---
Log message:
Fix a couple of typo's.
---
Diffs of the changes: (+2 -2)
X86InstrX86-64.td |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrX86-64.td
diff -u llvm/lib/Target/X86/X86InstrX86-64.td:1.11
llvm/lib/Target/X86/X86InstrX86-64.td:1.12
--- llvm/lib/Target/X86/X86InstrX86-64.td:1.11 Tue Dec 5 13:50:18 2006
+++ llvm/lib/Target/X86/X86InstrX86-64.td Thu Dec 14 13:46:06 2006
@@ -1119,10 +1119,10 @@
(v2i64 (scalar_to_vector (loadi64 addr:$src]>;
def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (ops GR64:$dst, VR128:$src),
- "movd {$src, $dst|$dst, $src}",
+ "movq {$src, $dst|$dst, $src}",
[(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
(iPTR 0)))]>;
def MOVPQIto64mr : RPDI<0x7E, MRMDestMem, (ops i64mem:$dst, VR128:$src),
- "movd {$src, $dst|$dst, $src}",
+ "movq {$src, $dst|$dst, $src}",
[(store (i64 (vector_extract (v2i64 VR128:$src),
(iPTR 0))), addr:$dst)]>;
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineJumpTableInfo.h
Changes in directory llvm/include/llvm/CodeGen:
MachineJumpTableInfo.h updated: 1.9 -> 1.10
---
Log message:
File missing from last check in.
---
Diffs of the changes: (+4 -4)
MachineJumpTableInfo.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/CodeGen/MachineJumpTableInfo.h
diff -u llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.9
llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.10
--- llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.9Thu Dec 14
13:17:33 2006
+++ llvm/include/llvm/CodeGen/MachineJumpTableInfo.hThu Dec 14 15:03:17 2006
@@ -38,12 +38,12 @@
};
class MachineJumpTableInfo {
- const TargetData *TD;
unsigned EntrySize;
+ unsigned Alignment;
std::vector JumpTables;
public:
- MachineJumpTableInfo(const TargetData *td, unsigned ES)
- : TD(td), EntrySize(ES) {}
+ MachineJumpTableInfo(unsigned Size, unsigned Align)
+ : EntrySize(Size), Alignment(Align) {}
/// getJumpTableIndex - Create a new jump table or return an existing one.
///
@@ -84,7 +84,7 @@
unsigned getEntrySize() const { return EntrySize; }
/// getAlignment - returns the target's preferred alignment for jump tables
- unsigned getAlignment() const;
+ unsigned getAlignment() const { return Alignment; }
/// print - Used by the MachineFunction printer to print information about
/// jump tables. Implemented in MachineFunction.cpp
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrX86-64.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.305 -> 1.306
X86InstrX86-64.td updated: 1.12 -> 1.13
X86RegisterInfo.cpp updated: 1.185 -> 1.186
---
Log message:
f64 <-> i64 bit_convert using movq in 64-bit mode.
---
Diffs of the changes: (+16 -4)
X86ISelLowering.cpp |4
X86InstrX86-64.td | 14 ++
X86RegisterInfo.cpp |2 ++
3 files changed, 16 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.305
llvm/lib/Target/X86/X86ISelLowering.cpp:1.306
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.305 Sun Dec 10 17:12:42 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Dec 14 15:55:39 2006
@@ -158,10 +158,6 @@
setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
}
- if (Subtarget->is64Bit()) {
-setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
-setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
- }
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BRCOND , MVT::Other, Custom);
Index: llvm/lib/Target/X86/X86InstrX86-64.td
diff -u llvm/lib/Target/X86/X86InstrX86-64.td:1.12
llvm/lib/Target/X86/X86InstrX86-64.td:1.13
--- llvm/lib/Target/X86/X86InstrX86-64.td:1.12 Thu Dec 14 13:46:06 2006
+++ llvm/lib/Target/X86/X86InstrX86-64.td Thu Dec 14 15:55:39 2006
@@ -1126,3 +1126,17 @@
"movq {$src, $dst|$dst, $src}",
[(store (i64 (vector_extract (v2i64 VR128:$src),
(iPTR 0))), addr:$dst)]>;
+
+def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (ops FR64:$dst, GR64:$src),
+ "movq {$src, $dst|$dst, $src}",
+ [(set FR64:$dst, (bitconvert GR64:$src))]>;
+def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (ops FR64:$dst, i64mem:$src),
+ "movq {$src, $dst|$dst, $src}",
+ [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
+
+def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (ops GR64:$dst, FR64:$src),
+"movq {$src, $dst|$dst, $src}",
+[(set GR64:$dst, (bitconvert FR64:$src))]>;
+def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (ops i64mem:$dst, FR64:$src),
+"movq {$src, $dst|$dst, $src}",
+[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.185
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.186
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.185 Thu Dec 14 13:44:45 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Dec 14 15:55:39 2006
@@ -511,6 +511,7 @@
{ X86::MOVPQIto64rr,X86::MOVPQIto64mr },
{ X86::MOVPS2SSrr, X86::MOVPS2SSmr },
{ X86::MOVSDrr, X86::MOVSDmr },
+ { X86::MOVSDto64rr, X86::MOVSDto64mr },
{ X86::MOVSS2DIrr, X86::MOVSS2DImr },
{ X86::MOVSSrr, X86::MOVSSmr },
{ X86::MOVUPDrr,X86::MOVUPDmr },
@@ -608,6 +609,7 @@
{ X86::MOV32rr, X86::MOV32rm },
{ X86::MOV64rr, X86::MOV64rm },
{ X86::MOV64toPQIrr,X86::MOV64toPQIrm },
+ { X86::MOV64toSDrr, X86::MOV64toSDrm },
{ X86::MOV8rr, X86::MOV8rm },
{ X86::MOVAPDrr,X86::MOVAPDrm },
{ X86::MOVAPSrr,X86::MOVAPSrm },
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[llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
Changes in directory llvm/lib/ExecutionEngine/JIT:
JITEmitter.cpp updated: 1.122 -> 1.123
---
Log message:
Simplify the fetching of relocation mode.
---
Diffs of the changes: (+4 -4)
JITEmitter.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.122
llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.123
--- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.122 Thu Dec 14 13:17:33 2006
+++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Thu Dec 14 16:53:42 2006
@@ -701,7 +701,7 @@
void emitConstantPool(MachineConstantPool *MCP);
void initJumpTableInfo(MachineJumpTableInfo *MJTI);
-void emitJumpTableInfo(MachineJumpTableInfo *MJTI, Reloc::Model RM);
+void emitJumpTableInfo(MachineJumpTableInfo *MJTI);
virtual void startFunctionStub(unsigned StubSize, unsigned Alignment = 1);
virtual void* finishFunctionStub(const Function *F);
@@ -792,7 +792,7 @@
abort();
}
- emitJumpTableInfo(F.getJumpTableInfo(), F.getTarget().getRelocationModel());
+ emitJumpTableInfo(F.getJumpTableInfo());
// FnStart is the start of the text, not the start of the constant pool and
// other per-function data.
@@ -915,11 +915,11 @@
JumpTableBase = allocateSpace(NumEntries * EntrySize, MJTI->getAlignment());
}
-void JITEmitter::emitJumpTableInfo(MachineJumpTableInfo *MJTI, Reloc::Model
RM){
+void JITEmitter::emitJumpTableInfo(MachineJumpTableInfo *MJTI) {
const std::vector &JT = MJTI->getJumpTables();
if (JT.empty() || JumpTableBase == 0) return;
- if (RM == Reloc::PIC_) {
+ if (TargetMachine::getRelocationModel() == Reloc::PIC_) {
assert(MJTI->getEntrySize() == 4 && "Cross JIT'ing?");
// For each jump table, place the offset from the beginning of the table
// to the target address.
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[llvm-commits] CVS: llvm/lib/VMCore/PassManager.cpp
Changes in directory llvm/lib/VMCore:
PassManager.cpp updated: 1.102 -> 1.103
---
Log message:
s/ForcedLastUses/TransferLastUses/g
Register pass has the its last user, otherwise sometimes no one will claim
LastUse.
Handle transferred last uses from child pass manager.
---
Diffs of the changes: (+26 -12)
PassManager.cpp | 38 ++
1 files changed, 26 insertions(+), 12 deletions(-)
Index: llvm/lib/VMCore/PassManager.cpp
diff -u llvm/lib/VMCore/PassManager.cpp:1.102
llvm/lib/VMCore/PassManager.cpp:1.103
--- llvm/lib/VMCore/PassManager.cpp:1.102 Thu Dec 14 12:22:14 2006
+++ llvm/lib/VMCore/PassManager.cpp Thu Dec 14 18:08:26 2006
@@ -250,7 +250,7 @@
/// Initialize available analysis information.
void initializeAnalysisInfo() {
-ForcedLastUses.clear();
+TransferLastUses.clear();
AvailableAnalysis.clear();
}
@@ -330,12 +330,18 @@
cerr << "\n";
}
}
+
+ std::vector& getTransferredLastUses() {
+return TransferLastUses;
+ }
+
protected:
- // Collection of pass whose last user asked this manager to claim
- // last use. If a FunctionPass F is the last user of ModulePass info M
+ // If a FunctionPass F is the last user of ModulePass info M
// then the F's manager, not F, records itself as a last user of M.
- std::vector ForcedLastUses;
+ // Current pass manage is requesting parent manager to record parent
+ // manager as the last user of these TrransferLastUses passes.
+ std::vector TransferLastUses;
// Top level manager.
PMTopLevelManager *TPM;
@@ -853,7 +859,7 @@
LastUses.push_back(PRequired);
else if (PDepth > RDepth) {
// Let the parent claim responsibility of last use
-ForcedLastUses.push_back(PRequired);
+TransferLastUses.push_back(PRequired);
} else {
// Note : This feature is not yet implemented
assert (0 &&
@@ -861,8 +867,8 @@
}
}
-if (!LastUses.empty())
- TPM->setLastUser(LastUses, P);
+LastUses.push_back(P);
+TPM->setLastUser(LastUses, P);
// Take a note of analysis required and made available by this pass.
// Remove the analysis not preserved by this pass
@@ -1161,10 +1167,14 @@
// Add pass into new manager. This time it must succeed.
if (!activeBBPassManager->addPass(BP))
assert(0 && "Unable to add Pass");
+
+ // If activeBBPassManager transfered any Last Uses then handle them here.
+ std::vector &TLU = activeBBPassManager->getTransferredLastUses();
+ if (!TLU.empty())
+TPM->setLastUser(TLU, this);
+
}
-if (!ForcedLastUses.empty())
- TPM->setLastUser(ForcedLastUses, this);
return true;
}
@@ -1326,10 +1336,14 @@
// Add pass into new manager. This time it must succeed.
if (!activeFunctionPassManager->addPass(FP))
assert(0 && "Unable to add pass");
-}
-if (!ForcedLastUses.empty())
- TPM->setLastUser(ForcedLastUses, this);
+ // If activeFunctionPassManager transfered any Last Uses then
+ // handle them here.
+ std::vector &TLU =
+activeFunctionPassManager->getTransferredLastUses();
+ if (!TLU.empty())
+TPM->setLastUser(TLU, this);
+}
return true;
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.441 -> 1.442
---
Log message:
Expand FP compares to soft-fp call(s)
---
Diffs of the changes: (+102 -7)
LegalizeDAG.cpp | 109
1 files changed, 102 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.441
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.442
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.441 Thu Dec 14 13:17:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Dec 14 20:59:56 2006
@@ -2011,10 +2011,10 @@
isCustom = true;
// FALLTHROUGH.
case TargetLowering::Legal:
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
if (isCustom) {
-Tmp3 = TLI.LowerOperation(Result, DAG);
-if (Tmp3.Val) Result = Tmp3;
+Tmp4 = TLI.LowerOperation(Result, DAG);
+if (Tmp4.Val) Result = Tmp4;
}
break;
case TargetLowering::Promote: {
@@ -2045,7 +2045,7 @@
}
Tmp1 = LegalizeOp(Tmp1);
Tmp2 = LegalizeOp(Tmp2);
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
Result = LegalizeOp(Result);
break;
}
@@ -2055,7 +2055,7 @@
MVT::ValueType VT = Node->getValueType(0);
Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
- Node->getOperand(2));
+ Tmp3);
break;
}
break;
@@ -3533,10 +3533,104 @@
}
}
break;
- case Expand:
+ case Expand: {
+MVT::ValueType VT = LHS.getValueType();
+if (VT == MVT::f32 || VT == MVT::f64) {
+ // Expand into one or more soft-fp libcall(s).
+ const char *FnName1 = NULL, *FnName2 = NULL;
+ ISD::CondCode CC1, CC2;
+ switch (cast(CC)->get()) {
+ case ISD::SETEQ:
+ case ISD::SETOEQ:
+FnName1 = (VT == MVT::f32) ? "__eqsf2" : "__eqdf2";
+CC1 = ISD::SETEQ;
+break;
+ case ISD::SETNE:
+ case ISD::SETUNE:
+FnName1 = (VT == MVT::f32) ? "__nesf2" : "__nedf2";
+CC1 = ISD::SETNE;
+break;
+ case ISD::SETGE:
+ case ISD::SETOGE:
+FnName1 = (VT == MVT::f32) ? "__gesf2" : "__gedf2";
+CC1 = ISD::SETGE;
+break;
+ case ISD::SETLT:
+ case ISD::SETOLT:
+FnName1 = (VT == MVT::f32) ? "__ltsf2" : "__ltdf2";
+CC1 = ISD::SETLT;
+break;
+ case ISD::SETLE:
+ case ISD::SETOLE:
+FnName1 = (VT == MVT::f32) ? "__lesf2" : "__ledf2";
+CC1 = ISD::SETLE;
+break;
+ case ISD::SETGT:
+ case ISD::SETOGT:
+FnName1 = (VT == MVT::f32) ? "__gtsf2" : "__gtdf2";
+CC1 = ISD::SETGT;
+break;
+ case ISD::SETUO:
+ case ISD::SETO:
+FnName1 = (VT == MVT::f32) ? "__unordsf2" : "__unorddf2";
+CC1 = cast(CC)->get() == ISD::SETO
+ ? ISD::SETEQ : ISD::SETNE;
+break;
+ default:
+FnName1 = (VT == MVT::f32) ? "__unordsf2" : "__unorddf2";
+CC1 = ISD::SETNE;
+switch (cast(CC)->get()) {
+case ISD::SETONE:
+ // SETONE = SETOLT | SETOGT
+ FnName1 = (VT == MVT::f32) ? "__ltsf2" : "__ltdf2";
+ CC1 = ISD::SETLT;
+ // Fallthrough
+case ISD::SETUGT:
+ FnName2 = (VT == MVT::f32) ? "__gtsf2" : "__gtdf2";
+ CC2 = ISD::SETGT;
+ break;
+case ISD::SETUGE:
+ FnName2 = (VT == MVT::f32) ? "__gesf2" : "__gedf2";
+ CC2 = ISD::SETGE;
+ break;
+case ISD::SETULT:
+ FnName2 = (VT == MVT::f32) ? "__ltsf2" : "__ltdf2";
+ CC2 = ISD::SETLT;
+ break;
+case ISD::SETULE:
+ FnName2 = (VT == MVT::f32) ? "__lesf2" : "__ledf2";
+ CC2 = ISD::SETLE;
+ break;
+ case ISD::SETUEQ:
+FnName2 = (VT == MVT::f32) ? "__eqsf2" : "__eqdf2";
+CC2 = ISD::SETEQ;
+break;
+default: assert(0 && "Unsupported FP setcc!");
+}
+ }
+
+ SDOperand Dummy;
+ Tmp1 = ExpandLibCall(FnName1,
+ DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
Dummy);
+ Tmp2 = DAG.getConstant(0, MVT::i32);
+ CC = DAG.getCondCode(CC1);
+ if (FnName2) {
+Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
+LHS = ExpandLibCall(FnName2,
+ DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
Dummy);
+Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
+ DAG.getCondCode(CC2));
+Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(
Re: [llvm-commits] SETCC Patches: #3
Hi Chris,
Some feedback on your review ..
On Mon, 2006-12-11 at 22:51 -0800, Chris Lattner wrote:
>
> On Dec 10, 2006, at 3:43 PM, Reid Spencer wrote:
>
> > All,
> >
> >
> > Here's the SETCC patch to convert SetCondInst (SetCC) instructions
> > into
> > ICmpInst. Here's somethings you should know about this patch:
>
>
>
> This is all the rest, except for instcombine.
Most of the changes you suggested were just done. There's a couple
questions below that I need the answers for.
>
>
> Index: tools/llvm-upgrade/UpgradeParser.y
> ===
> RCS file: /var/cvs/llvm/llvm/tools/llvm-upgrade/UpgradeParser.y,v
> retrieving revision 1.24
> diff -t -d -u -p -5 -r1.24 UpgradeParser.y
> --- tools/llvm-upgrade/UpgradeParser.y 9 Dec 2006 19:40:41 - 1.24
> +++ tools/llvm-upgrade/UpgradeParser.y 10 Dec 2006 23:27:00 -
> @@ -21,11 +21,11 @@
> #include
>
>
>
> #define YYERROR_VERBOSE 1
> #define YYINCLUDED_STDLIB_H
> #define YYDEBUG 1
> -#define UPGRADE_SETCOND_OPS 0
> +#define UPGRADE_SETCOND_OPS 1
> #define GENERATE_FCMP_INSTS 0
>
>
>
> int yylex(); // declaration" of xxx warnings.
> int yyparse();
> extern int yydebug;
>
>
> This #ifdef should go away now, since it's always on.
Yup. Done.
>
>
>
>
> Index: lib/ExecutionEngine/Interpreter/Execution.cpp
> ===
> RCS
> file: /var/cvs/llvm/llvm/lib/ExecutionEngine/Interpreter/Execution.cpp,v
> retrieving revision 1.152
> diff -t -d -u -p -5 -r1.152 Execution.cpp
> --- lib/ExecutionEngine/Interpreter/Execution.cpp 7 Dec 2006 01:30:31
> - 1.152
> +++ lib/ExecutionEngine/Interpreter/Execution.cpp 10 Dec 2006 23:26:54
> -
> ...
>
>
> +static GenericValue executeICMP_ULT(GenericValue Src1, GenericValue
> Src2,
> +const Type *Ty) {
> + GenericValue Dest;
> + switch (Ty->getTypeID()) {
> +IMPLEMENT_CMP(<, UByte);
> +IMPLEMENT_CMP(<, UShort);
> +IMPLEMENT_CMP(<, UInt);
> +IMPLEMENT_CMP(<, ULong);
> +IMPLEMENT_POINTERCMP(<);
> + default:
> +cerr << "Unhandled type for ICMP_ULT predicate: " << *Ty << "\n";
> +abort();
> + }
> + return Dest;
> +}
>
>
> The interpreter is broken: all unsigned comparisons with signed
> operands will hit the unhandled type case.
Yup. Fixed the macro to take two arguments. The first is to match the
type of the operand.
The second is the type to use to pull the values out of the GenericValue
union, effecitvely doing the type cast by field selection.
>
>
>
>
> Index: lib/Target/CBackend/Writer.cpp
> ===
> RCS file: /var/cvs/llvm/llvm/lib/Target/CBackend/Writer.cpp,v
> retrieving revision 1.294
> diff -t -d -u -p -5 -r1.294 Writer.cpp
> --- lib/Target/CBackend/Writer.cpp 7 Dec 2006 23:41:45 - 1.294
> +++ lib/Target/CBackend/Writer.cpp 10 Dec 2006 23:26:54 -
> @@ -712,10 +717,44 @@ void CWriter::printConstant(Constant *CP
>case Instruction::SetGT: Out << " > "; break;
>case Instruction::SetGE: Out << " >= "; break;
>case Instruction::Shl: Out << " << "; break;
>case Instruction::LShr:
>case Instruction::AShr: Out << " >> "; break;
> + case Instruction::ICmp:
> +switch (CE->getPredicate()) {
> + case ICmpInst::ICMP_EQ: Out << " == "; break;
> + case ICmpInst::ICMP_NE: Out << " != "; break;
> + case ICmpInst::ICMP_SLT:
> + case ICmpInst::ICMP_ULT: Out << " < "; break;
> + case ICmpInst::ICMP_SLE:
> + case ICmpInst::ICMP_ULE: Out << " <= "; break;
> ...
>
>
> This apparently doesn't cast the operands of icmp constant exprs to
> the right sign.
It does, you just didn't see it in the patch because that part didn't
change.
>
>
>
>
>
>
> @@ -1122,10 +1161,65 @@ void CWriter::writeOperandWithCast(Value
> +
> +// generateCompilerSpecificCode - This is where we add conditional
> compilation
> +// directives to cater to specific compilers as need be.
> +//
> +
> // generateCompilerSpecificCode - This is where we add conditional
> compilation
> // directives to cater to specific compilers as need be.
> //
>
>
> ... There ya go again, trying to inflate your LOC count.
Just a blunder.
>
>
>
>
> @@ -1982,10 +2076,49 @@ void CWriter::visitBinaryOperator(Instru
>if (needsCast) {
> Out << "))";
>}
> }
>
>
>
> +void CWriter::visitICmpInst(Instruction &I) {
> + // icmp instruction.
> + assert(isa(I));
> +
>
>
> Drop the isa and later casts, change the argument to visitICmpInst to
> ICmpInst.
Yup. The patch didn't catch up with the visitICmpInst change. This was
actually a bug. It provided an overload of visitICmpInst that would
never be called. Unfortunately there's no -Woverload-nonvirtual
option :)
>
>
>
>
> Index: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> =
[llvm-commits] CVS: llvm/lib/Target/X86/README-SSE.txt
Changes in directory llvm/lib/Target/X86: README-SSE.txt updated: 1.13 -> 1.14 --- Log message: This is done. --- Diffs of the changes: (+0 -5) README-SSE.txt |5 - 1 files changed, 5 deletions(-) Index: llvm/lib/Target/X86/README-SSE.txt diff -u llvm/lib/Target/X86/README-SSE.txt:1.13 llvm/lib/Target/X86/README-SSE.txt:1.14 --- llvm/lib/Target/X86/README-SSE.txt:1.13 Thu Dec 14 13:45:32 2006 +++ llvm/lib/Target/X86/README-SSE.txt Thu Dec 14 23:50:39 2006 @@ -18,11 +18,6 @@ //===-===// -Bitcast to<->from SSE registers should use movd/movq instead of going through -the stack. Testcase here: CodeGen/X86/bitcast.ll - -//===-===// - This testcase should have no SSE instructions in it, and only one load from a constant pool: ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h
Changes in directory llvm/include/llvm/Target:
TargetInstrInfo.h updated: 1.109 -> 1.110
---
Log message:
Silly assertion. Forgot variable_ops instructions can have arbitrary number of
operands.
---
Diffs of the changes: (+4 -2)
TargetInstrInfo.h |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.109
llvm/include/llvm/Target/TargetInstrInfo.h:1.110
--- llvm/include/llvm/Target/TargetInstrInfo.h:1.109Fri Dec 8 12:44:26 2006
+++ llvm/include/llvm/Target/TargetInstrInfo.h Fri Dec 15 00:37:08 2006
@@ -132,8 +132,10 @@
/// it is set. Returns -1 if it is not set.
int getOperandConstraint(unsigned OpNum,
TOI::OperandConstraint Constraint) const {
-assert(OpNum < numOperands && "Invalid operand # of TargetInstrInfo");
-if (OpInfo[OpNum].Constraints & (1 << Constraint)) {
+assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
+ "Invalid operand # of TargetInstrInfo");
+if (OpNum < numOperands &&
+(OpInfo[OpNum].Constraints & (1 << Constraint))) {
unsigned Pos = 16 + Constraint * 4;
return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
}
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[llvm-commits] fix for !__builtin_isunordered(X, Y);
This fixes a bug compiling:
int test2(float X, float Y) {
return !__builtin_isunordered(X, Y);
}
because we checked the wrong 'opcode', we compiled it to the same
code as:
int test1(float X, float Y) {
return __builtin_isunordered(X, Y);
}
Reid/Sheng, please make sure that the corresponding patch makes it
into your llvm-gcc changes, thx.
-Chris
Index: llvm-convert.cpp
===
--- llvm-convert.cpp(revision 121370)
+++ llvm-convert.cpp(working copy)
@@ -2329,7 +2329,7 @@
Result = IsUnord;
// If this is an ORDERED_EXPR, invert the result of the
isunordered call.
-if (Opc == ORDERED_EXPR)
+if (TREE_CODE(exp) == ORDERED_EXPR)
Result = BinaryOperator::createNot(Result, "tmp", CurBB);
}
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[llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.89 -> 1.90
---
Log message:
Minor clean up.
---
Diffs of the changes: (+3 -2)
VirtRegMap.cpp |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.89
llvm/lib/CodeGen/VirtRegMap.cpp:1.90
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.89Thu Dec 14 01:54:05 2006
+++ llvm/lib/CodeGen/VirtRegMap.cpp Fri Dec 15 00:41:01 2006
@@ -573,7 +573,8 @@
// Loop over all of the implicit defs, clearing them from our available
// sets.
-const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
+const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
+const unsigned *ImpDef = TID->ImplicitDefs;
if (ImpDef) {
for ( ; *ImpDef; ++ImpDef) {
PhysRegsUsed[*ImpDef] = true;
@@ -626,7 +627,7 @@
// aren't allowed to modify the reused register. If none of these
cases
// apply, reuse it.
bool CanReuse = true;
-int ti = MI.getInstrDescriptor()->getOperandConstraint(i,
TOI::TIED_TO);
+int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
if (ti != -1 &&
MI.getOperand(ti).isReg() &&
MI.getOperand(ti).getReg() == VirtReg) {
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[llvm-commits] CVS: llvm/test/Regression/CFrontend/2006-12-14-ordered_expr.c
Changes in directory llvm/test/Regression/CFrontend:
2006-12-14-ordered_expr.c added (r1.1)
---
Log message:
New testcase for llvm-gcc bugfix
---
Diffs of the changes: (+7 -0)
2006-12-14-ordered_expr.c |7 +++
1 files changed, 7 insertions(+)
Index: llvm/test/Regression/CFrontend/2006-12-14-ordered_expr.c
diff -c /dev/null llvm/test/Regression/CFrontend/2006-12-14-ordered_expr.c:1.1
*** /dev/null Fri Dec 15 00:49:30 2006
--- llvm/test/Regression/CFrontend/2006-12-14-ordered_expr.cFri Dec 15
00:49:20 2006
***
*** 0
--- 1,7
+ // RUN: %llvmgcc -O3 -S %s -o - | grep llvm.isunordered &&
+ // RUN: %llvmgcc -O3 -S %s -o - | grep xor
+
+ int test2(float X, float Y) {
+ return !__builtin_isunordered(X, Y);
+ }
+
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[llvm-commits] CVS: llvm/test/Regression/Transforms/ScalarRepl/union-fp-int.ll union-packed.ll
Changes in directory llvm/test/Regression/Transforms/ScalarRepl:
union-fp-int.ll updated: 1.2 -> 1.3
union-packed.ll updated: 1.2 -> 1.3
---
Log message:
reenable these
---
Diffs of the changes: (+0 -4)
union-fp-int.ll |2 --
union-packed.ll |2 --
2 files changed, 4 deletions(-)
Index: llvm/test/Regression/Transforms/ScalarRepl/union-fp-int.ll
diff -u llvm/test/Regression/Transforms/ScalarRepl/union-fp-int.ll:1.2
llvm/test/Regression/Transforms/ScalarRepl/union-fp-int.ll:1.3
--- llvm/test/Regression/Transforms/ScalarRepl/union-fp-int.ll:1.2 Wed Dec
13 11:42:40 2006
+++ llvm/test/Regression/Transforms/ScalarRepl/union-fp-int.ll Fri Dec 15
01:32:49 2006
@@ -1,8 +1,6 @@
; RUN: llvm-upgrade < %s | llvm-as | opt -scalarrepl | llvm-dis | not grep
alloca &&
; RUN: llvm-upgrade < %s | llvm-as | opt -scalarrepl | llvm-dis | grep
'bitcast.*float.*int'
-; XFAIL: *
-
int %test(float %X) {
%X_addr = alloca float
store float %X, float* %X_addr
Index: llvm/test/Regression/Transforms/ScalarRepl/union-packed.ll
diff -u llvm/test/Regression/Transforms/ScalarRepl/union-packed.ll:1.2
llvm/test/Regression/Transforms/ScalarRepl/union-packed.ll:1.3
--- llvm/test/Regression/Transforms/ScalarRepl/union-packed.ll:1.2 Wed Dec
13 11:42:40 2006
+++ llvm/test/Regression/Transforms/ScalarRepl/union-packed.ll Fri Dec 15
01:32:49 2006
@@ -1,8 +1,6 @@
; RUN: llvm-upgrade < %s | llvm-as | opt -scalarrepl | llvm-dis | not grep
alloca &&
; RUN: llvm-upgrade < %s | llvm-as | opt -scalarrepl | llvm-dis | grep
'bitcast'
-; XFAIL: *
-
target endian = little
<4 x int> %test(<4 x float> %X) {
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
Changes in directory llvm/lib/Transforms/Scalar:
ScalarReplAggregates.cpp updated: 1.57 -> 1.58
---
Log message:
re-enable a temporarily-reverted patch
---
Diffs of the changes: (+132 -53)
ScalarReplAggregates.cpp | 185 +--
1 files changed, 132 insertions(+), 53 deletions(-)
Index: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
diff -u llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.57
llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.58
--- llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.57Tue Dec 12
20:26:45 2006
+++ llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp Fri Dec 15 01:32:38 2006
@@ -419,39 +419,64 @@
/// types are incompatible, return true, otherwise update Accum and return
/// false.
///
-/// There are two cases we handle here:
-/// 1) An effectively integer union, where the pieces are stored into as
+/// There are three cases we handle here:
+/// 1) An effectively-integer union, where the pieces are stored into as
/// smaller integers (common with byte swap and other idioms).
-/// 2) A union of a vector and its elements. Here we turn element accesses
-/// into insert/extract element operations.
+/// 2) A union of vector types of the same size and potentially its elements.
+/// Here we turn element accesses into insert/extract element operations.
+/// 3) A union of scalar types, such as int/float or int/pointer. Here we
+/// merge together into integers, allowing the xform to work with #1 as
+/// well.
static bool MergeInType(const Type *In, const Type *&Accum,
const TargetData &TD) {
// If this is our first type, just use it.
const PackedType *PTy;
if (Accum == Type::VoidTy || In == Accum) {
Accum = In;
+ } else if (In == Type::VoidTy) {
+// Noop.
} else if (In->isIntegral() && Accum->isIntegral()) { // integer union.
// Otherwise pick whichever type is larger.
if (In->getTypeID() > Accum->getTypeID())
Accum = In;
} else if (isa(In) && isa(Accum)) {
// Pointer unions just stay as one of the pointers.
- } else if ((PTy = dyn_cast(Accum)) &&
- PTy->getElementType() == In) {
-// Accum is a vector, and we are accessing an element: ok.
- } else if ((PTy = dyn_cast(In)) &&
- PTy->getElementType() == Accum) {
-// In is a vector, and accum is an element: ok, remember In.
-Accum = In;
- } else if (isa(In) && Accum->isIntegral()) {
-// Pointer/Integer unions merge together as integers.
-return MergeInType(TD.getIntPtrType(), Accum, TD);
- } else if (isa(Accum) && In->isIntegral()) {
-// Pointer/Integer unions merge together as integers.
-Accum = TD.getIntPtrType();
-return MergeInType(In, Accum, TD);
+ } else if (isa(In) || isa(Accum)) {
+if ((PTy = dyn_cast(Accum)) &&
+PTy->getElementType() == In) {
+ // Accum is a vector, and we are accessing an element: ok.
+} else if ((PTy = dyn_cast(In)) &&
+ PTy->getElementType() == Accum) {
+ // In is a vector, and accum is an element: ok, remember In.
+ Accum = In;
+} else if ((PTy = dyn_cast(In)) && isa(Accum) &&
+ PTy->getBitWidth() == cast(Accum)->getBitWidth()) {
+ // Two vectors of the same size: keep Accum.
+} else {
+ // Cannot insert an short into a <4 x int> or handle
+ // <2 x int> -> <4 x int>
+ return true;
+}
} else {
-return true;
+// Pointer/FP/Integer unions merge together as integers.
+switch (Accum->getTypeID()) {
+case Type::PointerTyID: Accum = TD.getIntPtrType(); break;
+case Type::FloatTyID: Accum = Type::UIntTy; break;
+case Type::DoubleTyID: Accum = Type::ULongTy; break;
+default:
+ assert(Accum->isIntegral() && "Unknown FP type!");
+ break;
+}
+
+switch (In->getTypeID()) {
+case Type::PointerTyID: In = TD.getIntPtrType(); break;
+case Type::FloatTyID: In = Type::UIntTy; break;
+case Type::DoubleTyID: In = Type::ULongTy; break;
+default:
+ assert(In->isIntegral() && "Unknown FP type!");
+ break;
+}
+return MergeInType(In, Accum, TD);
}
return false;
}
@@ -493,8 +518,7 @@
if (MergeInType(SI->getOperand(0)->getType(), UsedType, TD))
return 0;
-} else if (CastInst *CI = dyn_cast(User)) {
- if (!isa(CI->getType())) return 0;
+} else if (BitCastInst *CI = dyn_cast(User)) {
IsNotTrivial = true;
const Type *SubTy = CanConvertToScalar(CI, IsNotTrivial);
if (!SubTy || MergeInType(SubTy, UsedType, TD)) return 0;
@@ -608,24 +632,54 @@
Value *NV = new LoadInst(NewAI, LI->getName(), LI);
if (NV->getType() != LI->getType()) {
if (const PackedType *PTy = dyn_cast(NV->getType())) {
- // Must be an element access.
- unsigned Elt = Offset/(TD.getTypeSize(PTy->getElementType())*8);
- NV = new Extrac
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.442 -> 1.443
---
Log message:
silence a bogus warning
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.442
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.443
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.442 Thu Dec 14 20:59:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Dec 15 01:36:19 2006
@@ -3538,7 +3538,7 @@
if (VT == MVT::f32 || VT == MVT::f64) {
// Expand into one or more soft-fp libcall(s).
const char *FnName1 = NULL, *FnName2 = NULL;
- ISD::CondCode CC1, CC2;
+ ISD::CondCode CC1, CC2 = ISD::SETCC_INVALID;
switch (cast(CC)->get()) {
case ISD::SETEQ:
case ISD::SETOEQ:
___
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Re: [llvm-commits] SETCC Patches: #3
On Dec 14, 2006, at 7:48 PM, Reid Spencer wrote: >> >> The interpreter is broken: all unsigned comparisons with signed >> operands will hit the unhandled type case. > > Yup. Fixed the macro to take two arguments. The first is to match the > type of the operand. > The second is the type to use to pull the values out of the > GenericValue > union, effecitvely doing the type cast by field selection. Ok >> --- lib/Target/CBackend/Writer.cpp 7 Dec 2006 23:41:45 - 1.294 >> +++ lib/Target/CBackend/Writer.cpp 10 Dec 2006 23:26:54 - >> @@ -712,10 +717,44 @@ void CWriter::printConstant(Constant *CP >>case Instruction::SetGT: Out << " > "; break; >> >> This apparently doesn't cast the operands of icmp constant exprs to >> the right sign. > > It does, you just didn't see it in the patch because that part didn't > change. Ok. >> ... There ya go again, trying to inflate your LOC count. > > Just a blunder. Uh huh, sure... right... :) >> >> This (when it becomes active) isn't sufficient. When >> FiniteOnlyFPMath >> is enabled, all the 'o's and 'u's should get dropped. > > Right, missed that. One question: > > For the FCMP_ORD and FCMP_UNO cases, what should the FininteOnlyFPMath > condition be? > There isn't really a mapping for it, right? Just make it the same > as the > regular case? Yeah, please just make them do the 'correct' thing, even though they strictly don't have to. I'm still behind in patch review, I'll try to respond to your other email tomorrow, -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
