[llvm-commits] CVS: llvm/lib/Target/TargetMachine.cpp
Changes in directory llvm/lib/Target: TargetMachine.cpp updated: 1.50 -> 1.51 --- Log message: Tidy up options. --- Diffs of the changes: (+9 -9) TargetMachine.cpp | 18 +- 1 files changed, 9 insertions(+), 9 deletions(-) Index: llvm/lib/Target/TargetMachine.cpp diff -u llvm/lib/Target/TargetMachine.cpp:1.50 llvm/lib/Target/TargetMachine.cpp:1.51 --- llvm/lib/Target/TargetMachine.cpp:1.50 Wed Jul 26 16:12:04 2006 +++ llvm/lib/Target/TargetMachine.cpp Tue Aug 29 10:13:10 2006 @@ -63,13 +63,13 @@ cl::init(Reloc::Default), cl::values( clEnumValN(Reloc::Default, "default", - "Target default relocation model"), + " Target default relocation model"), clEnumValN(Reloc::Static, "static", - "Non-relocatable code"), + " Non-relocatable code"), clEnumValN(Reloc::PIC_, "pic", - "Fully relocatable, position independent code"), + " Fully relocatable, position independent code"), clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", - "Relocatable external references, non-relocatable code"), + " Relocatable external references, non-relocatable code"), clEnumValEnd)); cl::opt DefCodeModel( @@ -79,15 +79,15 @@ cl::init(CodeModel::Default), cl::values( clEnumValN(CodeModel::Default, "default", - "Target default code model"), + " Target default code model"), clEnumValN(CodeModel::Small, "small", - "Small code model"), + " Small code model"), clEnumValN(CodeModel::Kernel, "kernel", - "Kernel code model"), + " Kernel code model"), clEnumValN(CodeModel::Medium, "medium", - "Medium code model"), + " Medium code model"), clEnumValN(CodeModel::Large, "large", - "Large code model"), + " Large code model"), clEnumValEnd)); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.71 -> 1.72
---
Log message:
Handle callee saved registers in dwarf frame info (lead up to exception
handling.)
---
Diffs of the changes: (+35 -9)
DwarfWriter.cpp | 44 +++-
1 files changed, 35 insertions(+), 9 deletions(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.71
llvm/lib/CodeGen/DwarfWriter.cpp:1.72
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.71 Fri Aug 25 14:39:52 2006
+++ llvm/lib/CodeGen/DwarfWriter.cppTue Aug 29 11:24:26 2006
@@ -35,7 +35,7 @@
static cl::opt
DwarfVerbose("dwarf-verbose", cl::Hidden,
-cl::desc("Add comments to Dwarf directives."));
+ cl::desc("Add comments to Dwarf directives."));
namespace llvm {
@@ -1946,7 +1946,7 @@
// Advance row if new location.
if (BaseLabel && LabelID && BaseLabelID != LabelID) {
- EmitULEB128Bytes(DW_CFA_advance_loc4);
+ EmitInt8(DW_CFA_advance_loc4);
EOL("DW_CFA_advance_loc4");
EmitDifference("loc", LabelID, BaseLabel, BaseLabelID);
EOL("");
@@ -1955,30 +1955,56 @@
BaseLabel = "loc";
}
+int stackGrowth =
+Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
+ TargetFrameInfo::StackGrowsUp ?
+AddressSize : -AddressSize;
+
// If advancing cfa.
if (Dst.isRegister() && Dst.getRegister() == MachineLocation::VirtualFP) {
if (!Src.isRegister()) {
if (Src.getRegister() == MachineLocation::VirtualFP) {
- EmitULEB128Bytes(DW_CFA_def_cfa_offset);
+ EmitInt8(DW_CFA_def_cfa_offset);
EOL("DW_CFA_def_cfa_offset");
} else {
- EmitULEB128Bytes(DW_CFA_def_cfa);
+ EmitInt8(DW_CFA_def_cfa);
EOL("DW_CFA_def_cfa");
EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister()));
EOL("Register");
}
-int stackGrowth =
-Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
- TargetFrameInfo::StackGrowsUp ?
-AddressSize : -AddressSize;
+int Offset = Src.getOffset() / stackGrowth;
-EmitULEB128Bytes(Src.getOffset() / stackGrowth);
+EmitULEB128Bytes(Offset);
EOL("Offset");
} else {
+assert(0 && "Machine move no supported yet.");
}
} else {
+ unsigned Reg = RI->getDwarfRegNum(Src.getRegister());
+ int Offset = Dst.getOffset() / stackGrowth;
+
+ if (Offset < 0) {
+EmitInt8(DW_CFA_offset_extended_sf);
+EOL("DW_CFA_offset_extended_sf");
+EmitULEB128Bytes(Reg);
+EOL("Reg");
+EmitSLEB128Bytes(Offset);
+EOL("Offset");
+ } else if (Reg < 64) {
+EmitInt8(DW_CFA_offset + Reg);
+EOL("DW_CFA_offset + Reg");
+EmitULEB128Bytes(Offset);
+EOL("Offset");
+ } else {
+EmitInt8(DW_CFA_offset_extended);
+EOL("DW_CFA_offset_extended");
+EmitULEB128Bytes(Reg);
+EOL("Reg");
+EmitULEB128Bytes(Offset);
+EOL("Offset");
+ }
}
}
}
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.74 -> 1.75
---
Log message:
Handle callee saved registers in dwarf frame info (lead up to exception
handling.)
---
Diffs of the changes: (+13 -6)
PPCRegisterInfo.cpp | 19 +--
1 files changed, 13 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.74
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.75
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.74Fri Aug 25 14:40:59 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Aug 29 11:24:26 2006
@@ -668,15 +668,22 @@
std::vector &Moves = DebugInfo->getFrameMoves();
unsigned LabelID = DebugInfo->NextLabelID();
-// Show update of SP.
-MachineLocation Dst(MachineLocation::VirtualFP);
-MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
-Moves.push_back(new MachineMove(LabelID, Dst, Src));
-
// Mark effective beginning of when frame pointer becomes valid.
BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
-
+// Show update of SP.
+MachineLocation SPDst(MachineLocation::VirtualFP);
+MachineLocation SPSrc(MachineLocation::VirtualFP, NegNumbytes);
+Moves.push_back(new MachineMove(LabelID, SPDst, SPSrc));
+
+// Add callee saved registers to move list.
+const std::vector &CSI = MFI->getCalleeSavedInfo();
+for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
+ MachineLocation CSDst(MachineLocation::VirtualFP,
+MFI->getObjectOffset(CSI[I].getFrameIdx()));
+ MachineLocation CSSrc(CSI[I].getReg());
+ Moves.push_back(new MachineMove(LabelID, CSDst, CSSrc));
+}
}
// If there is a frame pointer, copy R1 (SP) into R31 (FP)
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[llvm-commits] CVS: llvm/utils/NewNightlyTest.pl NightlyTest.pl
Changes in directory llvm/utils:
NewNightlyTest.pl updated: 1.57 -> 1.58
NightlyTest.pl updated: 1.112 -> 1.113
---
Log message:
Issue cvs co with -P option to prune empty directories. Remove the unnecessary
update stage.
---
Diffs of the changes: (+2 -11)
NewNightlyTest.pl |6 +-
NightlyTest.pl|7 +--
2 files changed, 2 insertions(+), 11 deletions(-)
Index: llvm/utils/NewNightlyTest.pl
diff -u llvm/utils/NewNightlyTest.pl:1.57 llvm/utils/NewNightlyTest.pl:1.58
--- llvm/utils/NewNightlyTest.pl:1.57 Tue Aug 22 13:11:19 2006
+++ llvm/utils/NewNightlyTest.plTue Aug 29 13:01:18 2006
@@ -488,7 +488,7 @@
# Use compression if going over ssh.
$CVSOPT = "-z3"
if $CVSRootDir =~ /^:ext:/;
-my $CVSCMD = "$NICE cvs $CVSOPT -d $CVSRootDir co $CVSCOOPT";
+my $CVSCMD = "$NICE cvs $CVSOPT -d $CVSRootDir co -P $CVSCOOPT";
if (!$NOCHECKOUT) {
if ( $VERBOSE ) {
print "CHECKOUT STAGE:\n";
@@ -500,10 +500,6 @@
ChangeDir( $BuildDir , "CVS Checkout directory") ;
}
ChangeDir( "llvm" , "llvm source directory") ;
-if (!$NOCHECKOUT) {
- if ( $VERBOSE ) { print "UPDATE STAGE\n"; }
- system "$NICE cvs update -PdRA >> $CVSLog 2>&1" ;
-}
##
#
Index: llvm/utils/NightlyTest.pl
diff -u llvm/utils/NightlyTest.pl:1.112 llvm/utils/NightlyTest.pl:1.113
--- llvm/utils/NightlyTest.pl:1.112 Wed Jun 28 19:54:37 2006
+++ llvm/utils/NightlyTest.pl Tue Aug 29 13:01:18 2006
@@ -409,7 +409,7 @@
my $CVSOPT = "";
# Use compression if going over ssh.
$CVSOPT = "-z3" if $CVSRootDir =~ /^:ext:/;
-my $CVSCMD = "$NICE cvs $CVSOPT -d $CVSRootDir co $CVSCOOPT";
+my $CVSCMD = "$NICE cvs $CVSOPT -d $CVSRootDir co -P $CVSCOOPT";
if (!$NOCHECKOUT) {
if ( $VERBOSE ) { print "CHECKOUT STAGE\n"; }
system "( time -p $CVSCMD llvm; cd llvm/projects ; " .
@@ -419,11 +419,6 @@
ChangeDir( "llvm" , "llvm source directory") ;
-if (!$NOCHECKOUT) {
- if ( $VERBOSE ) { print "UPDATE STAGE\n"; }
- system "$NICE cvs update -PdRA >> $CVSLog 2>&1" ;
-}
-
if ( $Template eq "" ) {
$Template = "$BuildDir/llvm/utils/NightlyTestTemplate.html";
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86.h X86ISelDAGToDAG.cpp X86TargetMachine.cpp
Changes in directory llvm/lib/Target/X86:
X86.h updated: 1.46 -> 1.47
X86ISelDAGToDAG.cpp updated: 1.100 -> 1.101
X86TargetMachine.cpp updated: 1.121 -> 1.122
---
Log message:
- Enable x86 isel preprocessing by default unless -fast is specified.
- Also disable isel load folding if -fast.
---
Diffs of the changes: (+13 -8)
X86.h|2 +-
X86ISelDAGToDAG.cpp | 15 ++-
X86TargetMachine.cpp |4 ++--
3 files changed, 13 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86.h
diff -u llvm/lib/Target/X86/X86.h:1.46 llvm/lib/Target/X86/X86.h:1.47
--- llvm/lib/Target/X86/X86.h:1.46 Tue Jul 25 15:40:54 2006
+++ llvm/lib/Target/X86/X86.h Tue Aug 29 13:28:33 2006
@@ -28,7 +28,7 @@
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
/// createX86FloatingPointStackifierPass - This function returns a pass which
/// converts floating point register references and pseudo instructions into
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.100
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.101
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.100 Tue Aug 29 01:44:17 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Aug 29 13:28:33 2006
@@ -92,6 +92,10 @@
/// register should set this to true.
bool ContainsFPCode;
+/// FastISel - Enable fast(er) instruction selection.
+///
+bool FastISel;
+
/// X86Lowering - This object fully describes how to lower LLVM code to an
/// X86-specific SelectionDAG.
X86TargetLowering X86Lowering;
@@ -103,8 +107,9 @@
unsigned GlobalBaseReg;
public:
-X86DAGToDAGISel(X86TargetMachine &TM)
+X86DAGToDAGISel(X86TargetMachine &TM, bool fast)
: SelectionDAGISel(X86Lowering),
+ContainsFPCode(false), FastISel(fast),
X86Lowering(*TM.getTargetLowering()),
Subtarget(&TM.getSubtarget()) {}
@@ -237,7 +242,7 @@
// /[X]
// | ^
// [U]|
- return !isNonImmUse(U, N);
+ return !FastISel && !isNonImmUse(U, N);
}
/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain
operand
@@ -370,7 +375,7 @@
DEBUG(BB->dump());
MachineFunction::iterator FirstMBB = BB;
- if (X86ISelPreproc)
+ if (!FastISel)
InstructionSelectPreprocess(DAG);
// Codegen the basic block.
@@ -1071,6 +1076,6 @@
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
-FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM) {
- return new X86DAGToDAGISel(TM);
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
+ return new X86DAGToDAGISel(TM, Fast);
}
Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.121
llvm/lib/Target/X86/X86TargetMachine.cpp:1.122
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.121 Wed Aug 23 16:08:52 2006
+++ llvm/lib/Target/X86/X86TargetMachine.cppTue Aug 29 13:28:33 2006
@@ -103,7 +103,7 @@
PM.add(createUnreachableBlockEliminationPass());
// Install an instruction selector.
- PM.add(createX86ISelDag(*this));
+ PM.add(createX86ISelDag(*this, Fast));
// Print the instruction selected machine code...
if (PrintMachineCode)
@@ -168,7 +168,7 @@
PM.add(createUnreachableBlockEliminationPass());
// Install an instruction selector.
- PM.add(createX86ISelDag(TM));
+ PM.add(createX86ISelDag(TM, false));
// Print the instruction selected machine code...
if (PrintMachineCode)
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.101 -> 1.102 --- Log message: Don't performance load/op/store transformation if op produces a floating point or vector result. X86 does not have load/mod/store variants of those instructions. --- Diffs of the changes: (+3 -1) X86ISelDAGToDAG.cpp |4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.101 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.102 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.101 Tue Aug 29 13:28:33 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Aug 29 13:37:37 2006 @@ -312,7 +312,9 @@ SDOperand N1 = I->getOperand(1); SDOperand N2 = I->getOperand(2); -if (!N1.hasOneUse()) +if (MVT::isFloatingPoint(N1.getValueType()) && +MVT::isVector(N1.getValueType()) && +!N1.hasOneUse()) continue; bool RModW = false; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/store_op_load_fold2.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
store_op_load_fold2.ll updated: 1.2 -> 1.3
---
Log message:
Undo xfail.
---
Diffs of the changes: (+1 -5)
store_op_load_fold2.ll |6 +-
1 files changed, 1 insertion(+), 5 deletions(-)
Index: llvm/test/Regression/CodeGen/X86/store_op_load_fold2.ll
diff -u llvm/test/Regression/CodeGen/X86/store_op_load_fold2.ll:1.2
llvm/test/Regression/CodeGen/X86/store_op_load_fold2.ll:1.3
--- llvm/test/Regression/CodeGen/X86/store_op_load_fold2.ll:1.2 Mon Jul 24
02:37:33 2006
+++ llvm/test/Regression/CodeGen/X86/store_op_load_fold2.ll Tue Aug 29
13:49:41 2006
@@ -1,8 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep 'and DWORD
PTR' | wc -l | grep 1
-;
-; FIXME: The number of (store (and (load ..) ..) ..) really should be 2. But
the current hack
-; only allow one of the folding to happen.
-; XFAIL: *
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep 'and DWORD
PTR' | wc -l | grep 2
%struct.Macroblock = type { int, int, int, int, int, [8 x int],
%struct.Macroblock*, %struct.Macroblock*, int, [2 x [4 x [4 x [2 x int, [16
x sbyte], [16 x sbyte], int, long, [4 x int], [4 x int], long, int, int, int,
int, int, int, int, int, int, int, int, int, int, int, int, short, double, int,
int, int, int, int, int, int, int, int }
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