[llvm-commits] CVS: llvm/lib/Transforms/Utils/LCSSA.cpp
Changes in directory llvm/lib/Transforms/Utils:
LCSSA.cpp updated: 1.23 -> 1.24
---
Log message:
Add a fix for an issue where LCSSA would fail to insert undef's in some corner
cases. Ideally, this issue will go away in the future as LCSSA gets smarter
about which Phi nodes it inserts.
---
Diffs of the changes: (+21 -14)
LCSSA.cpp | 35 +--
1 files changed, 21 insertions(+), 14 deletions(-)
Index: llvm/lib/Transforms/Utils/LCSSA.cpp
diff -u llvm/lib/Transforms/Utils/LCSSA.cpp:1.23
llvm/lib/Transforms/Utils/LCSSA.cpp:1.24
--- llvm/lib/Transforms/Utils/LCSSA.cpp:1.23Tue Jun 13 20:13:57 2006
+++ llvm/lib/Transforms/Utils/LCSSA.cpp Sun Jul 9 03:14:06 2006
@@ -28,6 +28,7 @@
//===--===//
#include "llvm/Transforms/Scalar.h"
+#include "llvm/Constants.h"
#include "llvm/Pass.h"
#include "llvm/Function.h"
#include "llvm/Instructions.h"
@@ -73,12 +74,12 @@
}
private:
SetVector getLoopValuesUsedOutsideLoop(Loop *L);
-Instruction *getValueDominatingBlock(BasicBlock *BB,
- std::map& PotDoms)
{
+Value *getValueDominatingBlock(BasicBlock *BB,
+ std::map& PotDoms) {
return getValueDominatingDTNode(DT->getNode(BB), PotDoms);
}
-Instruction *getValueDominatingDTNode(DominatorTree::Node *Node,
- std::map&
PotDoms);
+Value *getValueDominatingDTNode(DominatorTree::Node *Node,
+ std::map& PotDoms);
/// inLoop - returns true if the given block is within the current loop
const bool inLoop(BasicBlock* B) {
@@ -149,7 +150,7 @@
{
++NumLCSSA; // We are applying the transformation
- std::map Phis;
+ std::map Phis;
// Add the base instruction to the Phis list. This makes tracking down
// the dominating values easier when we're filling in Phi nodes. This will
@@ -161,7 +162,7 @@
for (std::vector::const_iterator BBI = exitBlocks.begin(),
BBE = exitBlocks.end(); BBI != BBE; ++BBI) {
-Instruction*& phi = Phis[*BBI];
+Value*& phi = Phis[*BBI];
if (phi == 0 &&
DT->getNode(Instr->getParent())->dominates(DT->getNode(*BBI))) {
phi = new PHINode(Instr->getType(), Instr->getName()+".lcssa",
@@ -191,7 +192,7 @@
for (DominanceFrontier::DomSetType::const_iterator P = S.begin(),
PE = S.end(); P != PE; ++P) {
if (DT->getNode(Instr->getParent())->dominates(DT->getNode(*P))) {
- Instruction *&Phi = Phis[*P];
+ Value *&Phi = Phis[*P];
if (Phi == 0) {
// Still doesn't have operands...
Phi = new PHINode(Instr->getType(), Instr->getName()+".lcssa",
@@ -206,12 +207,11 @@
// Fill in all Phis we've inserted that need their incoming values filled in.
for (std::vector::iterator IVI = needIncomingValues.begin(),
- IVE = needIncomingValues.end(); IVI != IVE; ++IVI) {
+ IVE = needIncomingValues.end(); IVI != IVE; ++IVI)
for (pred_iterator PI = pred_begin((*IVI)->getParent()),
E = pred_end((*IVI)->getParent()); PI != E; ++PI)
(*IVI)->addIncoming(getValueDominatingBlock(*PI, Phis),
*PI);
- }
// Find all uses of the affected value, and replace them with the
// appropriate Phi.
@@ -235,7 +235,7 @@
if (PHINode* phi = dyn_cast(*II)) {
for (unsigned int i = 0; i < phi->getNumIncomingValues(); ++i) {
if (phi->getIncomingValue(i) == Instr) {
- Instruction* dominator =
+ Value* dominator =
getValueDominatingBlock(phi->getIncomingBlock(i),
Phis);
phi->setIncomingValue(i, dominator);
}
@@ -279,10 +279,17 @@
/// getValueDominatingBlock - Return the value within the potential dominators
/// map that dominates the given block.
-Instruction *LCSSA::getValueDominatingDTNode(DominatorTree::Node *Node,
- std::map& PotDoms) {
- assert(Node != 0 && "Didn't find dom value?");
- Instruction *&CacheSlot = PotDoms[Node->getBlock()];
+Value *LCSSA::getValueDominatingDTNode(DominatorTree::Node *Node,
+ std::map& PotDoms) {
+ // FIXME: The following insertion should be in place rather than the if
+ // statement. Currently, this is due to the fact that LCSSA isn't smart
+ // enough to avoid inserting IDF Phis that don't dominate any uses. In some
+ // of those cases, it could ask us to provide a dominating value for a block
+ // that has none, so we need to return undef.
+ //assert(Node != 0 && "Didn't find dom value?");
+ if (Node == 0) return UndefValue::get(PotDoms.begin()->second->getType());
+
+ Value *&CacheSlot = PotDoms[Node->getBlock()];
if (CacheSlot) return CacheSlot;
// Otherwise, return the value of the idom and remember this for next time.
[llvm-commits] CVS: llvm/test/Regression/Transforms/LCSSA/2006-07-09-NoDominator.ll
Changes in directory llvm/test/Regression/Transforms/LCSSA:
2006-07-09-NoDominator.ll added (r1.1)
---
Log message:
Add a test for the LCSSA issue I just fixed.
---
Diffs of the changes: (+31 -0)
2006-07-09-NoDominator.ll | 31 +++
1 files changed, 31 insertions(+)
Index: llvm/test/Regression/Transforms/LCSSA/2006-07-09-NoDominator.ll
diff -c /dev/null
llvm/test/Regression/Transforms/LCSSA/2006-07-09-NoDominator.ll:1.1
*** /dev/null Sun Jul 9 03:17:40 2006
--- llvm/test/Regression/Transforms/LCSSA/2006-07-09-NoDominator.ll Sun Jul
9 03:17:30 2006
***
*** 0
--- 1,31
+ ; RUN: llvm-as < %s | opt -lcssa
+
+ %struct.SetJmpMapEntry = type { sbyte*, uint, %struct.SetJmpMapEntry* }
+
+ implementation ; Functions:
+
+ void %__llvm_sjljeh_try_catching_longjmp_exception() {
+ entry:
+ br label %loopentry
+
+ loopentry:; preds = %endif, %entry
+ %SJE.0 = phi %struct.SetJmpMapEntry* [ null, %entry ], [ %tmp.25,
%endif ] ; <%struct.SetJmpMapEntry*> [#uses=1]
+ br bool false, label %no_exit, label %loopexit
+
+ no_exit: ; preds = %loopentry
+ br bool false, label %then, label %endif
+
+ then: ; preds = %no_exit
+ %tmp.21 = getelementptr %struct.SetJmpMapEntry* %SJE.0, int 0, uint 1
; [#uses=0]
+ br label %return
+
+ endif:; preds = %after_ret.0, %no_exit
+ %tmp.25 = load %struct.SetJmpMapEntry** null;
<%struct.SetJmpMapEntry*> [#uses=1]
+ br label %loopentry
+
+ loopexit: ; preds = %loopentry
+ br label %return
+
+ return: ; preds = %after_ret.1, %loopexit, %then
+ ret void
+ }
___
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[llvm-commits] CVS: llvm/lib/Transforms/Utils/LCSSA.cpp
Changes in directory llvm/lib/Transforms/Utils:
LCSSA.cpp updated: 1.24 -> 1.25
---
Log message:
Fix typo in the comment.
---
Diffs of the changes: (+1 -1)
LCSSA.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Transforms/Utils/LCSSA.cpp
diff -u llvm/lib/Transforms/Utils/LCSSA.cpp:1.24
llvm/lib/Transforms/Utils/LCSSA.cpp:1.25
--- llvm/lib/Transforms/Utils/LCSSA.cpp:1.24Sun Jul 9 03:14:06 2006
+++ llvm/lib/Transforms/Utils/LCSSA.cpp Sun Jul 9 16:35:40 2006
@@ -281,7 +281,7 @@
/// map that dominates the given block.
Value *LCSSA::getValueDominatingDTNode(DominatorTree::Node *Node,
std::map& PotDoms) {
- // FIXME: The following insertion should be in place rather than the if
+ // FIXME: The following assertion should be in place rather than the if
// statement. Currently, this is due to the fact that LCSSA isn't smart
// enough to avoid inserting IDF Phis that don't dominate any uses. In some
// of those cases, it could ask us to provide a dominating value for a block
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.cpp ARMInstrInfo.h ARMInstrInfo.td ARMRegisterInfo.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.13 -> 1.14
ARMInstrInfo.cpp updated: 1.3 -> 1.4
ARMInstrInfo.h updated: 1.1 -> 1.2
ARMInstrInfo.td updated: 1.5 -> 1.6
ARMRegisterInfo.cpp updated: 1.5 -> 1.6
---
Log message:
create the raddr addressing mode that matches any register and the frame index
use raddr for the ldr instruction. This removes a dummy mov from the assembly
output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
---
Diffs of the changes: (+14 -51)
ARMISelDAGToDAG.cpp | 21 +
ARMInstrInfo.cpp| 22 --
ARMInstrInfo.h | 14 --
ARMInstrInfo.td |6 --
ARMRegisterInfo.cpp |2 +-
5 files changed, 14 insertions(+), 51 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.13
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.14
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.13Tue Jun 27 16:52:45 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Sun Jul 9 20:41:35 2006
@@ -95,8 +95,7 @@
// If the argument is actually used, emit a load from the right stack
// slot.
if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
- //hack
- unsigned ArgOffset = 0;
+ unsigned ArgOffset = (ArgNo - num_regs) * 4;
MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
@@ -165,6 +164,7 @@
void Select(SDOperand &Result, SDOperand Op);
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
+ bool SelectAddrReg(SDOperand N, SDOperand &Base);
// Include the pieces autogenerated from the target description.
#include "ARMGenDAGISel.inc"
@@ -183,12 +183,13 @@
ScheduleAndEmitDAG(DAG);
}
-static void SelectFrameIndex(SelectionDAG *CurDAG, SDOperand &Result, SDNode
*N, SDOperand Op) {
- int FI = cast(N)->getIndex();
-
- SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
-
- Result = CurDAG->SelectNodeTo(N, ARM::movri, Op.getValueType(), TFI);
+bool ARMDAGToDAGISel::SelectAddrReg(SDOperand N, SDOperand &Base) {
+ if (FrameIndexSDNode *FI = dyn_cast(N)) {
+Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
+ }
+ else
+Base = N;
+ return true; //any address fits in a register
}
void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
@@ -198,10 +199,6 @@
default:
SelectCode(Result, Op);
break;
-
- case ISD::FrameIndex:
-SelectFrameIndex(CurDAG, Result, N, Op);
-break;
}
}
Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.3
llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.4
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.3Tue Jun 27 16:52:45 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.cppSun Jul 9 20:41:35 2006
@@ -41,25 +41,3 @@
return true;
}
}
-
-/// isLoadFromStackSlot - If the specified machine instruction is a direct
-/// load from a stack slot, return the virtual or physical register number of
-/// the destination along with the FrameIndex of the loaded stack slot. If
-/// not, return 0. This predicate must return 0 if the instruction has
-/// any side effects other than loading from the stack slot.
-unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
- int &FrameIndex) const {
- assert(0 && "not implemented");
- return 0;
-}
-
-/// isStoreToStackSlot - If the specified machine instruction is a direct
-/// store to a stack slot, return the virtual or physical register number of
-/// the source reg along with the FrameIndex of the loaded stack slot. If
-/// not, return 0. This predicate must return 0 if the instruction has
-/// any side effects other than storing to the stack slot.
-unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI,
-int &FrameIndex) const {
- assert(0 && "not implemented");
- return 0;
-}
Index: llvm/lib/Target/ARM/ARMInstrInfo.h
diff -u llvm/lib/Target/ARM/ARMInstrInfo.h:1.1
llvm/lib/Target/ARM/ARMInstrInfo.h:1.2
--- llvm/lib/Target/ARM/ARMInstrInfo.h:1.1 Sun May 14 17:18:28 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.h Sun Jul 9 20:41:35 2006
@@ -36,20 +36,6 @@
///
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const;
-
- /// isLoadFromStackSlot - If the specified machine instruction is a direct
- /// load from a stack slot, return the virtual or physical register number of
- /// the destination along with the FrameIndex of the loaded stack slot. If
- /// not, return 0. This predicate must return 0 if the instruction has
- /// any side effects other than loading from the stack slot.
- virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex)
const;
-
- /// isStoreToStackSlot - If the specified machine instruction is a direct
- /// store to a
