[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGRRList.cpp updated: 1.4 -> 1.5
---
Log message:
Turn on -sched-commute-nodes by default.
---
Diffs of the changes: (+2 -7)
ScheduleDAGRRList.cpp |9 ++---
1 files changed, 2 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.4
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.5
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.4 Sat May 13
03:22:24 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu May 25 03:37:31 2006
@@ -31,10 +31,6 @@
using namespace llvm;
namespace {
- cl::opt SchedCommuteNodes("sched-commute-nodes", cl::Hidden);
-}
-
-namespace {
//===--===//
/// ScheduleDAGRRList - The actual register reduction list scheduler
/// implementation. This supports both top-down and bottom-up scheduling.
@@ -100,8 +96,7 @@
AvailableQueue->releaseState();
- if (SchedCommuteNodes)
-CommuteNodesToReducePressure();
+ CommuteNodesToReducePressure();
DEBUG(std::cerr << "*** Final schedule ***\n");
DEBUG(dumpSchedule());
@@ -685,7 +680,7 @@
SUnit *SuccSU = I->first;
if (SuccSU != SU &&
(!canClobber(SuccSU, DUSU) ||
- (SchedCommuteNodes && !SU->isCommutable &&
SuccSU->isCommutable))){
+ (!SU->isCommutable && SuccSU->isCommutable))){
if (SuccSU->Depth == SU->Depth && !isReachable(SuccSU, SU)) {
DEBUG(std::cerr << "Adding an edge from SU # " << SU->NodeNum
<< " to SU #" << SuccSU->NodeNum << "\n");
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.212 -> 1.213 --- Log message: Set x86 llcbeta to -sched=list-tdrr --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.212 llvm-test/Makefile.programs:1.213 --- llvm-test/Makefile.programs:1.212 Thu May 11 20:58:52 2006 +++ llvm-test/Makefile.programs Thu May 25 03:38:21 2006 @@ -197,7 +197,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -sched-commute-nodes +LLCBETAOPTION := -sched=list-tdrr endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-05-11-InstrSched.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
2006-05-11-InstrSched.ll updated: 1.1 -> 1.2
---
Log message:
-sched-commute-nodes is now on by default.
---
Diffs of the changes: (+1 -2)
2006-05-11-InstrSched.ll |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/test/Regression/CodeGen/X86/2006-05-11-InstrSched.ll
diff -u llvm/test/Regression/CodeGen/X86/2006-05-11-InstrSched.ll:1.1
llvm/test/Regression/CodeGen/X86/2006-05-11-InstrSched.ll:1.2
--- llvm/test/Regression/CodeGen/X86/2006-05-11-InstrSched.ll:1.1 Thu May
11 20:59:17 2006
+++ llvm/test/Regression/CodeGen/X86/2006-05-11-InstrSched.ll Thu May 25
03:39:25 2006
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -sched-commute-nodes &&
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -sched-commute-nodes -stats
2>&1 | grep 'asm-printer' | grep 39
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats 2>&1 | grep
'asm-printer' | grep 39
void %foo(int* %mc, int* %bp, int* %ms, int* %xmb, int* %mpp, int* %tpmm, int*
%ip, int* %tpim, int* %dpp, int* %tpdm, int* %bpi, int %M) {
entry:
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/
Changes in directory llvm/test/Regression/CodeGen/ARM: --- Log message: Directory /var/cvs/llvm/llvm/test/Regression/CodeGen/ARM added to the repository --- Diffs of the changes: (+0 -0) 0 files changed ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/dg.exp ret0.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
dg.exp added (r1.1)
ret0.ll added (r1.1)
---
Log message:
create test/Regression/CodeGen/ARM/ and add a minimal test to it
---
Diffs of the changes: (+7 -0)
dg.exp |3 +++
ret0.ll |4
2 files changed, 7 insertions(+)
Index: llvm/test/Regression/CodeGen/ARM/dg.exp
diff -c /dev/null llvm/test/Regression/CodeGen/ARM/dg.exp:1.1
*** /dev/null Thu May 25 05:49:29 2006
--- llvm/test/Regression/CodeGen/ARM/dg.exp Thu May 25 05:49:19 2006
***
*** 0
--- 1,3
+ load_lib llvm-dg.exp
+
+ llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]]
$objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext
$llvmgcc_version
Index: llvm/test/Regression/CodeGen/ARM/ret0.ll
diff -c /dev/null llvm/test/Regression/CodeGen/ARM/ret0.ll:1.1
*** /dev/null Thu May 25 05:49:32 2006
--- llvm/test/Regression/CodeGen/ARM/ret0.llThu May 25 05:49:19 2006
***
*** 0
--- 1,4
+ ; RUN: llvm-as < %s | llc -march=arm
+ int %test() {
+ ret int 0
+ }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.7 -> 1.8
---
Log message:
port the ARM backend to use ISD::CALL instead of LowerCallTo
---
Diffs of the changes: (+3 -12)
ARMISelDAGToDAG.cpp | 15 +++
1 files changed, 3 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.7
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.8
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.7 Wed May 24 19:24:28 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu May 25 06:00:18 2006
@@ -40,13 +40,6 @@
public:
ARMTargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
-
-virtual std::pair
- LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
- unsigned CC,
- bool isTailCall, SDOperand Callee, ArgListTy &Args,
- SelectionDAG &DAG);
-
};
}
@@ -56,11 +49,7 @@
setOperationAction(ISD::RET, MVT::Other, Custom);
}
-std::pair
-ARMTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
- bool isVarArg, unsigned CC,
- bool isTailCall, SDOperand Callee,
- ArgListTy &Args, SelectionDAG &DAG) {
+static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
assert(0 && "Not implemented");
abort();
}
@@ -127,6 +116,8 @@
abort();
case ISD::FORMAL_ARGUMENTS:
return LowerFORMAL_ARGUMENTS(Op, DAG);
+ case ISD::CALL:
+return LowerCALL(Op, DAG);
case ISD::RET:
return LowerRET(Op, DAG);
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.2 -> 1.3
---
Log message:
implement initial version of ARMAsmPrinter::printOperand
---
Diffs of the changes: (+31 -1)
ARMAsmPrinter.cpp | 32 +++-
1 files changed, 31 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.2
llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.3
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.2 Mon May 22 21:48:20 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp Thu May 25 07:57:06 2006
@@ -133,7 +133,37 @@
}
void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
- assert(0 && "not implemented");
+ const MachineOperand &MO = MI->getOperand (opNum);
+ const MRegisterInfo &RI = *TM.getRegisterInfo();
+ switch (MO.getType()) {
+ case MachineOperand::MO_Register:
+if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
+ O << LowercaseString (RI.get(MO.getReg()).Name);
+else
+ assert(0 && "not implemented");
+break;
+ case MachineOperand::MO_Immediate:
+O << "#" << (int)MO.getImmedValue();
+break;
+ case MachineOperand::MO_MachineBasicBlock:
+assert(0 && "not implemented");
+abort();
+return;
+ case MachineOperand::MO_GlobalAddress:
+assert(0 && "not implemented");
+abort();
+break;
+ case MachineOperand::MO_ExternalSymbol:
+assert(0 && "not implemented");
+abort();
+break;
+ case MachineOperand::MO_ConstantPoolIndex:
+assert(0 && "not implemented");
+abort();
+break;
+ default:
+O << ""; abort (); break;
+ }
}
void ARMAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.189 -> 1.190
---
Log message:
Fix Benchmarks/MallocBench/cfrac
---
Diffs of the changes: (+2 -0)
PPCISelDAGToDAG.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.189
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.190
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.189 Wed May 24 19:24:27 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu May 25 11:54:16 2006
@@ -714,8 +714,10 @@
switch (CC) {
default: assert(0 && "Unknown condition!"); abort();
case ISD::SETOEQ:// FIXME: This is incorrect see PR642.
+ case ISD::SETUEQ:
case ISD::SETEQ: return PPC::BEQ;
case ISD::SETONE:// FIXME: This is incorrect see PR642.
+ case ISD::SETUNE:
case ISD::SETNE: return PPC::BNE;
case ISD::SETOLT:// FIXME: This is incorrect see PR642.
case ISD::SETULT:
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/SingleSource/Benchmarks/Shootout/fib2.c
Changes in directory llvm-test/SingleSource/Benchmarks/Shootout:
fib2.c updated: 1.2 -> 1.3
---
Log message:
Fix fib2 in the PPC JIT
---
Diffs of the changes: (+3 -3)
fib2.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm-test/SingleSource/Benchmarks/Shootout/fib2.c
diff -u llvm-test/SingleSource/Benchmarks/Shootout/fib2.c:1.2
llvm-test/SingleSource/Benchmarks/Shootout/fib2.c:1.3
--- llvm-test/SingleSource/Benchmarks/Shootout/fib2.c:1.2 Tue Jun 8
12:21:42 2004
+++ llvm-test/SingleSource/Benchmarks/Shootout/fib2.c Thu May 25 12:25:32 2006
@@ -1,10 +1,10 @@
/* -*- mode: c -*-
- * $Id: fib2.c,v 1.2 2004/06/08 17:21:42 lattner Exp $
+ * $Id: fib2.c,v 1.3 2006/05/25 17:25:32 lattner Exp $
* http://www.bagley.org/~doug/shootout/
*/
int atoi(char *);
-void printf(char *, unsigned long);
+#include
unsigned long
fib(unsigned long n) {
@@ -16,7 +16,7 @@
int
main(int argc, char *argv[]) {
-int N = ((argc == 2) ? atoi(argv[1]) : 43);
+int N = ((argc == 2) ? atoi(argv[1]) : 4);
printf("%ld\n", fib(N));
return(0);
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.190 -> 1.191 --- Log message: Fix build failure of povray --- Diffs of the changes: (+2 -0) PPCISelDAGToDAG.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.190 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.191 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.190 Thu May 25 11:54:16 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu May 25 13:06:16 2006 @@ -757,8 +757,10 @@ case ISD::SETULE: case ISD::SETLE: Inv = true; return 1; case ISD::SETOEQ: // FIXME: This is incorrect see PR642. + case ISD::SETUEQ: case ISD::SETEQ: Inv = false; return 2; case ISD::SETONE: // FIXME: This is incorrect see PR642. + case ISD::SETUNE: case ISD::SETNE: Inv = true; return 2; case ISD::SETO: Inv = true; return 3; case ISD::SETUO: Inv = false; return 3; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/SingleSource/Benchmarks/Shootout/fib2.c
Changes in directory llvm-test/SingleSource/Benchmarks/Shootout:
fib2.c updated: 1.3 -> 1.4
---
Log message:
Restore the problem size
---
Diffs of the changes: (+2 -2)
fib2.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm-test/SingleSource/Benchmarks/Shootout/fib2.c
diff -u llvm-test/SingleSource/Benchmarks/Shootout/fib2.c:1.3
llvm-test/SingleSource/Benchmarks/Shootout/fib2.c:1.4
--- llvm-test/SingleSource/Benchmarks/Shootout/fib2.c:1.3 Thu May 25
12:25:32 2006
+++ llvm-test/SingleSource/Benchmarks/Shootout/fib2.c Thu May 25 13:31:14 2006
@@ -1,5 +1,5 @@
/* -*- mode: c -*-
- * $Id: fib2.c,v 1.3 2006/05/25 17:25:32 lattner Exp $
+ * $Id: fib2.c,v 1.4 2006/05/25 18:31:14 lattner Exp $
* http://www.bagley.org/~doug/shootout/
*/
@@ -16,7 +16,7 @@
int
main(int argc, char *argv[]) {
-int N = ((argc == 2) ? atoi(argv[1]) : 4);
+int N = ((argc == 2) ? atoi(argv[1]) : 43);
printf("%ld\n", fib(N));
return(0);
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.212 -> 1.213
---
Log message:
Build breakage.
---
Diffs of the changes: (+11 -15)
X86ISelLowering.cpp | 26 +++---
1 files changed, 11 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.212
llvm/lib/Target/X86/X86ISelLowering.cpp:1.213
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.212 Wed May 24 19:59:30 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu May 25 13:56:34 2006
@@ -555,14 +555,15 @@
switch (Arg.getValueType()) {
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i8:
-case MVT::i16:
+case MVT::i16: {
// Promote the integer to 32 bits. If the input type is signed use a
// sign extend, otherwise use a zero extend.
unsigned ExtOp =
dyn_cast(Op.getOperand(5+2*i+1))->getValue() ?
ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
Arg = DAG.getNode(ExtOp, MVT::i32, Arg);
- // Fallthrough
+}
+// Fallthrough
case MVT::i32:
case MVT::f32: {
@@ -690,7 +691,6 @@
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64:
- case MVT::Vector:
Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
NodeTys.push_back(RetVT);
@@ -979,16 +979,15 @@
case MVT::f64:
MF.addLiveOut(X86::ST0);
break;
- case MVT::Vector: {
-const PackedType *PTy =
cast(MF.getFunction()->getReturnType());
-MVT::ValueType EVT;
-MVT::ValueType LVT;
-unsigned NumRegs = getPackedTypeBreakdown(PTy, EVT, LVT);
-assert(NumRegs == 1 && "Unsupported type!");
+ case MVT::v16i8:
+ case MVT::v8i16:
+ case MVT::v4i32:
+ case MVT::v2i64:
+ case MVT::v4f32:
+ case MVT::v2f64:
MF.addLiveOut(X86::XMM0);
break;
}
- }
// Return the new list of results.
std::vector RetVTs(Op.Val->value_begin(),
@@ -1046,14 +1045,13 @@
case MVT::v4i32:
case MVT::v2i64:
case MVT::v4f32:
-case MVT::v2f64: {
+case MVT::v2f64:
if (NumXMMRegs < 3)
NumXMMRegs++;
else
NumBytes += 16;
break;
}
-}
}
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
@@ -1106,7 +1104,7 @@
case MVT::v4i32:
case MVT::v2i64:
case MVT::v4f32:
-case MVT::v2f64: {
+case MVT::v2f64:
if (NumXMMRegs < 3) {
RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
NumXMMRegs++;
@@ -1118,7 +1116,6 @@
ArgOffset += 16;
}
}
-}
}
if (!MemOpChains.empty())
@@ -1202,7 +1199,6 @@
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64:
- case MVT::Vector:
Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
NodeTys.push_back(RetVT);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.206 -> 1.207
---
Log message:
Can't trust NodeDepth when checking for possibility of load folding creating
a cycle. This increase the search space and will increase compile time (in
practice it appears to be small, e.g. 176.gcc goes from 62 sec to 65 sec)
that will be addressed later.
---
Diffs of the changes: (+5 -7)
DAGISelEmitter.cpp | 12 +---
1 files changed, 5 insertions(+), 7 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.206
llvm/utils/TableGen/DAGISelEmitter.cpp:1.207
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.206Wed May 24 19:21:44 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Thu May 25 15:16:55 2006
@@ -3481,13 +3481,11 @@
OS << " if (found || !Visited.insert(Use).second) return;\n";
OS << " for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {\n";
OS << "SDNode *N = Use->getOperand(i).Val;\n";
- OS << "if (N->getNodeDepth() >= Def->getNodeDepth()) {\n";
- OS << " if (N != Def) {\n";
- OS << "findNonImmUse(N, Def, found, Visited);\n";
- OS << " } else {\n";
- OS << "found = true;\n";
- OS << "break;\n";
- OS << " }\n";
+ OS << "if (N != Def) {\n";
+ OS << " findNonImmUse(N, Def, found, Visited);\n";
+ OS << "} else {\n";
+ OS << " found = true;\n";
+ OS << " break;\n";
OS << "}\n";
OS << " }\n";
OS << "}\n";
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-05-25-CycleInDAG.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
2006-05-25-CycleInDAG.ll added (r1.1)
---
Log message:
New test case. x86 isel was creating a cycle in the DAG.
---
Diffs of the changes: (+21 -0)
2006-05-25-CycleInDAG.ll | 21 +
1 files changed, 21 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/2006-05-25-CycleInDAG.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/2006-05-25-CycleInDAG.ll:1.1
*** /dev/null Thu May 25 15:21:29 2006
--- llvm/test/Regression/CodeGen/X86/2006-05-25-CycleInDAG.ll Thu May 25
15:21:19 2006
***
*** 0
--- 1,21
+ ; RUN: llvm-as < %s | llc -march=x86
+
+ int %test() {
+ br bool false, label %cond_next33, label %cond_true12
+
+ cond_true12:
+ ret int 0
+
+ cond_next33:
+ %tmp44.i = call double %foo( double 0.00e+00, int 32 )
+ %tmp61.i = load ubyte* null
+ %tmp61.i = cast ubyte %tmp61.i to int
+ %tmp58.i = or int 0, %tmp61.i
+ %tmp62.i = or int %tmp58.i, 0
+ %tmp62.i = cast int %tmp62.i to double
+ %tmp64.i = add double %tmp62.i, %tmp44.i
+ %tmp68.i = call double %foo( double %tmp64.i, int 0 )
+ ret int 0
+ }
+
+ declare double %foo(double, int)
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/2006-05-10-InvalidIndexUndef.ll
Changes in directory llvm/test/Regression/Transforms/InstCombine: 2006-05-10-InvalidIndexUndef.ll updated: 1.1 -> 1.2 --- Log message: The patch corresponding to this test had to be reverted as unsafe. --- Diffs of the changes: (+1 -0) 2006-05-10-InvalidIndexUndef.ll |1 + 1 files changed, 1 insertion(+) Index: llvm/test/Regression/Transforms/InstCombine/2006-05-10-InvalidIndexUndef.ll diff -u llvm/test/Regression/Transforms/InstCombine/2006-05-10-InvalidIndexUndef.ll:1.1 llvm/test/Regression/Transforms/InstCombine/2006-05-10-InvalidIndexUndef.ll:1.2 --- llvm/test/Regression/Transforms/InstCombine/2006-05-10-InvalidIndexUndef.ll:1.1 Wed May 24 12:34:02 2006 +++ llvm/test/Regression/Transforms/InstCombine/2006-05-10-InvalidIndexUndef.ll Thu May 25 16:25:54 2006 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep undef +; XFAIL: * %str = constant [4 x ubyte] c"str\00" ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Utils/Local.cpp
Changes in directory llvm/lib/Transforms/Utils:
Local.cpp updated: 1.56 -> 1.57
---
Log message:
Revert a patch that is unsafe, due to out of range array accesses in inner
array scopes possibly accessing valid memory in outer subscripts.
---
Diffs of the changes: (+2 -2)
Local.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Transforms/Utils/Local.cpp
diff -u llvm/lib/Transforms/Utils/Local.cpp:1.56
llvm/lib/Transforms/Utils/Local.cpp:1.57
--- llvm/lib/Transforms/Utils/Local.cpp:1.56Wed May 24 12:34:30 2006
+++ llvm/lib/Transforms/Utils/Local.cpp Thu May 25 16:25:12 2006
@@ -274,7 +274,7 @@
} else if (ConstantInt *CI = dyn_cast(I.getOperand())) {
if (const ArrayType *ATy = dyn_cast(*I)) {
if ((uint64_t)CI->getRawValue() >= ATy->getNumElements())
- C = UndefValue::get(ATy->getElementType());
+ return 0;
if (ConstantArray *CA = dyn_cast(C))
C = CA->getOperand((unsigned)CI->getRawValue());
else if (isa(C))
@@ -285,7 +285,7 @@
return 0;
} else if (const PackedType *PTy = dyn_cast(*I)) {
if ((uint64_t)CI->getRawValue() >= PTy->getNumElements())
- C = UndefValue::get(PTy->getElementType());
+ return 0;
if (ConstantPacked *CP = dyn_cast(C))
C = CP->getOperand((unsigned)CI->getRawValue());
else if (isa(C))
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86AsmPrinter.cpp X86AsmPrinter.h X86Subtarget.cpp
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.cpp updated: 1.47 -> 1.48
X86AsmPrinter.cpp updated: 1.181 -> 1.182
X86AsmPrinter.h updated: 1.18 -> 1.19
X86Subtarget.cpp updated: 1.26 -> 1.27
---
Log message:
X86 / Cygwin asm / alignment fixes.
Patch contributed by Anton Korobeynikov!
---
Diffs of the changes: (+42 -30)
X86ATTAsmPrinter.cpp | 32
X86AsmPrinter.cpp| 30 +-
X86AsmPrinter.h |8
X86Subtarget.cpp |2 +-
4 files changed, 42 insertions(+), 30 deletions(-)
Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.47
llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.48
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.47 Tue May 16 02:21:53 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cppThu May 25 16:59:08 2006
@@ -26,11 +26,9 @@
/// method to print assembly for each instruction.
///
bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
- // if (forDarwin) {
-// Let PassManager know we need debug information and relay
-// the MachineDebugInfo address on to DwarfWriter.
-DW.SetDebugInfo(&getAnalysis());
-// }
+ // Let PassManager know we need debug information and relay
+ // the MachineDebugInfo address on to DwarfWriter.
+ DW.SetDebugInfo(&getAnalysis());
SetupMachineFunction(MF);
O << "\n\n";
@@ -56,11 +54,17 @@
break;
case Function::WeakLinkage:
case Function::LinkOnceLinkage:
-if (forDarwin) {
+if (Subtarget->TargetType == X86Subtarget::isDarwin) {
SwitchToTextSection(
".section __TEXT,__textcoal_nt,coalesced,pure_instructions",
F);
O << "\t.globl\t" << CurrentFnName << "\n";
O << "\t.weak_definition\t" << CurrentFnName << "\n";
+} else if (Subtarget->TargetType == X86Subtarget::isCygwin) {
+ EmitAlignment(4, F); // FIXME: This should be parameterized
somewhere.
+ O << "\t.section\t.llvm.linkonce.t." << CurrentFnName
+<< ",\"ax\"\n";
+ SwitchToTextSection("", F);
+ O << "\t.weak " << CurrentFnName << "\n";
} else {
EmitAlignment(4, F); // FIXME: This should be parameterized
somewhere.
O << "\t.section\t.llvm.linkonce.t." << CurrentFnName
@@ -72,7 +76,7 @@
}
O << CurrentFnName << ":\n";
- if (forDarwin) {
+ if (Subtarget->TargetType == X86Subtarget::isDarwin) {
// Emit pre-function debug information.
DW.BeginFunction(&MF);
}
@@ -95,7 +99,7 @@
if (HasDotTypeDotSizeDirective)
O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
- if (forDarwin) {
+ if (Subtarget->TargetType == X86Subtarget::isDarwin) {
// Emit post-function debug information.
DW.EndFunction();
}
@@ -145,7 +149,8 @@
if (!isMemOp) O << '$';
O << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << "_"
<< MO.getConstantPoolIndex();
-if (forDarwin && TM.getRelocationModel() == Reloc::PIC)
+if (Subtarget->TargetType == X86Subtarget::isDarwin &&
+TM.getRelocationModel() == Reloc::PIC)
O << "-\"L" << getFunctionNumber() << "$pb\"";
int Offset = MO.getOffset();
if (Offset > 0)
@@ -159,7 +164,8 @@
bool isMemOp = Modifier && !strcmp(Modifier, "mem");
if (!isMemOp && !isCallOp) O << '$';
// Darwin block shameless ripped from PPCAsmPrinter.cpp
-if (forDarwin && TM.getRelocationModel() != Reloc::Static) {
+if (Subtarget->TargetType == X86Subtarget::isDarwin &&
+TM.getRelocationModel() != Reloc::Static) {
GlobalValue *GV = MO.getGlobal();
std::string Name = Mang->getValueName(GV);
// Link-once, External, or Weakly-linked global variables need
@@ -190,7 +196,9 @@
}
case MachineOperand::MO_ExternalSymbol: {
bool isCallOp = Modifier && !strcmp(Modifier, "call");
-if (isCallOp && forDarwin && TM.getRelocationModel() != Reloc::Static) {
+if (isCallOp &&
+Subtarget->TargetType == X86Subtarget::isDarwin &&
+TM.getRelocationModel() != Reloc::Static) {
std::string Name(GlobalPrefix);
Name += MO.getSymbolName();
FnStubs.insert(Name);
@@ -332,7 +340,7 @@
void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
++EmittedInsts;
// This works around some Darwin assembler bugs.
- if (forDarwin) {
+ if (Subtarget->TargetType == X86Subtarget::isDarwin) {
switch (MI->getOpcode()) {
case X86::REP_MOVSB:
O << "rep/movsb (%esi),(%edi)\n";
Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.181
llvm/lib/Target/X86/X86AsmPrinter.cpp:1.182
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.181 Tue May 9 00:12:53 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp Thu May 25 16:59:08 2006
@@ -46,9 +46,6 @@
/// doInitialization
bool X86SharedAsmPrinter::doInitialization(Module &M) {
- const X86Subtarget *Subtarget = &TM.getSubtarget();
-
-
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.213 -> 1.214
---
Log message:
Remove some dead code.
---
Diffs of the changes: (+0 -21)
X86ISelLowering.cpp | 21 -
1 files changed, 21 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.213
llvm/lib/Target/X86/X86ISelLowering.cpp:1.214
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.213 Thu May 25 13:56:34 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu May 25 17:25:52 2006
@@ -403,27 +403,6 @@
}
}
-/// getFormalArgObjects - Returns itself if Op is a FORMAL_ARGUMENTS, otherwise
-/// returns the FORMAL_ARGUMENTS node(s) that made up parts of the node.
-static std::vector getFormalArgObjects(SDOperand Op) {
- unsigned Opc = Op.getOpcode();
- std::vector Objs;
- if (Opc == ISD::TRUNCATE) {
-Op = Op.getOperand(0);
-assert(Op.getOpcode() == ISD::AssertSext ||
- Op.getOpcode() == ISD::AssertZext);
-Objs.push_back(Op.getOperand(0));
- } else if (Opc == ISD::FP_ROUND || Opc == ISD::VBIT_CONVERT) {
-Objs.push_back(Op.getOperand(0));
- } else if (Opc == ISD::BUILD_PAIR) {
-Objs.push_back(Op.getOperand(0));
-Objs.push_back(Op.getOperand(1));
- } else {
-Objs.push_back(Op);
- }
- return Objs;
-}
-
SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG
&DAG) {
unsigned NumArgs = Op.Val->getNumValues() - 1;
MachineFunction &MF = DAG.getMachineFunction();
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/Sparc:
SparcISelDAGToDAG.cpp updated: 1.96 -> 1.97
---
Log message:
Add support for the missing FP condition codes
---
Diffs of the changes: (+12 -6)
SparcISelDAGToDAG.cpp | 18 --
1 files changed, 12 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.96
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.97
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.96Wed May 24 19:24:27 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu May 25 17:26:02 2006
@@ -75,12 +75,18 @@
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown fp condition code!");
- case ISD::SETEQ: return SPCC::FCC_E;
- case ISD::SETNE: return SPCC::FCC_NE;
- case ISD::SETLT: return SPCC::FCC_L;
- case ISD::SETGT: return SPCC::FCC_G;
- case ISD::SETLE: return SPCC::FCC_LE;
- case ISD::SETGE: return SPCC::FCC_GE;
+ case ISD::SETEQ:
+ case ISD::SETOEQ: return SPCC::FCC_E;
+ case ISD::SETNE:
+ case ISD::SETUNE: return SPCC::FCC_NE;
+ case ISD::SETLT:
+ case ISD::SETOLT: return SPCC::FCC_L;
+ case ISD::SETGT:
+ case ISD::SETOGT: return SPCC::FCC_G;
+ case ISD::SETLE:
+ case ISD::SETOLE: return SPCC::FCC_LE;
+ case ISD::SETGE:
+ case ISD::SETOGE: return SPCC::FCC_GE;
case ISD::SETULT: return SPCC::FCC_UL;
case ISD::SETULE: return SPCC::FCC_ULE;
case ISD::SETUGT: return SPCC::FCC_UG;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.214 -> 1.215
---
Log message:
Some clean up.
---
Diffs of the changes: (+3 -4)
X86ISelLowering.cpp |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.214
llvm/lib/Target/X86/X86ISelLowering.cpp:1.215
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.214 Thu May 25 17:25:52 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu May 25 17:38:31 2006
@@ -510,14 +510,13 @@
case MVT::v4i32:
case MVT::v2i64:
case MVT::v4f32:
-case MVT::v2f64: {
+case MVT::v2f64:
if (NumXMMRegs < 3)
++NumXMMRegs;
else
NumBytes += 16;
break;
}
-}
}
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
getPointerTy()));
@@ -567,7 +566,7 @@
case MVT::v4i32:
case MVT::v2i64:
case MVT::v4f32:
-case MVT::v2f64: {
+case MVT::v2f64:
if (NumXMMRegs < 3) {
RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
NumXMMRegs++;
@@ -579,7 +578,6 @@
ArgOffset += 16;
}
}
-}
}
if (!MemOpChains.empty())
@@ -1013,6 +1011,7 @@
++NumIntRegs;
break;
}
+ // Fall through
case MVT::f32:
NumBytes += 4;
break;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll
Changes in directory llvm/test/Regression/Transforms/InstCombine:
vec_shuffle.ll updated: 1.2 -> 1.3
---
Log message:
new testcases
---
Diffs of the changes: (+12 -0)
vec_shuffle.ll | 12
1 files changed, 12 insertions(+)
Index: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll
diff -u llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.2
llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.3
--- llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.2 Mon Apr
10 18:06:18 2006
+++ llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll Thu May 25
17:52:49 2006
@@ -22,3 +22,15 @@
ret float %E
}
+int %test4(<4 x int> %X) {
+%tmp152.i53899.i = shufflevector <4 x int> %X, <4 x int> undef, <4 x
uint> zeroinitializer
+%tmp34 = extractelement <4 x int> %tmp152.i53899.i, uint 0
+ret int %tmp34
+}
+
+int %test5(<4 x int> %X) {
+%tmp152.i53899.i = shufflevector <4 x int> %X, <4 x int> undef, <4 x
uint>
+%tmp34 = extractelement <4 x int> %tmp152.i53899.i, uint 0
+ret int %tmp34
+}
+
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.483 -> 1.484
---
Log message:
extract element from a shuffle vector can be trivially turned into an
extractelement from the SV's source. This implement vec_shuffle.ll:test[45]
---
Diffs of the changes: (+41 -12)
InstructionCombining.cpp | 53 ---
1 files changed, 41 insertions(+), 12 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.483
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.484
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.483 Sat May 20
18:14:03 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Thu May 25 17:53:38 2006
@@ -7072,7 +7072,7 @@
return ReplaceInstUsesWith(EI, Elt);
}
- if (Instruction *I = dyn_cast(EI.getOperand(0)))
+ if (Instruction *I = dyn_cast(EI.getOperand(0))) {
if (I->hasOneUse()) {
// Push extractelement into predecessor operation if legal and
// profitable to do so
@@ -7097,20 +7097,49 @@
I->getName() + ".gep");
InsertNewInstBefore(GEP, EI);
return new LoadInst(GEP);
- } else if (InsertElementInst *IE = dyn_cast(I)) {
-// Extracting the inserted element?
-if (IE->getOperand(2) == EI.getOperand(1))
- return ReplaceInstUsesWith(EI, IE->getOperand(1));
-// If the inserted and extracted elements are constants, they must not
-// be the same value, extract from the pre-inserted value instead.
-if (isa(IE->getOperand(2)) &&
-isa(EI.getOperand(1))) {
- AddUsesToWorkList(EI);
- EI.setOperand(0, IE->getOperand(0));
- return &EI;
+ }
+}
+if (InsertElementInst *IE = dyn_cast(I)) {
+ // Extracting the inserted element?
+ if (IE->getOperand(2) == EI.getOperand(1))
+return ReplaceInstUsesWith(EI, IE->getOperand(1));
+ // If the inserted and extracted elements are constants, they must not
+ // be the same value, extract from the pre-inserted value instead.
+ if (isa(IE->getOperand(2)) &&
+ isa(EI.getOperand(1))) {
+AddUsesToWorkList(EI);
+EI.setOperand(0, IE->getOperand(0));
+return &EI;
+ }
+} else if (ShuffleVectorInst *SVI = dyn_cast(I)) {
+ // If this is extracting an element from a shufflevector, figure out
where
+ // it came from and extract from the appropriate input element instead.
+ if (ConstantUInt *Elt = dyn_cast(EI.getOperand(1))) {
+unsigned ExtractedIdx = Elt->getValue();
+if (ConstantPacked *CP = dyn_cast(SVI->getOperand(2)))
{
+ unsigned Idx = 0;
+ if (ConstantUInt *CI =
+ dyn_cast(CP->getOperand(ExtractedIdx)))
+Idx = CI->getValue();
+ Value *Src;
+ if (Idx < CP->getNumOperands())
+Src = SVI->getOperand(0);
+ else {
+Idx -= CP->getNumOperands();
+Src = SVI->getOperand(0);
+ }
+ return new ExtractElementInst(Src,
+ConstantUInt::get(Type::UIntTy, Idx));
+
+} else if (isa(SVI->getOperand(2))) {
+ // If extracting from a splat of the 0th element, return an extract
+ // of the zero'th element of the input to the splat.
+ return new ExtractElementInst(SVI->getOperand(0),
+ConstantUInt::get(Type::UIntTy, 0));
}
}
}
+ }
return 0;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll
Changes in directory llvm/test/Regression/Transforms/InstCombine:
vec_shuffle.ll updated: 1.3 -> 1.4
---
Log message:
new testcase
---
Diffs of the changes: (+8 -0)
vec_shuffle.ll |8
1 files changed, 8 insertions(+)
Index: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll
diff -u llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.3
llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.4
--- llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.3 Thu May
25 17:52:49 2006
+++ llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll Thu May 25
18:23:22 2006
@@ -34,3 +34,11 @@
ret int %tmp34
}
+float %test6(<4 x float> %X) {
+%X = cast <4 x float> %X to <4 x int>
+%tmp152.i53899.i = shufflevector <4 x int> %X, <4 x int> undef, <4 x
uint> zeroinitializer
+%tmp152.i53900.i = cast <4 x int> %tmp152.i53899.i to <4 x float>
+%tmp34 = extractelement <4 x float> %tmp152.i53900.i, uint 0
+ret float %tmp34
+}
+
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.484 -> 1.485
---
Log message:
Turn (cast (shuffle (cast)) -> shuffle (cast) if it reduces the # casts in
the program. This exposes more opportunities for the instcombiner, and
implements
vec_shuffle.ll:test6
---
Diffs of the changes: (+31 -2)
InstructionCombining.cpp | 33 +++--
1 files changed, 31 insertions(+), 2 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.484
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.485
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.484 Thu May 25
17:53:38 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Thu May 25 18:24:33 2006
@@ -413,7 +413,7 @@
if (V->getType()->isLosslesslyConvertibleTo(Ty))
return false;
- // If this is another cast that can be elimianted, it isn't codegen either.
+ // If this is another cast that can be eliminated, it isn't codegen either.
if (const CastInst *CI = dyn_cast(V))
if (isEliminableCastOfCast(CI->getOperand(0)->getType(), CI->getType(), Ty,
TD))
@@ -4970,7 +4970,7 @@
// If the source value is an instruction with only this use, we can attempt
to
// propagate the cast into the instruction. Also, only handle integral types
// for now.
- if (Instruction *SrcI = dyn_cast(Src))
+ if (Instruction *SrcI = dyn_cast(Src)) {
if (SrcI->hasOneUse() && Src->getType()->isIntegral() &&
CI.getType()->isInteger()) { // Don't mess with casts to bool here
@@ -5152,6 +5152,35 @@
break;
}
}
+
+if (SrcI->hasOneUse()) {
+ if (ShuffleVectorInst *SVI = dyn_cast(SrcI)) {
+// Okay, we have (cast (shuffle ..)). We know this cast is a
bitconvert
+// because the inputs are known to be a vector. Check to see if this
is
+// a cast to a vector with the same # elts.
+if (isa(CI.getType()) &&
+cast(CI.getType())->getNumElements() ==
+ SVI->getType()->getNumElements()) {
+ CastInst *Tmp;
+ // If either of the operands is a cast from CI.getType(), then
+ // evaluating the shuffle in the casted destination's type will allow
+ // us to eliminate at least one cast.
+ if (((Tmp = dyn_cast(SVI->getOperand(0))) &&
+ Tmp->getOperand(0)->getType() == CI.getType()) ||
+ ((Tmp = dyn_cast(SVI->getOperand(1))) &&
+ Tmp->getOperand(1)->getType() == CI.getType())) {
+Value *LHS = InsertOperandCastBefore(SVI->getOperand(0),
+ CI.getType(), &CI);
+Value *RHS = InsertOperandCastBefore(SVI->getOperand(1),
+ CI.getType(), &CI);
+// Return a new shuffle vector. Use the same element ID's, as we
+// know the vector types match #elts.
+return new ShuffleVectorInst(LHS, RHS, SVI->getOperand(2));
+ }
+}
+ }
+}
+ }
return 0;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.215 -> 1.216
---
Log message:
Consistency
---
Diffs of the changes: (+3 -0)
X86ISelLowering.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.215
llvm/lib/Target/X86/X86ISelLowering.cpp:1.216
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.215 Thu May 25 17:38:31 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu May 25 18:31:23 2006
@@ -380,6 +380,8 @@
static void
HowToPassCCCArgument(MVT::ValueType ObjectVT, unsigned NumXMMRegs,
unsigned &ObjSize, unsigned &ObjXMMRegs) {
+ NumXMMRegs = 0;
+
switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!");
case MVT::i1:
@@ -774,6 +776,7 @@
unsigned &ObjXMMRegs) {
ObjSize = 0;
NumIntRegs = 0;
+ NumXMMRegs = 0;
switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!");
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.485 -> 1.486
---
Log message:
Introduce a helper function that simplifies interpretation of shuffle masks.
No functionality change.
---
Diffs of the changes: (+64 -91)
InstructionCombining.cpp | 155 +++
1 files changed, 64 insertions(+), 91 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.485
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.486
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.485 Thu May 25
18:24:33 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Thu May 25 18:48:38 2006
@@ -7024,6 +7024,25 @@
return false;
}
+/// getShuffleMask - Read and decode a shufflevector mask. It turns undef
+/// elements into values that are larger than the #elts in the input.
+static std::vector getShuffleMask(const ShuffleVectorInst *SVI) {
+ unsigned NElts = SVI->getType()->getNumElements();
+ if (isa(SVI->getOperand(2)))
+return std::vector(NElts, 0);
+ if (isa(SVI->getOperand(2)))
+return std::vector(NElts, 2*NElts);
+
+ std::vector Result;
+ const ConstantPacked *CP = cast(SVI->getOperand(2));
+ for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i)
+if (isa(CP->getOperand(i)))
+ Result.push_back(NElts*2); // undef -> 8
+else
+ Result.push_back(cast(CP->getOperand(i))->getValue());
+ return Result;
+}
+
/// FindScalarElement - Given a vector and an element number, see if the scalar
/// value is already around as a register, for example if it were inserted then
/// extracted from the vector.
@@ -7053,18 +7072,13 @@
// vector input.
return FindScalarElement(III->getOperand(0), EltNo);
} else if (ShuffleVectorInst *SVI = dyn_cast(V)) {
-if (isa(SVI->getOperand(2))) {
- return FindScalarElement(SVI->getOperand(0), 0);
-} else if (ConstantPacked *CP =
- dyn_cast(SVI->getOperand(2))) {
- if (isa(CP->getOperand(EltNo)))
-return UndefValue::get(PTy->getElementType());
- unsigned InEl = cast(CP->getOperand(EltNo))->getValue();
- if (InEl < Width)
-return FindScalarElement(SVI->getOperand(0), InEl);
- else
-return FindScalarElement(SVI->getOperand(1), InEl - Width);
-}
+unsigned InEl = getShuffleMask(SVI)[EltNo];
+if (InEl < Width)
+ return FindScalarElement(SVI->getOperand(0), InEl);
+else if (InEl < Width*2)
+ return FindScalarElement(SVI->getOperand(1), InEl - Width);
+else
+ return UndefValue::get(PTy->getElementType());
}
// Otherwise, we don't know.
@@ -7144,28 +7158,18 @@
// If this is extracting an element from a shufflevector, figure out
where
// it came from and extract from the appropriate input element instead.
if (ConstantUInt *Elt = dyn_cast(EI.getOperand(1))) {
-unsigned ExtractedIdx = Elt->getValue();
-if (ConstantPacked *CP = dyn_cast(SVI->getOperand(2)))
{
- unsigned Idx = 0;
- if (ConstantUInt *CI =
- dyn_cast(CP->getOperand(ExtractedIdx)))
-Idx = CI->getValue();
- Value *Src;
- if (Idx < CP->getNumOperands())
-Src = SVI->getOperand(0);
- else {
-Idx -= CP->getNumOperands();
-Src = SVI->getOperand(0);
- }
- return new ExtractElementInst(Src,
-ConstantUInt::get(Type::UIntTy, Idx));
-
-} else if (isa(SVI->getOperand(2))) {
- // If extracting from a splat of the 0th element, return an extract
- // of the zero'th element of the input to the splat.
- return new ExtractElementInst(SVI->getOperand(0),
-ConstantUInt::get(Type::UIntTy, 0));
+unsigned SrcIdx = getShuffleMask(SVI)[Elt->getValue()];
+Value *Src;
+if (SrcIdx < SVI->getType()->getNumElements())
+ Src = SVI->getOperand(0);
+else if (SrcIdx < SVI->getType()->getNumElements()*2) {
+ SrcIdx -= SVI->getType()->getNumElements();
+ Src = SVI->getOperand(1);
+} else {
+ return ReplaceInstUsesWith(EI, UndefValue::get(EI.getType()));
}
+return new ExtractElementInst(Src,
+ ConstantUInt::get(Type::UIntTy, SrcIdx));
}
}
}
@@ -7373,84 +7377,53 @@
Instruction *InstCombiner::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
Value *LHS = SVI.getOperand(0);
Value *RHS = SVI.getOperand(1);
- Constant *Mask = cast(SVI.getOperand(2));
+ std::vector Mask = getShuffleMask(&SVI);
bool MadeChange = false;
- if (isa(Mask))
+ if (isa(SVI.getOperand(2)))
return ReplaceInstUsesWith(SVI, UndefValue::get(SVI.getType()));
// TODO: If we have shuffle(x, undef, mask) and any elements of mask ref
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.486 -> 1.487
---
Log message:
Transform things like (splat(splat)) -> splat
---
Diffs of the changes: (+50 -4)
InstructionCombining.cpp | 54 +++
1 files changed, 50 insertions(+), 4 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.486
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.487
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.486 Thu May 25
18:48:38 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Thu May 25 19:29:06 2006
@@ -7398,18 +7398,26 @@
// Remap any references to RHS to use LHS.
std::vector Elts;
for (unsigned i = 0, e = Mask.size(); i != e; ++i) {
- if (Mask[i] > 2*e)
+ if (Mask[i] >= 2*e)
Elts.push_back(UndefValue::get(Type::UIntTy));
- else
-Elts.push_back(ConstantUInt::get(Type::UIntTy, Mask[i] & (e-1)));
+ else {
+if ((Mask[i] >= e && isa(RHS)) ||
+(Mask[i] < e && isa(LHS)))
+ Mask[i] = 2*e; // Turn into undef.
+else
+ Mask[i] &= (e-1); // Force to LHS.
+Elts.push_back(ConstantUInt::get(Type::UIntTy, Mask[i]));
+ }
}
SVI.setOperand(0, SVI.getOperand(1));
SVI.setOperand(1, UndefValue::get(RHS->getType()));
SVI.setOperand(2, ConstantPacked::get(Elts));
+LHS = SVI.getOperand(0);
+RHS = SVI.getOperand(1);
MadeChange = true;
}
- // Analyze the shuffle, are the LHS or RHS and identity shuffle?
+ // Analyze the shuffle, are the LHS or RHS and identity shuffles?
bool isLHSID = true, isRHSID = true;
for (unsigned i = 0, e = Mask.size(); i != e; ++i) {
@@ -7425,6 +7433,44 @@
if (isLHSID) return ReplaceInstUsesWith(SVI, LHS);
if (isRHSID) return ReplaceInstUsesWith(SVI, RHS);
+ // If the LHS is a shufflevector itself, see if we can combine it with this
+ // one without producing an unusual shuffle. Here we are really
conservative:
+ // we are absolutely afraid of producing a shuffle mask not in the input
+ // program, because the code gen may not be smart enough to turn a merged
+ // shuffle into two specific shuffles: it may produce worse code. As such,
+ // we only merge two shuffles if the result is one of the two input shuffle
+ // masks. In this case, merging the shuffles just removes one instruction,
+ // which we know is safe. This is good for things like turning:
+ // (splat(splat)) -> splat.
+ if (ShuffleVectorInst *LHSSVI = dyn_cast(LHS)) {
+if (isa(RHS)) {
+ std::vector LHSMask = getShuffleMask(LHSSVI);
+
+ std::vector NewMask;
+ for (unsigned i = 0, e = Mask.size(); i != e; ++i)
+if (Mask[i] >= 2*e)
+ NewMask.push_back(2*e);
+else
+ NewMask.push_back(LHSMask[Mask[i]]);
+
+ // If the result mask is equal to the src shuffle or this shuffle mask,
do
+ // the replacement.
+ if (NewMask == LHSMask || NewMask == Mask) {
+std::vector Elts;
+for (unsigned i = 0, e = NewMask.size(); i != e; ++i) {
+ if (NewMask[i] >= e*2) {
+Elts.push_back(UndefValue::get(Type::UIntTy));
+ } else {
+Elts.push_back(ConstantUInt::get(Type::UIntTy, NewMask[i]));
+ }
+}
+return new ShuffleVectorInst(LHSSVI->getOperand(0),
+ LHSSVI->getOperand(1),
+ ConstantPacked::get(Elts));
+ }
+}
+ }
+
return MadeChange ? &SVI : 0;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp
Changes in directory llvm/lib/Target/X86:
X86AsmPrinter.cpp updated: 1.182 -> 1.183
---
Log message:
Minor bug caught by Ashwin Chandra
---
Diffs of the changes: (+1 -1)
X86AsmPrinter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.182
llvm/lib/Target/X86/X86AsmPrinter.cpp:1.183
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.182 Thu May 25 16:59:08 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp Fri May 26 01:22:34 2006
@@ -129,7 +129,7 @@
} else
O << COMMDirective << name << "," << Size;
} else {
- if (Subtarget->TargetType == X86Subtarget::isCygwin) {
+ if (Subtarget->TargetType != X86Subtarget::isCygwin) {
if (I->hasInternalLinkage())
O << "\t.local\t" << name << "\n";
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
