[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.54 -> 1.55
---
Log message:
Suppress debug label when not debug.
---
Diffs of the changes: (+1 -1)
PPCRegisterInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.54
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.54Fri Apr 7 11:34:45 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 03:11:53 2006
@@ -407,7 +407,7 @@
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
}
- if (DebugInfo) {
+ if (DebugInfo && DebugInfo->hasInfo()) {
std::vector &Moves = DebugInfo->getFrameMoves();
unsigned LabelID = DebugInfo->NextLabelID();
___
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[llvm-commits] CVS: llvm/CREDITS.TXT
Changes in directory llvm: CREDITS.TXT updated: 1.48 -> 1.49 --- Log message: Update credibility. --- Diffs of the changes: (+1 -0) CREDITS.TXT |1 + 1 files changed, 1 insertion(+) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.48 llvm/CREDITS.TXT:1.49 --- llvm/CREDITS.TXT:1.48 Tue Apr 11 00:48:40 2006 +++ llvm/CREDITS.TXTTue Apr 11 03:16:45 2006 @@ -89,6 +89,7 @@ N: Jim Laskey E: [EMAIL PROTECTED] D: Improvements to the PPC backend, instruction scheduling +D: Debug implementation, Dwarf implementation N: Chris Lattner E: [EMAIL PROTECTED] ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.74 -> 1.75 --- Log message: Misc. intrinsics. --- Diffs of the changes: (+13 -13) X86InstrSSE.td | 26 +- 1 files changed, 13 insertions(+), 13 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.74 llvm/lib/Target/X86/X86InstrSSE.td:1.75 --- llvm/lib/Target/X86/X86InstrSSE.td:1.74 Tue Apr 11 01:57:30 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 12:35:57 2006 @@ -1516,18 +1516,18 @@ Imp<[EDI],[]>; // Prefetching loads -def PREFETCHT0 : I<0x18, MRM1m, (ops i8mem:$src), - "prefetcht0 $src", []>, TB, - Requires<[HasSSE1]>; -def PREFETCHT1 : I<0x18, MRM2m, (ops i8mem:$src), - "prefetcht0 $src", []>, TB, - Requires<[HasSSE1]>; -def PREFETCHT2 : I<0x18, MRM3m, (ops i8mem:$src), - "prefetcht0 $src", []>, TB, - Requires<[HasSSE1]>; -def PREFETCHTNTA : I<0x18, MRM0m, (ops i8mem:$src), - "prefetcht0 $src", []>, TB, - Requires<[HasSSE1]>; +def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), + "prefetcht0 $src", + [(int_x86_sse_prefetch addr:$src, 1)]>; +def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), + "prefetcht1 $src", + [(int_x86_sse_prefetch addr:$src, 2)]>; +def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), + "prefetcht2 $src", + [(int_x86_sse_prefetch addr:$src, 3)]>; +def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src), + "prefetchtnta $src", + [(int_x86_sse_prefetch addr:$src, 0)]>; // Non-temporal stores def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), @@ -1546,7 +1546,7 @@ // Store fence def SFENCE : I<0xAE, MRM7m, (ops), - "sfence", []>, TB, Requires<[HasSSE1]>; + "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>; // MXCSR register def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.16 -> 1.17
---
Log message:
Misc. intrinsics.
---
Diffs of the changes: (+2 -1)
IntrinsicsX86.td |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.16
llvm/include/llvm/IntrinsicsX86.td:1.17
--- llvm/include/llvm/IntrinsicsX86.td:1.16 Tue Apr 11 01:56:27 2006
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 12:35:57 2006
@@ -140,7 +140,8 @@
// Cacheability support ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">,
- Intrinsic<[llvm_ptr_ty, llvm_int_ty], [IntrWriteMem]>;
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_int_ty], [IntrWriteMem]>;
def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
Intrinsic<[llvm_void_ty, llvm_ptr_ty,
llvm_v4f32_ty], [IntrWriteMem]>;
___
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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.17 -> 1.18
---
Log message:
gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support
later.
---
Diffs of the changes: (+0 -3)
IntrinsicsX86.td |3 ---
1 files changed, 3 deletions(-)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.17
llvm/include/llvm/IntrinsicsX86.td:1.18
--- llvm/include/llvm/IntrinsicsX86.td:1.17 Tue Apr 11 12:35:57 2006
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 13:04:57 2006
@@ -139,9 +139,6 @@
// Cacheability support ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
- def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">,
- Intrinsic<[llvm_void_ty, llvm_ptr_ty,
- llvm_int_ty], [IntrWriteMem]>;
def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
Intrinsic<[llvm_void_ty, llvm_ptr_ty,
llvm_v4f32_ty], [IntrWriteMem]>;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.75 -> 1.76 --- Log message: gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support later. --- Diffs of the changes: (+4 -8) X86InstrSSE.td | 12 1 files changed, 4 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.75 llvm/lib/Target/X86/X86InstrSSE.td:1.76 --- llvm/lib/Target/X86/X86InstrSSE.td:1.75 Tue Apr 11 12:35:57 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 13:04:57 2006 @@ -1517,17 +1517,13 @@ // Prefetching loads def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), - "prefetcht0 $src", - [(int_x86_sse_prefetch addr:$src, 1)]>; + "prefetcht0 $src", []>; def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), - "prefetcht1 $src", - [(int_x86_sse_prefetch addr:$src, 2)]>; + "prefetcht1 $src", []>; def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), - "prefetcht2 $src", - [(int_x86_sse_prefetch addr:$src, 3)]>; + "prefetcht2 $src", []>; def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src), - "prefetchtnta $src", - [(int_x86_sse_prefetch addr:$src, 0)]>; + "prefetchtnta $src", []>; // Non-temporal stores def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC: README_ALTIVEC.txt updated: 1.19 -> 1.20 --- Log message: we have a shuffle instr, add an example. --- Diffs of the changes: (+6 -5) README_ALTIVEC.txt | 11 ++- 1 files changed, 6 insertions(+), 5 deletions(-) Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.19 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.20 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.19 Thu Apr 6 18:16:19 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Tue Apr 11 13:47:03 2006 @@ -96,11 +96,6 @@ //===--===// -We need an LLVM 'shuffle' instruction, that corresponds to the VECTOR_SHUFFLE -node. - -//===--===// - We need a way to teach tblgen that some operands of an intrinsic are required to be constants. The verifier should enforce this constraint. @@ -133,4 +128,10 @@ of instructions (e.g. a vsldoi + vpkuhum). We should pattern match these, but there are a huge number of these. +Specific examples: + +C = vector_shuffle A, B, <0, 1, 2, 4> +-> t = vsldoi A, A, 12 +-> C = vsldoi A, B, 4 + //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.55 -> 1.56
---
Log message:
Fix PR727: http://llvm.cs.uiuc.edu/PR727 , correctly handling large stack
aligments on ppc
---
Diffs of the changes: (+28 -32)
PPCRegisterInfo.cpp | 60
1 files changed, 28 insertions(+), 32 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55Tue Apr 11 03:11:53 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 14:29:21 2006
@@ -202,12 +202,10 @@
const MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
- // If frame pointers are forced, if there are variable sized stack objects,
- // or if there is an object on the stack that requires more alignment than is
- // normally provided, use a frame pointer.
+ // If frame pointers are forced, or if there are variable sized stack
objects,
+ // use a frame pointer.
//
- return NoFramePointerElim || MFI->hasVarSizedObjects() ||
- MFI->getMaxAlignment() > TargetAlign;
+ return NoFramePointerElim || MFI->hasVarSizedObjects();
}
void PPCRegisterInfo::
@@ -396,15 +394,26 @@
int NegNumbytes = -NumBytes;
// Adjust stack pointer: r1 -= numbytes.
- if (NumBytes <= 32768) {
-BuildMI(MBB, MBBI, PPC::STWU, 3)
- .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
+ // If there is a preferred stack alignment, align R1 now
+ if (MaxAlign > TargetAlign) {
+assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid
alignment!");
+assert(NumBytes <= 32768 && "Unhandled stack size and alignment combo!");
+BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
+ .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
+BuildMI(MBB, MBBI,
PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0).addSImm(MaxAlign);
+BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R0).addReg(PPC::R0)
+ .addSImm(NegNumbytes);
+BuildMI(MBB, MBBI, PPC::STWUX, 3)
+ .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+ } else if (NumBytes <= 32768) {
+BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes)
+ .addReg(PPC::R1);
} else {
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
-BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
-.addReg(PPC::R0).addImm(NegNumbytes & 0x);
-BuildMI(MBB, MBBI, PPC::STWUX, 3)
-.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
+ .addImm(NegNumbytes & 0x);
+BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
+ .addReg(PPC::R0);
}
if (DebugInfo && DebugInfo->hasInfo()) {
@@ -419,19 +428,6 @@
BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID);
}
- // If there is a preferred stack alignment, align R1 now
- // FIXME: If this ever matters, this could be made more efficient by folding
- // this into the code above, so that we don't issue two store+update
- // instructions.
- if (MaxAlign > TargetAlign) {
-assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid
alignment!");
-BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
- .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
-BuildMI(MBB, MBBI, PPC::SUBFIC,
2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign);
-BuildMI(MBB, MBBI, PPC::STWUX, 3)
- .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
- }
-
// If there is a frame pointer, copy R1 (SP) into R31 (FP)
if (HasFP) {
BuildMI(MBB, MBBI, PPC::STW, 3)
@@ -446,8 +442,12 @@
assert(MBBI->getOpcode() == PPC::BLR &&
"Can only insert epilog into returning blocks");
+ // Get alignment info so we know how to restore r1
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
+
// Get the number of bytes allocated from the FrameInfo.
- unsigned NumBytes = MF.getFrameInfo()->getStackSize();
+ unsigned NumBytes = MFI->getStackSize();
unsigned GPRSize = 4;
if (NumBytes != 0) {
@@ -460,15 +460,11 @@
// The loaded (or persistent) stack pointer value is offseted by the 'stwu'
// on entry to the function. Add this offset back now.
-if (NumBytes < 32768) {
+if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
.addReg(PPC::R1).addSImm(NumBytes);
} else {
- BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16);
- BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
- .addReg(PPC::R0).addImm(NumBytes & 0x);
- BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1)
-.addReg(PPC::R0).addReg(PPC::R1);
+ BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).a
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.56 -> 1.57
---
Log message:
Fix SingleSource/UnitTests/Vector/sumarray-dbl
---
Diffs of the changes: (+3 -4)
PPCRegisterInfo.cpp |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.57
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56Tue Apr 11 14:29:21 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 14:44:43 2006
@@ -397,12 +397,11 @@
// If there is a preferred stack alignment, align R1 now
if (MaxAlign > TargetAlign) {
assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid
alignment!");
-assert(NumBytes <= 32768 && "Unhandled stack size and alignment combo!");
+assert(isInt16(MaxAlign-NumBytes) && "Unhandled stack size and
alignment!");
BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
-BuildMI(MBB, MBBI,
PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0).addSImm(MaxAlign);
-BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R0).addReg(PPC::R0)
- .addSImm(NegNumbytes);
+BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
+ .addSImm(MaxAlign-NumBytes);
BuildMI(MBB, MBBI, PPC::STWUX, 3)
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
} else if (NumBytes <= 32768) {
___
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[llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html
Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.5 -> 1.6 --- Log message: First pass over Reid's document. Changed the order of operations so that more of the fine tuning is performed in the release branch. This should free up mainline sooner to resume development. Removed information on the special release Makefile targets as I've never used them for a release; Tanya is investigating their integration, and they can be re-added if she uses them. Added an outline for building the LLVM GCC binary distributions. I will be filling that section out later (but before the 1.7 release). --- Diffs of the changes: (+186 -42) HowToReleaseLLVM.html | 228 -- 1 files changed, 186 insertions(+), 42 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.5 llvm/docs/HowToReleaseLLVM.html:1.6 --- llvm/docs/HowToReleaseLLVM.html:1.5 Tue Apr 11 01:22:15 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 15:24:28 2006 @@ -24,9 +24,21 @@ This document collects information about successfully releasing LLVM to the public. It is the release manager's guide to ensuring that a high quality build -of LLVM is released. Mostly, its just a bunch of reminders of things to do at +of LLVM is released. Mostly, it's just a bunch of reminders of things to do at release time so we don't inadvertently ship something that is utility deficient. + + +There are three main tasks for building a release of LLVM: + + Create the LLVM source distribution. + Create the LLVM GCC source distribtuion. + Create a set of LLVM GCC binary distribtuions for each supported + platform. These binary distributions must include compiled versions + of the libraries found in llvm/runtime from the LLVM + source distribution created in Step 1. + + @@ -37,46 +49,143 @@ Process Overview +Update Documentation Merge Branches +Make LibDeps.txt Settle LLVM HEAD +Tag LLVM and Create the Release Branch Build LLVM Run 'make check' Run LLVM Test Suite -make LibDeps.txt -cvs tag -make dist -release +Build the LLVM Source Distributions +Build the LLVM GCC Binary Distribution +Update Documentation + + + Review the documentation and ensure that it is up to date. The Release Notes + must be updated to reflect bug fixes, new known issues, and changes in the + list of supported platforms. The Getting Started Guide should be updated to + reflect the new release version number tag avaiable from CVS and changes in + basic system requirements. + + + + Merge Branches -Merge any work done on branches intended for release into mainline. Work that -is not to be incorporated into the release should not be merged from the branch. + +Merge any work done on branches intended for release into mainline. Finish and +commit all new features or bug fixes that are scheduled to go into the release. +Work that is not to be incorporated into the release should not be merged from +branchs or commited from developer's working directories. + + + +From this point until the release branch is created, developers should +not +commit changes to the llvm and llvm-gcc CVS repositories unless it is a bug +fix for the release. +Make LibDeps.txt + + Rebuild the LibDeps.txt target in utils/llvm-config. This + makes sure that the llvm-config utility remains relevant for the + release, reflecting any changes in the library dependencies. + + + + Settle CVS HEAD - Use the nightly test reports, and 'make check' (deja-gnu based tests) to - increase the quality of LLVM and ensure that merged branches have not - destabilized LLVM. + + Use the nightly test reports and 'make check' (deja-gnu based tests) to + ensure that recent changes and merged branches have not destabilized LLVM. + Platforms which are used less often should be given special attention as they + are the most likely to break from commits from the previous step. + + + + +CVS Tag And Branch + + Tag and branch the CVS HEAD using the following procedure: + + +Request all developers to refrain from committing. Offenders get commit +rights taken away (temporarily). + + + +The Release Manager updates his/her llvm, llvm-test, and llvm-gcc source +trees with the +latest sources from mainline CVS. The Release Manage may want to consider +using a new working directory for this to keep current uncommitted work +separate from release work. + + + +The Release Manager tags his/her llvm, llvm-test, and llvm-gcc working +directories with +"ROOT_RELEASE_XX" where XX is the major and minor +release numbers (you can't have . in a cvs tag name). So, for Release 1.2, +XX=12 and for Release 1.10, XX=110. + + + +Immediately create cvs branches based on the ROOT_RELEASE_XX tag. The tag +should be "release_XX" (where XX matches that
[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.127 -> 1.128 --- Log message: new dag node --- Diffs of the changes: (+8 -0) SelectionDAGNodes.h |8 1 files changed, 8 insertions(+) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.127 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.128 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.127 Sat Apr 8 17:16:01 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Tue Apr 11 16:30:42 2006 @@ -113,6 +113,14 @@ // UNDEF - An undefined node UNDEF, + +/// FORMAL_ARGUMENTS(CC#, ISVARARG) - This node represents the formal +/// arguments for a function. CC# is a Constant value indicating the +/// calling convention of the function, and ISVARARG is a flag that +/// indicates whether the function is varargs or not. This node has one +/// result value for each incoming argument, and is typically custom +/// legalized. +FORMAL_ARGUMENTS, // EXTRACT_ELEMENT - This is used to get the first or second (determined by // a Constant, which is required to be operand #1), element of the aggregate ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html
Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.6 -> 1.7 --- Log message: Add the contents of my email about distribution targets as a new section. Attribute John as an author. --- Diffs of the changes: (+170 -3) HowToReleaseLLVM.html | 173 +- 1 files changed, 170 insertions(+), 3 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.6 llvm/docs/HowToReleaseLLVM.html:1.7 --- llvm/docs/HowToReleaseLLVM.html:1.6 Tue Apr 11 15:24:28 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 16:59:37 2006 @@ -12,9 +12,11 @@ Introduction Release Process + Distribution Make Targets - Written by mailto:[EMAIL PROTECTED]">Reid Spencer + Written by mailto:[EMAIL PROTECTED]">Reid Spencer, + mailto:[EMAIL PROTECTED]">John Criswell @@ -273,7 +275,6 @@ Release Release the distribution tarball to the public. This consists of generating @@ -291,6 +292,172 @@ --> +Distribution Make Targets + + +Overview + +The first thing you need to understand is that there are multiple make +targets to support this feature. Here's an overview, we'll delve into the +details later. + + distdir - builds the distribution directory from which the + distribution will be packaged + dist - builds each of the distribution tarballs (tar.gz, + tar.bzip2, .zip). These can be built individually as well, with separate + targets. + dist-check - this is identical to dist but includes a + check on the distribution that ensures the tarball can: unpack successfully, + compile correctly, pass 'make check', and pass 'make clean'. + dist-clean- this just does a normal clean but also cleans up the + stuff generated by the other three dist targets (above). + +Okay, that's the basic functionality. When making a release, we want to +ensure that the tree you build the distribution from passes +dist-check. Beyond fixing the usual bugs, there is generally one +impediment to making the release in this fashion: missing files. The +dist-check process guards against that possibility. It will either +fail and that failure will indicate what's missing, or it will succeed +meaning that it has proved that the tarballs can actually succeed in +building LLVM correctly and that it passes make check. + +distdir +This target builds the distribution directory which is the directory from +which the tarballs are generated. The distribution directory has the same +name as the release, e.g. LLVM-1.7). This target goes through the following +process: + + First, if there was an old distribution directory (for the current + release), it is removed in its entirety and you see Removing old + LLVM-1.7 + Second, it issues a make all ENABLE_OPTIMIZED=3D1 to ensure + that the everything in your tree can be built in release mode. Often times + there are discrepancies in building between debug and release modes so it + enforces release mode first. If that fails, the distdir target + fails too. This is preceded by the message Making 'all' to verify + build. + Next, it traverses your source tree and copies it to a new directory + that has the name of the release (LLVM-M.m in our current case). + This is the directory that will get tar'd. It contains all the software + that needs to be in the distribution. During the copying process, it omits + generated files, CVS directories, and any other "cruft" that's in your + build tree. This is done to eliminate the possibility of huge distribution + tarballs that include useless or irrelevant stuff in them. This is the + trickiest part of making the distribution. Done manually you will either + include stuff that shouldn't be in the distribution or exclude stuff that + should. This step is preceded by the message Building Distribution + Directory LLVM-1.7 + The distribution directory is then traversed and all CVS or + .svn directories are removed. You see: Eliminating CVS/.svn + directories from distribution + The recursive dist-hook target is executed. This gives each + directory a chance to modify the distribution in some way (more on this + below). + The distribution directory is traversed and the correct file + permissions and modes are set based on the type of file. + +To control the process of making the distribution directory correctly, +each Makefile can utilize two features: + + EXTRA_DIST - this make variable specifies which files + it should distribute. By default, all source files are automatically + included for distribution as well as certain well known files + (see DistAlways variable in Makefile.rules for details). Each Makefile + specifies, via the EXTRA_DIST variable, which additional files + need to be distributed. Only those files that are needed to build LLVM + should be added to EXTRA_DIST. EXTRA_DIST contains a + list of file or directory names that should be distributed. For example, + t
[llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html
Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.7 -> 1.8 --- Log message: Don't overload anchor names, silly browser's can't handle it. --- Diffs of the changes: (+3 -3) HowToReleaseLLVM.html |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.7 llvm/docs/HowToReleaseLLVM.html:1.8 --- llvm/docs/HowToReleaseLLVM.html:1.7 Tue Apr 11 16:59:37 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 17:02:18 2006 @@ -12,7 +12,7 @@ Introduction Release Process - Distribution Make Targets + Distribution Targets Written by mailto:[EMAIL PROTECTED]">Reid Spencer, @@ -292,7 +292,7 @@ --> -Distribution Make Targets +Distribution Targets Overview @@ -468,7 +468,7 @@ mailto:[EMAIL PROTECTED]">Reid Spencer http://llvm.cs.uiuc.edu";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/04/11 21:59:37 $ + Last modified: $Date: 2006/04/11 22:02:18 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.18 -> 1.19
---
Log message:
Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si,
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.
---
Diffs of the changes: (+11 -0)
IntrinsicsX86.td | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.18
llvm/include/llvm/IntrinsicsX86.td:1.19
--- llvm/include/llvm/IntrinsicsX86.td:1.18 Tue Apr 11 13:04:57 2006
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 17:28:25 2006
@@ -269,6 +269,8 @@
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_loadu_pd : GCCBuiltin<"__builtin_ia32_loadupd">,
Intrinsic<[llvm_v2f64_ty, llvm_ptr_ty], [IntrReadMem]>;
+ def int_x86_sse2_loadu_dq : GCCBuiltin<"__builtin_ia32_loaddqu">,
+ Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>;
}
// SIMD store ops
@@ -276,6 +278,12 @@
def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">,
Intrinsic<[llvm_void_ty, llvm_ptr_ty,
llvm_v2f64_ty], [IntrWriteMem]>;
+ def int_x86_sse2_storeu_dq : GCCBuiltin<"__builtin_ia32_storedqu">,
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_v16i8_ty], [IntrWriteMem]>;
+ def int_x86_sse2_storel_dq : GCCBuiltin<"__builtin_ia32_storelv4si">,
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_v4i32_ty], [IntrWriteMem]>;
}
// Cacheability support ops
@@ -302,6 +310,9 @@
def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">,
Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem]>;
+ // FIXME: Temporary workaround since 2-wide shuffle is broken.
+ def int_x86_sse2_movl_dq : GCCBuiltin<"__builtin_ia32_movqv4si">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">,
Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>;
def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.76 -> 1.77
---
Log message:
Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si,
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.
---
Diffs of the changes: (+21 -2)
X86InstrSSE.td | 23 +--
1 files changed, 21 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.76
llvm/lib/Target/X86/X86InstrSSE.td:1.77
--- llvm/lib/Target/X86/X86InstrSSE.td:1.76 Tue Apr 11 13:04:57 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 17:28:25 2006
@@ -724,6 +724,14 @@
def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
"movupd {$src, $dst|$dst, $src}",
[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
+def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
+ "movdqu {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
+ XS, Requires<[HasSSE2]>;
+def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
+ "movdqu {$src, $dst|$dst, $src}",
+ [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
+ XS, Requires<[HasSSE2]>;
let isTwoAddress = 1 in {
def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
@@ -1657,6 +1665,16 @@
MOVS_shuffle_mask)))]>;
}
+// Store / copy lower 64-bits of a XMM register.
+def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
+ "movq {$src, $dst|$dst, $src}",
+ [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
+
+// FIXME: Temporary workaround since 2-wide shuffle is broken.
+def MOVLQ128rr : PDI<0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "movq {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>;
+
// Move to lower bits of a VR128 and zeroing upper bits.
// Loading from memory automatically zeroing upper bits.
def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
@@ -1672,9 +1690,10 @@
[(set VR128:$dst,
(v4i32 (X86zexts2vec (loadi32 addr:$src]>;
def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
- "movd {$src, $dst|$dst, $src}",
+ "movq {$src, $dst|$dst, $src}",
[(set VR128:$dst,
- (v2i64 (X86zexts2vec (loadi64 addr:$src]>;
+ (bc_v2i64 (v2f64 (X86zexts2vec
+ (loadf64 addr:$src)]>;
//===--===//
// Non-Instruction Patterns
___
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[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.360 -> 1.361 --- Log message: Remove extraneous building in target dist-check. There is no reason that a distribution should need to be able to make a distribution so eliminate the "make dist" from the list of targets attempted. --- Diffs of the changes: (+0 -2) Makefile.rules |2 -- 1 files changed, 2 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.360 llvm/Makefile.rules:1.361 --- llvm/Makefile.rules:1.360 Mon Apr 10 11:46:04 2006 +++ llvm/Makefile.rules Tue Apr 11 22:07:02 2006 @@ -1502,8 +1502,6 @@ $(MAKE) check && \ $(MAKE) install && \ $(MAKE) uninstall && \ - $(MAKE) dist && \ - $(MAKE) clean && \ $(MAKE) dist-clean && \ $(EchoCmd) = $(DistTarGZip) Ready For Distribution = ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll
Changes in directory llvm/test/Regression/CodeGen/Generic:
2006-04-11-vecload.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+12 -0)
2006-04-11-vecload.ll | 12
1 files changed, 12 insertions(+)
Index: llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll:1.1
*** /dev/null Tue Apr 11 22:24:56 2006
--- llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll Tue Apr 11
22:24:46 2006
***
*** 0
--- 1,12
+ ; RUN: llvm-as < %s | llc
+
+ ; The vload was getting memoized to the previous scalar load!
+
+ void %VertexProgram2() {
+ %xFloat0.688 = load float* null ; [#uses=0]
+ %loadVector37.712 = load <4 x float>* null ; <<4 x
float>> [#uses=1]
+ %inFloat3.713 = insertelement <4 x float> %loadVector37.712, float
0.00e+00, uint 3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %inFloat3.713, <4 x float>* null
+ unreachable
+ }
+
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.297 -> 1.298
---
Log message:
Don't memoize vloads in the load map! Don't memoize them anywhere here, let
getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll
---
Diffs of the changes: (+0 -2)
SelectionDAG.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.297
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.298
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.297Sat Apr 8
17:22:57 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Apr 11 22:25:41 2006
@@ -1508,8 +1508,6 @@
SDOperand SelectionDAG::getVecLoad(unsigned Count, MVT::ValueType EVT,
SDOperand Chain, SDOperand Ptr,
SDOperand SV) {
- SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, EVT))];
- if (N) return SDOperand(N, 0);
std::vector Ops;
Ops.reserve(5);
Ops.push_back(Chain);
___
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[llvm-commits] CVS: llvm-www/OpenProjects.html
Changes in directory llvm-www: OpenProjects.html updated: 1.12 -> 1.13 --- Log message: Nate went and did one of the projects, so remove it. The skeleton backend is no more. --- Diffs of the changes: (+1 -17) OpenProjects.html | 18 +- 1 files changed, 1 insertion(+), 17 deletions(-) Index: llvm-www/OpenProjects.html diff -u llvm-www/OpenProjects.html:1.12 llvm-www/OpenProjects.html:1.13 --- llvm-www/OpenProjects.html:1.12 Thu Mar 16 13:02:22 2006 +++ llvm-www/OpenProjects.html Tue Apr 11 23:18:36 2006 @@ -304,8 +304,6 @@ Improve the instruction selectors. -Implement support for the "switch" instruction without requiring the -lower-switches pass. Implement interprocedural register allocation. The CallGraphSCCPass can be used to implement a bottom-up analysis that will determine the *actual* registers clobbered by a function. Use the pass to fine tune register usage @@ -314,20 +312,6 @@ (ARM? MIPS? http://www-cs-faculty.stanford.edu/~knuth/mmix.html";>MMIX?) -Improve the usefulness and utility of the Skeleton target backend: - - Convert the non-functional Skeleton target to become an abstract machine - target (choose some simple instructions, a register set, etc). This will - become a much more useful example of a backend since it would be a simple - but functional backend. Examples of such architectures include MIX, - MMIX, http://www.cs.cinvestav.mx/SC/prof_personal/adiaz/vhdl/DLX/";>DLX, - or come up with your own! - Use the new Skeleton backend in the Interpreter: compile LLVM to Skeleton - target, and then interpret that code instead of LLVM. Performance win would - be the primary goal, as the number of registers would be a small constant - instead of unbounded, for example. - @@ -381,7 +365,7 @@ src="http://www.w3.org/Icons/valid-html401"; alt="Valid HTML 4.01!"> http://llvm.org";>LLVM Compiler Infrastructure - Last modified: $Date: 2006/03/16 19:02:22 $ + Last modified: $Date: 2006/04/12 04:18:36 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.19 -> 1.20
---
Log message:
Various SSE2 conversion intrinsics
---
Diffs of the changes: (+24 -0)
IntrinsicsX86.td | 24
1 files changed, 24 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.19
llvm/include/llvm/IntrinsicsX86.td:1.20
--- llvm/include/llvm/IntrinsicsX86.td:1.19 Tue Apr 11 17:28:25 2006
+++ llvm/include/llvm/IntrinsicsX86.td Wed Apr 12 00:20:24 2006
@@ -265,6 +265,30 @@
llvm_int_ty], [IntrNoMem]>;
}
+// Conversion ops
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse2_cvtdq2pd : GCCBuiltin<"__builtin_ia32_cvtdq2pd">,
+ Intrinsic<[llvm_v2f64_ty, llvm_v4i32_ty], [IntrNoMem]>;
+ def int_x86_sse2_cvtdq2ps : GCCBuiltin<"__builtin_ia32_cvtdq2ps">,
+ Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+ def int_x86_sse2_cvtpd2dq : GCCBuiltin<"__builtin_ia32_cvtpd2dq">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v2f64_ty], [IntrNoMem]>;
+ def int_x86_sse2_cvttpd2dq : GCCBuiltin<"__builtin_ia32_cvttpd2dq">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v2f64_ty], [IntrNoMem]>;
+ def int_x86_sse2_cvtpd2ps : GCCBuiltin<"__builtin_ia32_cvtpd2ps">,
+ Intrinsic<[llvm_v4f32_ty, llvm_v2f64_ty], [IntrNoMem]>;
+ def int_x86_sse2_cvtps2dq : GCCBuiltin<"__builtin_ia32_cvtps2dq">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty], [IntrNoMem]>;
+ def int_x86_sse2_cvttps2dq : GCCBuiltin<"__builtin_ia32_cvttps2dq">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty], [IntrNoMem]>;
+ def int_x86_sse2_cvtps2pd : GCCBuiltin<"__builtin_ia32_cvtps2pd">,
+ Intrinsic<[llvm_v2f64_ty, llvm_v4f32_ty], [IntrNoMem]>;
+ def int_x86_sse2_cvtsd2si : GCCBuiltin<"__builtin_ia32_cvtsd2si">,
+ Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>;
+ def int_x86_sse2_cvttsd2si : GCCBuiltin<"__builtin_ia32_cvttsd2si">,
+ Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>;
+}
+
// SIMD load ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_loadu_pd : GCCBuiltin<"__builtin_ia32_loadupd">,
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.77 -> 1.78
---
Log message:
Various SSE2 conversion intrinsics
---
Diffs of the changes: (+94 -39)
X86InstrSSE.td | 133 -
1 files changed, 94 insertions(+), 39 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.77
llvm/lib/Target/X86/X86InstrSSE.td:1.78
--- llvm/lib/Target/X86/X86InstrSSE.td:1.77 Tue Apr 11 17:28:25 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 00:20:24 2006
@@ -524,6 +524,23 @@
[(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
Requires<[HasSSE2]>;
+// Aliases to match intrinsics which expect XMM operand(s).
+def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
+ "cvttsd2si {$src, $dst|$dst, $src}",
+ [(set R32:$dst, (int_x86_sse2_cvttsd2si
VR128:$src))]>;
+def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
+ "cvttsd2si {$src, $dst|$dst, $src}",
+ [(set R32:$dst, (int_x86_sse2_cvttsd2si
+ (load addr:$src)))]>;
+
+def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
+"cvtsd2si {$src, $dst|$dst, $src}",
+[(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
+def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
+"cvtsd2si {$src, $dst|$dst, $src}",
+[(set R32:$dst, (int_x86_sse2_cvtsd2si
+ (load addr:$src)))]>;
+
// Comparison instructions
let isTwoAddress = 1 in {
def CMPSSrr : SSI<0xC2, MRMSrcReg,
@@ -800,62 +817,100 @@
}
// Conversion instructions
-def CVTPI2PSr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
+def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
"cvtpi2ps {$src, $dst|$dst, $src}", []>;
-def CVTPI2PSm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
"cvtpi2ps {$src, $dst|$dst, $src}", []>;
-def CVTPI2PDr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
+def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
"cvtpi2pd {$src, $dst|$dst, $src}", []>;
-def CVTPI2PDm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
"cvtpi2pd {$src, $dst|$dst, $src}", []>;
// SSE2 instructions without OpSize prefix
-def CVTDQ2PSr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB,
-Requires<[HasSSE2]>;
-def CVTDQ2PSm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
- "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB,
-Requires<[HasSSE2]>;
+def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "cvtdq2ps {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
+ TB, Requires<[HasSSE2]>;
+def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
+ "cvtdq2ps {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
+ (load addr:$src)))]>,
+ TB, Requires<[HasSSE2]>;
// SSE2 instructions with XS prefix
-def CVTDQ2PDr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR64:$src),
- "cvtdq2pd {$src, $dst|$dst, $src}", []>,
-XS, Requires<[HasSSE2]>;
-def CVTDQ2PDm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
- "cvtdq2pd {$src, $dst|$dst, $src}", []>,
-XS, Requires<[HasSSE2]>;
+def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "cvtdq2pd {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
+ XS, Requires<[HasSSE2]>;
+def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+ "cvtdq2pd {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
+ (load addr:$src)))]>,
+ XS, Requires<[HasSSE2]>;
-def CVTPS2PIr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
+def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
"cvtps2pi {$src, $dst|$dst, $src}", []>;
-def CVTPS2PIm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
+def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
"cvtps2pi {$src, $dst|$dst, $src}", []>;
-def CVTPD2PIr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
+def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$sr
