[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.135 -> 1.136
---
Log message:
Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available
for SSE1.
---
Diffs of the changes: (+1 -1)
X86RegisterInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.135
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.136
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.135 Fri Apr 7 11:34:46 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Apr 10 02:21:31 2006
@@ -115,7 +115,7 @@
} else if (RC == &X86::FR64RegClass) {
Opc = X86::FsMOVAPDrr;
} else if (RC == &X86::VR128RegClass) {
-Opc = X86::MOVAPDrr;
+Opc = X86::MOVAPSrr;
} else {
assert(0 && "Unknown regclass");
abort();
___
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[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.81 -> 1.82
---
Log message:
New entries
---
Diffs of the changes: (+19 -0)
README.txt | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.81 llvm/lib/Target/X86/README.txt:1.82
--- llvm/lib/Target/X86/README.txt:1.81 Fri Apr 7 16:19:53 2006
+++ llvm/lib/Target/X86/README.txt Mon Apr 10 02:22:03 2006
@@ -765,3 +765,22 @@
A Mac OS X IA-32 specific ABI bug wrt returning value > 8 bytes:
http://llvm.org/bugs/show_bug.cgi?id=729
+
+//===-===//
+
+#include
+
+void test(__m128 *res, __m128 *A) {
+ *res = _mm_shuffle_ps(*A, *A, 0xF0);
+}
+
+We should emit
+ shufps $240, (%eax), %xmm0
+instead of
+ pshufd $240, (%eax), %xmm0
+
+//===-===//
+
+X86RegisterInfo::copyRegToReg() returns X86::MOVAPSrr for VR128. Is it possible
+to choose between movaps, movapd, and movdqa based on types of source and
+destination?
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.160 -> 1.161
X86InstrSSE.td updated: 1.68 -> 1.69
---
Log message:
Conditional move of vector types.
---
Diffs of the changes: (+63 -37)
X86ISelLowering.cpp | 85 +---
X86InstrSSE.td | 15 +
2 files changed, 63 insertions(+), 37 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.160
llvm/lib/Target/X86/X86ISelLowering.cpp:1.161
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.160 Fri Apr 7 16:53:05 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 10 02:23:14 2006
@@ -275,13 +275,14 @@
if (Subtarget->hasSSE1()) {
addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
-setOperationAction(ISD::ADD, MVT::v4f32, Legal);
-setOperationAction(ISD::SUB, MVT::v4f32, Legal);
-setOperationAction(ISD::MUL, MVT::v4f32, Legal);
-setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
-setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
+setOperationAction(ISD::ADD,MVT::v4f32, Legal);
+setOperationAction(ISD::SUB,MVT::v4f32, Legal);
+setOperationAction(ISD::MUL,MVT::v4f32, Legal);
+setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
+setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
+setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
}
if (Subtarget->hasSSE2()) {
@@ -291,37 +292,46 @@
addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
-
-setOperationAction(ISD::ADD, MVT::v2f64, Legal);
-setOperationAction(ISD::ADD, MVT::v16i8, Legal);
-setOperationAction(ISD::ADD, MVT::v8i16, Legal);
-setOperationAction(ISD::ADD, MVT::v4i32, Legal);
-setOperationAction(ISD::SUB, MVT::v2f64, Legal);
-setOperationAction(ISD::SUB, MVT::v16i8, Legal);
-setOperationAction(ISD::SUB, MVT::v8i16, Legal);
-setOperationAction(ISD::SUB, MVT::v4i32, Legal);
-setOperationAction(ISD::MUL, MVT::v2f64, Legal);
-setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
-setOperationAction(ISD::LOAD, MVT::v16i8, Legal);
-setOperationAction(ISD::LOAD, MVT::v8i16, Legal);
-setOperationAction(ISD::LOAD, MVT::v4i32, Legal);
-setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
-setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
-setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
-setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
-setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
-setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom);
-setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
-setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
+setOperationAction(ISD::ADD,MVT::v2f64, Legal);
+setOperationAction(ISD::ADD,MVT::v16i8, Legal);
+setOperationAction(ISD::ADD,MVT::v8i16, Legal);
+setOperationAction(ISD::ADD,MVT::v4i32, Legal);
+setOperationAction(ISD::SUB,MVT::v2f64, Legal);
+setOperationAction(ISD::SUB,MVT::v16i8, Legal);
+setOperationAction(ISD::SUB,MVT::v8i16, Legal);
+setOperationAction(ISD::SUB,MVT::v4i32, Legal);
+setOperationAction(ISD::MUL,MVT::v2f64, Legal);
+setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
+setOperationAction(ISD::LOAD, MVT::v16i8, Legal);
+setOperationAction(ISD::LOAD, MVT::v8i16, Legal);
+setOperationAction(ISD::LOAD, MVT::v4i32, Legal);
+setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
+setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
+setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
+setOperationAction(ISD::BUILD_VECTOR,
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_select.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
vec_select.ll added (r1.1)
---
Log message:
Add a vselect test case.
---
Diffs of the changes: (+11 -0)
vec_select.ll | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/vec_select.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/vec_select.ll:1.1
*** /dev/null Mon Apr 10 02:30:23 2006
--- llvm/test/Regression/CodeGen/X86/vec_select.ll Mon Apr 10 02:30:13 2006
***
*** 0
--- 1,11
+ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse
+
+ void %test(int %C, <4 x float>* %A, <4 x float>* %B) {
+ %tmp = load <4 x float>* %A
+ %tmp3 = load <4 x float>* %B
+ %tmp9 = mul <4 x float> %tmp3, %tmp3
+ %tmp = seteq int %C, 0
+ %iftmp.38.0 = select bool %tmp, <4 x float> %tmp9, <4 x float> %tmp
+ store <4 x float> %iftmp.38.0, <4 x float>* %A
+ ret void
+ }
___
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[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.359 -> 1.360 --- Log message: ENABLE_ASSERTIONS -> DISABLE_ASSERTIONS --- Diffs of the changes: (+4 -4) Makefile.rules |8 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.359 llvm/Makefile.rules:1.360 --- llvm/Makefile.rules:1.359 Sun Apr 9 18:41:14 2006 +++ llvm/Makefile.rules Mon Apr 10 11:46:04 2006 @@ -222,8 +222,8 @@ endif endif -# If ENABLE_ASSERTIONS=1 is specified (make command line or configured), -# then enable assertions by defining the appropriate preprocessor symbols. +# If DISABLE_ASSERTIONS=1 is specified (make command line or configured), +# then disable assertions by defining the appropriate preprocessor symbols. ifdef DISABLE_ASSERTIONS BuildMode := $(BuildMode)-Asserts CXX.Flags += -DNDEBUG @@ -1527,7 +1527,7 @@ $(EchoCmd) Removing old $(DistDir) ; \ $(RM) -rf $(DistDir); \ $(EchoCmd) Making 'all' to verify build ; \ - $(MAKE) ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 all ; \ + $(MAKE) ENABLE_OPTIMIZED=1 all ; \ fi $(Echo) Building Distribution Directory $(DistDir) $(Verb) $(MKDIR) $(DistDir) @@ -1588,7 +1588,7 @@ if test "$$subdir" \!= "." ; then \ new_distdir="$(DistDir)/$$subdir" ; \ test -d "$$new_distdir" || $(MKDIR) "$$new_distdir" || exit 1; \ - ( cd $$subdir && $(MAKE) ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 \ + ( cd $$subdir && $(MAKE) ENABLE_OPTIMIZED=1 \ DistDir="$$new_distdir" distdir ) || exit 1; \ fi; \ done ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.357 -> 1.358 --- Log message: Missing break --- Diffs of the changes: (+1 -0) LegalizeDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.357 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.358 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.357 Sat Apr 8 17:22:57 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 10 13:54:36 2006 @@ -4773,6 +4773,7 @@ assert(0 && "Cast from unsupported vector type not implemented yet!"); } } +break; case ISD::VSELECT: Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), PackVectorOp(Op.getOperand(1), NewVT), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/IPO/IndMemRemoval.cpp
Changes in directory llvm/lib/Transforms/IPO:
IndMemRemoval.cpp added (r1.1)
---
Log message:
Add a simple pass to make sure that all (non-library) calls to malloc and free
are visible to analysis as intrinsics. That is, make sure someone doesn't pass
free around by address in some struct (as happens in say 176.gcc).
This doesn't get rid of any indirect calls, just ensure calls to free and malloc
are always direct.
---
Diffs of the changes: (+92 -0)
IndMemRemoval.cpp | 92 ++
1 files changed, 92 insertions(+)
Index: llvm/lib/Transforms/IPO/IndMemRemoval.cpp
diff -c /dev/null llvm/lib/Transforms/IPO/IndMemRemoval.cpp:1.1
*** /dev/null Mon Apr 10 14:26:10 2006
--- llvm/lib/Transforms/IPO/IndMemRemoval.cpp Mon Apr 10 14:25:59 2006
***
*** 0
--- 1,92
+ //===-- IndMemRemoval.cpp - Remove indirect allocations and frees
--===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // This pass finds places where memory allocation functions may escape into
+ // indirect land. Some transforms are much easier (aka possible) only if
free
+ // or malloc are not called indirectly.
+ // Thus find places where the address of memory functions are taken and
construct
+ // bounce functions with direct calls of those functions.
+ //
+
//===--===//
+
+ #include "llvm/Transforms/IPO.h"
+ #include "llvm/Pass.h"
+ #include "llvm/Module.h"
+ #include "llvm/Function.h"
+ #include "llvm/Instructions.h"
+ #include "llvm/Type.h"
+ #include "llvm/Support/Debug.h"
+ #include "llvm/ADT/Statistic.h"
+ #include
+ #include
+ #include
+ using namespace llvm;
+
+ namespace {
+ Statistic<> NumBounceSites("indmemrem", "Number of sites modified");
+ Statistic<> NumBounce ("indmemrem", "Number of bounce functions created");
+
+ class IndMemRemPass : public ModulePass {
+
+ public:
+ IndMemRemPass();
+ virtual bool runOnModule(Module &M);
+ };
+ RegisterOpt X("indmemrem", "Indirect Malloc and Free
Removal");
+ } // end anonymous namespace
+
+
+ IndMemRemPass::IndMemRemPass()
+ {
+ }
+
+ bool IndMemRemPass::runOnModule(Module &M) {
+ //in Theory, all direct calls of malloc and free should be promoted
+ //to intrinsics. Therefor, this goes through and finds where the
+ //address of free or malloc are taken and replaces those with bounce
+ //functions, ensuring that all malloc and free that might happen
+ //happens through intrinsics.
+ bool changed = false;
+ if (Function* F = M.getNamedFunction("free")) {
+ assert(F->isExternal() && "free not external?");
+ if (F->getNumUses()) {
+ Function* FN = new Function(F->getFunctionType(),
+ GlobalValue::LinkOnceLinkage,
+ "free_llvm_bounce", &M);
+ BasicBlock* bb = new BasicBlock("entry",FN);
+ Instruction* R = new ReturnInst(bb);
+ new FreeInst(FN->arg_begin(), R);
+ ++NumBounce;
+ NumBounceSites += F->getNumUses();
+ F->replaceAllUsesWith(FN);
+ changed = true;
+ }
+ }
+ if (Function* F = M.getNamedFunction("malloc")) {
+ assert(F->isExternal() && "malloc not external?");
+ if (F->getNumUses()) {
+ Function* FN = new Function(F->getFunctionType(),
+ GlobalValue::LinkOnceLinkage,
+ "malloc_llvm_bounce", &M);
+ BasicBlock* bb = new BasicBlock("entry",FN);
+ Instruction* c = new CastInst(FN->arg_begin(), Type::UIntTy, "c", bb);
+ Instruction* a = new MallocInst(Type::SByteTy, c, "m", bb);
+ Instruction* R = new ReturnInst(a, bb);
+ ++NumBounce;
+ NumBounceSites += F->getNumUses();
+ F->replaceAllUsesWith(FN);
+ changed = true;
+ }
+ }
+ return changed;
+ }
+
+ ModulePass *llvm::createIndMemRemPass() {
+ return new IndMemRemPass();
+ }
___
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[llvm-commits] CVS: llvm/include/llvm/Transforms/IPO.h LinkAllPasses.h
Changes in directory llvm/include/llvm/Transforms: IPO.h updated: 1.44 -> 1.45 LinkAllPasses.h updated: 1.29 -> 1.30 --- Log message: Add a simple pass to make sure that all (non-library) calls to malloc and free are visible to analysis as intrinsics. That is, make sure someone doesn't pass free around by address in some struct (as happens in say 176.gcc). This doesn't get rid of any indirect calls, just ensure calls to free and malloc are always direct. --- Diffs of the changes: (+6 -1) IPO.h |5 + LinkAllPasses.h |2 +- 2 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Transforms/IPO.h diff -u llvm/include/llvm/Transforms/IPO.h:1.44 llvm/include/llvm/Transforms/IPO.h:1.45 --- llvm/include/llvm/Transforms/IPO.h:1.44 Tue Oct 18 01:28:16 2005 +++ llvm/include/llvm/Transforms/IPO.h Mon Apr 10 14:26:09 2006 @@ -169,6 +169,11 @@ // specific well-known (library) functions. ModulePass *createSimplifyLibCallsPass(); + +// createIndMemRemPass - This pass removes potential indirect calls of +// malloc and free +ModulePass *createIndMemRemPass(); + } // End llvm namespace #endif Index: llvm/include/llvm/Transforms/LinkAllPasses.h diff -u llvm/include/llvm/Transforms/LinkAllPasses.h:1.29 llvm/include/llvm/Transforms/LinkAllPasses.h:1.30 --- llvm/include/llvm/Transforms/LinkAllPasses.h:1.29 Wed Feb 22 10:23:43 2006 +++ llvm/include/llvm/Transforms/LinkAllPasses.hMon Apr 10 14:26:09 2006 @@ -107,7 +107,7 @@ (void) llvm::createCondPropagationPass(); (void) llvm::createNullProfilerRSPass(); (void) llvm::createRSProfilingPass(); - + (void) llvm::createIndMemRemPass(); } } ForcePassLinking; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.13 -> 1.14
---
Log message:
__builtin_ia32_loadup{s|d}, __builtin_ia32_storeup{s|d}
---
Diffs of the changes: (+15 -1)
IntrinsicsX86.td | 16 +++-
1 files changed, 15 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.13
llvm/include/llvm/IntrinsicsX86.td:1.14
--- llvm/include/llvm/IntrinsicsX86.td:1.13 Fri Apr 7 19:47:01 2006
+++ llvm/include/llvm/IntrinsicsX86.td Mon Apr 10 16:09:59 2006
@@ -133,7 +133,8 @@
// SIMD store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
- Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_v4f32_ty], [IntrWriteMem]>;
}
// Cacheability support ops
@@ -267,6 +268,19 @@
llvm_int_ty], [InstrNoMem]>;
}
+// SIMD load ops
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse2_loadu_pd : GCCBuiltin<"__builtin_ia32_loadupd">,
+ Intrinsic<[llvm_v2f64_ty, llvm_ptr_ty], [IntrReadMem]>;
+}
+
+// SIMD store ops
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">,
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_v2f64_ty], [IntrWriteMem]>;
+}
+
// Misc.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.69 -> 1.70
---
Log message:
movups / movupd
---
Diffs of the changes: (+10 -6)
X86InstrSSE.td | 16 ++--
1 files changed, 10 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.69
llvm/lib/Target/X86/X86InstrSSE.td:1.70
--- llvm/lib/Target/X86/X86InstrSSE.td:1.69 Mon Apr 10 02:23:14 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 16:11:06 2006
@@ -722,16 +722,20 @@
def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
"movups {$src, $dst|$dst, $src}", []>;
-def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
- "movups {$src, $dst|$dst, $src}", []>;
-def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
- "movups {$src, $dst|$dst, $src}", []>;
+def MOVUPSrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
+ "movups {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
+def MOVUPSmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
+ "movups {$src, $dst|$dst, $src}",
+ [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
"movupd {$src, $dst|$dst, $src}", []>;
def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
- "movupd {$src, $dst|$dst, $src}", []>;
+ "movupd {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
- "movupd {$src, $dst|$dst, $src}", []>;
+ "movupd {$src, $dst|$dst, $src}",
+ [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
let isTwoAddress = 1 in {
def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.70 -> 1.71
---
Log message:
Added some missing shuffle patterns.
---
Diffs of the changes: (+22 -5)
X86InstrSSE.td | 27 ++-
1 files changed, 22 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.70
llvm/lib/Target/X86/X86InstrSSE.td:1.71
--- llvm/lib/Target/X86/X86InstrSSE.td:1.70 Mon Apr 10 16:11:06 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 16:42:19 2006
@@ -1365,7 +1365,7 @@
(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
"pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
[(set VR128:$dst, (v8i16 (vector_shuffle
- (bc_v8i16 (loadv2i64 addr:$src1)),
(undef),
+ (load addr:$src1), (undef),
PSHUFHW_shuffle_mask:$src2)))]>,
XS, Requires<[HasSSE2]>;
@@ -1381,7 +1381,7 @@
(ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
"pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
[(set VR128:$dst, (v8i16 (vector_shuffle
- (bc_v8i16 (loadv2i64 addr:$src1)),
(undef),
+ (load addr:$src1), (undef),
PSHUFLW_shuffle_mask:$src2)))]>,
XD, Requires<[HasSSE2]>;
@@ -1823,11 +1823,28 @@
(v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
SHUFP_int_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
-// Shuffle v4f32 with PSHUF* if others do not match.
+// Special pshuf* cases: folding (bit_convert (loadv2i64 addr)).
+def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src1)), (undef),
+ PSHUFD_shuffle_mask:$src2)),
+ (PSHUFDmi addr:$src1, PSHUFD_shuffle_mask:$src2)>,
+ Requires<[HasSSE2]>;
+def : Pat<(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
+ PSHUFHW_shuffle_mask:$src2)),
+ (PSHUFHWmi addr:$src1, PSHUFHW_shuffle_mask:$src2)>,
+ Requires<[HasSSE2]>;
+def : Pat<(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
+ PSHUFLW_shuffle_mask:$src2)),
+ (PSHUFLWmi addr:$src1, PSHUFHW_shuffle_mask:$src2)>,
+ Requires<[HasSSE2]>;
+
+
+// Special SHUFPSrr case: looks like a PSHUFD, like make both operands src1.
+// FIXME: when we want non two-address code, then we should use PSHUFD!
def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
PSHUFD_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFDri VR128:$src1, PSHUFD_fp_shuffle_mask:$sm))>,
- Requires<[HasSSE2]>;
+ (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1,
PSHUFD_fp_shuffle_mask:$sm))>,
+ Requires<[HasSSE1]>;
+// Shuffle v4f32 with PSHUF* if others do not match.
def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
PSHUFD_fp_shuffle_mask:$sm),
(v4f32 (PSHUFDmi addr:$src1, PSHUFD_fp_shuffle_mask:$sm))>,
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[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.83 -> 1.84
---
Log message:
Remove an entry that is now done.
---
Diffs of the changes: (+0 -13)
README.txt | 13 -
1 files changed, 13 deletions(-)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.83 llvm/lib/Target/X86/README.txt:1.84
--- llvm/lib/Target/X86/README.txt:1.83 Mon Apr 10 16:41:39 2006
+++ llvm/lib/Target/X86/README.txt Mon Apr 10 16:42:57 2006
@@ -768,19 +768,6 @@
//===-===//
-#include
-
-void test(__m128 *res, __m128 *A, __m128 *B) {
- *res = _mm_shuffle_ps(*A, *B, 0xF0);
-}
-
-We should emit
- shufps $240, (%eax), %xmm0
-instead of
- pshufd $240, (%eax), %xmm0
-
-//===-===//
-
X86RegisterInfo::copyRegToReg() returns X86::MOVAPSrr for VR128. Is it possible
to choose between movaps, movapd, and movdqa based on types of source and
destination?
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[llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html
Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.2 -> 1.3 --- Log message: * Remove duplicated table of contents for a section and at the top level * Fix relative links within the file * Add tags around command names and literal file names and directories --- Diffs of the changes: (+15 -26) HowToReleaseLLVM.html | 41 +++-- 1 files changed, 15 insertions(+), 26 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.2 llvm/docs/HowToReleaseLLVM.html:1.3 --- llvm/docs/HowToReleaseLLVM.html:1.2 Fri Mar 24 00:42:09 2006 +++ llvm/docs/HowToReleaseLLVM.html Mon Apr 10 16:43:05 2006 @@ -11,18 +11,7 @@ NOTE: THIS DOCUMENT IS A WORK IN PROGRESS! Introduction - Release Process - -Overview -Merge Branches -Build LLVM -Run 'make check' -Run LLVM Test Suite -make LibDeps.txt -cvs tag -make dist -Release - + Release Process Written by mailto:[EMAIL PROTECTED]">Reid Spencer @@ -48,14 +37,14 @@ Process Overview -Merge Branches -Build LLVM -Run 'make check' -Run LLVM Test Suite -make LibDeps.txt -cvs tag -make dist -release +Merge Branches +Build LLVM +Run 'make check' +Run LLVM Test Suite +make LibDeps.txt +cvs tag +make dist +release @@ -74,8 +63,8 @@ Run 'make check' - Run "make check" and ensure there are no unexpected failures. If there - are, resolve the failures and go back to step 2. + Run make check and ensure there are no unexpected failures. If + there are, resolve the failures and go back to step 2. @@ -88,9 +77,9 @@ Make LibDeps.txt - Rebuild the LibDeps.txt target in utils/llvm-config. This makes sure that - the llvm-config utility remains relevant for the release, reflecting any - changes in the library dependencies. + Rebuild the LibDeps.txt target in utils/llvm-config. This + makes sure that the llvm-config utility remains relevant for the + release, reflecting any changes in the library dependencies. @@ -122,7 +111,7 @@ mailto:[EMAIL PROTECTED]">Reid Spencer http://llvm.cs.uiuc.edu";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/03/24 06:42:09 $ + Last modified: $Date: 2006/04/10 21:43:05 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.82 -> 1.83
---
Log message:
Correct an entry
---
Diffs of the changes: (+2 -2)
README.txt |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.82 llvm/lib/Target/X86/README.txt:1.83
--- llvm/lib/Target/X86/README.txt:1.82 Mon Apr 10 02:22:03 2006
+++ llvm/lib/Target/X86/README.txt Mon Apr 10 16:41:39 2006
@@ -770,8 +770,8 @@
#include
-void test(__m128 *res, __m128 *A) {
- *res = _mm_shuffle_ps(*A, *A, 0xF0);
+void test(__m128 *res, __m128 *A, __m128 *B) {
+ *res = _mm_shuffle_ps(*A, *B, 0xF0);
}
We should emit
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[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.84 -> 1.85
---
Log message:
add a note
---
Diffs of the changes: (+23 -0)
README.txt | 23 +++
1 files changed, 23 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.84 llvm/lib/Target/X86/README.txt:1.85
--- llvm/lib/Target/X86/README.txt:1.84 Mon Apr 10 16:42:57 2006
+++ llvm/lib/Target/X86/README.txt Mon Apr 10 16:51:03 2006
@@ -675,6 +675,29 @@
//===-===//
+Better codegen for:
+
+void f(float a, float b, vector float * out) { *out = (vector float){ a, 0.0,
0.0, b}; }
+void f(float a, float b, vector float * out) { *out = (vector float){ a, b,
0.0, 0}; }
+
+For the later we generate:
+
+_f:
+pxor %xmm0, %xmm0
+movss 8(%esp), %xmm1
+movaps %xmm0, %xmm2
+unpcklps %xmm1, %xmm2
+movss 4(%esp), %xmm1
+unpcklps %xmm0, %xmm1
+unpcklps %xmm2, %xmm1
+movl 12(%esp), %eax
+movaps %xmm1, (%eax)
+ret
+
+This seems like it should use shufps, one for each of a & b.
+
+//===-===//
+
Adding to the list of cmp / test poor codegen issues:
int test(__m128 *A, __m128 *B) {
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[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.62 -> 1.63
---
Log message:
Fix a typo: Instr* -> Intr*
---
Diffs of the changes: (+3 -3)
CodeGenTarget.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.62
llvm/utils/TableGen/CodeGenTarget.cpp:1.63
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.62 Mon Mar 27 18:15:00 2006
+++ llvm/utils/TableGen/CodeGenTarget.cpp Mon Apr 10 17:02:59 2006
@@ -439,13 +439,13 @@
assert(Property->isSubClassOf("IntrinsicProperty") &&
"Expected a property!");
-if (Property->getName() == "InstrNoMem")
+if (Property->getName() == "IntrNoMem")
ModRef = NoMem;
-else if (Property->getName() == "InstrReadArgMem")
+else if (Property->getName() == "IntrReadArgMem")
ModRef = ReadArgMem;
else if (Property->getName() == "IntrReadMem")
ModRef = ReadMem;
-else if (Property->getName() == "InstrWriteArgMem")
+else if (Property->getName() == "IntrWriteArgMem")
ModRef = WriteArgMem;
else if (Property->getName() == "IntrWriteMem")
ModRef = WriteMem;
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[llvm-commits] CVS: llvm/include/llvm/Intrinsics.td IntrinsicsPowerPC.td IntrinsicsX86.td
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.32 -> 1.33
IntrinsicsPowerPC.td updated: 1.23 -> 1.24
IntrinsicsX86.td updated: 1.14 -> 1.15
---
Log message:
Fix a typo: Instr* -> Intr*
---
Diffs of the changes: (+170 -170)
Intrinsics.td| 26 +++
IntrinsicsPowerPC.td | 166 +--
IntrinsicsX86.td | 148 ++---
3 files changed, 170 insertions(+), 170 deletions(-)
Index: llvm/include/llvm/Intrinsics.td
diff -u llvm/include/llvm/Intrinsics.td:1.32
llvm/include/llvm/Intrinsics.td:1.33
--- llvm/include/llvm/Intrinsics.td:1.32Tue Apr 4 16:48:31 2006
+++ llvm/include/llvm/Intrinsics.td Mon Apr 10 17:02:38 2006
@@ -24,24 +24,24 @@
// if correct) to the least aggressive. If no property is set, the worst case
// is assumed (IntrWriteMem).
-// InstrNoMem - The intrinsic does not access memory or have any other side
+// IntrNoMem - The intrinsic does not access memory or have any other side
// effects. It may be CSE'd deleted if dead, etc.
-def InstrNoMem : IntrinsicProperty;
+def IntrNoMem : IntrinsicProperty;
-// InstrReadArgMem - This intrinsic reads only from memory that one of its
+// IntrReadArgMem - This intrinsic reads only from memory that one of its
// arguments points to, but may read an unspecified amount.
-def InstrReadArgMem : IntrinsicProperty;
+def IntrReadArgMem : IntrinsicProperty;
// IntrReadMem - This intrinsic reads from unspecified memory, so it cannot be
// moved across stores. However, it can be reordered otherwise and can be
// deleted if dead.
def IntrReadMem : IntrinsicProperty;
-// InstrWriteArgMem - This intrinsic reads and writes only from memory that one
+// IntrWriteArgMem - This intrinsic reads and writes only from memory that one
// of its arguments points to, but may access an unspecified amount. It has no
// other side effects. This may only be used if the intrinsic doesn't
"capture"
// the argument pointer (e.g. storing it someplace).
-def InstrWriteArgMem : IntrinsicProperty;
+def IntrWriteArgMem : IntrinsicProperty;
// IntrWriteMem - This intrinsic may read or modify unspecified memory or has
// other side effects. It cannot be modified by the optimizer. This is the
@@ -130,14 +130,14 @@
//
def int_gcroot : Intrinsic<[llvm_void_ty, llvm_ptrptr_ty, llvm_ptr_ty]>;
def int_gcread : Intrinsic<[llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty],
-[InstrReadArgMem]>;
+[IntrReadArgMem]>;
def int_gcwrite : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty,
- llvm_ptrptr_ty], [InstrWriteArgMem]>;
+ llvm_ptrptr_ty], [IntrWriteArgMem]>;
//===- Code Generator Intrinsics
--===//
//
-def int_returnaddress : Intrinsic<[llvm_ptr_ty, llvm_uint_ty], [InstrNoMem]>;
-def int_frameaddress : Intrinsic<[llvm_ptr_ty, llvm_uint_ty], [InstrNoMem]>;
+def int_returnaddress : Intrinsic<[llvm_ptr_ty, llvm_uint_ty], [IntrNoMem]>;
+def int_frameaddress : Intrinsic<[llvm_ptr_ty, llvm_uint_ty], [IntrNoMem]>;
def int_stacksave : Intrinsic<[llvm_ptr_ty], [IntrReadMem]>;
def int_stackrestore : Intrinsic<[llvm_void_ty, llvm_ptr_ty]>;
def int_prefetch : Intrinsic<[llvm_void_ty, llvm_ptr_ty,
@@ -149,7 +149,7 @@
//===--- Standard C Library Intrinsics
===//
//
-let Properties = [InstrWriteArgMem] in {
+let Properties = [IntrWriteArgMem] in {
def int_memcpy_i32 : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty,
llvm_uint_ty, llvm_uint_ty]>;
def int_memcpy_i64 : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty,
@@ -164,7 +164,7 @@
llvm_ulong_ty, llvm_uint_ty]>;
}
-let Properties = [InstrNoMem] in {
+let Properties = [IntrNoMem] in {
def int_isunordered_f32 : Intrinsic<[llvm_bool_ty,
llvm_float_ty, llvm_float_ty]>;
def int_isunordered_f64 : Intrinsic<[llvm_bool_ty,
@@ -183,7 +183,7 @@
//
// None of these intrinsics accesses memory at all.
-let Properties = [InstrNoMem] in {
+let Properties = [IntrNoMem] in {
def int_bswap_i16 : Intrinsic<[llvm_ushort_ty, llvm_ushort_ty]>;
def int_bswap_i32 : Intrinsic<[llvm_uint_ty, llvm_uint_ty]>;
def int_bswap_i64 : Intrinsic<[llvm_ulong_ty, llvm_ulong_ty]>;
Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.23
llvm/include/llvm/IntrinsicsPowerPC.td:1.24
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.23 Thu Apr 6 16:12:48 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td Mon Apr 10 17:02:38 2006
@@ -31,35 +31,35 @@
/// vector and returns one. These intrinsics have no side effects.
class PowerPC_Vec_FF_Intrinsic
: PowerPC_Vec_Intrinsic;
+ [llvm_v4f32_ty, llvm_v4f32_ty], [Intr
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.71 -> 1.72
---
Log message:
Remove some bogus patterns; clean up.
---
Diffs of the changes: (+20 -53)
X86InstrSSE.td | 73 +++--
1 files changed, 20 insertions(+), 53 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.71
llvm/lib/Target/X86/X86InstrSSE.td:1.72
--- llvm/lib/Target/X86/X86InstrSSE.td:1.71 Mon Apr 10 16:42:19 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 17:35:16 2006
@@ -128,32 +128,16 @@
return X86::isPSHUFLWMask(N);
}], SHUFFLE_get_pshuflw_imm>;
-// Only use PSHUF* for v4f32 if SHUFP does not match.
-def PSHUFD_fp_shuffle_mask : PatLeaf<(build_vector), [{
- return !X86::isSHUFPMask(N) &&
- X86::isPSHUFDMask(N);
+def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
+ return X86::isPSHUFDMask(N);
}], SHUFFLE_get_shuf_imm>;
-def PSHUFHW_fp_shuffle_mask : PatLeaf<(build_vector), [{
- return !X86::isSHUFPMask(N) &&
- X86::isPSHUFHWMask(N);
-}], SHUFFLE_get_pshufhw_imm>;
-
-def PSHUFLW_fp_shuffle_mask : PatLeaf<(build_vector), [{
- return !X86::isSHUFPMask(N) &&
- X86::isPSHUFLWMask(N);
-}], SHUFFLE_get_pshuflw_imm>;
-
def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
return X86::isSHUFPMask(N);
}], SHUFFLE_get_shuf_imm>;
-// Only use SHUFP for v4i32 if PSHUF* do not match.
-def SHUFP_int_shuffle_mask : PatLeaf<(build_vector), [{
- return !X86::isPSHUFDMask(N) &&
- !X86::isPSHUFHWMask(N) &&
- !X86::isPSHUFLWMask(N) &&
- X86::isSHUFPMask(N);
+def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
+ return X86::isSHUFPMask(N);
}], SHUFFLE_get_shuf_imm>;
//===--===//
@@ -1813,16 +1797,6 @@
(v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
Requires<[HasSSE1]>;
-// Shuffle v4i32 with SHUFP* if others do not match.
-def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
- SHUFP_int_shuffle_mask:$sm),
- (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
- SHUFP_int_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2),
- SHUFP_int_shuffle_mask:$sm),
- (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
- SHUFP_int_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
-
// Special pshuf* cases: folding (bit_convert (loadv2i64 addr)).
def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src1)), (undef),
PSHUFD_shuffle_mask:$src2)),
@@ -1838,33 +1812,26 @@
Requires<[HasSSE2]>;
-// Special SHUFPSrr case: looks like a PSHUFD, like make both operands src1.
-// FIXME: when we want non two-address code, then we should use PSHUFD!
+// Special unary SHUFPSrr case.
+// FIXME: when we want non two-address code, then we should use PSHUFD?
def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
- PSHUFD_fp_shuffle_mask:$sm),
- (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1,
PSHUFD_fp_shuffle_mask:$sm))>,
+ SHUFP_unary_shuffle_mask:$sm),
+ (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1,
SHUFP_unary_shuffle_mask:$sm))>,
Requires<[HasSSE1]>;
-// Shuffle v4f32 with PSHUF* if others do not match.
+// Unary v4f32 shuffle with PSHUF* in order to fold a load.
def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
- PSHUFD_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFDmi addr:$src1, PSHUFD_fp_shuffle_mask:$sm))>,
- Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
- PSHUFHW_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFHWri VR128:$src1, PSHUFHW_fp_shuffle_mask:$sm))>,
- Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
- PSHUFHW_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFHWmi addr:$src1, PSHUFHW_fp_shuffle_mask:$sm))>,
- Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
- PSHUFLW_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFLWri VR128:$src1, PSHUFLW_fp_shuffle_mask:$sm))>,
- Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
- PSHUFLW_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFLWmi addr:$src1, PSHUFLW_fp_shuffle_mask:$sm))>,
+ SHUFP_unary_shuffle_mask:$sm),
+ (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm))>,
Requires<[HasSSE2]>;
+// Special binary v4i32 shuffle cases with SHUFPS.
+def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
+ PSHUFD_binary_shuffle_mask:$sm),
+ (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
+ PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2),
+ PSHUFD_binary_shuffle_mask:$sm),
+
[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll
Changes in directory llvm/test/Regression/Transforms/InstCombine:
vec_shuffle.ll added (r1.1)
---
Log message:
New testcase
---
Diffs of the changes: (+17 -0)
vec_shuffle.ll | 17 +
1 files changed, 17 insertions(+)
Index: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll
diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.1
*** /dev/null Mon Apr 10 17:45:47 2006
--- llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll Mon Apr 10
17:45:37 2006
***
*** 0
--- 1,17
+ ; RUN: llvm-as < %s | opt -instcombine -disable-output &&
+ ; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep vector_shuffle
+
+ %T = type <4 x float>
+
+ implementation
+
+ %T %test1(%T %v1) {
+ %v2 = shufflevector %T %v1, %T undef, <4 x uint>
+ ret %T %v2
+ }
+
+ %T %test2(%T %v1) {
+ %v2 = shufflevector %T %v1, %T %v1, <4 x uint>
+ ret %T %v2
+ }
+
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.462 -> 1.463
---
Log message:
Implement InstCombine/vec_shuffle.ll:test[12]
---
Diffs of the changes: (+62 -0)
InstructionCombining.cpp | 62 +++
1 files changed, 62 insertions(+)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.462
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.463
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.462 Thu Apr 6
14:19:17 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Apr 10 17:45:52 2006
@@ -138,6 +138,7 @@
Instruction *visitBranchInst(BranchInst &BI);
Instruction *visitSwitchInst(SwitchInst &SI);
Instruction *visitExtractElementInst(ExtractElementInst &EI);
+Instruction *visitShuffleVectorInst(ShuffleVectorInst &SVI);
// visitInstruction - Specify what to return for unhandled instructions...
Instruction *visitInstruction(Instruction &I) { return 0; }
@@ -6876,6 +6877,67 @@
return 0;
}
+Instruction *InstCombiner::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
+ Value *LHS = SVI.getOperand(0);
+ Value *RHS = SVI.getOperand(1);
+ Constant *Mask = cast(SVI.getOperand(2));
+
+ bool MadeChange = false;
+
+ if (isa(Mask))
+return ReplaceInstUsesWith(SVI, UndefValue::get(SVI.getType()));
+
+ // Canonicalize shuffle(x,x) -> shuffle(x,undef)
+ if (LHS == RHS) {
+if (isa(LHS)) {
+ // shuffle(undef,undef,mask) -> undef.
+ return ReplaceInstUsesWith(SVI, LHS);
+}
+
+if (!isa(Mask)) {
+ // Remap any references to RHS to use LHS.
+ ConstantPacked *CP = cast(Mask);
+ std::vector Elts;
+ for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i) {
+Elts.push_back(CP->getOperand(i));
+if (isa(CP->getOperand(i)))
+ continue;
+unsigned MV = cast(CP->getOperand(i))->getRawValue();
+if (MV >= e)
+ Elts.back() = ConstantUInt::get(Type::UIntTy, MV & (e-1));
+ }
+ Mask = ConstantPacked::get(Elts);
+}
+SVI.setOperand(1, UndefValue::get(RHS->getType()));
+SVI.setOperand(2, Mask);
+MadeChange = true;
+ }
+
+ if (ConstantPacked *CP = dyn_cast(Mask)) {
+bool isLHSID = true, isRHSID = true;
+
+// Analyze the shuffle.
+for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i) {
+ if (isa(CP->getOperand(i)))
+continue;
+ unsigned MV = cast(CP->getOperand(i))->getRawValue();
+
+ // Is this an identity shuffle of the LHS value?
+ isLHSID &= (MV == i);
+
+ // Is this an identity shuffle of the RHS value?
+ isRHSID &= (MV-e == i);
+}
+
+// Eliminate identity shuffles.
+if (isLHSID) return ReplaceInstUsesWith(SVI, LHS);
+if (isRHSID) return ReplaceInstUsesWith(SVI, RHS);
+ }
+
+ return MadeChange ? &SVI : 0;
+}
+
+
void InstCombiner::removeFromWorkList(Instruction *I) {
WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), I),
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[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll
Changes in directory llvm/test/Regression/Transforms/InstCombine:
vec_shuffle.ll updated: 1.1 -> 1.2
---
Log message:
new testcase
---
Diffs of the changes: (+7 -0)
vec_shuffle.ll |7 +++
1 files changed, 7 insertions(+)
Index: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll
diff -u llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.1
llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.2
--- llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.1 Mon Apr
10 17:45:37 2006
+++ llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll Mon Apr 10
18:06:18 2006
@@ -15,3 +15,10 @@
ret %T %v2
}
+float %test3(%T %A, %T %B, float %f) {
+%C = insertelement %T %A, float %f, uint 0
+%D = shufflevector %T %C, %T %B, <4 x uint>
+%E = extractelement %T %D, uint 1
+ret float %E
+}
+
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.463 -> 1.464
---
Log message:
Implement vec_shuffle.ll:test3
---
Diffs of the changes: (+17 -2)
InstructionCombining.cpp | 19 +--
1 files changed, 17 insertions(+), 2 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.463
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.464
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.463 Mon Apr 10
17:45:52 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Apr 10 18:06:36 2006
@@ -6779,7 +6779,8 @@
static Value *FindScalarElement(Value *V, unsigned EltNo) {
assert(isa(V->getType()) && "Not looking at a vector?");
const PackedType *PTy = cast(V->getType());
- if (EltNo >= PTy->getNumElements()) // Out of range access.
+ unsigned Width = PTy->getNumElements();
+ if (EltNo >= Width) // Out of range access.
return UndefValue::get(PTy->getElementType());
if (isa(V))
@@ -6800,6 +6801,19 @@
// Otherwise, the insertelement doesn't modify the value, recurse on its
// vector input.
return FindScalarElement(III->getOperand(0), EltNo);
+ } else if (ShuffleVectorInst *SVI = dyn_cast(V)) {
+if (isa(SVI->getOperand(2))) {
+ return FindScalarElement(SVI->getOperand(0), 0);
+} else if (ConstantPacked *CP =
+ dyn_cast(SVI->getOperand(2))) {
+ if (isa(CP->getOperand(EltNo)))
+return UndefValue::get(PTy->getElementType());
+ unsigned InEl = cast(CP->getOperand(EltNo))->getValue();
+ if (InEl < Width)
+return FindScalarElement(SVI->getOperand(0), InEl);
+ else
+return FindScalarElement(SVI->getOperand(1), InEl - Width);
+}
}
// Otherwise, we don't know.
@@ -6831,9 +6845,10 @@
// If extracting a specified index from the vector, see if we can recursively
// find a previously computed scalar that was inserted into the vector.
- if (ConstantUInt *IdxC = dyn_cast(EI.getOperand(1)))
+ if (ConstantUInt *IdxC = dyn_cast(EI.getOperand(1))) {
if (Value *Elt = FindScalarElement(EI.getOperand(0), IdxC->getValue()))
return ReplaceInstUsesWith(EI, Elt);
+ }
if (Instruction *I = dyn_cast(EI.getOperand(0)))
if (I->hasOneUse()) {
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[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.56 -> 1.57
---
Log message:
Use existing information.
---
Diffs of the changes: (+14 -3)
DwarfWriter.cpp | 17 ++---
1 files changed, 14 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.56
llvm/lib/CodeGen/DwarfWriter.cpp:1.57
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.56 Fri Apr 7 19:35:59 2006
+++ llvm/lib/CodeGen/DwarfWriter.cppMon Apr 10 18:09:19 2006
@@ -25,6 +25,7 @@
#include "llvm/Support/Mangler.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetFrameInfo.h"
#include
@@ -1829,8 +1830,13 @@
EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister()));
EOL("Register");
}
-
-EmitULEB128Bytes(Src.getOffset() / RI->getStackDirection());
+
+int stackGrowth =
+Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
+ TargetFrameInfo::StackGrowsUp ?
+AddressSize : -AddressSize;
+
+EmitULEB128Bytes(Src.getOffset() / stackGrowth);
EOL("Offset");
} else {
}
@@ -2049,6 +2055,11 @@
/// EmitInitialDebugFrame - Emit common frame info into a debug frame section.
///
void DwarfWriter::EmitInitialDebugFrame() {
+ int stackGrowth =
+ Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
+TargetFrameInfo::StackGrowsUp ?
+ AddressSize : -AddressSize;
+
// Start the dwarf frame section.
Asm->SwitchSection(DwarfFrameSection, 0);
@@ -2061,7 +2072,7 @@
EmitInt8(DW_CIE_VERSION); EOL("CIE Version");
EmitString(""); EOL("CIE Augmentation");
EmitULEB128Bytes(1); EOL("CIE Code Alignment Factor");
- EmitSLEB128Bytes(RI->getStackDirection()); EOL("CIE Data Alignment Factor");
+ EmitSLEB128Bytes(stackGrowth); EOL("CIE Data Alignment Factor");
EmitInt8(RI->getDwarfRegNum(RI->getRARegister())); EOL("CIE RA Column");
std::vector Moves;
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.74 -> 1.75 --- Log message: Use existing information. --- Diffs of the changes: (+0 -5) MRegisterInfo.h |5 - 1 files changed, 5 deletions(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.74 llvm/include/llvm/Target/MRegisterInfo.h:1.75 --- llvm/include/llvm/Target/MRegisterInfo.h:1.74 Fri Apr 7 11:34:45 2006 +++ llvm/include/llvm/Target/MRegisterInfo.hMon Apr 10 18:09:19 2006 @@ -359,11 +359,6 @@ /// address can be found. virtual unsigned getRARegister() const = 0; - /// getStackDirection - This method should return the factor by which stacks - /// grow. The tyical value is -4 which is the grows negatively in 4 byte - /// increments. - virtual int getStackDirection() const; - /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/MRegisterInfo.cpp
Changes in directory llvm/lib/Target:
MRegisterInfo.cpp updated: 1.14 -> 1.15
---
Log message:
Use existing information.
---
Diffs of the changes: (+0 -7)
MRegisterInfo.cpp |7 ---
1 files changed, 7 deletions(-)
Index: llvm/lib/Target/MRegisterInfo.cpp
diff -u llvm/lib/Target/MRegisterInfo.cpp:1.14
llvm/lib/Target/MRegisterInfo.cpp:1.15
--- llvm/lib/Target/MRegisterInfo.cpp:1.14 Fri Apr 7 11:34:45 2006
+++ llvm/lib/Target/MRegisterInfo.cpp Mon Apr 10 18:09:19 2006
@@ -44,13 +44,6 @@
return Allocatable;
}
-/// getStackDirection - This method should return the factor by which stacks
-/// grow. The tyical value is -4 which is the grows negatively in 4 byte
-/// increments.
-int MRegisterInfo::getStackDirection() const {
- return -sizeof(int32_t);
-}
-
/// getLocation - This method should return the actual location of a frame
/// variable given the frame index. The location is returned in ML.
/// Subclasses should override this method for special handling of frame
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.161 -> 1.162
X86ISelLowering.h updated: 1.53 -> 1.54
X86InstrSSE.td updated: 1.72 -> 1.73
---
Log message:
Added support for _mm_move_ss and _mm_move_sd.
---
Diffs of the changes: (+46 -2)
X86ISelLowering.cpp | 29 +++--
X86ISelLowering.h |4
X86InstrSSE.td | 15 +++
3 files changed, 46 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.161
llvm/lib/Target/X86/X86ISelLowering.cpp:1.162
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.161 Mon Apr 10 02:23:14 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 10 19:19:04 2006
@@ -1684,6 +1684,26 @@
return true;
}
+/// isMOVSMask - Return true if the specified VECTOR_SHUFFLE operand
+/// specifies a shuffle of elements that is suitable for input to MOVS{S|D}.
+bool X86::isMOVSMask(SDNode *N) {
+ assert(N->getOpcode() == ISD::BUILD_VECTOR);
+
+ unsigned NumElems = N->getNumOperands();
+ if (NumElems != 2 && NumElems != 4)
+return false;
+
+ if (!isUndefOrEqual(N->getOperand(0), NumElems))
+return false;
+
+ for (unsigned i = 1; i < NumElems; ++i) {
+SDOperand Arg = N->getOperand(i);
+if (!isUndefOrEqual(Arg, i))
+ return false;
+ }
+
+ return true;
+}
/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
/// a splat of a single element.
@@ -2680,6 +2700,10 @@
if (NumElems == 2)
return Op;
+if (X86::isMOVSMask(PermMask.Val))
+ // Leave the VECTOR_SHUFFLE alone. It matches MOVS{S|D}.
+ return Op;
+
if (X86::isUNPCKLMask(PermMask.Val) ||
X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
X86::isUNPCKHMask(PermMask.Val))
@@ -3106,10 +3130,11 @@
// Only do shuffles on 128-bit vector types for now.
if (MVT::getSizeInBits(VT) == 64) return false;
return (Mask.Val->getNumOperands() == 2 ||
- X86::isSplatMask(Mask.Val) ||
+ X86::isSplatMask(Mask.Val) ||
+ X86::isMOVSMask(Mask.Val) ||
X86::isPSHUFDMask(Mask.Val) ||
isPSHUFHW_PSHUFLWMask(Mask.Val) ||
- X86::isSHUFPMask(Mask.Val) ||
+ X86::isSHUFPMask(Mask.Val) ||
X86::isUNPCKLMask(Mask.Val) ||
X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
X86::isUNPCKHMask(Mask.Val));
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.53
llvm/lib/Target/X86/X86ISelLowering.h:1.54
--- llvm/lib/Target/X86/X86ISelLowering.h:1.53 Thu Apr 6 18:23:56 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Mon Apr 10 19:19:04 2006
@@ -233,6 +233,10 @@
/// <0, 0, 1, 1>
bool isUNPCKL_v_undef_Mask(SDNode *N);
+ /// isMOVSMask - Return true if the specified VECTOR_SHUFFLE operand
+ /// specifies a shuffle of elements that is suitable for input to MOVS{S|D}.
+ bool isMOVSMask(SDNode *N);
+
/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a splat of a single element.
bool isSplatMask(SDNode *N);
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.72
llvm/lib/Target/X86/X86InstrSSE.td:1.73
--- llvm/lib/Target/X86/X86InstrSSE.td:1.72 Mon Apr 10 17:35:16 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 19:19:04 2006
@@ -104,6 +104,10 @@
return X86::isMOVLPMask(N);
}]>;
+def MOVS_shuffle_mask : PatLeaf<(build_vector), [{
+ return X86::isMOVSMask(N);
+}]>;
+
def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
return X86::isUNPCKLMask(N);
}]>;
@@ -1641,6 +1645,17 @@
"movsd {$src2, $dst|$dst, $src2}", []>;
def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
R32:$src2),
"movd {$src2, $dst|$dst, $src2}", []>;
+
+def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ "movss {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst,
+ (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
+ MOVS_shuffle_mask)))]>;
+def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ "movsd {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst,
+ (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
+ MOVS_shuffle_mask)))]>;
}
// Move to lower bits of a VR128 and zeroing upper bits.
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunction.h
Changes in directory llvm/include/llvm/CodeGen:
MachineFunction.h updated: 1.57 -> 1.58
---
Log message:
Add helper methods.
---
Diffs of the changes: (+2 -0)
MachineFunction.h |2 ++
1 files changed, 2 insertions(+)
Index: llvm/include/llvm/CodeGen/MachineFunction.h
diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.57
llvm/include/llvm/CodeGen/MachineFunction.h:1.58
--- llvm/include/llvm/CodeGen/MachineFunction.h:1.57Wed Jan 4 07:44:43 2006
+++ llvm/include/llvm/CodeGen/MachineFunction.h Mon Apr 10 20:09:25 2006
@@ -192,8 +192,10 @@
typedef std::vector::const_iterator liveout_iterator;
livein_iterator livein_begin() const { return LiveIns.begin(); }
livein_iterator livein_end() const { return LiveIns.end(); }
+ boollivein_empty() const { return LiveIns.empty(); }
liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
liveout_iterator liveout_end() const { return LiveOuts.end(); }
+ bool liveout_empty() const { return LiveOuts.empty(); }
/// getBlockNumbered - MachineBasicBlocks are automatically numbered when
they
/// are inserted into the machine function. The block number for a machine
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.142 -> 1.143
---
Log message:
Move some return-handling code from lowerarguments to the ISD::RET handling
stuff.
No functionality change.
---
Diffs of the changes: (+9 -20)
PPCISelLowering.cpp | 29 +
1 files changed, 9 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.142
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.143
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.142 Sat Apr 8 17:59:15 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 10 20:21:43 2006
@@ -880,12 +880,21 @@
unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1;
Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
SDOperand());
+
+ // If we haven't noted the R3/F1 are live out, do so now.
+ if (DAG.getMachineFunction().liveout_empty())
+DAG.getMachineFunction().addLiveOut(ArgReg);
break;
}
case 3:
Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
SDOperand());
Copy = DAG.getCopyToReg(Copy, PPC::R4,
Op.getOperand(1),Copy.getValue(1));
+ // If we haven't noted the R3+R4 are live out, do so now.
+ if (DAG.getMachineFunction().liveout_empty()) {
+DAG.getMachineFunction().addLiveOut(PPC::R3);
+DAG.getMachineFunction().addLiveOut(PPC::R4);
+ }
break;
}
return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
@@ -1249,26 +1258,6 @@
}
}
- // Finally, inform the code generator which regs we return values in.
- switch (getValueType(F.getReturnType())) {
-default: assert(0 && "Unknown type!");
-case MVT::isVoid: break;
-case MVT::i1:
-case MVT::i8:
-case MVT::i16:
-case MVT::i32:
- MF.addLiveOut(PPC::R3);
- break;
-case MVT::i64:
- MF.addLiveOut(PPC::R3);
- MF.addLiveOut(PPC::R4);
- break;
-case MVT::f32:
-case MVT::f64:
- MF.addLiveOut(PPC::F1);
- break;
- }
-
return ArgValues;
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.358 -> 1.359
---
Log message:
Add basic support for legalizing returns of vectors
---
Diffs of the changes: (+36 -9)
LegalizeDAG.cpp | 45 -
1 files changed, 36 insertions(+), 9 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.358
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.359
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.358 Mon Apr 10 13:54:36 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 10 20:31:51 2006
@@ -1397,20 +1397,47 @@
Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
LastCALLSEQ_END = DAG.getEntryNode();
-
+Tmp2 = Node->getOperand(1);
+
switch (Node->getNumOperands()) {
case 2: // ret val
- switch (getTypeAction(Node->getOperand(1).getValueType())) {
+ switch (getTypeAction(Tmp2.getValueType())) {
case Legal:
-Tmp2 = LegalizeOp(Node->getOperand(1));
-Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2));
break;
- case Expand: {
-SDOperand Lo, Hi;
-ExpandOp(Node->getOperand(1), Lo, Hi);
-Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
+ case Expand:
+if (Tmp2.getValueType() != MVT::Vector) {
+ SDOperand Lo, Hi;
+ ExpandOp(Tmp2, Lo, Hi);
+ Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
+} else {
+ SDNode *InVal = Tmp2.Val;
+ unsigned NumElems =
+cast(*(InVal->op_end()-2))->getValue();
+ MVT::ValueType EVT = cast(*(InVal->op_end()-1))->getVT();
+
+ // Figure out if there is a Packed type corresponding to this Vector
+ // type. If so, convert to the packed type.
+ MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+ if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
+// Turn this into a return of the packed type.
+Tmp2 = PackVectorOp(Tmp2, TVT);
+Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+ } else if (NumElems == 1) {
+// Turn this into a return of the scalar type.
+Tmp2 = PackVectorOp(Tmp2, EVT);
+Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+// The scalarized value type may not be legal, e.g. it might
require
+// promotion or expansion. Relegalize the return.
+Result = LegalizeOp(Result);
+ } else {
+SDOperand Lo, Hi;
+SplitVectorOp(Tmp2, Lo, Hi);
+Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
+Result = LegalizeOp(Result);
+ }
+}
break;
- }
case Promote:
Tmp2 = PromoteOp(Node->getOperand(1));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.143 -> 1.144
---
Log message:
Vector function results go into V2 according to GCC. The darwin ABI doc
doesn't say where they go :-/
---
Diffs of the changes: (+10 -1)
PPCISelLowering.cpp | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.143
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.144
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.143 Mon Apr 10 20:21:43 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 10 20:38:39 2006
@@ -877,7 +877,16 @@
return SDOperand(); // ret void is legal
case 2: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
- unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1;
+ unsigned ArgReg;
+ if (MVT::isVector(ArgVT))
+ArgReg = PPC::V2;
+ else if (MVT::isInteger(ArgVT))
+ArgReg = PPC::R3;
+ else {
+assert(MVT::isFloatingPoint(ArgVT));
+ArgReg = PPC::F1;
+ }
+
Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
SDOperand());
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.359 -> 1.360
---
Log message:
add some todos
---
Diffs of the changes: (+8 -0)
LegalizeDAG.cpp |8
1 files changed, 8 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.359
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.360
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.359 Mon Apr 10 20:31:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 10 21:00:08 2006
@@ -1427,10 +1427,16 @@
// Turn this into a return of the scalar type.
Tmp2 = PackVectorOp(Tmp2, EVT);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+
+// FIXME: Returns of gcc generic vectors smaller than a legal type
+// should be returned in integer registers!
+
// The scalarized value type may not be legal, e.g. it might
require
// promotion or expansion. Relegalize the return.
Result = LegalizeOp(Result);
} else {
+// FIXME: Returns of gcc generic vectors larger than a legal vector
+// type should be returned by reference!
SDOperand Lo, Hi;
SplitVectorOp(Tmp2, Lo, Hi);
Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
@@ -1458,6 +1464,8 @@
break;
case Expand: {
SDOperand Lo, Hi;
+ assert(Node->getOperand(i).getValueType() != MVT::Vector &&
+ "FIXME: TODO: implement returning non-legal vector types!");
ExpandOp(Node->getOperand(i), Lo, Hi);
NewValues.push_back(Lo);
NewValues.push_back(Hi);
___
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[llvm-commits] CVS: llvm/win32/Transforms/Transforms.vcproj
Changes in directory llvm/win32/Transforms: Transforms.vcproj updated: 1.21 -> 1.22 --- Log message: Keep Visual Studio happy. --- Diffs of the changes: (+3 -0) Transforms.vcproj |3 +++ 1 files changed, 3 insertions(+) Index: llvm/win32/Transforms/Transforms.vcproj diff -u llvm/win32/Transforms/Transforms.vcproj:1.21 llvm/win32/Transforms/Transforms.vcproj:1.22 --- llvm/win32/Transforms/Transforms.vcproj:1.21Sun Jan 29 22:07:07 2006 +++ llvm/win32/Transforms/Transforms.vcproj Mon Apr 10 21:01:22 2006 @@ -179,6 +179,9 @@ RelativePath="..\..\lib\Transforms\Ipo\GlobalOpt.cpp"> + + http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/CREDITS.TXT
Changes in directory llvm: CREDITS.TXT updated: 1.46 -> 1.47 --- Log message: update my credits entry per clattner's request! --- Diffs of the changes: (+2 -1) CREDITS.TXT |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.46 llvm/CREDITS.TXT:1.47 --- llvm/CREDITS.TXT:1.46 Thu Mar 23 17:21:29 2006 +++ llvm/CREDITS.TXTTue Apr 11 00:47:45 2006 @@ -18,7 +18,8 @@ N: Nate Begeman E: [EMAIL PROTECTED] -D: Primary PowerPC backend developer +D: PowerPC backend developer +D: Target-independent code generator and analysis improvements N: Daniel Berlin E: [EMAIL PROTECTED] ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/CREDITS.TXT
Changes in directory llvm: CREDITS.TXT updated: 1.47 -> 1.48 --- Log message: Update my entry. --- Diffs of the changes: (+3 -1) CREDITS.TXT |4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.47 llvm/CREDITS.TXT:1.48 --- llvm/CREDITS.TXT:1.47 Tue Apr 11 00:47:45 2006 +++ llvm/CREDITS.TXTTue Apr 11 00:48:40 2006 @@ -138,7 +138,9 @@ N: Reid Spencer E: [EMAIL PROTECTED] W: http://llvm.x10sys.com/rspencer -D: Stacker, llvmc, bytecode, other. See web page for current notes. +D: Stacker, llvmc, llvm-ld, llvm-ar, lib/Archive, lib/Linker, lib/System, +D: bytecode enhancements, symtab hacking, unoverloading of intrinsics, makefile +D: and configuration system, documentation. N: Adam Treat E: [EMAIL PROTECTED] ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html
Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.3 -> 1.4 --- Log message: Flesh out the documentation a little bit more. --- Diffs of the changes: (+55 -9) HowToReleaseLLVM.html | 64 ++ 1 files changed, 55 insertions(+), 9 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.3 llvm/docs/HowToReleaseLLVM.html:1.4 --- llvm/docs/HowToReleaseLLVM.html:1.3 Mon Apr 10 16:43:05 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 01:21:25 2006 @@ -38,6 +38,7 @@ Merge Branches +Settle LLVM HEAD Build LLVM Run 'make check' Run LLVM Test Suite @@ -51,27 +52,45 @@ Merge Branches -Merge any work done on branches intended for release into mainline. +Merge any work done on branches intended for release into mainline. Work that +is not to be incorporated into the release should not be merged from the branch. + + + + +Settle CVS HEAD + + Use the nightly test reports, and 'make check' (deja-gnu based tests) to + increase the quality of LLVM and ensure that merged branches have not + destabilized LLVM. Build LLVM - Build LLVM + Build both debug and release versions of LLVM on all platforms. Ensure + build is warning and error free on each platform. Run 'make check' Run make check and ensure there are no unexpected failures. If - there are, resolve the failures and go back to step 2. + there are, resolve the failures and go back to step 2. + Ensure that 'make check' passes on all platforms for all targets. If certain + failures cannot be resolved before release time, determine if marking them + XFAIL is appropriate. If not, fix the bug and go back. The test suite must + complete with "0 unexpected failures" for release. + LLVM Test Suite Run the llvm-test suite and ensure there are no unacceptable failures. - If there are, resolve the failures and go back to step 2. + If there are, resolve the failures and go back to step 2. The test suite + should be run in Nightly Test mode. All tests must pass. If they do not, + investigate and go back to settling CVS HEAD. @@ -83,21 +102,48 @@ -CVS Tag +CVS Tag And Branch - Tag the release. + Tag and branch the CVS HEAD using the following procedure: + +Request all developers to refrain from committing. Offenders get commit +rights taken away (temporarily). +Tag the cvs HEAD with "ROOT_RELEASE_XX" where XX is the major and minor +release numbers (you can't have . in a cvs tag name). So, for Release 1.2, +XX=12 and for Release 1.10, XX=110. +Immediately create a cvs branch based on the ROOT_RELEASE tag. This is +where the release distribution will be created. +Advise developers they can work on CVS HEAD again. +Ensure all subsequent building and fixing is done on this branch. Run 'make dist' - Build the distribution, ensuring it is installable and working + Build the distribution, ensuring it is installable and working. This is a + two step process. First, use "make dist" to simply build the distribution. Any + failures need to be corrected (on the branch). Once "make dist" can be + successful, do "make dist-check". This target will do the same thing as the + 'dist' target but also test that distribution to make sure it works. This + ensures that needed files are not missing and that the src tarball can be + successfully unbacked, built, installed, and cleaned. This two-level testing + needs to be done on each target platform. Release - Release the distribution tarball to the public. + Release the distribution tarball to the public. This consists of generating + several tarballs. The first set, the source distributions, are automatically + generated by the "make dist" and "make dist-check". There are gzip, bzip2, and + zip versions of these bundles. + The second set of tarballs is the binary release. When "make dist-check" + succeeds, it will have created an _install directory into which it installed + the binary release. You need to rename that directory as "llvm" and then + create tarballs from the contents of that "llvm" directory. + Finally, use rpm to make an rpm package based on the llvm.spec file. Don't + forget to update the version number, documentation, etc. in the llvm.spec + file. @@ -111,7 +157,7 @@ mailto:[EMAIL PROTECTED]">Reid Spencer http://llvm.cs.uiuc.edu";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/04/10 21:43:05 $ + Last modified: $Date: 2006/04/11 06:21:25 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html
Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.4 -> 1.5 --- Log message: Fix an anchor. --- Diffs of the changes: (+2 -2) HowToReleaseLLVM.html |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.4 llvm/docs/HowToReleaseLLVM.html:1.5 --- llvm/docs/HowToReleaseLLVM.html:1.4 Tue Apr 11 01:21:25 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 01:22:15 2006 @@ -58,7 +58,7 @@ -Settle CVS HEAD +Settle CVS HEAD Use the nightly test reports, and 'make check' (deja-gnu based tests) to increase the quality of LLVM and ensure that merged branches have not @@ -157,7 +157,7 @@ mailto:[EMAIL PROTECTED]">Reid Spencer http://llvm.cs.uiuc.edu";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/04/11 06:21:25 $ + Last modified: $Date: 2006/04/11 06:22:15 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.360 -> 1.361
---
Log message:
Only get Tmp2 for cases where number of operands is > 1. Fixed return void.
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.360
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.361
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.360 Mon Apr 10 21:00:08 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Apr 11 01:33:39 2006
@@ -1397,10 +1397,10 @@
Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
LastCALLSEQ_END = DAG.getEntryNode();
-Tmp2 = Node->getOperand(1);
switch (Node->getNumOperands()) {
case 2: // ret val
+ Tmp2 = Node->getOperand(1);
switch (getTypeAction(Tmp2.getValueType())) {
case Legal:
Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2));
___
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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.15 -> 1.16
---
Log message:
movnt* and maskmovdqu intrinsics
---
Diffs of the changes: (+19 -4)
IntrinsicsX86.td | 23 +++
1 files changed, 19 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.15
llvm/include/llvm/IntrinsicsX86.td:1.16
--- llvm/include/llvm/IntrinsicsX86.td:1.15 Mon Apr 10 17:02:38 2006
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 01:56:27 2006
@@ -141,10 +141,9 @@
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">,
Intrinsic<[llvm_ptr_ty, llvm_int_ty], [IntrWriteMem]>;
- def int_x86_sse_movntq : GCCBuiltin<"__builtin_ia32_movntq">,
- Intrinsic<[llvm_ptr_ty, llvm_v2i32_ty], [IntrWriteMem]>;
- def int_x86_sse_movntps : GCCBuiltin<"__builtin_ia32_movntps">,
- Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
+ def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_v4f32_ty], [IntrWriteMem]>;
def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
Intrinsic<[llvm_void_ty], [IntrWriteMem]>;
}
@@ -281,6 +280,19 @@
llvm_v2f64_ty], [IntrWriteMem]>;
}
+// Cacheability support ops
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse2_movnt_dq : GCCBuiltin<"__builtin_ia32_movntdq">,
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_v2i64_ty], [IntrWriteMem]>;
+ def int_x86_sse2_movnt_pd : GCCBuiltin<"__builtin_ia32_movntpd">,
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_v2f64_ty], [IntrWriteMem]>;
+ def int_x86_sse2_movnt_i : GCCBuiltin<"__builtin_ia32_movnti">,
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_int_ty], [IntrWriteMem]>;
+}
+
// Misc.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
@@ -296,6 +308,9 @@
Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>;
def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [IntrNoMem]>;
+ def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">,
+ Intrinsic<[llvm_void_ty, llvm_v16i8_ty,
+ llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>;
}
//===--===//
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrMMX.td updated: 1.9 -> 1.10
X86InstrSSE.td updated: 1.73 -> 1.74
---
Log message:
movnt* and maskmovdqu intrinsics
---
Diffs of the changes: (+44 -16)
X86InstrMMX.td | 25 +
X86InstrSSE.td | 35 +++
2 files changed, 44 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.9
llvm/lib/Target/X86/X86InstrMMX.td:1.10
--- llvm/lib/Target/X86/X86InstrMMX.td:1.9 Sat Mar 25 00:00:03 2006
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Apr 11 01:57:30 2006
@@ -13,6 +13,13 @@
//
//===--===//
+// Instruction templates
+// MMXi8 - MMX instructions with ImmT == Imm8 and TB prefix.
+class MMXIi8 o, Format F, dag ops, string asm, list pattern>
+ : X86Inst, TB, Requires<[HasMMX]> {
+ let Pattern = pattern;
+}
+
// Some 'special' instructions
def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
"#IMPLICIT_DEF $dst",
@@ -50,3 +57,21 @@
def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
Requires<[HasMMX]>;
+
+// Shuffle and unpack instructions
+def PSHUFWri : MMXIi8<0x70, MRMSrcReg,
+ (ops VR64:$dst, VR64:$src1, i8imm:$src2),
+ "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
+def PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
+ (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
+ "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
+
+// Misc.
+def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+ "movntq {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasMMX]>;
+
+def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
+ "maskmovq {$mask, $src|$src, $mask}", []>, TB,
+ Requires<[HasMMX]>;
+
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.73
llvm/lib/Target/X86/X86InstrSSE.td:1.74
--- llvm/lib/Target/X86/X86InstrSSE.td:1.73 Mon Apr 10 19:19:04 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 01:57:30 2006
@@ -1321,13 +1321,6 @@
}
// Shuffle and unpack instructions
-def PSHUFWri : PSIi8<0x70, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, i8imm:$src2),
- "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
-def PSHUFWmi : PSIi8<0x70, MRMSrcMem,
- (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
- "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
-
def PSHUFDri : PDIi8<0x70, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, i8imm:$src2),
"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
@@ -1516,6 +1509,12 @@
"pmovmskb {$src, $dst|$dst, $src}",
[(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
+// Conditional store
+def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
+ "maskmovdqu {$mask, $src|$src, $mask}",
+ [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask,
EDI)]>,
+ Imp<[EDI],[]>;
+
// Prefetching loads
def PREFETCHT0 : I<0x18, MRM1m, (ops i8mem:$src),
"prefetcht0 $src", []>, TB,
@@ -1531,15 +1530,19 @@
Requires<[HasSSE1]>;
// Non-temporal stores
-def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
- "movntq {$src, $dst|$dst, $src}", []>, TB,
- Requires<[HasSSE1]>;
-def MOVNTPS : I<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
-"movntps {$src, $dst|$dst, $src}", []>, TB,
- Requires<[HasSSE1]>;
-def MASKMOVQ : I<0xF7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
- "maskmovq {$src, $dst|$dst, $src}", []>, TB,
- Requires<[HasSSE1]>;
+def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
+"movntps {$src, $dst|$dst, $src}",
+[(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
+def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
+"movntpd {$src, $dst|$dst, $src}",
+[(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
+def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
+"movntdq {$src, $dst|$dst, $src}",
+[(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
+def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
+"movnti {$src, $dst|$dst, $src}",
+[(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>,
+ TB, Requires<[HasSSE2]>;
// Store fence
def SFENCE : I<0xAE, MRM7m, (ops),
_
