[llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td
Changes in directory llvm/include/llvm:
IntrinsicsPowerPC.td updated: 1.11 -> 1.12
---
Log message:
Add some classes to make it easier to define intrinsics. Add min/max
intrinsics.
---
Diffs of the changes: (+87 -45)
IntrinsicsPowerPC.td | 132 +--
1 files changed, 87 insertions(+), 45 deletions(-)
Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.11
llvm/include/llvm/IntrinsicsPowerPC.td:1.12
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.11 Thu Mar 30 17:32:58 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td Mon Apr 3 10:43:07 2006
@@ -11,6 +11,54 @@
//
//===--===//
+//===--===//
+// Definitions for all PowerPC intrinsics.
+//
+
+let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
+ /// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
+ class PowerPC_Vec_Intrinsic types,
+ list properties>
+: GCCBuiltin,
+ Intrinsic;
+}
+
+//===--===//
+// PowerPC Altivec Intrinsic Class Definitions.
+//
+
+/// PowerPC_Vec_FFF_Intrinsic - A PowerPC intrinsic that takes two v4f32
+/// vectors and returns one. These intrinsics have no side effects.
+class PowerPC_Vec_FFF_Intrinsic
+ : PowerPC_Vec_Intrinsic;
+
+/// PowerPC_Vec_BBB_Intrinsic - A PowerPC intrinsic that takes two v16f8
+/// vectors and returns one. These intrinsics have no side effects.
+class PowerPC_Vec_BBB_Intrinsic
+ : PowerPC_Vec_Intrinsic;
+
+/// PowerPC_Vec_HHH_Intrinsic - A PowerPC intrinsic that takes two v8i16
+/// vectors and returns one. These intrinsics have no side effects.
+class PowerPC_Vec_HHH_Intrinsic
+ : PowerPC_Vec_Intrinsic;
+
+/// PowerPC_Vec_WWW_Intrinsic - A PowerPC intrinsic that takes two v4i32
+/// vectors and returns one. These intrinsics have no side effects.
+class PowerPC_Vec_WWW_Intrinsic
+ : PowerPC_Vec_Intrinsic;
+
+
+//===--===//
+// PowerPC Altivec Intrinsic Definitions.
+
let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
// Loads. These don't map directly to GCC builtins because they represent
the
// source address with a single pointer.
@@ -130,26 +178,46 @@
def int_ppc_altivec_vcmpgtub_p : GCCBuiltin<"__builtin_altivec_vcmpgtub_p">,
Intrinsic<[llvm_int_ty, llvm_int_ty,
llvm_v16i8_ty,llvm_v16i8_ty],
[InstrNoMem]>;
+}
- // Saturating adds, subs, and multiply-adds
- def int_ppc_altivec_vaddubs : GCCBuiltin<"__builtin_altivec_vaddubs">,
- Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
-[InstrNoMem]>;
- def int_ppc_altivec_vaddsbs : GCCBuiltin<"__builtin_altivec_vaddsbs">,
- Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
-[InstrNoMem]>;
- def int_ppc_altivec_vadduhs : GCCBuiltin<"__builtin_altivec_vadduhs">,
- Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
-[InstrNoMem]>;
- def int_ppc_altivec_vaddshs : GCCBuiltin<"__builtin_altivec_vaddshs">,
- Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
-[InstrNoMem]>;
- def int_ppc_altivec_vadduws : GCCBuiltin<"__builtin_altivec_vadduws">,
- Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
-[InstrNoMem]>;
- def int_ppc_altivec_vaddsws : GCCBuiltin<"__builtin_altivec_vaddsws">,
- Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
-[InstrNoMem]>;
+// Vector maximum.
+def int_ppc_altivec_vmaxfp : PowerPC_Vec_FFF_Intrinsic<"vmaxfp">;
+def int_ppc_altivec_vmaxsb : PowerPC_Vec_BBB_Intrinsic<"vmaxsb">;
+def int_ppc_altivec_vmaxsh : PowerPC_Vec_HHH_Intrinsic<"vmaxsh">;
+def int_ppc_altivec_vmaxsw : PowerPC_Vec_WWW_Intrinsic<"vmaxsw">;
+def int_ppc_altivec_vmaxub : PowerPC_Vec_BBB_Intrinsic<"vmaxub">;
+def int_ppc_altivec_vmaxuh : PowerPC_Vec_HHH_Intrinsic<"vmaxuh">;
+def int_ppc_altivec_vmaxuw : PowerPC_Vec_WWW_Intrinsic<"vmaxuw">;
+
+// Vector minimum.
+def int_ppc_altivec_vminfp : PowerPC_Vec_FFF_Intrinsic<"vminfp">;
+def int_ppc_altivec_vminsb : PowerPC_Vec_BBB_Intrinsic<"vminsb">;
+def int_ppc_altivec_vminsh : PowerPC_Vec_HHH_Intrinsic<"vminsh">;
+def int_ppc_altivec_vminsw : PowerPC_Vec_WWW_Intrinsic<"vminsw">;
+def int_ppc_altivec_vminub : PowerPC_Vec_BBB_Intrinsic<"vminub">;
+def int_ppc_altivec_vminuh : PowerPC_Vec_HHH_Intrinsic<"vminuh">;
+def int_ppc_altivec_vminuw : PowerPC_Vec_WWW_Intrinsic<"vminuw">;
+
+// Saturating adds.
+def int_ppc_altivec_vaddubs : PowerPC_Vec_BBB_Intrinsic<"vaddubs">;
+def int_ppc_altivec_vaddsbs : PowerPC_Vec_BBB_Intrinsic<"vaddsbs">;
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.30 -> 1.31 --- Log message: Add the full set of min/max instructions --- Diffs of the changes: (+14 -6) PPCInstrAltivec.td | 20 ++-- 1 files changed, 14 insertions(+), 6 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.30 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.31 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.30 Sat Apr 1 16:41:47 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Mon Apr 3 10:58:28 2006 @@ -203,12 +203,20 @@ def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>; def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>; -def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vmaxfp $vD, $vA, $vB", VecFP, - []>; -def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vminfp $vD, $vA, $vB", VecFP, - []>; +def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>; +def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>; +def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>; +def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>; +def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>; +def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>; +def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>; +def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>; +def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>; +def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>; +def VMINSW : VX1_Int< 896, "vminsw", int_ppc_altivec_vminsw>; +def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>; +def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; +def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>; def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.141 -> 1.142
---
Log message:
Add a missing check, which broke a bunch of vector tests.
---
Diffs of the changes: (+6 -3)
DAGCombiner.cpp |9 ++---
1 files changed, 6 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.141
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.142
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.141 Sun Apr 2 22:16:50 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 3 12:21:50 2006
@@ -2756,9 +2756,12 @@
Ops.back().getOpcode() == ISD::ConstantFP) &&
"Scalar binop didn't fold!");
}
-Ops.push_back(*(LHS.Val->op_end()-2));
-Ops.push_back(*(LHS.Val->op_end()-1));
-return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+
+if (Ops.size() == LHS.getNumOperands()-2) {
+ Ops.push_back(*(LHS.Val->op_end()-2));
+ Ops.push_back(*(LHS.Val->op_end()-1));
+ return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+}
}
return SDOperand();
___
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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td
Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.12 -> 1.13 --- Log message: shrinkify intrinsics more by using some local classes --- Diffs of the changes: (+32 -60) IntrinsicsPowerPC.td | 92 +-- 1 files changed, 32 insertions(+), 60 deletions(-) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.12 llvm/include/llvm/IntrinsicsPowerPC.td:1.13 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.12 Mon Apr 3 10:43:07 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Mon Apr 3 12:20:06 2006 @@ -27,6 +27,12 @@ // PowerPC Altivec Intrinsic Class Definitions. // +/// PowerPC_Vec_FF_Intrinsic - A PowerPC intrinsic that takes one v4f32 +/// vector and returns one. These intrinsics have no side effects. +class PowerPC_Vec_FF_Intrinsic + : PowerPC_Vec_Intrinsic; + /// PowerPC_Vec_FFF_Intrinsic - A PowerPC intrinsic that takes two v4f32 /// vectors and returns one. These intrinsics have no side effects. class PowerPC_Vec_FFF_Intrinsic @@ -371,58 +377,29 @@ def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_int_ty], [InstrNoMem]>; - def int_ppc_altivec_vslo : GCCBuiltin<"__builtin_altivec_vslo">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], -[InstrNoMem]>; - - def int_ppc_altivec_vslb : GCCBuiltin<"__builtin_altivec_vslb">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], -[InstrNoMem]>; - def int_ppc_altivec_vslh : GCCBuiltin<"__builtin_altivec_vslh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], -[InstrNoMem]>; - def int_ppc_altivec_vslw : GCCBuiltin<"__builtin_altivec_vslw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], -[InstrNoMem]>; - - // Right Shifts. - def int_ppc_altivec_vsr : GCCBuiltin<"__builtin_altivec_vsr">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], -[InstrNoMem]>; - def int_ppc_altivec_vsro : GCCBuiltin<"__builtin_altivec_vsro">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], -[InstrNoMem]>; - - def int_ppc_altivec_vsrb : GCCBuiltin<"__builtin_altivec_vsrb">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], -[InstrNoMem]>; - def int_ppc_altivec_vsrh : GCCBuiltin<"__builtin_altivec_vsrh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], -[InstrNoMem]>; - def int_ppc_altivec_vsrw : GCCBuiltin<"__builtin_altivec_vsrw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], -[InstrNoMem]>; - def int_ppc_altivec_vsrab : GCCBuiltin<"__builtin_altivec_vsrab">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], -[InstrNoMem]>; - def int_ppc_altivec_vsrah : GCCBuiltin<"__builtin_altivec_vsrah">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], -[InstrNoMem]>; - def int_ppc_altivec_vsraw : GCCBuiltin<"__builtin_altivec_vsraw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], -[InstrNoMem]>; - - // Rotates. - def int_ppc_altivec_vrlb : GCCBuiltin<"__builtin_altivec_vrlb">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], -[InstrNoMem]>; - def int_ppc_altivec_vrlh : GCCBuiltin<"__builtin_altivec_vrlh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], -[InstrNoMem]>; - def int_ppc_altivec_vrlw : GCCBuiltin<"__builtin_altivec_vrlw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], -[InstrNoMem]>; +} +def int_ppc_altivec_vslo : PowerPC_Vec_WWW_Intrinsic<"vslo">; +def int_ppc_altivec_vslb : PowerPC_Vec_BBB_Intrinsic<"vslb">; +def int_ppc_altivec_vslh : PowerPC_Vec_HHH_Intrinsic<"vslh">; +def int_ppc_altivec_vslw : PowerPC_Vec_WWW_Intrinsic<"vslw">; + +// Right Shifts. +def int_ppc_altivec_vsr : PowerPC_Vec_WWW_Intrinsic<"vsr">; +def int_ppc_altivec_vsro : PowerPC_Vec_WWW_Intrinsic<"vsro">; + +def int_ppc_altivec_vsrb : PowerPC_Vec_BBB_Intrinsic<"vsrb">; +def int_ppc_altivec_vsrh : PowerPC_Vec_HHH_Intrinsic<"vsrh">; +def int_ppc_altivec_vsrw : PowerPC_Vec_WWW_Intrinsic<"vsrw">; +def int_ppc_altivec_vsrab : PowerPC_Vec_BBB_Intrinsic<"vsrab">; +def int_ppc_altivec_vsrah : PowerPC_Vec_HHH_Intrinsic<"vsrah">; +def int_ppc_altivec_vsraw : PowerPC_Vec_WWW_Intrinsic<"vsraw">; + +// Rotates. +def int_ppc_altivec_vrlb : PowerPC_Vec_BBB_Intrinsic<"vrlb">; +def int_ppc_altivec_vrlh : PowerPC_Vec_HHH_Intrinsic<"vrlh">; +def int_p
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.142 -> 1.143
---
Log message:
Add a missing check, this fixes UnitTests/Vector/sumarray.c
---
Diffs of the changes: (+2 -2)
DAGCombiner.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.142
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.143
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.142 Mon Apr 3 12:21:50 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 3 12:29:28 2006
@@ -2017,8 +2017,8 @@
break;
}
-if (isSimple) {
- MVT::ValueType DestEltVT = cast(N->getOperand(2))->getVT();
+MVT::ValueType DestEltVT = cast(N->getOperand(2))->getVT();
+if (isSimple && !MVT::isVector(DestEltVT)) {
return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
}
}
___
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[llvm-commits] CVS: llvm/lib/Target/TargetData.cpp
Changes in directory llvm/lib/Target:
TargetData.cpp updated: 1.59 -> 1.60
---
Log message:
Align vectors to the size in bytes, not bits.
---
Diffs of the changes: (+1 -1)
TargetData.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/TargetData.cpp
diff -u llvm/lib/Target/TargetData.cpp:1.59 llvm/lib/Target/TargetData.cpp:1.60
--- llvm/lib/Target/TargetData.cpp:1.59 Fri Mar 31 16:33:42 2006
+++ llvm/lib/Target/TargetData.cpp Mon Apr 3 14:28:50 2006
@@ -217,7 +217,7 @@
Size = AlignedSize*PTy->getNumElements();
// FIXME: The alignments of specific packed types are target dependent.
// For now, just set it to be equal to Size.
-Alignment = Size;
+Alignment = (Size+7)/8;
return;
}
case Type::StructTyID: {
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.cpp X86InstrInfo.td X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.151 -> 1.152
X86InstrInfo.cpp updated: 1.47 -> 1.48
X86InstrInfo.td updated: 1.259 -> 1.260
X86InstrSSE.td updated: 1.53 -> 1.54
---
Log message:
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
- Some bug fixes and naming inconsistency fixes.
---
Diffs of the changes: (+151 -70)
X86ISelLowering.cpp | 62 +++--
X86InstrInfo.cpp|6 +-
X86InstrInfo.td |1
X86InstrSSE.td | 152 ++--
4 files changed, 151 insertions(+), 70 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.151
llvm/lib/Target/X86/X86ISelLowering.cpp:1.152
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.151 Fri Mar 31 15:55:24 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 3 15:53:28 2006
@@ -280,6 +280,7 @@
setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
+setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
}
if (Subtarget->hasSSE2()) {
@@ -316,7 +317,9 @@
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
+setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
+setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
}
@@ -1484,11 +1487,20 @@
// Dest { 2, 1 } <= shuffle( Dest { 1, 0 }, Src { 3, 2 }
// Expect bit 0 == 1, bit1 == 2
SDOperand Bit0 = N->getOperand(0);
+if (Bit0.getOpcode() != ISD::UNDEF) {
+ assert(isa(Bit0) && "Invalid VECTOR_SHUFFLE mask!");
+ if (cast(Bit0)->getValue() != 1)
+return false;
+}
+
SDOperand Bit1 = N->getOperand(1);
-assert(isa(Bit0) && isa(Bit1) &&
- "Invalid VECTOR_SHUFFLE mask!");
-return (cast(Bit0)->getValue() == 1 &&
-cast(Bit1)->getValue() == 2);
+if (Bit1.getOpcode() != ISD::UNDEF) {
+ assert(isa(Bit1) && "Invalid VECTOR_SHUFFLE mask!");
+ if (cast(Bit1)->getValue() != 2)
+return false;
+}
+
+return true;
}
if (NumElems != 4) return false;
@@ -2660,15 +2672,55 @@
return SDOperand();
}
case ISD::EXTRACT_VECTOR_ELT: {
-// Transform it so it match pextrw which produces a 32-bit result.
+if (!isa(Op.getOperand(1)))
+return SDOperand();
+
MVT::ValueType VT = Op.getValueType();
if (MVT::getSizeInBits(VT) == 16) {
+ // Transform it so it match pextrw which produces a 32-bit result.
MVT::ValueType EVT = (MVT::ValueType)(VT+1);
SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
Op.getOperand(0), Op.getOperand(1));
SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, VT, Assert);
+} else if (MVT::getSizeInBits(VT) == 32) {
+ SDOperand Vec = Op.getOperand(0);
+ unsigned Idx = cast(Op.getOperand(1))->getValue();
+ if (Idx == 0)
+return Op;
+
+ // TODO: if Idex == 2, we can use unpckhps
+ // SHUFPS the element to the lowest double word, then movss.
+ MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
+ SDOperand IdxNode = DAG.getConstant((Idx < 2) ? Idx : Idx+4,
+ MVT::getVectorBaseType(MaskVT));
+ std::vector IdxVec;
+ IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
+ IdxVec.push_back(DAG.getNode(ISD::UNDEF,
MVT::getVectorBaseType(MaskVT)));
+ IdxVec.push_back(DAG.getNode(ISD::UNDEF,
MVT::getVectorBaseType(MaskVT)));
+ IdxVec.push_back(DAG.getNode(ISD::UNDEF,
MVT::getVectorBaseType(MaskVT)));
+ SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec);
+ Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
+Vec, Vec, Mask);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
+ DAG.getConstant(0, MVT::i32));
+} else if (MVT::getSizeInBits(VT) == 64) {
+ SDOperand Vec = Op.getOperand(0);
+ unsigned Idx = cast(Op.getOperand(1))->getValue();
+ if (Idx == 0)
+return Op;
+
+ // UNPCKHPD the element to the lowest double word, then movsd.
+ MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
+ std::vector IdxVec;
+ IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
+ IdxVec.push_back(DAG.getNode(ISD::UNDEF,
MVT::getVectorBaseTyp
[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFrameInfo.h
Changes in directory llvm/include/llvm/CodeGen:
MachineFrameInfo.h updated: 1.14 -> 1.15
---
Log message:
Keep track of max stack alignment as objects are added. Remove an obsolete
method.
---
Diffs of the changes: (+3 -5)
MachineFrameInfo.h |8 +++-
1 files changed, 3 insertions(+), 5 deletions(-)
Index: llvm/include/llvm/CodeGen/MachineFrameInfo.h
diff -u llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.14
llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.15
--- llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.14 Sun Nov 6 11:40:18 2005
+++ llvm/include/llvm/CodeGen/MachineFrameInfo.hMon Apr 3 16:38:39 2006
@@ -210,16 +210,14 @@
/// a postive identifier to represent it.
///
int CreateStackObject(unsigned Size, unsigned Alignment) {
+// Keep track of the maximum alignment.
+if (MaxAlignment < Alignment) MaxAlignment = Alignment;
+
assert(Size != 0 && "Cannot allocate zero size stack objects!");
Objects.push_back(StackObject(Size, Alignment, -1));
return Objects.size()-NumFixedObjects-1;
}
- /// CreateStackObject - Create a stack object for a value of the specified
- /// LLVM type.
- ///
- int CreateStackObject(const Type *Ty, const TargetData &TD);
-
/// CreateVariableSizedObject - Notify the MachineFrameInfo object that a
/// variable sized object has been created. This must be created whenever a
/// variable sized object is created, whether or not the index returned is
___
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[llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp
Changes in directory llvm/lib/CodeGen:
MachineFunction.cpp updated: 1.86 -> 1.87
---
Log message:
Remove unused method
---
Diffs of the changes: (+0 -8)
MachineFunction.cpp |8
1 files changed, 8 deletions(-)
Index: llvm/lib/CodeGen/MachineFunction.cpp
diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.86
llvm/lib/CodeGen/MachineFunction.cpp:1.87
--- llvm/lib/CodeGen/MachineFunction.cpp:1.86 Wed Feb 8 22:46:04 2006
+++ llvm/lib/CodeGen/MachineFunction.cppMon Apr 3 16:39:03 2006
@@ -297,14 +297,6 @@
// MachineFrameInfo implementation
//===--===//
-/// CreateStackObject - Create a stack object for a value of the specified
type.
-///
-int MachineFrameInfo::CreateStackObject(const Type *Ty, const TargetData &TD) {
- return CreateStackObject((unsigned)TD.getTypeSize(Ty),
- TD.getTypeAlignment(Ty));
-}
-
-
void MachineFrameInfo::print(const MachineFunction &MF, std::ostream &OS)
const{
int ValOffset = MF.getTarget().getFrameInfo()->getOffsetOfLocalArea();
___
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[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp
Changes in directory llvm/lib/CodeGen: PrologEpilogInserter.cpp updated: 1.51 -> 1.52 --- Log message: The stack alignment is now computed dynamically, just verify it is correct. --- Diffs of the changes: (+2 -1) PrologEpilogInserter.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.51 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.52 --- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.51 Sun Nov 6 11:43:20 2005 +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Mon Apr 3 16:39:57 2006 @@ -321,7 +321,8 @@ // Remember the required stack alignment in case targets need it to perform // dynamic stack alignment. - FFI->setMaxAlignment(MaxAlign); + assert(FFI->getMaxAlignment() == MaxAlign && + "Stack alignment calculation broken!"); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.52 -> 1.53
---
Log message:
Force use of a frame-pointer if there is anything on the stack that is aligned
more than the OS keeps the stack aligned.
---
Diffs of the changes: (+18 -7)
PPCRegisterInfo.cpp | 25 ++---
1 files changed, 18 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.52
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.53
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.52Tue Mar 28 07:48:33 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Apr 3 17:03:29 2006
@@ -196,8 +196,16 @@
// pointer register. This is true if the function has variable sized allocas
or
// if frame pointer elimination is disabled.
//
-static bool hasFP(MachineFunction &MF) {
- return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
+static bool hasFP(const MachineFunction &MF) {
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
+
+ // If frame pointers are forced, if there are variable sized stack objects,
+ // or if there is an object on the stack that requires more alignment than is
+ // normally provided, use a frame pointer.
+ //
+ return NoFramePointerElim || MFI->hasVarSizedObjects() ||
+ MFI->getMaxAlignment() > TargetAlign;
}
void PPCRegisterInfo::
@@ -331,9 +339,12 @@
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
+
+ // Do we have a frame pointer for this function?
+ bool HasFP = hasFP(MF);
- // Scan the first few instructions of the prolog, looking for an
UPDATE_VRSAVE
- // instruction. If we find it, process it.
+ // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
+ // process it.
for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
@@ -364,7 +375,7 @@
// If we are a leaf function, and use up to 224 bytes of stack space,
// and don't have a frame pointer, then we do not need to adjust the stack
// pointer (we fit in the Red Zone).
- if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls() &&
+ if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() &&
MaxAlign <= TargetAlign)) {
MFI->setStackSize(0);
return;
@@ -374,7 +385,7 @@
// of the stack and round the size to a multiple of the alignment.
unsigned Align = std::max(TargetAlign, MaxAlign);
unsigned GPRSize = 4;
- unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
+ unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
NumBytes = (NumBytes+Size+Align-1)/Align*Align;
// Update frame info to pretend that this is part of the stack...
@@ -407,7 +418,7 @@
}
// If there is a frame pointer, copy R1 (SP) into R31 (FP)
- if (hasFP(MF)) {
+ if (HasFP) {
BuildMI(MBB, MBBI, PPC::STW, 3)
.addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.152 -> 1.153
X86InstrSSE.td updated: 1.54 -> 1.55
---
Log message:
Use movlpd to: store lower f64 extracted from v2f64.
Use movhpd to: store upper f64 extracted from v2f64.
---
Diffs of the changes: (+10 -6)
X86ISelLowering.cpp |2 ++
X86InstrSSE.td | 14 --
2 files changed, 10 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.152
llvm/lib/Target/X86/X86ISelLowering.cpp:1.153
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.152 Mon Apr 3 15:53:28 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 3 17:30:54 2006
@@ -2712,6 +2712,8 @@
return Op;
// UNPCKHPD the element to the lowest double word, then movsd.
+ // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
+ // to a f64mem, the whole operation is folded into a single MOVHPDmr.
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
std::vector IdxVec;
IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.54
llvm/lib/Target/X86/X86InstrSSE.td:1.55
--- llvm/lib/Target/X86/X86InstrSSE.td:1.54 Mon Apr 3 15:53:28 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 17:30:54 2006
@@ -713,12 +713,18 @@
def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
"movlps {$src, $dst|$dst, $src}", []>;
def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
- "movlpd {$src, $dst|$dst, $src}", []>;
+ "movlpd {$src, $dst|$dst, $src}",
+ [(store (f64 (vector_extract (v2f64 VR128:$src),
+ (i32 0))), addr:$dst)]>;
def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
"movhps {$src, $dst|$dst, $src}", []>;
def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
- "movhpd {$src, $dst|$dst, $src}", []>;
+ "movhpd {$src, $dst|$dst, $src}",
+ [(store (f64 (vector_extract
+ (v2f64 (vector_shuffle VR128:$src, (undef),
+ UNPCKH_shuffle_mask)), (i32 0))),
+ addr:$dst)]>;
let isTwoAddress = 1 in {
def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
@@ -1561,10 +1567,6 @@
"movsd {$src, $dst|$dst, $src}",
[(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
(i32 0)))]>;
-def MOVPD2SDmr : SDI<0x10, MRMDestMem, (ops f64mem:$dst, VR128:$src),
- "movsd {$src, $dst|$dst, $src}",
- [(store (f64 (vector_extract (v2f64 VR128:$src),
- (i32 0))), addr:$dst)]>;
def MOVPDI2DIrr : PDI<0x7E, MRMSrcReg, (ops R32:$dst, VR128:$src),
"movd {$src, $dst|$dst, $src}",
[(set R32:$dst, (vector_extract (v4i32 VR128:$src),
___
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[llvm-commits] CVS: llvm/lib/Target/TargetData.cpp
Changes in directory llvm/lib/Target:
TargetData.cpp updated: 1.60 -> 1.61
---
Log message:
revert previous patch
---
Diffs of the changes: (+1 -1)
TargetData.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/TargetData.cpp
diff -u llvm/lib/Target/TargetData.cpp:1.60 llvm/lib/Target/TargetData.cpp:1.61
--- llvm/lib/Target/TargetData.cpp:1.60 Mon Apr 3 14:28:50 2006
+++ llvm/lib/Target/TargetData.cpp Mon Apr 3 18:14:49 2006
@@ -217,7 +217,7 @@
Size = AlignedSize*PTy->getNumElements();
// FIXME: The alignments of specific packed types are target dependent.
// For now, just set it to be equal to Size.
-Alignment = (Size+7)/8;
+Alignment = Size;
return;
}
case Type::StructTyID: {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.55 -> 1.56
---
Log message:
Some SSE1 intrinsics: min, max, sqrt, etc.
---
Diffs of the changes: (+91 -78)
X86InstrSSE.td | 169 ++---
1 files changed, 91 insertions(+), 78 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.55
llvm/lib/Target/X86/X86InstrSSE.td:1.56
--- llvm/lib/Target/X86/X86InstrSSE.td:1.55 Mon Apr 3 17:30:54 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 18:49:17 2006
@@ -171,6 +171,45 @@
//===--===//
// Helpers for defining instructions that directly correspond to intrinsics.
+class SS_Intrr o, string asm, Intrinsic IntId, ValueType Ty>
+ : SSI;
+class SS_Intrm o, string asm, Intrinsic IntId, ValueType Ty>
+ : SSI;
+class SD_Intrr o, string asm, Intrinsic IntId, ValueType Ty>
+ : SDI;
+class SD_Intrm o, string asm, Intrinsic IntId, ValueType Ty>
+ : SDI;
+
+class PS_Intr o, string asm, Intrinsic IntId>
+ : PSI;
+class PS_Intm o, string asm, Intrinsic IntId>
+ : PSI;
+class PD_Intr o, string asm, Intrinsic IntId>
+ : PDI;
+class PD_Intm o, string asm, Intrinsic IntId>
+ : PDI;
+
+class PS_Intrr o, string asm, Intrinsic IntId>
+ : PSI;
+class PS_Intrm o, string asm, Intrinsic IntId>
+ : PSI;
+class PD_Intrr o, string asm, Intrinsic IntId>
+ : PDI;
+class PD_Intrm o, string asm, Intrinsic IntId>
+ : PDI;
+
class S3S_Intrr o, string asm, Intrinsic IntId>
: S3SI;
@@ -435,46 +474,22 @@
(load addr:$src)))]>;
let isTwoAddress = 1 in {
-def Int_MAXSSrr : SSI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
- "maxss {$src2, $dst|$dst, $src2}",
- [(set VR128:$dst, (int_x86_sse_max_ss VR128:$src1,
- VR128:$src2))]>;
-def Int_MAXSSrm : SSI<0x5F, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f32mem:$src2),
- "maxss {$src2, $dst|$dst, $src2}",
- [(set VR128:$dst, (int_x86_sse_max_ss VR128:$src1,
- (load addr:$src2)))]>;
-def Int_MAXSDrr : SDI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
- "maxsd {$src2, $dst|$dst, $src2}",
- [(set VR128:$dst, (int_x86_sse2_max_sd VR128:$src1,
- VR128:$src2))]>;
-def Int_MAXSDrm : SDI<0x5F, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f64mem:$src2),
- "maxsd {$src2, $dst|$dst, $src2}",
- [(set VR128:$dst, (int_x86_sse2_max_sd VR128:$src1,
- (load addr:$src2)))]>;
-def Int_MINSSrr : SSI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
- "minss {$src2, $dst|$dst, $src2}",
- [(set VR128:$dst, (int_x86_sse_min_ss VR128:$src1,
- VR128:$src2))]>;
-def Int_MINSSrm : SSI<0x5D, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f32mem:$src2),
- "minss {$src2, $dst|$dst, $src2}",
- [(set VR128:$dst, (int_x86_sse_min_ss VR128:$src1,
- (load addr:$src2)))]>;
-def Int_MINSDrr : SDI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
- "minsd {$src2, $dst|$dst, $src2}",
- [(set VR128:$dst, (int_x86_sse2_min_sd VR128:$src1,
- VR128:$src2))]>;
-def Int_MINSDrm : SDI<0x5D, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f64mem:$src2),
- "minsd {$src2, $dst|$dst, $src2}",
- [(set VR128:$dst, (int_x86_sse2_min_sd VR128:$src1,
- (load addr:$src2)))]>;
+def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}",
+ int_x86_sse_max_ss, v4f32>;
+def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}",
+ int_x86_sse_max_ss, v4f32>;
+def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
+ int_x86_sse2_max_sd, v2f64>;
+def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
+ int_x86_sse2_max_sd, v2f64>;
+def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}",
+ int_x86_sse_min_ss, v4f32>;
+def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}",
+ int_x86_sse_min_
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.126 -> 1.127 --- Log message: Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand. --- Diffs of the changes: (+5 -1) PPCISelLowering.cpp |6 +- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.126 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.127 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.126 Sun Apr 2 00:26:07 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 3 18:55:43 2006 @@ -182,7 +182,7 @@ setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal); // We can custom expand all VECTOR_SHUFFLEs to VPERM. - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); @@ -192,8 +192,12 @@ setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); + + setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); } +setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); + addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.127 -> 1.128 --- Log message: Revert accidentally committed hunks. --- Diffs of the changes: (+1 -3) PPCISelLowering.cpp |4 +--- 1 files changed, 1 insertion(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.127 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.128 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.127 Mon Apr 3 18:55:43 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 3 18:58:04 2006 @@ -182,7 +182,7 @@ setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal); // We can custom expand all VECTOR_SHUFFLEs to VPERM. - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); @@ -196,8 +196,6 @@ setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); } -setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); - addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.31 -> 1.32 --- Log message: Plug in the byte and short splats --- Diffs of the changes: (+4 -2) PPCInstrAltivec.td |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.31 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.32 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.31 Mon Apr 3 10:58:28 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Mon Apr 3 19:05:13 2006 @@ -293,10 +293,12 @@ def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vspltb $vD, $vB, $UIMM", VecPerm, - []>; + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), + VSPLT_shuffle_mask:$UIMM))]>; def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vsplth $vD, $vB, $UIMM", VecPerm, - []>; + [(set VRRC:$vD, (vector_shuffle (v8i16 VRRC:$vB), (undef), + VSPLT_shuffle_mask:$UIMM))]>; def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vspltw $vD, $vB, $UIMM", VecPerm, [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.56 -> 1.57
---
Log message:
Compact some intrinsic definitions.
---
Diffs of the changes: (+84 -123)
X86InstrSSE.td | 207 +++--
1 files changed, 84 insertions(+), 123 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.56
llvm/lib/Target/X86/X86InstrSSE.td:1.57
--- llvm/lib/Target/X86/X86InstrSSE.td:1.56 Mon Apr 3 18:49:17 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 19:10:53 2006
@@ -171,18 +171,31 @@
//===--===//
// Helpers for defining instructions that directly correspond to intrinsics.
-class SS_Intrr o, string asm, Intrinsic IntId, ValueType Ty>
+class SS_Intr o, string asm, Intrinsic IntId>
+ : SSI;
+class SS_Intm o, string asm, Intrinsic IntId>
+ : SSI;
+class SD_Intr o, string asm, Intrinsic IntId>
+ : SDI;
+class SD_Intm o, string asm, Intrinsic IntId>
+ : SDI;
+
+class SS_Intrr o, string asm, Intrinsic IntId>
: SSI;
-class SS_Intrm o, string asm, Intrinsic IntId, ValueType Ty>
+[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
+class SS_Intrm o, string asm, Intrinsic IntId>
: SSI;
-class SD_Intrr o, string asm, Intrinsic IntId, ValueType Ty>
+[(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2]>;
+class SD_Intrr o, string asm, Intrinsic IntId>
: SDI;
-class SD_Intrm o, string asm, Intrinsic IntId, ValueType Ty>
+[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
+class SD_Intrm o, string asm, Intrinsic IntId>
: SDI;
+[(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2]>;
class PS_Intr o, string asm, Intrinsic IntId>
: PSI;
-def Int_ADDSDrr : SDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
-"addsd {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse2_add_sd VR128:$src1,
- VR128:$src2))]>;
-def Int_MULSSrr : SSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
-"mulss {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse_mul_ss VR128:$src1,
- VR128:$src2))]>;
-def Int_MULSDrr : SDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
-"mulsd {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse2_mul_sd VR128:$src1,
- VR128:$src2))]>;
-}
-
-def Int_ADDSSrm : SSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f32mem:$src2),
-"addss {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse_add_ss VR128:$src1,
- (load addr:$src2)))]>;
-def Int_ADDSDrm : SDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f64mem:$src2),
-"addsd {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse2_add_sd VR128:$src1,
- (load addr:$src2)))]>;
-def Int_MULSSrm : SSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f32mem:$src2),
-"mulss {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse_mul_ss VR128:$src1,
- (load addr:$src2)))]>;
-def Int_MULSDrm : SDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f64mem:$src2),
-"mulsd {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse2_mul_sd VR128:$src1,
- (load addr:$src2)))]>;
-
-def Int_DIVSSrr : SSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-"divss {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse_div_ss VR128:$src1,
- VR128:$src2))]>;
-def Int_DIVSSrm : SSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f32mem:$src2),
-"divss {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse_div_ss VR128:$src1,
- (load addr:$src2)))]>;
-def Int_DIVSDrr : SDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-"divsd {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse2_div_sd VR128:$src1,
- VR128:$src2))]>;
-def Int_DIVSDrm : SDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
-"divsd {$src2, $dst|$dst, $src2}",
-[(set VR128:$dst, (int_x86_sse2_div_sd VR128:$src1,
- (load addr:$s
[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.65 -> 1.66
---
Log message:
Allow targets to have fine grained control over which types various ops get
promoted to, if they desire.
---
Diffs of the changes: (+29 -5)
TargetLowering.h | 34 +-
1 files changed, 29 insertions(+), 5 deletions(-)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.65
llvm/include/llvm/Target/TargetLowering.h:1.66
--- llvm/include/llvm/Target/TargetLowering.h:1.65 Thu Mar 30 18:46:26 2006
+++ llvm/include/llvm/Target/TargetLowering.h Mon Apr 3 19:25:10 2006
@@ -24,9 +24,7 @@
#include "llvm/Type.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
-#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/Support/DataTypes.h"
-#include
+#include
namespace llvm {
class Value;
@@ -172,7 +170,7 @@
MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
return TransformToType[VT];
}
-
+
/// getPackedTypeBreakdown - Packed types are broken down into some number of
/// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values
/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP
stack.
@@ -223,6 +221,16 @@
MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
assert(getOperationAction(Op, VT) == Promote &&
"This operation isn't promoted!");
+
+// See if this has an explicit type specified.
+std::map,
+ MVT::ValueType>::const_iterator PTTI =
+ PromoteToType.find(std::make_pair(Op, VT));
+if (PTTI != PromoteToType.end()) return PTTI->second;
+
+assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
+ "Cannot autopromote this type, add it with AddPromotedToType.");
+
MVT::ValueType NVT = VT;
do {
NVT = (MVT::ValueType)(NVT+1);
@@ -484,6 +492,15 @@
OpActions[Op] &= ~(3ULL << VT*2);
OpActions[Op] |= (uint64_t)Action << VT*2;
}
+
+ /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
+ /// promotion code defaults to trying a larger integer/fp until it can find
+ /// one that works. If that default is insufficient, this method can be used
+ /// by the target to override the default.
+ void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
+ MVT::ValueType DestVT) {
+PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
+ }
/// addLegalFPImmediate - Indicate that this target can instruction select
/// the specified FP immediate natively.
@@ -629,7 +646,6 @@
private:
std::vector LegalAddressScales;
-private:
TargetMachine &TM;
const TargetData &TD;
@@ -715,6 +731,14 @@
/// which sets a bit in this array.
unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
+ /// PromoteToType - For operations that must be promoted to a specific type,
+ /// this holds the destination type. This map should be sparse, so don't
hold
+ /// it as an array.
+ ///
+ /// Targets add entries to this map with AddPromotedToType(..), clients
access
+ /// this with getTypeToPromoteTo(..).
+ std::map, MVT::ValueType> PromoteToType;
+
protected:
/// When lowering %llvm.memset this field specifies the maximum number of
/// store operations that may be substituted for the call to memset. Targets
___
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llvm-commits@cs.uiuc.edu
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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/
Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE: --- Log message: Directory /var/cvs/llvm/llvm-test/SingleSource/UnitTests/Vector/SSE added to the repository --- Diffs of the changes: (+0 -0) 0 files changed ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/Makefile
Changes in directory llvm-test/SingleSource/UnitTests/Vector: Makefile updated: 1.2 -> 1.3 --- Log message: Added some Altivec and SSE examples from: Introduction to Parallel Computing A practical guide with examples in C Oxford Texts in Applied and Engineering Mathematics No. 9 Oxford University Press, February 2004 ISBN: 0-19-851576-6 (hardback), 0-19-851577-4 (paperback) http://people.inf.ethz.ch/arbenz/book/ --- Diffs of the changes: (+4 -0) Makefile |4 1 files changed, 4 insertions(+) Index: llvm-test/SingleSource/UnitTests/Vector/Makefile diff -u llvm-test/SingleSource/UnitTests/Vector/Makefile:1.2 llvm-test/SingleSource/UnitTests/Vector/Makefile:1.3 --- llvm-test/SingleSource/UnitTests/Vector/Makefile:1.2Sun Mar 26 23:54:42 2006 +++ llvm-test/SingleSource/UnitTests/Vector/MakefileMon Apr 3 19:47:54 2006 @@ -9,6 +9,10 @@ DIRS += Altivec endif +ifeq ($(ARCH),x86) +DIRS += SSE +endif + include $(LEVEL)/SingleSource/Makefile.singlesrc ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c alti.isamax.c alti.sdot.c alti.stepfft.c
Changes in directory llvm-test/SingleSource/UnitTests/Vector/Altivec:
alti.expandfft.c added (r1.1)
alti.isamax.c added (r1.1)
alti.sdot.c added (r1.1)
alti.stepfft.c added (r1.1)
---
Log message:
Added some Altivec and SSE examples from:
Introduction to Parallel Computing
A practical guide with examples in C
Oxford Texts in Applied and Engineering Mathematics No. 9
Oxford University Press, February 2004
ISBN: 0-19-851576-6 (hardback), 0-19-851577-4 (paperback)
http://people.inf.ethz.ch/arbenz/book/
---
Diffs of the changes: (+725 -0)
alti.expandfft.c | 287 +++
alti.isamax.c| 131 +
alti.sdot.c | 103 +++
alti.stepfft.c | 204 +++
4 files changed, 725 insertions(+)
Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c
diff -c /dev/null
llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.1
*** /dev/null Mon Apr 3 19:48:04 2006
--- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.cMon Apr
3 19:47:54 2006
***
*** 0
--- 1,287
+ #include
+ #include
+ #include
+ #include
+ #define N 1048576
+ #define N2 N/2
+ main()
+ {
+ /*
+Example of Apple Altivec coded binary radix FFT
+using intrinsics from Petersen and Arbenz "Intro.
+to Parallel Computing," Section 3.6
+
+This is an expanded version of a generic work-space
+FFT: steps are in-line. cfft2(n,x,y,w,sign) takes complex
+n-array "x" (Fortran real,aimag,real,aimag,... order)
+and writes its DFT in "y". Both input "x" and the
+original contents of "y" are destroyed. Initialization
+for array "w" (size n/2 complex of twiddle factors
+(exp(twopi*i*k/n), for k=0..n/2-1)) is computed once
+by cffti(n,w).
+
+ WPP, SAM. Math. ETHZ, 1 June, 2002
+ */
+
+int first,i,icase,it,ln2,n;
+int nits=100;
+static float seed = 331.0;
+float error,fnm1,sign,z0,z1,ggl();
+float *x,*y,*z,*w;
+double t1,mflops;
+void cffti(),cfft2();
+ /* allocate storage for x,y,z,w on 4-word bndr. */
+x = (float *) malloc(8*N);
+y = (float *) malloc(8*N);
+z = (float *) malloc(8*N);
+w = (float *) malloc(4*N);
+n = 2;
+for(ln2=1;ln2<21;ln2++){
+ first = 1;
+ for(icase=0;icase<2;icase++){
+ if(first){
+ for(i=0;i<2*n;i+=2){
+z0 = ggl(&seed); /* real part of array */
+z1 = ggl(&seed); /* imaginary part of array */
+x[i] = z0;
+z[i] = z0; /* copy of initial real data */
+x[i+1] = z1;
+z[i+1] = z1; /* copy of initial imag. data */
+ }
+ } else {
+ for(i=0;i<2*n;i+=2){
+z0 = 0; /* real part of array */
+z1 = 0; /* imaginary part of array */
+x[i] = z0;
+z[i] = z0; /* copy of initial real data */
+x[i+1] = z1;
+z[i+1] = z1; /* copy of initial imag. data */
+ }
+ }
+ /* initialize sine/cosine tables */
+ cffti(n,w);
+ /* transform forward, back */
+ if(first){
+ sign = 1.0;
+ cfft2(n,x,y,w,sign);
+ sign = -1.0;
+ cfft2(n,y,x,w,sign);
+ /* results should be same as initial multiplied by n */
+ fnm1 = 1.0/((float) n);
+ error = 0.0;
+ for(i=0;i<2*n;i+=2){
+error += (z[i] - fnm1*x[i])*(z[i] - fnm1*x[i]) +
+(z[i+1] - fnm1*x[i+1])*(z[i+1] - fnm1*x[i+1]);
+ }
+ error = sqrt(fnm1*error);
+ printf(" for n=%d, fwd/bck error=%e\n",n,error);
+ first = 0;
+ } else {
+ t1 = ((double)clock())/((double) CLOCKS_PER_SEC);
+ for(it=0;it y */
+for(j=0;j
+ float ggl(float *ds)
+ {
+
+ /* generate u(0,1) distributed random numbers.
+Seed ds must be saved between calls. ggl is
+essentially the same as the IMSL routine RNUM.
+
+W. Petersen and M. Troyer, 24 Oct. 2002, ETHZ:
+a modification of a fortran version from
+I. Vattulainen, Tampere Univ. of Technology,
+Finland, 1992 */
+
+double t,d2=0.2147483647e10;
+t = (float) *ds;
+t = fmod(0.16807e5*t,d2);
+*ds = (float) t;
+return((float) ((t-1.0e0)/(d2-1.0e0)));
+ }
Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c
diff -c /dev/null
llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c:1.1
*** /dev/null Mon Apr 3 19:48:09 2006
--- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c Mon Apr
3 19:47:54 2006
***
*** 0
--- 1,131
+ #include
+ #include
+ #include
+ #define N 1027
+ main()
+ {
+ /*
+ Mac G-4 unit st
[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/Makefile sse.expandfft.c sse.isamax.c sse.stepfft.c
Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE:
Makefile added (r1.1)
sse.expandfft.c added (r1.1)
sse.isamax.c added (r1.1)
sse.stepfft.c added (r1.1)
---
Log message:
Added some Altivec and SSE examples from:
Introduction to Parallel Computing
A practical guide with examples in C
Oxford Texts in Applied and Engineering Mathematics No. 9
Oxford University Press, February 2004
ISBN: 0-19-851576-6 (hardback), 0-19-851577-4 (paperback)
http://people.inf.ethz.ch/arbenz/book/
---
Diffs of the changes: (+585 -0)
Makefile|8 +
sse.expandfft.c | 263
sse.isamax.c| 119 +
sse.stepfft.c | 195 +
4 files changed, 585 insertions(+)
Index: llvm-test/SingleSource/UnitTests/Vector/SSE/Makefile
diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/SSE/Makefile:1.1
*** /dev/null Mon Apr 3 19:48:04 2006
--- llvm-test/SingleSource/UnitTests/Vector/SSE/MakefileMon Apr 3
19:47:54 2006
***
*** 0
--- 1,8
+ # SingleSource/UnitTests/Vector/SSE/Makefile
+
+ DIRS =
+ LEVEL = ../../../..
+ include $(LEVEL)/SingleSource/Makefile.singlesrc
+
+ TARGET_CFLAGS += -msse3
+ LCCFLAGS += -msse3
Index: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c
diff -c /dev/null
llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.1
*** /dev/null Mon Apr 3 19:48:08 2006
--- llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c Mon Apr 3
19:47:54 2006
***
*** 0
--- 1,263
+ #include
+ #include
+ #include
+ #include
+ #include "xmmintrin.h"
+ #define N 256
+ #define N2 N/2
+ main()
+ {
+ /*
+SSE version of cfft2 - uses Intel intrinsics.
+Expanded version
+
+ wpp, SAM. Math. ETHZ 21 May, 2002
+ */
+int first,i,icase,it,n;
+float error,fnm1,seed,sign,z0,z1,ggl();
+float *x,*y,*z,*w;
+float t1,ln2,mflops;
+void cffti(),cfft2();
+ /* allocate storage for x,y,z,w on 4-word bndr. */
+x = (float *)_mm_malloc(8*N, 16);
+y = (float *)_mm_malloc(8*N, 16);
+z = (float *)_mm_malloc(8*N, 16);
+w = (float *)_mm_malloc(4*N, 16);
+first = 1;
+seed = 331.0;
+for(icase=0;icase<2;icase++){
+if(first){
+ for(i=0;i<2*N;i+=2){
+ z0 = ggl(&seed); /* real part of array */
+ z1 = ggl(&seed); /* imaginary part of array */
+ x[i] = z0;
+ z[i] = z0; /* copy of initial real data */
+ x[i+1] = z1;
+ z[i+1] = z1; /* copy of initial imag. data */
+ }
+} else {
+ for(i=0;i<2*N;i+=2){
+ z0 = 0; /* real part of array */
+ z1 = 0; /* imaginary part of array */
+ x[i] = z0;
+ z[i] = z0; /* copy of initial real data */
+ x[i+1] = z1;
+ z[i+1] = z1; /* copy of initial imag. data */
+ }
+}
+ /* initialize sine/cosine tables */
+n = N;
+cffti(n,w);
+ /* transform forward, back */
+if(first){
+ sign = 1.0;
+ cfft2(n,x,y,w,sign);
+ sign = -1.0;
+ cfft2(n,y,x,w,sign);
+ /* results should be same as initial multiplied by N */
+ fnm1 = 1.0/((float) n);
+ error = 0.0;
+ for(i=0;i<2*N;i+=2){
+ error += (z[i] - fnm1*x[i])*(z[i] - fnm1*x[i]) +
+ (z[i+1] - fnm1*x[i+1])*(z[i+1] - fnm1*x[i+1]);
+ }
+ error = sqrt(fnm1*error);
+ printf(" for n=%d, fwd/bck error=%e\n",N,error);
+ first = 0;
+} else {
+ t1 = ((float)clock())/((float) CLOCKS_PER_SEC);
+ for(it=0;it<1000;it++){
+ sign = +1.0;
+ cfft2(n,x,y,w,sign);
+ sign = -1.0;
+ cfft2(n,y,x,w,sign);
+ }
+ t1 = ((float)clock())/((float) CLOCKS_PER_SEC) - t1;
+ t1 = t1/2000.0;
+ ln2 = 10.0; // reset this for different N
+ mflops = 5.0*((float) N)*ln2/((1.e+6)*t1);
+ printf(" for n=%d, t1=%e, mflops=%e\n",n,t1,mflops);
+}
+}
+ }
+ void cfft2(n,x,y,w,sign)
+ int n;
+ float x[][2],y[][2],w[][2],sign;
+ {
+int jb, jc, jw, k, k2, lj, m, j, mj, mj2, pass, tgle;
+float (*a)[2],(*b)[2],(*c)[2],(*d)[2];
+float (*aa)[2],(*bb)[2],(*cb)[2],(*dd)[2];
+float rp,up,wr[4],wu[4];
+__m128 V0,V1,V2,V3,V4,V5,V6,V7;
+__m128 V8,V9,V10,V11,V12,V13,V14,V15;
+
+if(n<=1){
+ y[0][0] = x[0][0];
+ y[0][1] = x[0][1];
+ return;
+}
+m= (int) (log((float) n)/log(1.99));
+mj = 1;
+mj2 = 2;
+lj = n/2;
+ // first pass thru data: x -> y
+a = (void *)&x[0][0];
+b = (void *)&x[n/2][0];
+c = (void *)&y[0][0];
+d = (void *)&y[1][0];
+for(j=0;j
+ float ggl(float *ds)
+ {
+ /* generate u(0,1) distributed random numbers.
+Seed ds must be saved between calls. ggl is
+essentially the same as the IMSL routine RNUM.
+
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.295 -> 1.296 --- Log message: Constant fold bitconvert(undef) --- Diffs of the changes: (+2 -0) SelectionDAG.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.295 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.296 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.295Sat Apr 1 20:51:27 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Apr 3 20:02:22 2006 @@ -1167,6 +1167,8 @@ if (VT == Operand.getValueType()) return Operand; // noop conversion. if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); +if (OpOpcode == ISD::UNDEF) + return getNode(ISD::UNDEF, VT); break; case ISD::SCALAR_TO_VECTOR: assert(MVT::isVector(VT) && !MVT::isVector(Operand.getValueType()) && ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td
Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.13 -> 1.14 --- Log message: Fix the types for these intrinsics. --- Diffs of the changes: (+6 -6) IntrinsicsPowerPC.td | 12 ++-- 1 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.13 llvm/include/llvm/IntrinsicsPowerPC.td:1.14 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.13 Mon Apr 3 12:20:06 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Mon Apr 3 20:40:06 2006 @@ -122,23 +122,23 @@ [InstrNoMem]>; def int_ppc_altivec_vcmpequh : GCCBuiltin<"__builtin_altivec_vcmpequh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; def int_ppc_altivec_vcmpgtsh : GCCBuiltin<"__builtin_altivec_vcmpgtsh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; def int_ppc_altivec_vcmpgtuh : GCCBuiltin<"__builtin_altivec_vcmpgtuh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; def int_ppc_altivec_vcmpequb : GCCBuiltin<"__builtin_altivec_vcmpequb">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], [InstrNoMem]>; def int_ppc_altivec_vcmpgtsb : GCCBuiltin<"__builtin_altivec_vcmpgtsb">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], [InstrNoMem]>; def int_ppc_altivec_vcmpgtub : GCCBuiltin<"__builtin_altivec_vcmpgtub">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], [InstrNoMem]>; // Predicate Comparisons. The first operand specifies interpretation of CR6. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.57 -> 1.58
---
Log message:
cmpps / cmppd encoding bug
---
Diffs of the changes: (+16 -16)
X86InstrSSE.td | 32
1 files changed, 16 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.57
llvm/lib/Target/X86/X86InstrSSE.td:1.58
--- llvm/lib/Target/X86/X86InstrSSE.td:1.57 Mon Apr 3 19:10:53 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 22:04:07 2006
@@ -963,22 +963,22 @@
}
let isTwoAddress = 1 in {
-def CMPPSrr : PSI<0xC2, MRMSrcReg,
- (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
- "cmp${cc}ps {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
- VR128:$src, imm:$cc))]>;
-def CMPPSrm : PSI<0xC2, MRMSrcMem,
- (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
- "cmp${cc}ps {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
- (load addr:$src), imm:$cc))]>;
-def CMPPDrr : PDI<0xC2, MRMSrcReg,
- (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
- "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
-def CMPPDrm : PDI<0xC2, MRMSrcMem,
- (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
- "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
+def CMPPSrr : PSIi8<0xC2, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
+"cmp${cc}ps {$src, $dst|$dst, $src}",
+[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
+ VR128:$src, imm:$cc))]>;
+def CMPPSrm : PSIi8<0xC2, MRMSrcMem,
+(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
+"cmp${cc}ps {$src, $dst|$dst, $src}",
+[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
+ (load addr:$src), imm:$cc))]>;
+def CMPPDrr : PDIi8<0xC2, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
+"cmp${cc}pd {$src, $dst|$dst, $src}", []>;
+def CMPPDrm : PDIi8<0xC2, MRMSrcMem,
+(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
+"cmp${cc}pd {$src, $dst|$dst, $src}", []>;
}
// Shuffle and unpack instructions
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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c alti.isamax.c alti.sdot.c alti.stepfft.c
Changes in directory llvm-test/SingleSource/UnitTests/Vector/Altivec:
alti.expandfft.c updated: 1.1 -> 1.2
alti.isamax.c updated: 1.1 -> 1.2
alti.sdot.c updated: 1.1 -> 1.2
alti.stepfft.c updated: 1.1 -> 1.2
---
Log message:
adjust these to allow them to compile.
---
Diffs of the changes: (+8 -1)
alti.expandfft.c |6 +-
alti.isamax.c|1 +
alti.sdot.c |1 +
alti.stepfft.c |1 +
4 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c
diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.1
llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.2
--- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.1
Mon Apr 3 19:47:54 2006
+++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.cTue Apr
4 01:08:25 2006
@@ -2,8 +2,13 @@
#include
#include
#include
+#include
+#include
#define N 1048576
#define N2 N/2
+void cfft2(unsigned int n,float x[][2],float y[][2],float w[][2], float sign);
+void cffti(int n, float w[][2]);
+
main()
{
/*
@@ -29,7 +34,6 @@
float error,fnm1,sign,z0,z1,ggl();
float *x,*y,*z,*w;
double t1,mflops;
- void cffti(),cfft2();
/* allocate storage for x,y,z,w on 4-word bndr. */
x = (float *) malloc(8*N);
y = (float *) malloc(8*N);
Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c
diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c:1.1
llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c:1.2
--- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c:1.1 Mon Apr
3 19:47:54 2006
+++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c Tue Apr
4 01:08:25 2006
@@ -1,6 +1,7 @@
#include
#include
#include
+#include
#define N 1027
main()
{
Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c
diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c:1.1
llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c:1.2
--- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c:1.1 Mon Apr
3 19:47:54 2006
+++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c Tue Apr 4
01:08:25 2006
@@ -1,4 +1,5 @@
#include
+#include
#include
#include
#define N 1027
Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c
diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c:1.1
llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c:1.2
--- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c:1.1 Mon Apr
3 19:47:54 2006
+++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c Tue Apr
4 01:08:25 2006
@@ -2,6 +2,7 @@
#include
#include
#include
+#include
#define N 128
#define N2 N/2
main()
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[llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolution.cpp
Changes in directory llvm/lib/Analysis:
ScalarEvolution.cpp updated: 1.46 -> 1.47
---
Log message:
Signed shr by a constant is not the same as sdiv by 2^k
---
Diffs of the changes: (+0 -9)
ScalarEvolution.cpp |9 -
1 files changed, 9 deletions(-)
Index: llvm/lib/Analysis/ScalarEvolution.cpp
diff -u llvm/lib/Analysis/ScalarEvolution.cpp:1.46
llvm/lib/Analysis/ScalarEvolution.cpp:1.47
--- llvm/lib/Analysis/ScalarEvolution.cpp:1.46 Fri Mar 31 22:48:52 2006
+++ llvm/lib/Analysis/ScalarEvolution.cpp Tue Apr 4 01:11:42 2006
@@ -1374,15 +1374,6 @@
}
break;
-case Instruction::Shr:
- if (ConstantUInt *SA = dyn_cast(I->getOperand(1)))
-if (V->getType()->isSigned()) {
- Constant *X = ConstantInt::get(V->getType(), 1);
- X = ConstantExpr::getShl(X, SA);
- return SCEVSDivExpr::get(getSCEV(I->getOperand(0)), getSCEV(X));
-}
- break;
-
case Instruction::Cast:
return createNodeForCast(cast(I));
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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/multiplies.c helpers.h
Changes in directory llvm-test/SingleSource/UnitTests/Vector:
multiplies.c added (r1.1)
helpers.h updated: 1.4 -> 1.5
---
Log message:
new testcase for multiplies
---
Diffs of the changes: (+50 -0)
helpers.h| 16
multiplies.c | 34 ++
2 files changed, 50 insertions(+)
Index: llvm-test/SingleSource/UnitTests/Vector/multiplies.c
diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/multiplies.c:1.1
*** /dev/null Tue Apr 4 01:50:34 2006
--- llvm-test/SingleSource/UnitTests/Vector/multiplies.cTue Apr 4
01:50:24 2006
***
*** 0
--- 1,34
+ #include "helpers.h"
+
+ #define ARRAYSIZE 10
+ double TheArray[ARRAYSIZE];
+
+ #define ProcessArray(VECTY) { \
+ VECTY V = (VECTY)((v4i32){0,0,0,0}); \
+ VECTY *AP = (VECTY*)TheArray; \
+ IV vu; \
+ for (j = 0; j < 1000; ++j) \
+ for (i = 0; i != sizeof(TheArray)/sizeof(VECTY); ++i) \
+ V *= AP[i];\
+ vu.V = (v4i32)V;\
+ printIV(&vu);\
+ }
+
+
+ int main(int argc, char **Argv) {
+ unsigned i, j;
+ for (i = 0; i < ARRAYSIZE; ++i)
+ TheArray[i] = i*12.345;
+
+ ProcessArray(v16i8);
+ ProcessArray(v8i16);
+ ProcessArray(v4i32);
+ ProcessArray(v2i64);
+
+ // These break native gcc. :(
+ #if 0
+ ProcessArray(v4f32);
+ ProcessArray(v2f64);
+ #endif
+ }
+
Index: llvm-test/SingleSource/UnitTests/Vector/helpers.h
diff -u llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.4
llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.5
--- llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.4 Thu Mar 30
20:11:46 2006
+++ llvm-test/SingleSource/UnitTests/Vector/helpers.h Tue Apr 4 01:50:24 2006
@@ -7,6 +7,18 @@
typedef float v8sf __attribute__ ((__vector_size__ (32)));
typedef double v8sd __attribute__ ((__vector_size__ (64)));
+typedef intv2i64 __attribute__ ((__vector_size__ (16)));
+typedef intv4i32 __attribute__ ((__vector_size__ (16)));
+typedef short v8i16 __attribute__ ((__vector_size__ (16)));
+typedef char v16i8 __attribute__ ((__vector_size__ (16)));
+typedef float v4f32 __attribute__ ((__vector_size__ (16)));
+typedef double v2f64 __attribute__ ((__vector_size__ (16)));
+
+typedef union {
+ v4i32 V;
+ int A[4];
+} IV;
+
typedef union {
v4sf V;
float A[4];
@@ -22,6 +34,10 @@
double A[8];
} D8V;
+static void printIV(IV *F) {
+ printf("%u %u %u %u\n", F->A[0], F->A[1], F->A[2], F->A[3]);
+}
+
static void printFV(FV *F) {
printf("%f %f %f %f\n", F->A[0], F->A[1], F->A[2], F->A[3]);
}
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