[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.344 -> 1.345
---
Log message:
Scalarized vector stores need not be legal, e.g. if the vector element type
needs to be promoted or expanded. Relegalize the scalar store once created.
This fixes CodeGen/Generic/vector.ll:test1 on non-SSE x86 targets.
---
Diffs of the changes: (+3 -0)
LegalizeDAG.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.344
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.345
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.344 Thu Mar 30 20:06:55 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Mar 31 11:37:22 2006
@@ -1477,6 +1477,9 @@
Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
Node->getOperand(3));
+ // The scalarized value type may not be legal, e.g. it might require
+ // promotion or expansion. Relegalize the scalar store.
+ Result = LegalizeOp(Result);
break;
} else {
SplitVectorOp(Node->getOperand(1), Lo, Hi);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.345 -> 1.346
---
Log message:
Implement PromoteOp for VEXTRACT_VECTOR_ELT. Thsi fixes
Generic/vector.ll:test_extract_elt on non-sse X86 systems.
---
Diffs of the changes: (+54 -42)
LegalizeDAG.cpp | 96 +++-
1 files changed, 54 insertions(+), 42 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.345
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.346
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.345 Fri Mar 31 11:37:22 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Mar 31 11:55:51 2006
@@ -184,6 +184,8 @@
void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
SDOperand &Lo, SDOperand &Hi);
+ SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
+
SDOperand getIntPtrConstant(uint64_t Val) {
return DAG.getConstant(Val, TLI.getPointerTy());
}
@@ -910,49 +912,9 @@
}
break;
- case ISD::VEXTRACT_VECTOR_ELT: {
-// We know that operand #0 is the Vec vector. If the index is a constant
-// or if the invec is a supported hardware type, we can use it. Otherwise,
-// lower to a store then an indexed load.
-Tmp1 = Node->getOperand(0);
-Tmp2 = LegalizeOp(Node->getOperand(1));
-
-SDNode *InVal = Tmp1.Val;
-unsigned NumElems = cast(*(InVal->op_end()-2))->getValue();
-MVT::ValueType EVT = cast(*(InVal->op_end()-1))->getVT();
-
-// Figure out if there is a Packed type corresponding to this Vector
-// type. If so, convert to the packed type.
-MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
-if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
- // Turn this into a packed extract_vector_elt operation.
- Tmp1 = PackVectorOp(Tmp1, TVT);
- Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Node->getValueType(0),
- Tmp1, Tmp2);
- break;
-} else if (NumElems == 1) {
- // This must be an access of the only element.
- Result = PackVectorOp(Tmp1, EVT);
- break;
-} else if (ConstantSDNode *CIdx = dyn_cast(Tmp2)) {
- SDOperand Lo, Hi;
- SplitVectorOp(Tmp1, Lo, Hi);
- if (CIdx->getValue() < NumElems/2) {
-Tmp1 = Lo;
- } else {
-Tmp1 = Hi;
-Tmp2 = DAG.getConstant(CIdx->getValue() - NumElems/2,
- Tmp2.getValueType());
- }
-
- // It's now an extract from the appropriate high or low part.
- Result = LegalizeOp(DAG.UpdateNodeOperands(Result, Tmp1, Tmp2));
-} else {
- // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
- assert(0 && "unimp!");
-}
+ case ISD::VEXTRACT_VECTOR_ELT:
+Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
break;
- }
case ISD::CALLSEQ_START: {
SDNode *CallEnd = FindCallEndFromCallStart(Node);
@@ -2999,6 +2961,9 @@
break;
}
break;
+ case ISD::VEXTRACT_VECTOR_ELT:
+Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
+break;
}
assert(Result.Val && "Didn't set a result!");
@@ -3011,6 +2976,53 @@
return Result;
}
+/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
+/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
+/// on the vector type. The return type of this matches the element type of
the
+/// vector, which may not be legal for the target.
+SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
+ // We know that operand #0 is the Vec vector. If the index is a constant
+ // or if the invec is a supported hardware type, we can use it. Otherwise,
+ // lower to a store then an indexed load.
+ SDOperand Vec = Op.getOperand(0);
+ SDOperand Idx = LegalizeOp(Op.getOperand(1));
+
+ SDNode *InVal = Vec.Val;
+ unsigned NumElems = cast(*(InVal->op_end()-2))->getValue();
+ MVT::ValueType EVT = cast(*(InVal->op_end()-1))->getVT();
+
+ // Figure out if there is a Packed type corresponding to this Vector
+ // type. If so, convert to the packed type.
+ MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+ if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
+// Turn this into a packed extract_vector_elt operation.
+Vec = PackVectorOp(Vec, TVT);
+return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
+ } else if (NumElems == 1) {
+// This must be an access of the only element. Return it.
+return PackVectorOp(Vec, EVT);
+ } else if (ConstantSDNode *CIdx = dyn_cast(Idx)) {
+SDOperand Lo, Hi;
+SplitVectorOp(Vec, Lo, Hi);
+if (CIdx->getValue() < NumElems/2) {
+ Vec = Lo;
+} else {
+ Vec = Hi;
+ Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
+}
+
+// It's now an extract from the appropriate high or low part. Recurse.
+O
[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll
Changes in directory llvm/test/Regression/CodeGen/Generic:
vector.ll updated: 1.7 -> 1.8
---
Log message:
Make this test harder, always check generic x86 and SSE-enabled x86.
---
Diffs of the changes: (+10 -1)
vector.ll | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.7
llvm/test/Regression/CodeGen/Generic/vector.ll:1.8
--- llvm/test/Regression/CodeGen/Generic/vector.ll:1.7 Thu Mar 23 15:15:57 2006
+++ llvm/test/Regression/CodeGen/Generic/vector.ll Fri Mar 31 11:59:16 2006
@@ -1,13 +1,16 @@
; Test that vectors are scalarized/lowered correctly.
; RUN: llvm-as < %s | llc &&
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 &&
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 &&
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 &&
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah
%f1 = type <1 x float>
%f2 = type <2 x float>
%f4 = type <4 x float>
%i4 = type <4 x int>
%f8 = type <8 x float>
+%d8 = type <8 x double>
implementation
@@ -99,6 +102,12 @@
ret float %R
}
+double %test_extract_elt2(%d8 *%P) {
+ %p = load %d8* %P
+ %R = extractelement %d8 %p, uint 3
+ ret double %R
+}
+
void %test_cast_1(<4 x float>* %b, <4 x int>* %a) {
%tmp = load <4 x float>* %b
%tmp2 = add <4 x float> %tmp,
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.133 -> 1.134 --- Log message: Delete dead loads in the dag. This allows us to compile vector.ll:test_extract_elt2 into: _test_extract_elt2: lfd f1, 32(r3) blr instead of: _test_extract_elt2: lfd f0, 56(r3) lfd f0, 48(r3) lfd f0, 40(r3) lfd f1, 32(r3) lfd f0, 24(r3) lfd f0, 16(r3) lfd f0, 8(r3) lfd f0, 0(r3) blr --- Diffs of the changes: (+5 -0) DAGCombiner.cpp |5 + 1 files changed, 5 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.133 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.134 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.133 Tue Mar 28 16:19:47 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Mar 31 12:06:18 2006 @@ -2261,6 +2261,11 @@ SDOperand Chain= N->getOperand(0); SDOperand Ptr = N->getOperand(1); SDOperand SrcValue = N->getOperand(2); + + // If there are no uses of the loaded value, change uses of the chain value + // into uses of the chain input (i.e. delete the dead load). + if (N->hasNUsesOfValue(0, 0)) +return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); // If this load is directly stored, replace the load value with the stored // value. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.134 -> 1.135
---
Log message:
Remove dead *extloads. This allows us to codegen vector.ll:test_extract_elt
to:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 12, r32
;;
ldfs f8 = [r8]
mov ar.pfs = r3
br.ret.sptk.many rp
instead of:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 28, r32
adds r9 = 24, r32
adds r10 = 20, r32
adds r11 = 16, r32
;;
ldfs f6 = [r8]
;;
ldfs f6 = [r9]
adds r8 = 12, r32
adds r9 = 8, r32
adds r14 = 4, r32
;;
ldfs f6 = [r10]
;;
ldfs f6 = [r11]
ldfs f8 = [r8]
;;
ldfs f6 = [r9]
;;
ldfs f6 = [r14]
;;
ldfs f6 = [r32]
mov ar.pfs = r3
br.ret.sptk.many rp
---
Diffs of the changes: (+19 -0)
DAGCombiner.cpp | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.134
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.135
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.134 Fri Mar 31 12:06:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Mar 31 12:10:41 2006
@@ -208,6 +208,7 @@
SDOperand visitBRCOND(SDNode *N);
SDOperand visitBR_CC(SDNode *N);
SDOperand visitLOAD(SDNode *N);
+SDOperand visitXEXTLOAD(SDNode *N);
SDOperand visitSTORE(SDNode *N);
SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
@@ -643,6 +644,9 @@
case ISD::BRCOND: return visitBRCOND(N);
case ISD::BR_CC: return visitBR_CC(N);
case ISD::LOAD: return visitLOAD(N);
+ case ISD::EXTLOAD:
+ case ISD::SEXTLOAD:
+ case ISD::ZEXTLOAD: return visitXEXTLOAD(N);
case ISD::STORE: return visitSTORE(N);
case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
@@ -2278,6 +2282,21 @@
return SDOperand();
}
+/// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD.
+SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) {
+ SDOperand Chain= N->getOperand(0);
+ SDOperand Ptr = N->getOperand(1);
+ SDOperand SrcValue = N->getOperand(2);
+ SDOperand EVT = N->getOperand(3);
+
+ // If there are no uses of the loaded value, change uses of the chain value
+ // into uses of the chain input (i.e. delete the dead load).
+ if (N->hasNUsesOfValue(0, 0))
+return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
+
+ return SDOperand();
+}
+
SDOperand DAGCombiner::visitSTORE(SDNode *N) {
SDOperand Chain= N->getOperand(0);
SDOperand Value= N->getOperand(1);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.346 -> 1.347
---
Log message:
Do not endian swap the operands to a store if the operands came from a vector.
This fixes UnitTests/Vector/simple.c with altivec.
---
Diffs of the changes: (+3 -3)
LegalizeDAG.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.346
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.347
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.346 Fri Mar 31 11:55:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Mar 31 12:20:46 2006
@@ -1450,10 +1450,10 @@
} else {
ExpandOp(Node->getOperand(1), Lo, Hi);
IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
- }
- if (!TLI.isLittleEndian())
-std::swap(Lo, Hi);
+if (!TLI.isLittleEndian())
+ std::swap(Lo, Hi);
+ }
Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
Node->getOperand(3));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.347 -> 1.348
---
Log message:
Do not endian swap split vector loads. This fixes
UnitTests/Vector/sumarray-dbl on PPC.
Now all UnitTests/Vector/* tests pass on PPC.
---
Diffs of the changes: (+0 -2)
LegalizeDAG.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.347
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.348
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.347 Fri Mar 31 12:20:46 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Mar 31 12:22:37 2006
@@ -4453,8 +4453,6 @@
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
-if (!TLI.isLittleEndian())
- std::swap(Lo, Hi);
break;
}
case ISD::VBIT_CONVERT: {
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.454 -> 1.455
---
Log message:
extractelement(undef,x) -> undef
---
Diffs of the changes: (+8 -6)
InstructionCombining.cpp | 14 --
1 files changed, 8 insertions(+), 6 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.454
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.455
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.454 Thu Mar 30
16:02:40 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri Mar 31 12:25:14 2006
@@ -6655,12 +6655,14 @@
}
Instruction *InstCombiner::visitExtractElementInst(ExtractElementInst &EI) {
- if (ConstantAggregateZero *C =
- dyn_cast(EI.getOperand(0))) {
-// If packed val is constant 0, replace extract with scalar 0
-const Type *Ty = cast(C->getType())->getElementType();
-return ReplaceInstUsesWith(EI, Constant::getNullValue(Ty));
- }
+ // If packed val is undef, replace extract with scalar undef.
+ if (isa(EI.getOperand(0)))
+return ReplaceInstUsesWith(EI, UndefValue::get(EI.getType()));
+
+ // If packed val is constant 0, replace extract with scalar 0.
+ if (isa(EI.getOperand(0)))
+return ReplaceInstUsesWith(EI, Constant::getNullValue(EI.getType()));
+
if (ConstantPacked *C = dyn_cast(EI.getOperand(0))) {
// If packed val is constant with uniform operands, replace EI
// with that operand
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[llvm-commits] CVS: llvm/lib/VMCore/ConstantFolding.cpp
Changes in directory llvm/lib/VMCore:
ConstantFolding.cpp updated: 1.83 -> 1.84
---
Log message:
constant fold extractelement with undef operands.
---
Diffs of the changes: (+7 -1)
ConstantFolding.cpp |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/lib/VMCore/ConstantFolding.cpp
diff -u llvm/lib/VMCore/ConstantFolding.cpp:1.83
llvm/lib/VMCore/ConstantFolding.cpp:1.84
--- llvm/lib/VMCore/ConstantFolding.cpp:1.83Tue Jan 17 14:07:22 2006
+++ llvm/lib/VMCore/ConstantFolding.cpp Fri Mar 31 12:31:40 2006
@@ -726,11 +726,17 @@
Constant *llvm::ConstantFoldExtractElementInstruction(const Constant *Val,
const Constant *Idx) {
+ if (isa(Val)) // ee(undef, x) -> undef
+return UndefValue::get(cast(Val->getType())->getElementType());
+
if (const ConstantPacked *CVal = dyn_cast(Val)) {
if (const ConstantUInt *CIdx = dyn_cast(Idx)) {
return const_cast(CVal->getOperand(CIdx->getValue()));
+} else if (isa(Idx)) {
+ // ee({w,x,y,z}, undef) -> w (an arbitrary value).
+ return const_cast(CVal->getOperand(0));
}
- }
+ }
return 0;
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
Changes in directory llvm/lib/Target/PowerPC: README_ALTIVEC.txt updated: 1.8 -> 1.9 --- Log message: add a note --- Diffs of the changes: (+2 -0) README_ALTIVEC.txt |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.8 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.9 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.8 Fri Mar 31 00:02:07 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Fri Mar 31 13:00:22 2006 @@ -135,3 +135,5 @@ //===--===// +Handle VECTOR_SHUFFLE nodes with the appropriate shuffle mask with vsldoi, +vpkuhum and vpkuwum. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.62 -> 1.63 --- Log message: Add vector_extract and vector_insert nodes. --- Diffs of the changes: (+4 -0) TargetSelectionDAG.td |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.62 llvm/lib/Target/TargetSelectionDAG.td:1.63 --- llvm/lib/Target/TargetSelectionDAG.td:1.62 Mon Mar 27 18:40:33 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Mar 31 13:21:16 2006 @@ -310,6 +310,10 @@ def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>; def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, []>; +def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", +SDTypeProfile<1, 2, []>, []>; +def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", +SDTypeProfile<1, 3, []>, []>; // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use // these internally. Don't reference these directly. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.149 -> 1.150
X86ISelLowering.h updated: 1.48 -> 1.49
X86InstrSSE.td updated: 1.50 -> 1.51
---
Log message:
Add support to use pextrw and pinsrw to extract and insert a word element
from a 128-bit vector.
---
Diffs of the changes: (+69 -4)
X86ISelLowering.cpp | 38 --
X86ISelLowering.h |4
X86InstrSSE.td | 31 +--
3 files changed, 69 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.149
llvm/lib/Target/X86/X86ISelLowering.cpp:1.150
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.149 Thu Mar 30 19:30:39 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 31 13:22:53 2006
@@ -255,9 +255,9 @@
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
-setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
+setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
-setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
+setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
}
if (Subtarget->hasMMX()) {
@@ -316,6 +316,8 @@
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
+setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
+setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
}
computeRegisterProperties();
@@ -2657,6 +2659,37 @@
return SDOperand();
}
+ case ISD::EXTRACT_VECTOR_ELT: {
+// Transform it so it match pextrw which produces a 32-bit result.
+MVT::ValueType VT = Op.getValueType();
+if (MVT::getSizeInBits(VT) == 16) {
+ MVT::ValueType EVT = (MVT::ValueType)(VT+1);
+ SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
+ Op.getOperand(0), Op.getOperand(1));
+ SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
+ DAG.getValueType(VT));
+ return DAG.getNode(ISD::TRUNCATE, VT, Assert);
+}
+
+return SDOperand();
+ }
+ case ISD::INSERT_VECTOR_ELT: {
+// Transform it so it match pinsrw which expects a 16-bit value in a R32
+// as its second argument.
+MVT::ValueType VT = Op.getValueType();
+MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
+if (MVT::getSizeInBits(BaseVT) == 16) {
+ SDOperand N1 = Op.getOperand(1);
+ SDOperand N2 = Op.getOperand(2);
+ if (N1.getValueType() != MVT::i32)
+N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
+ if (N2.getValueType() != MVT::i32)
+N2 = DAG.getConstant(cast(N2)->getValue(), MVT::i32);
+ return DAG.getNode(ISD::INSERT_VECTOR_ELT, VT, Op.getOperand(0), N1, N2);
+}
+
+return SDOperand();
+ }
}
}
@@ -2692,6 +2725,7 @@
case X86ISD::Wrapper:return "X86ISD::Wrapper";
case X86ISD::S2VEC: return "X86ISD::S2VEC";
case X86ISD::ZEXT_S2VEC: return "X86ISD::ZEXT_S2VEC";
+ case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
}
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.48
llvm/lib/Target/X86/X86ISelLowering.h:1.49
--- llvm/lib/Target/X86/X86ISelLowering.h:1.48 Wed Mar 29 17:07:14 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Fri Mar 31 13:22:53 2006
@@ -153,6 +153,10 @@
/// ZEXT_S2VEC - SCALAR_TO_VECTOR with zero extension. The destination
base
/// does not have to match the operand type.
ZEXT_S2VEC,
+
+ /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
+ /// i32, corresponds to X86::PINSRW.
+ PEXTRW,
};
// X86 specific condition code. These correspond to X86_*_COND in
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.50
llvm/lib/Target/X86/X86InstrSSE.td:1.51
--- llvm/lib/Target/X86/X86InstrSSE.td:1.50 Thu Mar 30 13:54:57 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Mar 31 13:22:53 2006
@@ -28,8 +28,8 @@
def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
SDTypeProfile<1, 1, []>, []>;
-def SDTUnpckl : SDTypeProfile<1, 2,
- [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
+def X86pextrw : SDNode<"X86ISD::PEXTRW",
+SDTypeProfile<1, 2, []>, []>;
//===--===//
// SSE pattern fragments
@@ -1409,6 +1409,33 @@
UNPCKH_shuffle_mask)))]>
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.122 -> 1.123
---
Log message:
Add, sub and shuffle are legal for all vector types
---
Diffs of the changes: (+9 -8)
PPCISelLowering.cpp | 17 +
1 files changed, 9 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.122
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.123
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.122 Fri Mar 31 00:04:53 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Mar 31 13:48:58 2006
@@ -171,12 +171,16 @@
// First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd.
- for (unsigned VT = (unsigned)MVT::Vector + 1;
- VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
-setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
-setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
+ for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+ VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
+// Add and sub are legal for all supported VT's.
+setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
+setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
+setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Legal);
+
setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
-setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
+setOperationAction(ISD::DIV , (MVT::ValueType)VT, Expand);
+setOperationAction(ISD::REM , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
@@ -188,10 +192,7 @@
addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
-setOperationAction(ISD::ADD, MVT::v4f32, Legal);
-setOperationAction(ISD::SUB, MVT::v4f32, Legal);
setOperationAction(ISD::MUL, MVT::v4f32, Legal);
-setOperationAction(ISD::ADD, MVT::v4i32, Legal);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.123 -> 1.124
---
Log message:
Rearrange code a bit
---
Diffs of the changes: (+25 -21)
PPCISelLowering.cpp | 46 +-
1 files changed, 25 insertions(+), 21 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.123
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.124
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.123 Fri Mar 31 13:48:58 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Mar 31 13:52:36 2006
@@ -168,34 +168,38 @@
setOperationAction(ISD::SRL, MVT::i64, Custom);
setOperationAction(ISD::SRA, MVT::i64, Custom);
}
-
- // First set operation action for all vector types to expand. Then we
- // will selectively turn on ones that can be effectively codegen'd.
- for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
- VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
-// Add and sub are legal for all supported VT's.
-setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
-setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
-setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Legal);
-
-setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
-setOperationAction(ISD::DIV , (MVT::ValueType)VT, Expand);
-setOperationAction(ISD::REM , (MVT::ValueType)VT, Expand);
-setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
-setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
-setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
- }
if (TM.getSubtarget().hasAltivec()) {
+// First set operation action for all vector types to expand. Then we
+// will selectively turn on ones that can be effectively codegen'd.
+for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+ VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
+ // add/sub/and/or/xor are legal for all supported vector VT's.
+ setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
+ setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
+ setOperationAction(ISD::AND , (MVT::ValueType)VT, Legal);
+ setOperationAction(ISD::OR , (MVT::ValueType)VT, Legal);
+ setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal);
+
+ // We can custom expand all VECTOR_SHUFFLEs to VPERM.
+ setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
+
+ setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
+ setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
+ setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
+ setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
+ setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
+ setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
+}
+
addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
-setOperationAction(ISD::MUL, MVT::v4f32, Legal);
-
-setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
-setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
+setOperationAction(ISD::MUL, MVT::v4f32, Legal);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.24 -> 1.25 --- Log message: Add vperm support for all datatypes --- Diffs of the changes: (+13 -19) PPCInstrAltivec.td | 32 +--- 1 files changed, 13 insertions(+), 19 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.24 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.25 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.24 Thu Mar 30 23:38:32 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Fri Mar 31 14:00:35 2006 @@ -141,27 +141,18 @@ [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC), VRRC:$vB)))]>, Requires<[FPContractions]>; -def VMHADDSHS : VAForm_1a<32, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), - "vmhaddshs $vD, $vA, $vB, $vC", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vmhaddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; -def VMHRADDSHS : VAForm_1a<33, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), - "vmhraddshs $vD, $vA, $vB, $vC", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vmhraddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; -def VPERM : VAForm_1a<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), -"vperm $vD, $vA, $vB, $vC", VecPerm, -[(set VRRC:$vD, - (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>; +def VMHADDSHS : VA1a_Int<32, "vmhaddshs $vD, $vA, $vB, $vC", + int_ppc_altivec_vmhaddshs>; +def VMHRADDSHS : VA1a_Int<33, "vmhraddshs $vD, $vA, $vB, $vC", + int_ppc_altivec_vmhraddshs>; +def VPERM : VA1a_Int<43, "vperm $vD, $vA, $vB, $vC", int_ppc_altivec_vperm>; +def VPERM : VA1a_Int<42, "vsel $vD, $vA, $vB, $vC", int_ppc_altivec_vsel>; + def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH), "vsldoi $vD, $vA, $vB, $SH", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB, imm:$SH))]>; -def VSEL : VAForm_1a<42, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), - "vsel $vD, $vA, $vB, $vC", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vsel VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; // VX-Form instructions. AltiVec arithmetic ops. def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), @@ -537,11 +528,14 @@ (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; -def : Pat<(int_ppc_altivec_vperm VRRC:$A, VRRC:$B, VRRC:$C), - (VPERM VRRC:$A, VRRC:$B, VRRC:$C)>; def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM), (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>; def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC), (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; - +def : Pat<(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC), + (v4f32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; +def : Pat<(PPCvperm (v8i16 VRRC:$vA), VRRC:$vB, VRRC:$vC), + (v8i16 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; +def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC), + (v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.7 -> 1.8
---
Log message:
Added haddp{s|d} and hsubp{s|d} intrinsics.
---
Diffs of the changes: (+19 -0)
IntrinsicsX86.td | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.7
llvm/include/llvm/IntrinsicsX86.td:1.8
--- llvm/include/llvm/IntrinsicsX86.td:1.7 Thu Mar 30 00:21:22 2006
+++ llvm/include/llvm/IntrinsicsX86.td Fri Mar 31 15:28:46 2006
@@ -199,3 +199,22 @@
def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [InstrNoMem]>;
}
+
+//===--===//
+// SSE3
+
+// Horizontal ops.
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse3_hadd_ps : GCCBuiltin<"__builtin_ia32_haddps">,
+ Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+ llvm_v4f32_ty], [InstrNoMem]>;
+ def int_x86_sse3_hadd_pd : GCCBuiltin<"__builtin_ia32_haddpd">,
+ Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+ llvm_v2f64_ty], [InstrNoMem]>;
+ def int_x86_sse3_hsub_ps : GCCBuiltin<"__builtin_ia32_hsubps">,
+ Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+ llvm_v4f32_ty], [InstrNoMem]>;
+ def int_x86_sse3_hsub_pd : GCCBuiltin<"__builtin_ia32_hsubpd">,
+ Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+ llvm_v2f64_ty], [InstrNoMem]>;
+}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.25 -> 1.26 --- Log message: fix a pasto --- Diffs of the changes: (+1 -1) PPCInstrAltivec.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.25 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.26 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.25 Fri Mar 31 14:00:35 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Fri Mar 31 15:19:06 2006 @@ -146,7 +146,7 @@ def VMHRADDSHS : VA1a_Int<33, "vmhraddshs $vD, $vA, $vB, $vC", int_ppc_altivec_vmhraddshs>; def VPERM : VA1a_Int<43, "vperm $vD, $vA, $vB, $vC", int_ppc_altivec_vperm>; -def VPERM : VA1a_Int<42, "vsel $vD, $vA, $vB, $vC", int_ppc_altivec_vsel>; +def VSEL: VA1a_Int<42, "vsel $vD, $vA, $vB, $vC", int_ppc_altivec_vsel>; def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH), "vsldoi $vD, $vA, $vB, $SH", VecFP, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.51 -> 1.52
---
Log message:
Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}.
---
Diffs of the changes: (+43 -0)
X86InstrSSE.td | 43 +++
1 files changed, 43 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.51
llvm/lib/Target/X86/X86InstrSSE.td:1.52
--- llvm/lib/Target/X86/X86InstrSSE.td:1.51 Fri Mar 31 13:22:53 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Mar 31 15:29:33 2006
@@ -145,6 +145,8 @@
// PDI - SSE2 instructions with TB and OpSize prefixes.
// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
+// S3SI - SSE3 instructions with XD prefix.
+// S3DI - SSE3 instructions with TB and OpSize prefixes.
class SSI o, Format F, dag ops, string asm, list pattern>
: I, XS, Requires<[HasSSE1]>;
class SDI o, Format F, dag ops, string asm, list pattern>
@@ -161,6 +163,27 @@
: X86Inst, TB, OpSize, Requires<[HasSSE2]> {
let Pattern = pattern;
}
+class S3SI o, Format F, dag ops, string asm, list pattern>
+ : I, XD, Requires<[HasSSE3]>;
+class S3DI o, Format F, dag ops, string asm, list pattern>
+ : I, TB, OpSize, Requires<[HasSSE3]>;
+
+//===--===//
+// Helpers for defining instructions that directly correspond to intrinsics.
+class S3S_Intrr o, string asm, Intrinsic IntId>
+ : S3SI;
+class S3S_Intrm o, string asm, Intrinsic IntId>
+ : S3SI;
+class S3D_Intrr o, string asm, Intrinsic IntId>
+ : S3DI;
+class S3D_Intrm o, string asm, Intrinsic IntId>
+ : S3DI;
// Some 'special' instructions
def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
@@ -1073,6 +1096,26 @@
UNPCKL_shuffle_mask)))]>;
}
+// Horizontal ops
+let isTwoAddress = 1 in {
+def HADDPSrr : S3S_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
+ int_x86_sse3_hadd_ps>;
+def HADDPSrm : S3S_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
+ int_x86_sse3_hadd_ps>;
+def HADDPDrr : S3D_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
+ int_x86_sse3_hadd_pd>;
+def HADDPDrm : S3D_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
+ int_x86_sse3_hadd_pd>;
+def HSUBPSrr : S3S_Intrr<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
+ int_x86_sse3_hsub_ps>;
+def HSUBPSrm : S3S_Intrm<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
+ int_x86_sse3_hsub_ps>;
+def HSUBPDrr : S3D_Intrr<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
+ int_x86_sse3_hsub_pd>;
+def HSUBPDrm : S3D_Intrm<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
+ int_x86_sse3_hsub_pd>;
+}
+
//===--===//
// SSE integer instructions
//===--===//
___
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[llvm-commits] CVS: llvm/utils/TableGen/FileLexer.l FileParser.y Record.cpp Record.h
Changes in directory llvm/utils/TableGen:
FileLexer.l updated: 1.28 -> 1.29
FileParser.y updated: 1.41 -> 1.42
Record.cpp updated: 1.52 -> 1.53
Record.h updated: 1.56 -> 1.57
---
Log message:
Generalize the previous binary operator support and add a string concatenation
operation. This implements Regression/TableGen/strconcat.td.
---
Diffs of the changes: (+109 -38)
FileLexer.l |1
FileParser.y | 22 ---
Record.cpp | 84 ---
Record.h | 40 +++-
4 files changed, 109 insertions(+), 38 deletions(-)
Index: llvm/utils/TableGen/FileLexer.l
diff -u llvm/utils/TableGen/FileLexer.l:1.28
llvm/utils/TableGen/FileLexer.l:1.29
--- llvm/utils/TableGen/FileLexer.l:1.28Fri Mar 3 13:34:28 2006
+++ llvm/utils/TableGen/FileLexer.l Fri Mar 31 15:53:49 2006
@@ -202,6 +202,7 @@
!sra { return SRATOK; }
!srl { return SRLTOK; }
!shl { return SHLTOK; }
+!strconcat { return STRCONCATTOK; }
{Identifier} { Filelval.StrVal = new std::string(yytext, yytext+yyleng);
Index: llvm/utils/TableGen/FileParser.y
diff -u llvm/utils/TableGen/FileParser.y:1.41
llvm/utils/TableGen/FileParser.y:1.42
--- llvm/utils/TableGen/FileParser.y:1.41 Thu Mar 30 16:50:40 2006
+++ llvm/utils/TableGen/FileParser.yFri Mar 31 15:53:49 2006
@@ -200,7 +200,7 @@
};
%token INT BIT STRING BITS LIST CODE DAG CLASS DEF FIELD LET IN
-%token SHLTOK SRATOK SRLTOK
+%token SHLTOK SRATOK SRLTOK STRCONCATTOK
%token INTVAL
%token ID VARNAME STRVAL CODEFRAGMENT
@@ -352,23 +352,13 @@
}
delete $3;
} | SHLTOK '(' Value ',' Value ')' {
-$$ = $3->getBinaryOp(Init::SHL, $5);
-if ($$ == 0) {
- err() << "Cannot shift values '" << *$3 << "' and '" << *$5 << "'!\n";
- exit(1);
-}
+$$ = (new BinOpInit(BinOpInit::SHL, $3, $5))->Fold();
} | SRATOK '(' Value ',' Value ')' {
-$$ = $3->getBinaryOp(Init::SRA, $5);
-if ($$ == 0) {
- err() << "Cannot shift values '" << *$3 << "' and '" << *$5 << "'!\n";
- exit(1);
-}
+$$ = (new BinOpInit(BinOpInit::SRA, $3, $5))->Fold();
} | SRLTOK '(' Value ',' Value ')' {
-$$ = $3->getBinaryOp(Init::SRL, $5);
-if ($$ == 0) {
- err() << "Cannot shift values '" << *$3 << "' and '" << *$5 << "'!\n";
- exit(1);
-}
+$$ = (new BinOpInit(BinOpInit::SRL, $3, $5))->Fold();
+ } | STRCONCATTOK '(' Value ',' Value ')' {
+$$ = (new BinOpInit(BinOpInit::STRCONCAT, $3, $5))->Fold();
};
OptVarName : /* empty */ {
Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/TableGen/Record.cpp:1.52 llvm/utils/TableGen/Record.cpp:1.53
--- llvm/utils/TableGen/Record.cpp:1.52 Thu Mar 30 16:50:40 2006
+++ llvm/utils/TableGen/Record.cpp Fri Mar 31 15:53:49 2006
@@ -7,6 +7,7 @@
//
//===--===//
//
+// Implement the tablegen record classes.
//
//===--===//
@@ -125,6 +126,19 @@
return 0;
}
+Init *StringRecTy::convertValue(BinOpInit *BO) {
+ if (BO->getOpcode() == BinOpInit::STRCONCAT) {
+Init *L = BO->getLHS()->convertInitializerTo(this);
+Init *R = BO->getRHS()->convertInitializerTo(this);
+if (L == 0 || R == 0) return 0;
+if (L != BO->getLHS() || R != BO->getRHS())
+ return new BinOpInit(BinOpInit::STRCONCAT, L, R);
+return BO;
+ }
+ return 0;
+}
+
+
Init *StringRecTy::convertValue(TypedInit *TI) {
if (dynamic_cast(TI->getType()))
return TI; // Accept variable if already of the right type!
@@ -299,21 +313,6 @@
return this;
}
-Init *IntInit::getBinaryOp(BinaryOp Op, Init *RHS) {
- IntInit *RHSi = dynamic_cast(RHS);
- if (RHSi == 0) return 0;
-
- int NewValue;
- switch (Op) {
- default: assert(0 && "Unknown binop");
- case SHL: NewValue = Value << RHSi->getValue(); break;
- case SRA: NewValue = Value >> RHSi->getValue(); break;
- case SRL: NewValue = (unsigned)Value >> (unsigned)RHSi->getValue(); break;
- }
- return new IntInit(NewValue);
-}
-
-
Init *IntInit::convertInitializerBitRange(const std::vector &Bits) {
BitsInit *BI = new BitsInit(Bits.size());
@@ -368,6 +367,61 @@
OS << "]";
}
+Init *BinOpInit::Fold() {
+ switch (getOpcode()) {
+ default: assert(0 && "Unknown binop");
+ case STRCONCAT: {
+StringInit *LHSs = dynamic_cast(LHS);
+StringInit *RHSs = dynamic_cast(RHS);
+if (LHSs && RHSs)
+ return new StringInit(LHSs->getValue() + RHSs->getValue());
+break;
+ }
+ case SHL:
+ case SRA:
+ case SRL: {
+IntInit *LHSi = dynamic_cast(LHS);
+IntInit *RHSi = dynamic_cast(RHS);
+if (LHSi && RHSi) {
+ int LHSv = LHSi->getValue(), RHSv = RHSi->getValue();
+ int Result;
+ switch (getOpcode()) {
+ default: assert(0 && "Bad opcode!");
+ case SHL: Result = LHSv << RHSv; break;
+ case SRA: Result = L
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.150 -> 1.151
X86ISelLowering.h updated: 1.49 -> 1.50
X86InstrSSE.td updated: 1.52 -> 1.53
---
Log message:
Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.
---
Diffs of the changes: (+12 -6)
X86ISelLowering.cpp |3 ++-
X86ISelLowering.h |6 +-
X86InstrSSE.td |9 +
3 files changed, 12 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.150
llvm/lib/Target/X86/X86ISelLowering.cpp:1.151
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.150 Fri Mar 31 13:22:53 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 31 15:55:24 2006
@@ -2685,7 +2685,7 @@
N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
if (N2.getValueType() != MVT::i32)
N2 = DAG.getConstant(cast(N2)->getValue(), MVT::i32);
- return DAG.getNode(ISD::INSERT_VECTOR_ELT, VT, Op.getOperand(0), N1, N2);
+ return DAG.getNode(X86ISD::PINSRW, VT, Op.getOperand(0), N1, N2);
}
return SDOperand();
@@ -2726,6 +2726,7 @@
case X86ISD::S2VEC: return "X86ISD::S2VEC";
case X86ISD::ZEXT_S2VEC: return "X86ISD::ZEXT_S2VEC";
case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
+ case X86ISD::PINSRW: return "X86ISD::PINSRW";
}
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.49
llvm/lib/Target/X86/X86ISelLowering.h:1.50
--- llvm/lib/Target/X86/X86ISelLowering.h:1.49 Fri Mar 31 13:22:53 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Fri Mar 31 15:55:24 2006
@@ -155,8 +155,12 @@
ZEXT_S2VEC,
/// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
- /// i32, corresponds to X86::PINSRW.
+ /// i32, corresponds to X86::PEXTRW.
PEXTRW,
+
+ /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
+ /// corresponds to X86::PINSRW.
+ PINSRW,
};
// X86 specific condition code. These correspond to X86_*_COND in
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.52
llvm/lib/Target/X86/X86InstrSSE.td:1.53
--- llvm/lib/Target/X86/X86InstrSSE.td:1.52 Fri Mar 31 15:29:33 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Mar 31 15:55:24 2006
@@ -27,9 +27,10 @@
SDTypeProfile<1, 1, []>, []>;
def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
SDTypeProfile<1, 1, []>, []>;
-
def X86pextrw : SDNode<"X86ISD::PEXTRW",
SDTypeProfile<1, 2, []>, []>;
+def X86pinsrw : SDNode<"X86ISD::PINSRW",
+SDTypeProfile<1, 3, []>, []>;
//===--===//
// SSE pattern fragments
@@ -1468,13 +1469,13 @@
def PINSRWrr : PDIi8<0xC4, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
- [(set VR128:$dst, (v8i16 (vector_insert (v8i16
VR128:$src1),
- R32:$src2, (i32 imm:$src3]>;
+ [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
+ R32:$src2, (i32 imm:$src3]>;
def PINSRWrm : PDIi8<0xC4, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i16mem:$src2,
i32i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst,
- (v8i16 (vector_insert (v8i16 VR128:$src1),
+ (v8i16 (X86pinsrw (v8i16 VR128:$src1),
(i32 (anyext (loadi16 addr:$src2))),
(i32 imm:$src3]>;
}
___
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[llvm-commits] CVS: llvm/test/Regression/TableGen/strconcat.td
Changes in directory llvm/test/Regression/TableGen:
strconcat.td added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+7 -0)
strconcat.td |7 +++
1 files changed, 7 insertions(+)
Index: llvm/test/Regression/TableGen/strconcat.td
diff -c /dev/null llvm/test/Regression/TableGen/strconcat.td:1.1
*** /dev/null Fri Mar 31 15:53:11 2006
--- llvm/test/Regression/TableGen/strconcat.td Fri Mar 31 15:53:01 2006
***
*** 0
--- 1,7
+ // RUN: tblgen %s | grep fufoo
+
+ class Y {
+ string T = !strconcat(S, "foo");
+ }
+
+ def Z : Y<"fu">;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.26 -> 1.27 --- Log message: Fix 80 column violations :) --- Diffs of the changes: (+13 -14) PPCInstrAltivec.td | 27 +-- 1 files changed, 13 insertions(+), 14 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.26 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.27 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.26 Fri Mar 31 15:19:06 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Fri Mar 31 15:57:36 2006 @@ -64,8 +64,9 @@ // Helpers for defining instructions that directly correspond to intrinsics. // VA1a_Int - A VAForm_1a intrinsic definition. -class VA1a_Int xo, string asmstr, Intrinsic IntID> - : VAForm_1a xo, string opc, Intrinsic IntID> + : VAForm_1a; // VX1_Int - A VXForm_1 intrinsic definition. @@ -141,12 +142,10 @@ [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC), VRRC:$vB)))]>, Requires<[FPContractions]>; -def VMHADDSHS : VA1a_Int<32, "vmhaddshs $vD, $vA, $vB, $vC", - int_ppc_altivec_vmhaddshs>; -def VMHRADDSHS : VA1a_Int<33, "vmhraddshs $vD, $vA, $vB, $vC", - int_ppc_altivec_vmhraddshs>; -def VPERM : VA1a_Int<43, "vperm $vD, $vA, $vB, $vC", int_ppc_altivec_vperm>; -def VSEL: VA1a_Int<42, "vsel $vD, $vA, $vB, $vC", int_ppc_altivec_vsel>; +def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>; +def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>; +def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>; +def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>; def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH), "vsldoi $vD, $vA, $vB, $SH", VecFP, @@ -237,12 +236,12 @@ def VMRGLH : VX1_Int<332, "vmrglh $vD, $vA, $vB", int_ppc_altivec_vmrglh>; def VMRGLW : VX1_Int<396, "vmrglw $vD, $vA, $vB", int_ppc_altivec_vmrglw>; -def VMSUMMBM : VA1a_Int<37, "vmsummbm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsummbm>; -def VMSUMSHM : VA1a_Int<40, "vmsumshm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumshm>; -def VMSUMSHS : VA1a_Int<41, "vmsumshs $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumshs>; -def VMSUMUBM : VA1a_Int<36, "vmsumubm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumubm>; -def VMSUMUHM : VA1a_Int<38, "vmsumuhm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumuhm>; -def VMSUMUHS : VA1a_Int<39, "vmsumuhs $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumuhs>; +def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>; +def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>; +def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>; +def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>; +def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>; +def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>; def VMULESB : VX1_Int<776, "vmulesb $vD, $vA, $vB", int_ppc_altivec_vmulesb>; def VMULESH : VX1_Int<840, "vmulesh $vD, $vA, $vB", int_ppc_altivec_vmulesh>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.135 -> 1.136
---
Log message:
Delete identity shuffles, implementing
CodeGen/Generic/vector-identity-shuffle.ll
---
Diffs of the changes: (+56 -2)
DAGCombiner.cpp | 58 ++--
1 files changed, 56 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.135
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.136
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.135 Fri Mar 31 12:10:41 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Mar 31 16:16:43 2006
@@ -214,6 +214,7 @@
SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
SDOperand visitVBUILD_VECTOR(SDNode *N);
SDOperand visitVECTOR_SHUFFLE(SDNode *N);
+SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
@@ -652,6 +653,7 @@
case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
+ case ISD::VVECTOR_SHUFFLE:return visitVVECTOR_SHUFFLE(N);
}
return SDOperand();
}
@@ -2464,13 +2466,36 @@
}
SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
+ SDOperand ShufMask = N->getOperand(2);
+ unsigned NumElts = ShufMask.getNumOperands();
+
+ // If the shuffle mask is an identity operation on the LHS, return the LHS.
+ bool isIdentity = true;
+ for (unsigned i = 0; i != NumElts; ++i) {
+if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+cast(ShufMask.getOperand(i))->getValue() != i) {
+ isIdentity = false;
+ break;
+}
+ }
+ if (isIdentity) return N->getOperand(0);
+
+ // If the shuffle mask is an identity operation on the RHS, return the RHS.
+ isIdentity = true;
+ for (unsigned i = 0; i != NumElts; ++i) {
+if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+cast(ShufMask.getOperand(i))->getValue() != i+NumElts)
{
+ isIdentity = false;
+ break;
+}
+ }
+ if (isIdentity) return N->getOperand(1);
+
// If the LHS and the RHS are the same node, turn the RHS into an undef.
if (N->getOperand(0) == N->getOperand(1)) {
// Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
// first operand.
std::vector MappedOps;
-SDOperand ShufMask = N->getOperand(2);
-unsigned NumElts = ShufMask.getNumOperands();
for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
if (cast(ShufMask.getOperand(i))->getValue() >= NumElts)
{
unsigned NewIdx =
@@ -2491,6 +2516,35 @@
return SDOperand();
}
+SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
+ SDOperand ShufMask = N->getOperand(2);
+ unsigned NumElts = ShufMask.getNumOperands()-2;
+
+ // If the shuffle mask is an identity operation on the LHS, return the LHS.
+ bool isIdentity = true;
+ for (unsigned i = 0; i != NumElts; ++i) {
+if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+cast(ShufMask.getOperand(i))->getValue() != i) {
+ isIdentity = false;
+ break;
+}
+ }
+ if (isIdentity) return N->getOperand(0);
+
+ // If the shuffle mask is an identity operation on the RHS, return the RHS.
+ isIdentity = true;
+ for (unsigned i = 0; i != NumElts; ++i) {
+if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+cast(ShufMask.getOperand(i))->getValue() != i+NumElts)
{
+ isIdentity = false;
+ break;
+}
+ }
+ if (isIdentity) return N->getOperand(1);
+
+ return SDOperand();
+}
+
SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand
N2){
assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC
node!");
___
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector-identity-shuffle.ll
Changes in directory llvm/test/Regression/CodeGen/Generic:
vector-identity-shuffle.ll added (r1.1)
---
Log message:
An identity shuffle shouldn't generate any permute code.
---
Diffs of the changes: (+16 -0)
vector-identity-shuffle.ll | 16
1 files changed, 16 insertions(+)
Index: llvm/test/Regression/CodeGen/Generic/vector-identity-shuffle.ll
diff -c /dev/null
llvm/test/Regression/CodeGen/Generic/vector-identity-shuffle.ll:1.1
*** /dev/null Fri Mar 31 16:16:29 2006
--- llvm/test/Regression/CodeGen/Generic/vector-identity-shuffle.ll Fri Mar
31 16:16:19 2006
***
*** 0
--- 1,16
+ ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep _test &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vperm
+
+ void %test(<4 x float> *%tmp2.i) {
+ %tmp2.i = load <4x float>* %tmp2.i
+%xFloat0.48 = extractelement <4 x float> %tmp2.i, uint 0
; [#uses=1]
+ %inFloat0.49 = insertelement <4 x float> undef, float %xFloat0.48,
uint 0 ; <<4 x float>> [#uses=1]
+ %xFloat1.50 = extractelement <4 x float> %tmp2.i, uint 1
; [#uses=1]
+ %inFloat1.52 = insertelement <4 x float> %inFloat0.49, float
%xFloat1.50, uint 1; <<4 x float>> [#uses=1]
+ %xFloat2.53 = extractelement <4 x float> %tmp2.i, uint 2
; [#uses=1]
+ %inFloat2.55 = insertelement <4 x float> %inFloat1.52, float
%xFloat2.53, uint 2; <<4 x float>> [#uses=1]
+ %xFloat3.56 = extractelement <4 x float> %tmp2.i, uint 3
; [#uses=1]
+ %inFloat3.58 = insertelement <4 x float> %inFloat2.55, float
%xFloat3.56, uint 3; <<4 x float>> [#uses=4]
+ store <4 x float> %inFloat3.58, <4x float>* %tmp2.i
+ ret void
+ }
___
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[llvm-commits] CVS: llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp
Changes in directory llvm-poolalloc/lib/PoolAllocate:
TransformFunctionBody.cpp updated: 1.50 -> 1.51
---
Log message:
fall back on the complete call graph to get indirect targets if needed
---
Diffs of the changes: (+9 -0)
TransformFunctionBody.cpp |9 +
1 files changed, 9 insertions(+)
Index: llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp
diff -u llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.50
llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.51
--- llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.50 Wed Jan
25 16:07:36 2006
+++ llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp Fri Mar 31
16:27:40 2006
@@ -509,6 +509,15 @@
ECGraphs.getSomeCalleeForCallSite(cast(OrigInst)) :
ECGraphs.getSomeCalleeForCallSite(cast(OrigInst));
+if (!CF)
+ for (EquivClassGraphs::callee_iterator I =
ECGraphs.callee_begin(OrigInst),
+E = ECGraphs.callee_end(OrigInst); I != E; ++I)
+ if (I->second) {
+ CF = I->second;
+ break;
+ }
+
+
if (!CF) {
// FIXME: Unknown callees for a call-site. Warn and ignore.
std::cerr << "\n***\n*** WARNING (FuncTransform::visitCallSite): "
___
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[llvm-commits] CVS: llvm/lib/Target/TargetData.cpp
Changes in directory llvm/lib/Target:
TargetData.cpp updated: 1.58 -> 1.59
---
Log message:
TargetData.cpp::getTypeInfo() was returning alignment of element type as the
alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignment. The correct fix would
be to return a target dependent alignment value provided via TargetLowering
(or some other interface).
---
Diffs of the changes: (+3 -0)
TargetData.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/TargetData.cpp
diff -u llvm/lib/Target/TargetData.cpp:1.58 llvm/lib/Target/TargetData.cpp:1.59
--- llvm/lib/Target/TargetData.cpp:1.58 Fri Jan 13 18:07:34 2006
+++ llvm/lib/Target/TargetData.cpp Fri Mar 31 16:33:42 2006
@@ -215,6 +215,9 @@
getTypeInfo(PTy->getElementType(), TD, Size, Alignment);
unsigned AlignedSize = (Size + Alignment - 1)/Alignment*Alignment;
Size = AlignedSize*PTy->getNumElements();
+// FIXME: The alignments of specific packed types are target dependent.
+// For now, just set it to be equal to Size.
+Alignment = Size;
return;
}
case Type::StructTyID: {
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.27 -> 1.28 --- Log message: Pull operand asm string into base class, shrinkifying intrinsic definitions. No functionality change. --- Diffs of the changes: (+58 -77) PPCInstrAltivec.td | 135 ++--- 1 files changed, 58 insertions(+), 77 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.27 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.28 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.27 Fri Mar 31 15:57:36 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Fri Mar 31 16:34:05 2006 @@ -70,13 +70,15 @@ [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; // VX1_Int - A VXForm_1 intrinsic definition. -class VX1_Int xo, string asmstr, Intrinsic IntID> - : VXForm_1 xo, string opc, Intrinsic IntID> + : VXForm_1; // VX2_Int - A VXForm_2 intrinsic definition. -class VX2_Int xo, string asmstr, Intrinsic IntID> - : VXForm_2 xo, string opc, Intrinsic IntID> + : VXForm_2; //===--===// @@ -231,10 +233,10 @@ "vminfp $vD, $vA, $vB", VecFP, []>; -def VMRGHH : VX1_Int<76 , "vmrghh $vD, $vA, $vB", int_ppc_altivec_vmrghh>; -def VMRGHW : VX1_Int<140, "vmrghw $vD, $vA, $vB", int_ppc_altivec_vmrghw>; -def VMRGLH : VX1_Int<332, "vmrglh $vD, $vA, $vB", int_ppc_altivec_vmrglh>; -def VMRGLW : VX1_Int<396, "vmrglw $vD, $vA, $vB", int_ppc_altivec_vmrglw>; +def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>; +def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>; +def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>; +def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>; def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>; def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>; @@ -243,23 +245,23 @@ def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>; def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>; -def VMULESB : VX1_Int<776, "vmulesb $vD, $vA, $vB", int_ppc_altivec_vmulesb>; -def VMULESH : VX1_Int<840, "vmulesh $vD, $vA, $vB", int_ppc_altivec_vmulesh>; -def VMULEUB : VX1_Int<520, "vmuleub $vD, $vA, $vB", int_ppc_altivec_vmuleub>; -def VMULEUH : VX1_Int<584, "vmuleuh $vD, $vA, $vB", int_ppc_altivec_vmuleuh>; -def VMULOSB : VX1_Int<264, "vmulosb $vD, $vA, $vB", int_ppc_altivec_vmulosb>; -def VMULOSH : VX1_Int<328, "vmulosh $vD, $vA, $vB", int_ppc_altivec_vmulosh>; -def VMULOUB : VX1_Int< 8, "vmuloub $vD, $vA, $vB", int_ppc_altivec_vmuloub>; -def VMULOUH : VX1_Int< 72, "vmulouh $vD, $vA, $vB", int_ppc_altivec_vmulouh>; +def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>; +def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>; +def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>; +def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>; +def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>; +def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>; +def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>; +def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>; -def VREFP : VX2_Int<266, "vrefp $vD, $vB", int_ppc_altivec_vrefp>; -def VRFIM : VX2_Int<714, "vrfim $vD, $vB", int_ppc_altivec_vrfim>; -def VRFIN : VX2_Int<522, "vrfin $vD, $vB", int_ppc_altivec_vrfin>; -def VRFIP : VX2_Int<650, "vrfip $vD, $vB", int_ppc_altivec_vrfip>; -def VRFIZ : VX2_Int<586, "vrfiz $vD, $vB", int_ppc_altivec_vrfiz>; -def VRSQRTEFP : VX2_Int<330, "vrsqrtefp $vD, $vB", int_ppc_altivec_vrsqrtefp>; +def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>; +def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>; +def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>; +def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>; +def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>; +def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; -def VSUBCUW : VX1_Int<74, "vsubcuw $vD, $vA, $vB", int_ppc_altivec_vsubcuw>; +def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>; def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vsubfp $vD, $vA, $vB", VecGeneral, @@ -274,17 +276,17 @@ "vsubuwm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>; -def VSUBSBS : VX1_Int<1792, "vsubsbs $vD, $vA, $vB", int_ppc_altivec_vsubsbs>; -def VSUBSHS : VX1_Int<1856, "vsubshs $vD, $vA, $vB", int_ppc_altivec_vsubshs>; -def VSUBSWS : VX1_Int<1920, "vsubsws $vD, $vA, $vB", int_ppc_altivec_vsubsws>; -def VSUBUBS : VX1_Int<1536, "vsububs $vD, $vA, $vB", int_ppc_altivec_vsububs>; -def VSUBUHS : VX1_Int<1
[llvm-commits] CVS: llvm/lib/Target/README.txt
Changes in directory llvm/lib/Target: README.txt updated: 1.25 -> 1.26 --- Log message: An entry about packed type alignments. --- Diffs of the changes: (+4 -0) README.txt |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.25 llvm/lib/Target/README.txt:1.26 --- llvm/lib/Target/README.txt:1.25 Fri Mar 24 13:59:17 2006 +++ llvm/lib/Target/README.txt Fri Mar 31 16:35:14 2006 @@ -149,4 +149,8 @@ where c1/c2 are constants. +//===-===// +For packed types, TargetData.cpp::getTypeInfo() returns alignment that is equal +to the type size. It works but can be overly conservative as the alignment of +specific packed types are target dependent. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.28 -> 1.29 --- Log message: Shrinkify some more intrinsic definitions. --- Diffs of the changes: (+17 -52) PPCInstrAltivec.td | 69 + 1 files changed, 17 insertions(+), 52 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.28 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.29 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.28 Fri Mar 31 16:34:05 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Fri Mar 31 16:41:56 2006 @@ -156,10 +156,6 @@ imm:$SH))]>; // VX-Form instructions. AltiVec arithmetic ops. -def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vaddcuw $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>; def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vaddfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; @@ -174,31 +170,15 @@ "vadduwm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; -def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vaddsbs $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>; -def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vaddshs $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>; -def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vaddsws $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>; +def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>; +def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>; +def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>; +def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>; +def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>; +def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>; +def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>; + -def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vaddubs $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>; -def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vadduhs $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>; -def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vadduws $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>; def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vand $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; @@ -220,12 +200,9 @@ def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vctuxs $vD, $vB, $UIMM", VecFP, []>; -def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB), -"vexptefp $vD, $vB", VecFP, -[(set VRRC:$vD, (int_ppc_altivec_vexptefp VRRC:$vB))]>; -def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB), -"vlogefp $vD, $vB", VecFP, -[(set VRRC:$vD, (int_ppc_altivec_vlogefp VRRC:$vB))]>; +def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>; +def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>; + def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vmaxfp $vD, $vA, $vB", VecFP, []>; @@ -353,24 +330,12 @@ def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>; // Vector Unpack. -def VUPKHPX : VXForm_2<846, (ops VRRC:$vD, VRRC:$vB), - "vupkhpx $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_altivec_vupkhpx VRRC:$vB))]>; -def VUPKHSB : VXForm_2<526, (ops VRRC:$vD, VRRC:$vB), - "vupkhsb $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_altivec_vupkhsb VRRC:$vB))]>; -def VUPKHSH : VXForm_2<590, (ops VRRC:$vD, VRRC:$vB), - "vupkhsh $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_alti
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.455 -> 1.456
---
Log message:
If we can look through vector operations to find the scalar version of an
extract_element'd value, do so.
---
Diffs of the changes: (+40 -0)
InstructionCombining.cpp | 40
1 files changed, 40 insertions(+)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.455
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.456
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.455 Fri Mar 31
12:25:14 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri Mar 31 17:01:56 2006
@@ -6654,7 +6654,41 @@
return false;
}
+/// FindScalarElement - Given a vector and an element number, see if the scalar
+/// value is already around as a register, for example if it were inserted then
+/// extracted from the vector.
+static Value *FindScalarElement(Value *V, unsigned EltNo) {
+ assert(isa(V->getType()) && "Not looking at a vector?");
+ const PackedType *PTy = cast(V->getType());
+ if (EltNo >= PTy->getNumElements()) // Out of range access.
+return UndefValue::get(PTy->getElementType());
+
+ if (isa(V))
+return UndefValue::get(PTy->getElementType());
+ else if (isa(V))
+return Constant::getNullValue(PTy->getElementType());
+ else if (ConstantPacked *CP = dyn_cast(V))
+return CP->getOperand(EltNo);
+ else if (InsertElementInst *III = dyn_cast(V)) {
+// If this is an insert to a variable element, we don't know what it is.
+if (!isa(III->getOperand(2))) return 0;
+unsigned IIElt = cast(III->getOperand(2))->getValue();
+
+// If this is an insert to the element we are looking for, return the
+// inserted value.
+if (EltNo == IIElt) return III->getOperand(1);
+
+// Otherwise, the insertelement doesn't modify the value, recurse on its
+// vector input.
+return FindScalarElement(III->getOperand(0), EltNo);
+ }
+
+ // Otherwise, we don't know.
+ return 0;
+}
+
Instruction *InstCombiner::visitExtractElementInst(ExtractElementInst &EI) {
+
// If packed val is undef, replace extract with scalar undef.
if (isa(EI.getOperand(0)))
return ReplaceInstUsesWith(EI, UndefValue::get(EI.getType()));
@@ -6676,6 +6710,12 @@
return ReplaceInstUsesWith(EI, op0);
}
+ // If extracting a specified index from the vector, see if we can recursively
+ // find a previously computed scalar that was inserted into the vector.
+ if (ConstantUInt *IdxC = dyn_cast(EI.getOperand(1)))
+if (Value *Elt = FindScalarElement(EI.getOperand(0), IdxC->getValue()))
+ return ReplaceInstUsesWith(EI, Elt);
+
if (Instruction *I = dyn_cast(EI.getOperand(0)))
if (I->hasOneUse()) {
// Push extractelement into predecessor operation if legal and
___
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[llvm-commits] CVS: llvm/lib/Target/README.txt
Changes in directory llvm/lib/Target:
README.txt updated: 1.26 -> 1.27
---
Log message:
ADd a note
---
Diffs of the changes: (+12 -0)
README.txt | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.26 llvm/lib/Target/README.txt:1.27
--- llvm/lib/Target/README.txt:1.26 Fri Mar 31 16:35:14 2006
+++ llvm/lib/Target/README.txt Fri Mar 31 22:08:29 2006
@@ -154,3 +154,15 @@
For packed types, TargetData.cpp::getTypeInfo() returns alignment that is equal
to the type size. It works but can be overly conservative as the alignment of
specific packed types are target dependent.
+
+//===-===//
+
+We should add 'unaligned load/store' nodes, and produce them from code like
+this:
+
+v4sf example(float *P) {
+ return (v4sf){P[0], P[1], P[2], P[3] };
+}
+
+//===-===//
+
___
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[llvm-commits] CVS: llvm/test/Regression/Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll
Changes in directory llvm/test/Regression/Transforms/IndVarsSimplify:
2006-03-31-NegativeStride.ll added (r1.1)
---
Log message:
new testcase for PR726: http://llvm.cs.uiuc.edu/PR726
---
Diffs of the changes: (+21 -0)
2006-03-31-NegativeStride.ll | 21 +
1 files changed, 21 insertions(+)
Index:
llvm/test/Regression/Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll
diff -c /dev/null
llvm/test/Regression/Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll:1.1
*** /dev/null Fri Mar 31 22:47:27 2006
---
llvm/test/Regression/Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll
Fri Mar 31 22:47:17 2006
***
*** 0
--- 1,21
+ ; RUN: llvm-as < %s | opt -indvars | llvm-dis | grep 'ret int 27'
+
+ ; Make sure to compute the right exit value based on negative strides.
+ ; PR726
+
+ int %test() {
+ entry:
+ br label %cond_true
+
+ cond_true: ; preds = %cond_true, %entry
+ %a.0.0 = phi int [ 10, %entry ], [ %tmp4, %cond_true ] ;
[#uses=2]
+ %b.0.0 = phi int [ 0, %entry ], [ %tmp2, %cond_true ] ;
[#uses=1]
+ %tmp2 = add int %b.0.0, %a.0.0 ; [#uses=2]
+ %tmp4 = add int %a.0.0, -1 ; [#uses=2]
+ %tmp = setgt int %tmp4, 7 ; [#uses=1]
+ br bool %tmp, label %cond_true, label %bb7
+
+ bb7:; preds = %cond_true
+ ret int %tmp2
+ }
+
___
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[llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolution.cpp
Changes in directory llvm/lib/Analysis:
ScalarEvolution.cpp updated: 1.45 -> 1.46
---
Log message:
Fix Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll and
PR726: http://llvm.cs.uiuc.edu/PR726 by performing consistent signed division,
not consistent unsigned
division when evaluating scev's. Do not touch udivs.
---
Diffs of the changes: (+27 -27)
ScalarEvolution.cpp | 54 ++--
1 files changed, 27 insertions(+), 27 deletions(-)
Index: llvm/lib/Analysis/ScalarEvolution.cpp
diff -u llvm/lib/Analysis/ScalarEvolution.cpp:1.45
llvm/lib/Analysis/ScalarEvolution.cpp:1.46
--- llvm/lib/Analysis/ScalarEvolution.cpp:1.45 Sun Jan 22 17:19:18 2006
+++ llvm/lib/Analysis/ScalarEvolution.cpp Fri Mar 31 22:48:52 2006
@@ -294,22 +294,22 @@
}
-// SCEVUDivs - Only allow the creation of one SCEVUDivExpr for any particular
+// SCEVSDivs - Only allow the creation of one SCEVSDivExpr for any particular
// input. Don't use a SCEVHandle here, or else the object will never be
// deleted!
-static std::map, SCEVUDivExpr*> SCEVUDivs;
+static std::map, SCEVSDivExpr*> SCEVSDivs;
-SCEVUDivExpr::~SCEVUDivExpr() {
- SCEVUDivs.erase(std::make_pair(LHS, RHS));
+SCEVSDivExpr::~SCEVSDivExpr() {
+ SCEVSDivs.erase(std::make_pair(LHS, RHS));
}
-void SCEVUDivExpr::print(std::ostream &OS) const {
- OS << "(" << *LHS << " /u " << *RHS << ")";
+void SCEVSDivExpr::print(std::ostream &OS) const {
+ OS << "(" << *LHS << " /s " << *RHS << ")";
}
-const Type *SCEVUDivExpr::getType() const {
+const Type *SCEVSDivExpr::getType() const {
const Type *Ty = LHS->getType();
- if (Ty->isSigned()) Ty = Ty->getUnsignedVersion();
+ if (Ty->isUnsigned()) Ty = Ty->getSignedVersion();
return Ty;
}
@@ -540,7 +540,7 @@
for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
SCEVHandle BC = PartialFact(It, i);
Divisor *= i;
-SCEVHandle Val = SCEVUDivExpr::get(SCEVMulExpr::get(BC, getOperand(i)),
+SCEVHandle Val = SCEVSDivExpr::get(SCEVMulExpr::get(BC, getOperand(i)),
SCEVUnknown::getIntegerSCEV(Divisor,Ty));
Result = SCEVAddExpr::get(Result, Val);
}
@@ -982,20 +982,20 @@
return Result;
}
-SCEVHandle SCEVUDivExpr::get(const SCEVHandle &LHS, const SCEVHandle &RHS) {
+SCEVHandle SCEVSDivExpr::get(const SCEVHandle &LHS, const SCEVHandle &RHS) {
if (SCEVConstant *RHSC = dyn_cast(RHS)) {
if (RHSC->getValue()->equalsInt(1))
- return LHS;// X /u 1 --> x
+ return LHS;// X /s 1 --> x
if (RHSC->getValue()->isAllOnesValue())
- return SCEV::getNegativeSCEV(LHS); // X /u -1 --> -x
+ return SCEV::getNegativeSCEV(LHS); // X /s -1 --> -x
if (SCEVConstant *LHSC = dyn_cast(LHS)) {
Constant *LHSCV = LHSC->getValue();
Constant *RHSCV = RHSC->getValue();
- if (LHSCV->getType()->isSigned())
+ if (LHSCV->getType()->isUnsigned())
LHSCV = ConstantExpr::getCast(LHSCV,
- LHSCV->getType()->getUnsignedVersion());
- if (RHSCV->getType()->isSigned())
+ LHSCV->getType()->getSignedVersion());
+ if (RHSCV->getType()->isUnsigned())
RHSCV = ConstantExpr::getCast(RHSCV, LHSCV->getType());
return SCEVUnknown::get(ConstantExpr::getDiv(LHSCV, RHSCV));
}
@@ -1003,8 +1003,8 @@
// FIXME: implement folding of (X*4)/4 when we know X*4 doesn't overflow.
- SCEVUDivExpr *&Result = SCEVUDivs[std::make_pair(LHS, RHS)];
- if (Result == 0) Result = new SCEVUDivExpr(LHS, RHS);
+ SCEVSDivExpr *&Result = SCEVSDivs[std::make_pair(LHS, RHS)];
+ if (Result == 0) Result = new SCEVSDivExpr(LHS, RHS);
return Result;
}
@@ -1356,8 +1356,8 @@
return SCEVMulExpr::get(getSCEV(I->getOperand(0)),
getSCEV(I->getOperand(1)));
case Instruction::Div:
- if (V->getType()->isInteger() && V->getType()->isUnsigned())
-return SCEVUDivExpr::get(getSCEV(I->getOperand(0)),
+ if (V->getType()->isInteger() && V->getType()->isSigned())
+return SCEVSDivExpr::get(getSCEV(I->getOperand(0)),
getSCEV(I->getOperand(1)));
break;
@@ -1376,10 +1376,10 @@
case Instruction::Shr:
if (ConstantUInt *SA = dyn_cast(I->getOperand(1)))
-if (V->getType()->isUnsigned()) {
+if (V->getType()->isSigned()) {
Constant *X = ConstantInt::get(V->getType(), 1);
X = ConstantExpr::getShl(X, SA);
- return SCEVUDivExpr::get(getSCEV(I->getOperand(0)), getSCEV(X));
+ return SCEVSDivExpr::get(getSCEV(I->getOperand(0)), getSCEV(X));
}
break;
@@ -1982,14 +1982,14 @@
return Comm;
}
- if (SCEVUDivExpr *UDiv = dyn_cast(V)) {
-SCEVHandle LHS = getSCEVAtScope(UDiv->getLHS(), L);
+ if (SCEVSDivExpr *Div = dyn_cast(V)) {
+SCEVHandle
[llvm-commits] CVS: llvm/include/llvm/Analysis/ScalarEvolutionExpander.h ScalarEvolutionExpressions.h
Changes in directory llvm/include/llvm/Analysis:
ScalarEvolutionExpander.h updated: 1.4 -> 1.5
ScalarEvolutionExpressions.h updated: 1.6 -> 1.7
---
Log message:
Fix Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll and
PR726: http://llvm.cs.uiuc.edu/PR726 by performing consistent signed division,
not consistent unsigned
division when evaluating scev's. Do not touch udivs.
---
Diffs of the changes: (+12 -12)
ScalarEvolutionExpander.h|2 +-
ScalarEvolutionExpressions.h | 22 +++---
2 files changed, 12 insertions(+), 12 deletions(-)
Index: llvm/include/llvm/Analysis/ScalarEvolutionExpander.h
diff -u llvm/include/llvm/Analysis/ScalarEvolutionExpander.h:1.4
llvm/include/llvm/Analysis/ScalarEvolutionExpander.h:1.5
--- llvm/include/llvm/Analysis/ScalarEvolutionExpander.h:1.4Sat Feb 4
03:51:33 2006
+++ llvm/include/llvm/Analysis/ScalarEvolutionExpander.hFri Mar 31
22:48:52 2006
@@ -136,7 +136,7 @@
Value *visitMulExpr(SCEVMulExpr *S);
-Value *visitUDivExpr(SCEVUDivExpr *S) {
+Value *visitSDivExpr(SCEVSDivExpr *S) {
const Type *Ty = S->getType();
Value *LHS = expandInTy(S->getLHS(), Ty);
Value *RHS = expandInTy(S->getRHS(), Ty);
Index: llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
diff -u llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h:1.6
llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h:1.7
--- llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h:1.6 Thu Apr 21
15:16:32 2005
+++ llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h Fri Mar 31
22:48:52 2006
@@ -23,7 +23,7 @@
enum SCEVTypes {
// These should be ordered in terms of increasing complexity to make the
// folders simpler.
-scConstant, scTruncate, scZeroExtend, scAddExpr, scMulExpr, scUDivExpr,
+scConstant, scTruncate, scZeroExtend, scAddExpr, scMulExpr, scSDivExpr,
scAddRecExpr, scUnknown, scCouldNotCompute
};
@@ -293,16 +293,16 @@
//======//
- /// SCEVUDivExpr - This class represents a binary unsigned division
operation.
+ /// SCEVSDivExpr - This class represents a binary unsigned division
operation.
///
- class SCEVUDivExpr : public SCEV {
+ class SCEVSDivExpr : public SCEV {
SCEVHandle LHS, RHS;
-SCEVUDivExpr(const SCEVHandle &lhs, const SCEVHandle &rhs)
- : SCEV(scUDivExpr), LHS(lhs), RHS(rhs) {}
+SCEVSDivExpr(const SCEVHandle &lhs, const SCEVHandle &rhs)
+ : SCEV(scSDivExpr), LHS(lhs), RHS(rhs) {}
-virtual ~SCEVUDivExpr();
+virtual ~SCEVSDivExpr();
public:
-/// get method - This just gets and returns a new SCEVUDiv object.
+/// get method - This just gets and returns a new SCEVSDiv object.
///
static SCEVHandle get(const SCEVHandle &LHS, const SCEVHandle &RHS);
@@ -334,9 +334,9 @@
void print(std::ostream &OS) const;
/// Methods for support type inquiry through isa, cast, and dyn_cast:
-static inline bool classof(const SCEVUDivExpr *S) { return true; }
+static inline bool classof(const SCEVSDivExpr *S) { return true; }
static inline bool classof(const SCEV *S) {
- return S->getSCEVType() == scUDivExpr;
+ return S->getSCEVType() == scSDivExpr;
}
};
@@ -496,8 +496,8 @@
return ((SC*)this)->visitAddExpr((SCEVAddExpr*)S);
case scMulExpr:
return ((SC*)this)->visitMulExpr((SCEVMulExpr*)S);
- case scUDivExpr:
-return ((SC*)this)->visitUDivExpr((SCEVUDivExpr*)S);
+ case scSDivExpr:
+return ((SC*)this)->visitSDivExpr((SCEVSDivExpr*)S);
case scAddRecExpr:
return ((SC*)this)->visitAddRecExpr((SCEVAddRecExpr*)S);
case scUnknown:
___
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