[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.1 -> 1.2 --- Log message: implement a bunch of intrinsics --- Diffs of the changes: (+34 -3) PPCInstrAltivec.td | 37 ++--- 1 files changed, 34 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.1 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.2 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.1 Sat Mar 25 01:51:43 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Mar 25 02:01:02 2006 @@ -124,18 +124,49 @@ // VX-Form instructions. AltiVec arithmetic ops. +def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vaddcuw $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>; def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vaddfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; +def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vaddsbs $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>; +def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vaddshs $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>; +def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vaddsws $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>; +def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vaddubs $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>; +def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vadduhs $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>; def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vadduwm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; +def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vadduws $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>; + def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vcfsx $vD, $vB, $UIMM", VecFP, - []>; + [(set VRRC:$vD, + (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>; def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vcfux $vD, $vB, $UIMM", VecFP, - []>; + [(set VRRC:$vD, + (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>; def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vctsxs $vD, $vB, $UIMM", VecFP, []>; @@ -171,7 +202,7 @@ []>; def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB), "vrsqrtefp $vD, $vB", VecFP, - []>; + [(set VRRC:$vD,(int_ppc_altivec_vrsqrtefp VRRC:$vB))]>; def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vsubfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.131 -> 1.132
X86ISelLowering.h updated: 1.42 -> 1.43
X86InstrSSE.td updated: 1.30 -> 1.31
---
Log message:
Build arbitrary vector with more than 2 distinct scalar elements with a
series of unpack and interleave ops.
---
Diffs of the changes: (+104 -5)
X86ISelLowering.cpp | 29 +--
X86ISelLowering.h |4 ++
X86InstrSSE.td | 76 ++--
3 files changed, 104 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.131
llvm/lib/Target/X86/X86ISelLowering.cpp:1.132
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.131 Fri Mar 24 19:33:37 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Mar 25 03:37:23 2006
@@ -2376,7 +2376,9 @@
abort();
}
case ISD::BUILD_VECTOR: {
+std::set Values;
SDOperand Elt0 = Op.getOperand(0);
+Values.insert(Elt0);
bool Elt0IsZero = (isa(Elt0) &&
cast(Elt0)->getValue() == 0) ||
(isa(Elt0) &&
@@ -2384,15 +2386,16 @@
bool RestAreZero = true;
unsigned NumElems = Op.getNumOperands();
for (unsigned i = 1; i < NumElems; ++i) {
- SDOperand V = Op.getOperand(i);
- if (ConstantFPSDNode *FPC = dyn_cast(V)) {
+ SDOperand Elt = Op.getOperand(i);
+ if (ConstantFPSDNode *FPC = dyn_cast(Elt)) {
if (!FPC->isExactlyValue(+0.0))
RestAreZero = false;
- } else if (ConstantSDNode *C = dyn_cast(V)) {
+ } else if (ConstantSDNode *C = dyn_cast(Elt)) {
if (!C->isNullValue())
RestAreZero = false;
} else
RestAreZero = false;
+ Values.insert(Elt);
}
if (RestAreZero) {
@@ -2402,6 +2405,25 @@
return DAG.getNode(X86ISD::ZEXT_S2VEC, Op.getValueType(), Elt0);
}
+if (Values.size() > 2) {
+ // Expand into a number of unpckl*.
+ // e.g. for v4f32
+ // Step 1: unpcklps 0, 2 ==> X:
+ // : unpcklps 1, 3 ==> Y:
+ // Step 2: unpcklps X, Y ==><3, 2, 1, 0>
+ MVT::ValueType VT = Op.getValueType();
+ std::vector V(NumElems);
+ for (unsigned i = 0; i < NumElems; ++i)
+V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
+ NumElems >>= 1;
+ while (NumElems != 0) {
+for (unsigned i = 0; i < NumElems; ++i)
+ V[i] = DAG.getNode(X86ISD::UNPCKL, VT, V[i], V[i + NumElems]);
+NumElems >>= 1;
+ }
+ return V[0];
+}
+
return SDOperand();
}
}
@@ -2439,6 +2461,7 @@
case X86ISD::Wrapper:return "X86ISD::Wrapper";
case X86ISD::S2VEC: return "X86ISD::S2VEC";
case X86ISD::ZEXT_S2VEC: return "X86ISD::ZEXT_S2VEC";
+ case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
}
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.42
llvm/lib/Target/X86/X86ISelLowering.h:1.43
--- llvm/lib/Target/X86/X86ISelLowering.h:1.42 Fri Mar 24 17:15:12 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Sat Mar 25 03:37:23 2006
@@ -153,6 +153,10 @@
/// ZEXT_S2VEC - SCALAR_TO_VECTOR with zero extension. The destination
base
/// does not have to match the operand type.
ZEXT_S2VEC,
+
+ /// UNPCKL - Unpack and interleave low. This corresponds to
X86::UNPCKLPS,
+ /// X86::PUNPCKL*.
+ UNPCKL,
};
// X86 specific condition code. These correspond to X86_*_COND in
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.30
llvm/lib/Target/X86/X86InstrSSE.td:1.31
--- llvm/lib/Target/X86/X86InstrSSE.td:1.30 Sat Mar 25 00:03:26 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Mar 25 03:37:23 2006
@@ -28,6 +28,11 @@
def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
SDTypeProfile<1, 1, []>, []>;
+def SDTUnpckl : SDTypeProfile<1, 2,
+ [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
+def X86unpckl : SDNode<"X86ISD::UNPCKL", SDTUnpckl,
+[]>;
+
//===--===//
// SSE pattern fragments
//===--===//
@@ -787,10 +792,14 @@
"unpckhpd {$src2, $dst|$dst, $src2}", []>;
def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src2),
-"unpcklps {$src2, $dst|$dst, $src2}", []>;
+"unpcklps {$src2, $dst|$dst, $src2}",
+[(set VR128:$dst, (v4f32 (X86unpckl VR128:$src1,
+ VR128:$src2)))]>;
def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f128mem:$src2),
-"unpcklps {$src2, $dst|$dst, $src2}", []>;
+"unpckl
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.258 -> 1.259 --- Log message: Added missing (any_extend (load ...)) patterns. --- Diffs of the changes: (+3 -0) X86InstrInfo.td |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.258 llvm/lib/Target/X86/X86InstrInfo.td:1.259 --- llvm/lib/Target/X86/X86InstrInfo.td:1.258 Thu Mar 23 10:13:50 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Sat Mar 25 03:45:48 2006 @@ -2362,6 +2362,9 @@ def : Pat<(i16 (anyext R8 :$src)), (MOVZX16rr8 R8 :$src)>; def : Pat<(i32 (anyext R8 :$src)), (MOVZX32rr8 R8 :$src)>; def : Pat<(i32 (anyext R16:$src)), (MOVZX32rr16 R16:$src)>; +def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>; +def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>; +def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>; //===--===// // Some peepholes ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_set.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
vec_set.ll added (r1.1)
---
Log message:
Add a BUILD_VECTOR with unpack and interleave testcase.
---
Diffs of the changes: (+14 -0)
vec_set.ll | 14 ++
1 files changed, 14 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/vec_set.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/vec_set.ll:1.1
*** /dev/null Sat Mar 25 03:48:24 2006
--- llvm/test/Regression/CodeGen/X86/vec_set.ll Sat Mar 25 03:48:14 2006
***
*** 0
--- 1,14
+ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep punpckl | wc -l |
grep 7
+
+ void %test(<8 x short>* %b, short %a0, short %a1, short %a2, short %a3, short
%a4, short %a5, short %a6, short %a7) {
+ %tmp = insertelement <8 x short> zeroinitializer, short %a0, uint 0
+ %tmp2 = insertelement <8 x short> %tmp, short %a1, uint 1
+ %tmp4 = insertelement <8 x short> %tmp2, short %a2, uint 2
+ %tmp6 = insertelement <8 x short> %tmp4, short %a3, uint 3
+ %tmp8 = insertelement <8 x short> %tmp6, short %a4, uint 4
+ %tmp10 = insertelement <8 x short> %tmp8, short %a5, uint 5
+ %tmp12 = insertelement <8 x short> %tmp10, short %a6, uint 6
+ %tmp14 = insertelement <8 x short> %tmp12, short %a7, uint 7
+ store <8 x short> %tmp14, <8 x short>* %b
+ ret void
+ }
___
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[llvm-commits] CVS: llvm/lib/VMCore/AutoUpgrade.cpp
Changes in directory llvm/lib/VMCore:
AutoUpgrade.cpp updated: 1.16 -> 1.17
---
Log message:
Cast instruction not inserted into basic block.
---
Diffs of the changes: (+5 -41)
AutoUpgrade.cpp | 46 +-
1 files changed, 5 insertions(+), 41 deletions(-)
Index: llvm/lib/VMCore/AutoUpgrade.cpp
diff -u llvm/lib/VMCore/AutoUpgrade.cpp:1.16
llvm/lib/VMCore/AutoUpgrade.cpp:1.17
--- llvm/lib/VMCore/AutoUpgrade.cpp:1.16Thu Mar 23 14:13:25 2006
+++ llvm/lib/VMCore/AutoUpgrade.cpp Sat Mar 25 12:40:47 2006
@@ -201,51 +201,15 @@
// CastArg - Perform the appropriate cast of an upgraded argument.
//
-static Value *CastArg(Value *Arg, const Type *Ty) {
+static Value *CastArg(Value *Arg, const Type *Ty, Instruction *InsertBefore) {
if (Constant *C = dyn_cast(Arg)) {
return ConstantExpr::getCast(C, Ty);
} else {
-return new CastInst(Arg, Ty, "autoupgrade_cast");
+Value *Cast = new CastInst(Arg, Ty, "autoupgrade_cast", InsertBefore);
+return Cast;
}
}
-Instruction* llvm::MakeUpgradedCall(Function *F,
-const std::vector &Params,
-BasicBlock *BB, bool isTailCall,
-unsigned CallingConv) {
- assert(F && "Need a Function to make a CallInst");
- assert(BB && "Need a BasicBlock to make a CallInst");
-
- // Convert the params
- bool signedArg = false;
- std::vector Oprnds;
- for (std::vector::const_iterator PI = Params.begin(),
- PE = Params.end(); PI != PE; ++PI) {
-const Type* opTy = (*PI)->getType();
-if (opTy->isSigned()) {
- signedArg = true;
- Value *cast = CastArg(*PI, opTy->getUnsignedVersion());
- if (Instruction *I = dyn_cast(cast))
-BB->getInstList().push_back(I);
- Oprnds.push_back(cast);
-}
-else
- Oprnds.push_back(*PI);
- }
-
- Instruction *result = new CallInst(F, Oprnds);
- if (result->getType() != Type::VoidTy) result->setName("autoupgrade_call");
- if (isTailCall) cast(result)->setTailCall();
- if (CallingConv) cast(result)->setCallingConv(CallingConv);
- if (signedArg) {
-const Type* newTy = F->getReturnType()->getUnsignedVersion();
-CastInst* final = new CastInst(result, newTy, "autoupgrade_uncast");
-BB->getInstList().push_back(result);
-result = final;
- }
- return result;
-}
-
// UpgradeIntrinsicCall - In the BC reader, change a call to an intrinsic to be
// a call to an upgraded intrinsic. We may have to permute the order or
promote
// some arguments with a cast.
@@ -265,7 +229,7 @@
if (p) {
Value *V = CI->getOperand(p);
if (V->getType() != NewFnTy->getParamType(i))
- V = CastArg(V, NewFnTy->getParamType(i));
+ V = CastArg(V, NewFnTy->getParamType(i), CI);
Oprnds.push_back(V);
} else
Oprnds.push_back(UndefValue::get(NewFnTy->getParamType(i)));
@@ -276,7 +240,7 @@
for (unsigned i = 0; i != N; ++i) {
Value *V = CI->getOperand(i + 1);
if (V->getType() != NewFnTy->getParamType(i))
-V = CastArg(V, NewFnTy->getParamType(i));
+V = CastArg(V, NewFnTy->getParamType(i), CI);
Oprnds.push_back(V);
}
}
___
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[llvm-commits] CVS: llvm/include/llvm/Assembly/AutoUpgrade.h
Changes in directory llvm/include/llvm/Assembly: AutoUpgrade.h updated: 1.5 -> 1.6 --- Log message: Unused function - easier to throw away than fix. --- Diffs of the changes: (+0 -8) AutoUpgrade.h |8 1 files changed, 8 deletions(-) Index: llvm/include/llvm/Assembly/AutoUpgrade.h diff -u llvm/include/llvm/Assembly/AutoUpgrade.h:1.5 llvm/include/llvm/Assembly/AutoUpgrade.h:1.6 --- llvm/include/llvm/Assembly/AutoUpgrade.h:1.5Thu Mar 2 17:57:16 2006 +++ llvm/include/llvm/Assembly/AutoUpgrade.hSat Mar 25 12:42:45 2006 @@ -36,14 +36,6 @@ /// @brief Remove overloaded intrinsic function names. Function* UpgradeIntrinsicFunction(Function* F); - Instruction* MakeUpgradedCall( -Function* F, ///< The function to call -const std::vector& Params, ///< Operands of the call -BasicBlock* BB, ///< Basic block the caller will insert result to -bool isTailCall = false, ///< True if this is a tail call. -unsigned CallingConv = 0 ///< Calling convention to use - ); - /// In LLVM 1.7, the overloading of intrinsic functions was replaced with /// separate functions for each of the various argument sizes. This function /// implements the auto-upgrade feature from old overloaded names to the new ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/Instructions.cpp
Changes in directory llvm/lib/VMCore:
Instructions.cpp updated: 1.31 -> 1.32
---
Log message:
Teach BinaryOperator::createNot to work with packed integer types
---
Diffs of the changes: (+9 -2)
Instructions.cpp | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
Index: llvm/lib/VMCore/Instructions.cpp
diff -u llvm/lib/VMCore/Instructions.cpp:1.31
llvm/lib/VMCore/Instructions.cpp:1.32
--- llvm/lib/VMCore/Instructions.cpp:1.31 Tue Jan 17 14:07:22 2006
+++ llvm/lib/VMCore/Instructions.cppSat Mar 25 15:54:21 2006
@@ -923,8 +923,15 @@
BinaryOperator *BinaryOperator::createNot(Value *Op, const std::string &Name,
Instruction *InsertBefore) {
- return new BinaryOperator(Instruction::Xor, Op,
-ConstantIntegral::getAllOnesValue(Op->getType()),
+ Constant *C;
+ if (const PackedType *PTy = dyn_cast(Op->getType())) {
+C = ConstantIntegral::getAllOnesValue(PTy->getElementType());
+C = ConstantPacked::get(std::vector(PTy->getNumElements(), C));
+ } else {
+C = ConstantIntegral::getAllOnesValue(Op->getType());
+ }
+
+ return new BinaryOperator(Instruction::Xor, Op, C,
Op->getType(), Name, InsertBefore);
}
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.452 -> 1.453 --- Log message: Don't crash on packed logical ops --- Diffs of the changes: (+6 -3) InstructionCombining.cpp |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.452 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.453 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.452 Thu Mar 23 12:10:42 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Mar 25 15:58:26 2006 @@ -2380,7 +2380,8 @@ // See if we can simplify any instructions used by the instruction whose sole // purpose is to compute bits we don't care about. uint64_t KnownZero, KnownOne; - if (SimplifyDemandedBits(&I, I.getType()->getIntegralTypeMask(), + if (!isa(I.getType()) && + SimplifyDemandedBits(&I, I.getType()->getIntegralTypeMask(), KnownZero, KnownOne)) return &I; @@ -2624,7 +2625,8 @@ // See if we can simplify any instructions used by the instruction whose sole // purpose is to compute bits we don't care about. uint64_t KnownZero, KnownOne; - if (SimplifyDemandedBits(&I, I.getType()->getIntegralTypeMask(), + if (!isa(I.getType()) && + SimplifyDemandedBits(&I, I.getType()->getIntegralTypeMask(), KnownZero, KnownOne)) return &I; @@ -2861,7 +2863,8 @@ // See if we can simplify any instructions used by the instruction whose sole // purpose is to compute bits we don't care about. uint64_t KnownZero, KnownOne; - if (SimplifyDemandedBits(&I, I.getType()->getIntegralTypeMask(), + if (!isa(I.getType()) && + SimplifyDemandedBits(&I, I.getType()->getIntegralTypeMask(), KnownZero, KnownOne)) return &I; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.187 -> 1.188
---
Log message:
Add a missing check which cause an invalid .td file to crash tblgen
---
Diffs of the changes: (+3 -0)
DAGISelEmitter.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.187
llvm/utils/TableGen/DAGISelEmitter.cpp:1.188
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.187Sat Mar 25 00:47:53 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Sat Mar 25 16:12:44 2006
@@ -1342,6 +1342,9 @@
// Check that it exists in InstResults.
TreePatternNode *RNode = InstResults[OpName];
+ if (RNode == 0)
+I->error("Operand $" + OpName + " does not exist in operand list!");
+
if (i == 0)
Res0Node = RNode;
Record *R = dynamic_cast(RNode->getLeafValue())->getDef();
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.2 -> 1.3 --- Log message: Add some logical operations --- Diffs of the changes: (+19 -3) PPCInstrAltivec.td | 22 +++--- 1 files changed, 19 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.2 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.3 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.2 Sat Mar 25 02:01:02 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Mar 25 16:16:05 2006 @@ -158,7 +158,13 @@ "vadduws $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>; - +def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +"vand $vD, $vA, $vB", VecFP, +[(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; +def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vandc $vD, $vA, $vB", VecFP, + []>; + def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vcfsx $vD, $vB, $UIMM", VecFP, [(set VRRC:$vD, @@ -206,12 +212,15 @@ def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vsubfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; +def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +"vnor $vD, $vA, $vB", VecFP, +[]>; def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vor $vD, $vA, $vB", VecFP, - []>; + [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>; def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vxor $vD, $vA, $vB", VecFP, - []>; + [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>; def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vspltb $vD, $vB, $UIMM", VecPerm, @@ -297,6 +306,13 @@ def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>; def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>; +// Logical Operations +def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>; +def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>; +def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>; +def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>; +def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>; +def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>; def : Pat<(fmul VRRC:$vA, VRRC:$vB), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.128 -> 1.129
---
Log message:
Don't call SimplifyDemandedBits on vectors
---
Diffs of the changes: (+2 -1)
DAGCombiner.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.128
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.129
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.128 Sat Mar 18 19:27:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Mar 25 16:19:00 2006
@@ -1120,7 +1120,8 @@
}
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
// fold (and (sra)) -> (and (srl)) when possible.
- if (SimplifyDemandedBits(SDOperand(N, 0)))
+ if (!MVT::isVector(VT) &&
+ SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand();
// fold (zext_inreg (extload x)) -> (zextload x)
if (N0.getOpcode() == ISD::EXTLOAD) {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.281 -> 1.282
---
Log message:
Implement the ISD::isBuildVectorAllOnesInteger predicate
---
Diffs of the changes: (+32 -1)
SelectionDAG.cpp | 33 -
1 files changed, 32 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.281
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.282
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.281Thu Mar 23
20:20:47 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Mar 25 16:57:01 2006
@@ -66,9 +66,40 @@
}
//===--===//
-// ISD Class
+// ISD Namespace
//===--===//
+/// isBuildVectorAllOnesInteger - Return true if the specified node is a
+/// BUILD_VECTOR where all of the elements are ~0 or undef.
+bool ISD::isBuildVectorAllOnesInteger(const SDNode *N) {
+ if (N->getOpcode() != ISD::BUILD_VECTOR ||
+ !MVT::isInteger(N->getOperand(0).getValueType())) return false;
+
+ unsigned i = 0, e = N->getNumOperands();
+
+ // Skip over all of the undef values.
+ while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
+++i;
+
+ // Do not accept an all-undef vector.
+ if (i == e) return false;
+
+ // Do not accept build_vectors that aren't all constants or which have non-~0
+ // elements.
+ if (!isa(N) || !cast(N)->isAllOnesValue())
+return false;
+
+ // Okay, we have at least one ~0 value, check to see if the rest match or are
+ // undefs.
+ SDOperand NotZero = N->getOperand(i);
+ for (++i; i != e; ++i)
+if (N->getOperand(i) != NotZero &&
+N->getOperand(i).getOpcode() != ISD::UNDEF)
+ return false;
+ return true;
+}
+
+
/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
/// when given the operation for (X op Y).
ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.120 -> 1.121 --- Log message: Add a predicate --- Diffs of the changes: (+7 -0) SelectionDAGNodes.h |7 +++ 1 files changed, 7 insertions(+) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.120 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.121 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.120 Thu Mar 23 19:03:55 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Sat Mar 25 16:56:35 2006 @@ -453,6 +453,13 @@ BUILTIN_OP_END }; + /// Node predicates + + /// isBuildVectorAllOnesInteger - Return true if the specified node is a + /// BUILD_VECTOR where all of the elements are ~0 or undef. + bool isBuildVectorAllOnesInteger(const SDNode *N); + + //======// /// ISD::CondCode enum - These are ordered carefully to make the bitfields /// below work out, when considering SETFALSE (something that never exists ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.282 -> 1.283 --- Log message: Fix a bug in ISD::isBuildVectorAllOnesInteger that caused it to always return false --- Diffs of the changes: (+3 -2) SelectionDAG.cpp |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.282 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.283 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.282Sat Mar 25 16:57:01 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Mar 25 16:59:28 2006 @@ -86,12 +86,13 @@ // Do not accept build_vectors that aren't all constants or which have non-~0 // elements. - if (!isa(N) || !cast(N)->isAllOnesValue()) + SDOperand NotZero = N->getOperand(i); + if (!isa(NotZero) || + !cast(NotZero)->isAllOnesValue()) return false; // Okay, we have at least one ~0 value, check to see if the rest match or are // undefs. - SDOperand NotZero = N->getOperand(i); for (++i; i != e; ++i) if (N->getOperand(i) != NotZero && N->getOperand(i).getOpcode() != ISD::UNDEF) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.58 -> 1.59
---
Log message:
add a vnot helper node for matching 'not' on vectors
---
Diffs of the changes: (+6 -2)
TargetSelectionDAG.td |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.58
llvm/lib/Target/TargetSelectionDAG.td:1.59
--- llvm/lib/Target/TargetSelectionDAG.td:1.58 Fri Mar 24 20:29:35 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Sat Mar 25 17:00:08 2006
@@ -379,13 +379,17 @@
// Leaf fragments.
-def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT());
}]>;
-// Other helper fragments.
+def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
+def immAllOnesV: PatLeaf<(build_vector), [{
+ return ISD::isBuildVectorAllOnesInteger(N);
+}]>;
+// Other helper fragments.
def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
+def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
// extending load & truncstore fragments.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLinearScan.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocLinearScan.cpp updated: 1.119 -> 1.120
---
Log message:
Add some comments.
---
Diffs of the changes: (+4 -0)
RegAllocLinearScan.cpp |4
1 files changed, 4 insertions(+)
Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.119
llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.120
--- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.119 Thu Feb 23 00:44:17 2006
+++ llvm/lib/CodeGen/RegAllocLinearScan.cpp Sat Mar 25 17:00:56 2006
@@ -539,6 +539,7 @@
DEBUG(std::cerr << "\tassigning stack slot at interval "<< *cur << ":\n");
+ // Find a register to spill.
float minWeight = float(HUGE_VAL);
unsigned minReg = 0;
for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
@@ -549,6 +550,9 @@
minReg = reg;
}
}
+
+ // If we didn't find a register that is spillable, try aliases?
+
// FIXME: assert(minReg && "Didn't find any reg!");
DEBUG(std::cerr << "\t\tregister with min weight: "
<< mri_->getName(minReg) << " (" << minWeight << ")\n");
___
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
eqv-andc-orc-nor.ll updated: 1.2 -> 1.3
---
Log message:
new testcases
---
Diffs of the changes: (+27 -2)
eqv-andc-orc-nor.ll | 29 +++--
1 files changed, 27 insertions(+), 2 deletions(-)
Index: llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.ll:1.2
llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.ll:1.3
--- llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.ll:1.2Wed Sep
28 13:08:58 2005
+++ llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.llSat Mar 25
17:04:34 2006
@@ -1,7 +1,7 @@
; RUN: llvm-as < %s | llc -march=ppc32 | grep eqv | wc -l | grep 3 &&
-; RUN: llvm-as < %s | llc -march=ppc32 | grep andc | wc -l | grep 2 &&
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep andc | wc -l | grep 3 &&
; RUN: llvm-as < %s | llc -march=ppc32 | grep orc | wc -l | grep 2 &&
-; RUN: llvm-as < %s | llc -march=ppc32 | grep nor | wc -l | grep 2 &&
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep nor | wc -l | grep 3 &&
; RUN: llvm-as < %s | llc -march=ppc32 | grep nand | wc -l | grep 1
int %EQV1(int %X, int %Y) {
@@ -62,3 +62,28 @@
%W = xor int %Z, -1
ret int %W
}
+
+void %VNOR(<4 x float>* %P, <4 x float>* %Q) {
+%tmp = load <4 x float>* %P
+%tmp = cast <4 x float> %tmp to <4 x int>
+%tmp2 = load <4 x float>* %Q
+%tmp2 = cast <4 x float> %tmp2 to <4 x int>
+%tmp3 = or <4 x int> %tmp, %tmp2
+%tmp4 = xor <4 x int> %tmp3, < int -1, int -1, int -1, int -1 >
+%tmp4 = cast <4 x int> %tmp4 to <4 x float>
+store <4 x float> %tmp4, <4 x float>* %P
+ret void
+}
+
+void %VANDC(<4 x float>* %P, <4 x float>* %Q) {
+%tmp = load <4 x float>* %P
+%tmp = cast <4 x float> %tmp to <4 x int>
+%tmp2 = load <4 x float>* %Q
+%tmp2 = cast <4 x float> %tmp2 to <4 x int>
+%tmp3 = and <4 x int> %tmp, %tmp2
+%tmp4 = xor <4 x int> %tmp3, < int -1, int -1, int -1, int -1 >
+%tmp4 = cast <4 x int> %tmp4 to <4 x float>
+store <4 x float> %tmp4, <4 x float>* %P
+ret void
+}
+
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.3 -> 1.4 --- Log message: add patterns for VANDC/VNOR, implementing CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC --- Diffs of the changes: (+8 -3) PPCInstrAltivec.td | 11 --- 1 files changed, 8 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.3 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.4 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.3 Sat Mar 25 16:16:05 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Mar 25 17:05:29 2006 @@ -163,7 +163,7 @@ [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vandc $vD, $vA, $vB", VecFP, - []>; + [(set VRRC:$vD, (vnot (and (v4i32 VRRC:$vA), VRRC:$vB)))]>; def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vcfsx $vD, $vB, $UIMM", VecFP, @@ -214,7 +214,7 @@ [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vnor $vD, $vA, $vB", VecFP, -[]>; +[(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>; def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vor $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>; @@ -313,7 +313,12 @@ def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>; def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>; def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>; - +def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>; +def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>; +def : Pat<(v16i8 (vnot (and VRRC:$A, VRRC:$B))), + (v16i8 (VANDC VRRC:$A, VRRC:$B))>; +def : Pat<(v8i16 (vnot (and VRRC:$A, VRRC:$B))), + (v8i16 (VANDC VRRC:$A, VRRC:$B))>; def : Pat<(fmul VRRC:$vA, VRRC:$vB), (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.4 -> 1.5 --- Log message: fix the pattern for vandc, it's NOT vnand --- Diffs of the changes: (+3 -3) PPCInstrAltivec.td |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.4 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.5 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.4 Sat Mar 25 17:05:29 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Mar 25 17:10:40 2006 @@ -163,7 +163,7 @@ [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vandc $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, (vnot (and (v4i32 VRRC:$vA), VRRC:$vB)))]>; + [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>; def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vcfsx $vD, $vB, $UIMM", VecFP, @@ -315,9 +315,9 @@ def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>; def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>; def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>; -def : Pat<(v16i8 (vnot (and VRRC:$A, VRRC:$B))), +def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))), (v16i8 (VANDC VRRC:$A, VRRC:$B))>; -def : Pat<(v8i16 (vnot (and VRRC:$A, VRRC:$B))), +def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))), (v8i16 (VANDC VRRC:$A, VRRC:$B))>; def : Pat<(fmul VRRC:$vA, VRRC:$vB), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC: eqv-andc-orc-nor.ll updated: 1.3 -> 1.4 --- Log message: Correct the vandc testcase --- Diffs of the changes: (+3 -3) eqv-andc-orc-nor.ll |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.ll diff -u llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.ll:1.3 llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.ll:1.4 --- llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.ll:1.3Sat Mar 25 17:04:34 2006 +++ llvm/test/Regression/CodeGen/PowerPC/eqv-andc-orc-nor.llSat Mar 25 17:12:47 2006 @@ -80,9 +80,9 @@ %tmp = cast <4 x float> %tmp to <4 x int> %tmp2 = load <4 x float>* %Q %tmp2 = cast <4 x float> %tmp2 to <4 x int> -%tmp3 = and <4 x int> %tmp, %tmp2 -%tmp4 = xor <4 x int> %tmp3, < int -1, int -1, int -1, int -1 > -%tmp4 = cast <4 x int> %tmp4 to <4 x float> +%tmp4 = xor <4 x int> %tmp2, < int -1, int -1, int -1, int -1 > +%tmp3 = and <4 x int> %tmp, %tmp4 +%tmp4 = cast <4 x int> %tmp3 to <4 x float> store <4 x float> %tmp4, <4 x float>* %P ret void } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Intrinsics.td
Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.25 -> 1.26 --- Log message: add int_ppc_altivec_vsldoi intrinsic --- Diffs of the changes: (+4 -0) Intrinsics.td |4 1 files changed, 4 insertions(+) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.25 llvm/include/llvm/Intrinsics.td:1.26 --- llvm/include/llvm/Intrinsics.td:1.25Sat Mar 25 01:30:34 2006 +++ llvm/include/llvm/Intrinsics.td Sat Mar 25 18:25:43 2006 @@ -240,6 +240,10 @@ def int_ppc_altivec_vaddcuw : GCCBuiltin<"__builtin_altivec_vaddcuw">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; + def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">, + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + llvm_v4i32_ty, llvm_int_ty], +[InstrNoMem]>; // Saturating adds: def int_ppc_altivec_vaddubs : GCCBuiltin<"__builtin_altivec_vaddubs">, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td PPCInstrFormats.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.5 -> 1.6
PPCInstrFormats.td updated: 1.67 -> 1.68
---
Log message:
implement the vsldoi intrinsic.
---
Diffs of the changes: (+26 -4)
PPCInstrAltivec.td | 12
PPCInstrFormats.td | 18 ++
2 files changed, 26 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.5
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.6
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.5 Sat Mar 25 17:10:40 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Mar 25 18:41:48 2006
@@ -71,13 +71,13 @@
def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
"lvebx $vD, $src", LdStGeneral,
[(set VRRC:$vD, (v16i8 (PPClve_x xoaddr:$src)))]>;
-def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
+def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
"lvehx $vD, $src", LdStGeneral,
[(set VRRC:$vD, (v8i16 (PPClve_x xoaddr:$src)))]>;
-def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
+def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
"lvewx $vD, $src", LdStGeneral,
[(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
-def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
+def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
"lvx $vD, $src", LdStGeneral,
[(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
}
@@ -121,7 +121,11 @@
"vperm $vD, $vA, $vB, $vC", VecPerm,
[(set VRRC:$vD,
(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB,
VRRC:$vC))]>;
-
+def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
+ "vsldoi $vD, $vA, $vB, $SH", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
+ imm:$SH))]>;
// VX-Form instructions. AltiVec arithmetic ops.
def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.67
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.68
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.67 Tue Mar 21 19:44:36 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Sat Mar 25 18:41:48 2006
@@ -607,6 +607,24 @@
let Inst{26-31} = xo;
}
+class VAForm_2 xo, dag OL, string asmstr,
+ InstrItinClass itin, list pattern>
+: I<4, OL, asmstr, itin> {
+ bits<5> VD;
+ bits<5> VA;
+ bits<5> VB;
+ bits<4> SH;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = VA;
+ let Inst{16-20} = VB;
+ let Inst{21}= 0;
+ let Inst{22-25} = SH;
+ let Inst{26-31} = xo;
+}
+
// E-2 VX-Form
class VXForm_1 xo, dag OL, string asmstr,
InstrItinClass itin, list pattern>
___
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[llvm-commits] CVS: llvm/include/llvm/Intrinsics.td
Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.26 -> 1.27 --- Log message: Add saturating subtracts, non-predicate compares, and some other random intrinsics. --- Diffs of the changes: (+71 -2) Intrinsics.td | 73 -- 1 files changed, 71 insertions(+), 2 deletions(-) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.26 llvm/include/llvm/Intrinsics.td:1.27 --- llvm/include/llvm/Intrinsics.td:1.26Sat Mar 25 18:25:43 2006 +++ llvm/include/llvm/Intrinsics.td Sat Mar 25 20:34:07 2006 @@ -240,12 +240,61 @@ def int_ppc_altivec_vaddcuw : GCCBuiltin<"__builtin_altivec_vaddcuw">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; + def int_ppc_altivec_vsubcuw : GCCBuiltin<"__builtin_altivec_vsubcuw">, + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">, + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, - llvm_v4i32_ty, llvm_int_ty], + llvm_v4i32_ty, llvm_int_ty], [InstrNoMem]>; + + // Comparisons setting a vector. + def int_ppc_altivec_vcmpbfp : GCCBuiltin<"__builtin_altivec_vcmpbfp">, + Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpeqfp : GCCBuiltin<"__builtin_altivec_vcmpeqfp">, + Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgefp : GCCBuiltin<"__builtin_altivec_vcmpgefp">, + Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtfp : GCCBuiltin<"__builtin_altivec_vcmpgtfp">, + Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], +[InstrNoMem]>; + + def int_ppc_altivec_vcmpequw : GCCBuiltin<"__builtin_altivec_vcmpequw">, + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtsw : GCCBuiltin<"__builtin_altivec_vcmpgtsw">, + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtuw : GCCBuiltin<"__builtin_altivec_vcmpgtuw">, + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], +[InstrNoMem]>; + + def int_ppc_altivec_vcmpequh : GCCBuiltin<"__builtin_altivec_vcmpequh">, + Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtsh : GCCBuiltin<"__builtin_altivec_vcmpgtsh">, + Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtuh : GCCBuiltin<"__builtin_altivec_vcmpgtuh">, + Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; - // Saturating adds: + def int_ppc_altivec_vcmpequb : GCCBuiltin<"__builtin_altivec_vcmpequb">, + Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtsb : GCCBuiltin<"__builtin_altivec_vcmpgtsb">, + Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtub : GCCBuiltin<"__builtin_altivec_vcmpgtub">, + Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], +[InstrNoMem]>; + + // Saturating adds and subs. def int_ppc_altivec_vaddubs : GCCBuiltin<"__builtin_altivec_vaddubs">, Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], [InstrNoMem]>; @@ -264,6 +313,26 @@ def int_ppc_altivec_vaddsws : GCCBuiltin<"__builtin_altivec_vaddsws">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; + + def int_ppc_altivec_vsububs : GCCBuiltin<"__builtin_altivec_vsububs">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], +[InstrNoMem]>; + def int_ppc_altivec_vsubsbs : GCCBuiltin<"__builtin_altivec_vsubsbs">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], +[InstrNoMem]>; + def int_ppc_altivec_vsubuhs : GCCBuiltin<"__builtin_altivec_vsubuhs">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], +[In
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td IntrinsicsX86.td Intrinsics.td
Changes in directory llvm/include/llvm:
IntrinsicsPowerPC.td added (r1.1)
IntrinsicsX86.td added (r1.1)
Intrinsics.td updated: 1.27 -> 1.28
---
Log message:
Split the PPC and X86 intrinsics out to their own files.
---
Diffs of the changes: (+403 -378)
Intrinsics.td| 380 ---
IntrinsicsPowerPC.td | 138 ++
IntrinsicsX86.td | 263 +++
3 files changed, 403 insertions(+), 378 deletions(-)
Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -c /dev/null llvm/include/llvm/IntrinsicsPowerPC.td:1.1
*** /dev/null Sat Mar 25 20:37:30 2006
--- llvm/include/llvm/IntrinsicsPowerPC.td Sat Mar 25 20:37:19 2006
***
*** 0
--- 1,138
+ //===- IntrinsicsPowerPC.td - Defines PowerPC intrinsics ---*- tablegen
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file defines all of the PowerPC-specific intrinsics.
+ //
+
//===--===//
+
+ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
+ def int_ppc_altivec_lvx : GCCBuiltin<"__builtin_altivec_lvx">,
+ Intrinsic<[llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
+ [IntrReadMem]>;
+ def int_ppc_altivec_stvx : GCCBuiltin<"__builtin_altivec_stvx">,
+ Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_int_ty,
llvm_ptr_ty],
+ [IntrWriteMem]>;
+
+ def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">,
+ Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+ llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
+ def int_ppc_altivec_vnmsubfp : GCCBuiltin<"__builtin_altivec_vnmsubfp">,
+ Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+ llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
+
+ def int_ppc_altivec_vaddcuw : GCCBuiltin<"__builtin_altivec_vaddcuw">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+ [InstrNoMem]>;
+ def int_ppc_altivec_vsubcuw : GCCBuiltin<"__builtin_altivec_vsubcuw">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+ [InstrNoMem]>;
+ def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
+ llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>;
+ def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
+ llvm_v4i32_ty, llvm_int_ty], [InstrNoMem]>;
+
+ // Comparisons setting a vector.
+ def int_ppc_altivec_vcmpbfp : GCCBuiltin<"__builtin_altivec_vcmpbfp">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
+ [InstrNoMem]>;
+ def int_ppc_altivec_vcmpeqfp : GCCBuiltin<"__builtin_altivec_vcmpeqfp">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
+ [InstrNoMem]>;
+ def int_ppc_altivec_vcmpgefp : GCCBuiltin<"__builtin_altivec_vcmpgefp">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
+ [InstrNoMem]>;
+ def int_ppc_altivec_vcmpgtfp : GCCBuiltin<"__builtin_altivec_vcmpgtfp">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
+ [InstrNoMem]>;
+
+ def int_ppc_altivec_vcmpequw : GCCBuiltin<"__builtin_altivec_vcmpequw">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+ [InstrNoMem]>;
+ def int_ppc_altivec_vcmpgtsw : GCCBuiltin<"__builtin_altivec_vcmpgtsw">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+ [InstrNoMem]>;
+ def int_ppc_altivec_vcmpgtuw : GCCBuiltin<"__builtin_altivec_vcmpgtuw">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+ [InstrNoMem]>;
+
+ def int_ppc_altivec_vcmpequh : GCCBuiltin<"__builtin_altivec_vcmpequh">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+ [InstrNoMem]>;
+ def int_ppc_altivec_vcmpgtsh : GCCBuiltin<"__builtin_altivec_vcmpgtsh">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+ [InstrNoMem]>;
+ def int_ppc_altivec_vcmpgtuh : GCCBuiltin<"__builtin_altivec_vcmpgtuh">,
+ Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.6 -> 1.7 --- Log message: Add and 8/16-bit adds, add all integer subtracts, add saturating subtract intrinsics. --- Diffs of the changes: (+53 -3) PPCInstrAltivec.td | 56 ++--- 1 files changed, 53 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.6 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.7 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.6 Sat Mar 25 18:41:48 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Mar 25 20:39:02 2006 @@ -135,6 +135,17 @@ def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vaddfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; + +def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vaddubm $vD, $vA, $vB", VecGeneral, + [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>; +def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vadduhm $vD, $vA, $vB", VecGeneral, + [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>; +def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vadduwm $vD, $vA, $vB", VecGeneral, + [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; + def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vaddsbs $vD, $vA, $vB", VecFP, [(set VRRC:$vD, @@ -147,6 +158,7 @@ "vaddsws $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>; + def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vaddubs $vD, $vA, $vB", VecFP, [(set VRRC:$vD, @@ -155,9 +167,6 @@ "vadduhs $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>; -def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vadduwm $vD, $vA, $vB", VecGeneral, - [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vadduws $vD, $vA, $vB", VecFP, [(set VRRC:$vD, @@ -213,9 +222,50 @@ def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB), "vrsqrtefp $vD, $vB", VecFP, [(set VRRC:$vD,(int_ppc_altivec_vrsqrtefp VRRC:$vB))]>; +def VSUBCUW : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vsubcuw $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vsubcuw VRRC:$vA, VRRC:$vB))]>; def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vsubfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; + +def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vsububm $vD, $vA, $vB", VecGeneral, + [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>; +def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vsubuhm $vD, $vA, $vB", VecGeneral, + [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>; +def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vsubuwm $vD, $vA, $vB", VecGeneral, + [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>; + +def VSUBSBS : VXForm_1<1792, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vsubsbs $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vsubsbs VRRC:$vA, VRRC:$vB))]>; +def VSUBSHS : VXForm_1<1856, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vsubshs $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vsubshs VRRC:$vA, VRRC:$vB))]>; +def VSUBSWS : VXForm_1<1920, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vsubsws $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vsubsws VRRC:$vA, VRRC:$vB))]>; + +def VSUBUBS : VXForm_1<1536, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vsububs $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, + (int_ppc_altivec_vsububs VRRC:$vA, VRRC:$vB))]>; +def VSUBUHS : VXForm_1<1600, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), +
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td PPCInstrFormats.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.7 -> 1.8
PPCInstrFormats.td updated: 1.68 -> 1.69
---
Log message:
Add all of the altivec comparison instructions. Add patterns for the
non-predicate altivec compare intrinsics.
---
Diffs of the changes: (+108 -5)
PPCInstrAltivec.td | 108 +++--
PPCInstrFormats.td |5 +-
2 files changed, 108 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.7
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.8
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.7 Sat Mar 25 20:39:02 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Mar 25 22:57:17 2006
@@ -59,7 +59,10 @@
return PPC::isVecSplatImm(N, 4);
}], VSPLTISW_get_imm>;
-
+class isVDOT { // vector dot instruction.
+ list Defs = [CR6];
+ bit RC = 1;
+}
//===--===//
// Instruction Definitions.
@@ -297,9 +300,108 @@
"vspltisw $vD, $SIMM", VecPerm,
[(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
-
-// VX-Form Pseudo Instructions
+// Altivec Comparisons.
+
+// f32 element comparisons.
+def VCMPBFP : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpbfp $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+(int_ppc_altivec_vcmpbfp VRRC:$vA,
VRRC:$vB))]>;
+def VCMPBFPo : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpbfp. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPEQFP : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpeqfp $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpeqfp VRRC:$vA,
VRRC:$vB))]>;
+def VCMPEQFPo : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpeqfp. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGEFP : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgefp $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgefp VRRC:$vA,
VRRC:$vB))]>;
+def VCMPGEFPo : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgefp. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTFP : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtfp $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgtfp VRRC:$vA,
VRRC:$vB))]>;
+def VCMPGTFPo : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtfp. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+
+// i8 element comparisons.
+def VCMPEQUB : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpequb $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpequb VRRC:$vA,
VRRC:$vB))]>;
+def VCMPEQUBo : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpequb. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTSB : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtsb $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgtsb VRRC:$vA,
VRRC:$vB))]>;
+def VCMPGTSBo : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtsb. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTUB : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtub $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgtub VRRC:$vA,
VRRC:$vB))]>;
+def VCMPGTUBo : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtub. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+
+// i16 element comparisons.
+def VCMPEQUH : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpequh $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpequh VRRC:$vA,
VRRC:$vB))]>;
+def VCMPEQUHo : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpequh. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTSH : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtsh $vD, $vA, $vB", VecFPCompare,
+
[llvm-commits] CVS: llvm/lib/VMCore/Makefile
Changes in directory llvm/lib/VMCore: Makefile updated: 1.13 -> 1.14 --- Log message: Update dependencies to reflect split of the Intrinsics.td file --- Diffs of the changes: (+5 -2) Makefile |7 +-- 1 files changed, 5 insertions(+), 2 deletions(-) Index: llvm/lib/VMCore/Makefile diff -u llvm/lib/VMCore/Makefile:1.13 llvm/lib/VMCore/Makefile:1.14 --- llvm/lib/VMCore/Makefile:1.13 Fri Mar 17 01:39:44 2006 +++ llvm/lib/VMCore/MakefileSun Mar 26 01:45:48 2006 @@ -20,9 +20,12 @@ GENFILE:=$(PROJ_SRC_ROOT)/include/llvm/Intrinsics.gen -$(GENFILE): $(PROJ_SRC_ROOT)/include/llvm/Intrinsics.td $(TBLGEN) +INTRINSICTD := $(PROJ_SRC_ROOT)/include/llvm/Intrinsics.td +INTRINSICTDS := $(wildcard $(PROJ_SRC_ROOT)/include/llvm/Intrinsics*.td) + +$(GENFILE): $(INTRINSICTDS) $(TBLGEN) $(Echo) Building Intrinsics.gen from Intrinsics.td - $(Verb) $(TableGen) $< -o $@ -gen-intrinsic + $(Verb) $(TableGen) $(INTRINSICTD) -o $@ -gen-intrinsic install-local:: $(GENFILE) $(DataInstall) $(GENFILE) $(PROJ_includedir)/llvm/Intrinsics.gen ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td
Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.1 -> 1.2 --- Log message: Add predicate comparison intrinsics. --- Diffs of the changes: (+44 -0) IntrinsicsPowerPC.td | 44 1 files changed, 44 insertions(+) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.1 llvm/include/llvm/IntrinsicsPowerPC.td:1.2 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.1 Sat Mar 25 20:37:19 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Sun Mar 26 01:50:25 2006 @@ -83,6 +83,50 @@ Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], [InstrNoMem]>; + // Predicate Comparisons. The first operand specifies interpretation of CR6. + def int_ppc_altivec_vcmpbfp_p : GCCBuiltin<"__builtin_altivec_vcmpbfp_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4f32_ty,llvm_v4f32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpeqfp_p : GCCBuiltin<"__builtin_altivec_vcmpeqfp_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4f32_ty,llvm_v4f32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgefp_p : GCCBuiltin<"__builtin_altivec_vcmpgefp_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4f32_ty,llvm_v4f32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtfp_p : GCCBuiltin<"__builtin_altivec_vcmpgtfp_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4f32_ty,llvm_v4f32_ty], +[InstrNoMem]>; + + def int_ppc_altivec_vcmpequw_p : GCCBuiltin<"__builtin_altivec_vcmpequw_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4i32_ty,llvm_v4i32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtsw_p : GCCBuiltin<"__builtin_altivec_vcmpgtsw_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4i32_ty,llvm_v4i32_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtuw_p : GCCBuiltin<"__builtin_altivec_vcmpgtuw_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4i32_ty,llvm_v4i32_ty], +[InstrNoMem]>; + + def int_ppc_altivec_vcmpequh_p : GCCBuiltin<"__builtin_altivec_vcmpequh_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v8i16_ty,llvm_v8i16_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtsh_p : GCCBuiltin<"__builtin_altivec_vcmpgtsh_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v8i16_ty,llvm_v8i16_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtuh_p : GCCBuiltin<"__builtin_altivec_vcmpgtuh_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v8i16_ty,llvm_v8i16_ty], +[InstrNoMem]>; + + def int_ppc_altivec_vcmpequb_p : GCCBuiltin<"__builtin_altivec_vcmpequb_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtsb_p : GCCBuiltin<"__builtin_altivec_vcmpgtsb_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty], +[InstrNoMem]>; + def int_ppc_altivec_vcmpgtub_p : GCCBuiltin<"__builtin_altivec_vcmpgtub_p">, + Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty], +[InstrNoMem]>; + // Saturating adds and subs. def int_ppc_altivec_vaddubs : GCCBuiltin<"__builtin_altivec_vaddubs">, Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
