[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopStrengthReduce.cpp updated: 1.79 -> 1.80
---
Log message:
- Fixed a bogus if condition.
- Added more debugging info.
- Allow reuse of IV of negative stride. e.g. -4 stride == 2 * iv of -2 stride.
---
Diffs of the changes: (+25 -19)
LoopStrengthReduce.cpp | 44 +---
1 files changed, 25 insertions(+), 19 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.79
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.80
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.79 Fri Mar 17
18:44:49 2006
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Sat Mar 18 02:03:12 2006
@@ -77,15 +77,20 @@
};
/// IVInfo - This structure keeps track of one IV expression inserted during
- /// StrengthReduceStridedIVUsers. It contains the base value, as well as the
- /// PHI node and increment value created for rewrite.
+ /// StrengthReduceStridedIVUsers. It contains the stride, the common base, as
+ /// well as the PHI node and increment value created for rewrite.
struct IVExpr {
+SCEVHandle Stride;
SCEVHandle Base;
PHINode*PHI;
Value *IncV;
-IVExpr(const SCEVHandle &base, PHINode *phi, Value *incv)
- : Base(base), PHI(phi), IncV(incv) {}
+IVExpr()
+ : Stride(SCEVUnknown::getIntegerSCEV(0, Type::UIntTy)),
+Base (SCEVUnknown::getIntegerSCEV(0, Type::UIntTy)) {}
+IVExpr(const SCEVHandle &stride, const SCEVHandle &base, PHINode *phi,
+ Value *incv)
+ : Stride(stride), Base(base), PHI(phi), IncV(incv) {}
};
/// IVsOfOneStride - This structure keeps track of all IV expression inserted
@@ -93,8 +98,9 @@
struct IVsOfOneStride {
std::vector IVs;
-void addIV(const SCEVHandle &Base, PHINode *PHI, Value *IncV) {
- IVs.push_back(IVExpr(Base, PHI, IncV));
+void addIV(const SCEVHandle &Stride, const SCEVHandle &Base, PHINode *PHI,
+ Value *IncV) {
+ IVs.push_back(IVExpr(Stride, Base, PHI, IncV));
}
};
@@ -863,22 +869,20 @@
/// CheckForIVReuse - Returns the multiple if the stride is the multiple
/// of a previous stride and it is a legal value for the target addressing
/// mode scale component. This allows the users of this stride to be rewritten
-/// as prev iv * factor. It returns 1 if no reuse is possible.
+/// as prev iv * factor. It returns 0 if no reuse is possible.
unsigned LoopStrengthReduce::CheckForIVReuse(const SCEVHandle &Stride,
IVExpr &IV) {
- if (!TLI)
-return 1;
+ if (!TLI) return 0;
if (SCEVConstant *SC = dyn_cast(Stride)) {
-unsigned SInt = SC->getValue()->getRawValue();
-if (SInt == 1)
- return 1;
+int64_t SInt = SC->getValue()->getSExtValue();
+if (SInt == 1) return 0;
for (TargetLowering::legal_am_scale_iterator
I = TLI->legal_am_scale_begin(), E = TLI->legal_am_scale_end();
I != E; ++I) {
unsigned Scale = *I;
- if (SInt >= Scale && (SInt % Scale) != 0)
+ if (abs(SInt) < Scale || (SInt % Scale) != 0)
continue;
std::map::iterator SI =
IVsByStride.find(SCEVUnknown::getIntegerSCEV(SInt/Scale,
Type::UIntTy));
@@ -894,7 +898,7 @@
}
}
- return 1;
+ return 0;
}
@@ -929,9 +933,11 @@
// field of the target addressing mode.
PHINode *NewPHI = NULL;
Value *IncV = NULL;
- IVExpr ReuseIV(Stride, NULL, NULL);
+ IVExpr ReuseIV;
unsigned RewriteFactor = CheckForIVReuse(Stride, ReuseIV);
- if (RewriteFactor > 1) {
+ if (RewriteFactor != 0) {
+DEBUG(std::cerr << "BASED ON IV of STRIDE " << *ReuseIV.Stride
+ << " and BASE " << *ReuseIV.Base << " :\n");
NewPHI = ReuseIV.PHI;
IncV = ReuseIV.IncV;
}
@@ -994,7 +1000,7 @@
= PreheaderRewriter.expandCodeFor(CommonExprs, PreInsertPt,
ReplacedTy);
- if (RewriteFactor == 1) {
+ if (RewriteFactor == 0) {
// Create a new Phi for this base, and stick it in the loop header.
NewPHI = new PHINode(ReplacedTy, "iv.", PhiInsertBefore);
++NumInserted;
@@ -1018,7 +1024,7 @@
NewPHI->addIncoming(IncV, LatchBlock);
// Remember this in case a later stride is multiple of this.
-IVsByStride[Stride].addIV(CommonExprs, NewPHI, IncV);
+IVsByStride[Stride].addIV(Stride, CommonExprs, NewPHI, IncV);
} else {
Constant *C = dyn_cast(CommonBaseV);
if (!C ||
@@ -1076,7 +1082,7 @@
// If we are reusing the iv, then it must be multiplied by a constant
// factor take advantage of addressing mode scale component.
- if (RewriteFactor != 1) {
+ if (RewriteFactor != 0) {
RewriteExpr =
SCEVMulExpr::get(SCEVUnknown::getIntegerSCEV(RewriteFactor,
RewriteExpr->getType()),
_
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll fast-cc-pass-in-regs.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
fast-cc-callee-pops.ll updated: 1.1 -> 1.2
fast-cc-pass-in-regs.ll updated: 1.3 -> 1.4
---
Log message:
update testcases for x86 fastcc changes.
---
Diffs of the changes: (+4 -2)
fast-cc-callee-pops.ll |2 +-
fast-cc-pass-in-regs.ll |4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll
diff -u llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll:1.1
llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll:1.2
--- llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll:1.1 Fri May 13
17:15:26 2005
+++ llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll Sat Mar 18
17:48:54 2006
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc
| grep 'ret 20'
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc
| grep 'ret 28'
; Check that a fastcc function pops its stack variables before returning.
Index: llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll
diff -u llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll:1.3
llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll:1.4
--- llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll:1.3Fri May
13 11:20:59 2005
+++ llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.llSat Mar 18
17:48:54 2006
@@ -1,7 +1,9 @@
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc
| grep 'mov %EDX, 1'
-
; check that fastcc is passing stuff in regs.
+; Argument reg passing is disabled due to regalloc issues. FIXME!
+; XFAIL: *
+
declare fastcc long %callee(long)
long %caller() {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.317 -> 1.318
---
Log message:
Fix the remaining bugs in the vector expansion rework I commited yesterday.
This fixes CodeGen/Generic/vector.ll
---
Diffs of the changes: (+5 -4)
LegalizeDAG.cpp |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.317
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.318
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.317 Fri Mar 17 19:44:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Mar 18 18:07:49 2006
@@ -407,7 +407,7 @@
// Otherwise, this is a multiple element vector that isn't supported.
// Split it in half and legalize both parts.
SDOperand X, Y;
-ExpandOp(Op, X, Y);
+SplitVectorOp(Op, X, Y);
}
}
break;
@@ -4006,6 +4006,7 @@
}
switch (Node->getOpcode()) {
+ default: assert(0 && "Unknown vector operation!");
case ISD::VConstant: {
std::vector LoOps(Node->op_begin(),
Node->op_begin()+NewNumElts);
LoOps.push_back(NewNumEltsNode);
@@ -4098,10 +4099,10 @@
PackVectorOp(Node->getOperand(1), NewVT));
break;
case ISD::VLOAD: {
-SDOperand Ch = LegalizeOp(Node->getOperand(2)); // Legalize the chain.
-SDOperand Ptr = LegalizeOp(Node->getOperand(3)); // Legalize the pointer.
+SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
+SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
-Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(4));
+Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
___
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll
Changes in directory llvm/test/Regression/CodeGen/Generic:
vector.ll updated: 1.1 -> 1.2
---
Log message:
Add three new testcases
---
Diffs of the changes: (+25 -0)
vector.ll | 25 +
1 files changed, 25 insertions(+)
Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.1
llvm/test/Regression/CodeGen/Generic/vector.ll:1.2
--- llvm/test/Regression/CodeGen/Generic/vector.ll:1.1 Fri Mar 17 14:04:40 2006
+++ llvm/test/Regression/CodeGen/Generic/vector.ll Sat Mar 18 18:20:03 2006
@@ -8,6 +8,8 @@
implementation
+;;; TEST HANDLING OF VARIOUS VECTOR SIZES
+
void %test_f1(%f1 *%P, %f1* %Q, %f1 *%S) {
%p = load %f1 *%P
%q = load %f1* %Q
@@ -39,3 +41,26 @@
store %f8 %R, %f8 *%S
ret void
}
+
+;;; TEST VECTOR CONSTRUCTS
+
+void %test_cst(%f4 *%P, %f4 *%S) {
+ %p = load %f4* %P
+ %R = add %f4 %p,
+ store %f4 %R, %f4 *%S
+ ret void
+}
+
+void %test_zero(%f4 *%P, %f4 *%S) {
+ %p = load %f4* %P
+ %R = add %f4 %p, zeroinitializer
+ store %f4 %R, %f4 *%S
+ ret void
+}
+
+void %test_undef(%f4 *%P, %f4 *%S) {
+ %p = load %f4* %P
+ %R = add %f4 %p, undef
+ store %f4 %R, %f4 *%S
+ ret void
+}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.318 -> 1.319
SelectionDAGISel.cpp updated: 1.194 -> 1.195
---
Log message:
implement vector.ll:test_undef
---
Diffs of the changes: (+24 -9)
LegalizeDAG.cpp |8 ++--
SelectionDAGISel.cpp | 25 ++---
2 files changed, 24 insertions(+), 9 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.318
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.319
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.318 Sat Mar 18 18:07:49 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Mar 18 18:20:20 2006
@@ -730,12 +730,16 @@
std::vector CV;
if (MVT::isFloatingPoint(VT)) {
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
- double V = cast(Node->getOperand(i))->getValue();
+ double V = 0;
+ if (Node->getOperand(i).getOpcode() != ISD::UNDEF)
+V = cast(Node->getOperand(i))->getValue();
CV.push_back(ConstantFP::get(OpNTy, V));
}
} else {
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
- uint64_t V = cast(Node->getOperand(i))->getValue();
+ uint64_t V = 0;
+ if (Node->getOperand(i).getOpcode() != ISD::UNDEF)
+V = cast(Node->getOperand(i))->getValue();
CV.push_back(ConstantUInt::get(OpNTy, V));
}
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.194
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.195
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.194Fri Mar 17
19:44:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Mar 18 18:20:20 2006
@@ -516,13 +516,26 @@
} else if (isa(C)) {
return N = DAG.getConstant(0, TLI.getPointerTy());
} else if (isa(C)) {
- return N = DAG.getNode(ISD::UNDEF, VT);
+ if (!isa(VTy))
+return N = DAG.getNode(ISD::UNDEF, VT);
+
+ // Create a VConstant of undef nodes.
+ const PackedType *PTy = cast(VTy);
+ unsigned NumElements = PTy->getNumElements();
+ MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
+
+ std::vector Ops;
+ Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
+
+ // Create a VConstant node with generic Vector type.
+ Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
+ Ops.push_back(DAG.getValueType(PVT));
+ return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops);
} else if (ConstantFP *CFP = dyn_cast(C)) {
return N = DAG.getConstantFP(CFP->getValue(), VT);
} else if (const PackedType *PTy = dyn_cast(VTy)) {
unsigned NumElements = PTy->getNumElements();
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
- MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
// Now that we know the number and type of the elements, push a
// Constant or ConstantFP node onto the ops list for each element of
@@ -551,11 +564,9 @@
Ops.assign(NumElements, Op);
}
- // Create a ConstantVec node with generic Vector type.
- SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
- SDOperand Typ = DAG.getValueType(PVT);
- Ops.push_back(Num);
- Ops.push_back(Typ);
+ // Create a VConstant node with generic Vector type.
+ Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
+ Ops.push_back(DAG.getValueType(PVT));
return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops);
} else {
// Canonicalize all constant ints to be unsigned.
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.113 -> 1.114 --- Log message: Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow *BUILD_VECTOR to take variable inputs. --- Diffs of the changes: (+23 -24) SelectionDAGNodes.h | 47 +++ 1 files changed, 23 insertions(+), 24 deletions(-) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.113 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.114 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.113 Fri Mar 17 19:43:28 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Sat Mar 18 18:52:25 2006 @@ -67,15 +67,10 @@ Constant, ConstantFP, GlobalAddress, FrameIndex, ConstantPool, ExternalSymbol, -// ConstantVec works like Constant or ConstantFP, except that it is not a -// leaf node. All operands are either Constant or ConstantFP nodes. -ConstantVec, - // TargetConstant* - Like Constant*, but the DAG does not do any folding or // simplification of the constant. TargetConstant, TargetConstantFP, -TargetConstantVec, // TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or // anything else with this node, and this is valid in the target-specific @@ -85,12 +80,6 @@ TargetConstantPool, TargetExternalSymbol, -// Abstract version of ConstantVec with abstract Vector type. The first N-2 -// operands are the constants to initialize the vector, the N-2nd operand -// is a constant element count, and that last operand is the value type -// indicating the type of the elements. -VConstant, - // CopyToReg - This node has three operands: a chain, a register number to // set to this value, and a value. CopyToReg, @@ -148,26 +137,36 @@ // FCOPYSIGN(f32, f64) is allowed. FCOPYSIGN, -/// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR (a legal packed -/// type) with the element at IDX replaced with VAL. -INSERT_VECTOR_ELT, +/// VBUILD_VECTOR(ELT1, ELT2, ELT3, ELT4,..., COUNT,TYPE) - Return a vector +/// with the specified, possibly variable, elements. The number of elements +/// is required to be a power of two. +VBUILD_VECTOR, + +/// BUILD_VECTOR(ELT1, ELT2, ELT3, ELT4,...) - Return a vector +/// with the specified, possibly variable, elements. The number of elements +/// is required to be a power of two. +BUILD_VECTOR, -// BINOP(LHS, RHS, COUNT,TYPE) -// Simple abstract vector operators. Unlike the integer and floating point -// binary operators, these nodes also take two additional operands: -// a constant element count, and a value type node indicating the type of -// the elements. The order is count, type, op0, op1. All vector opcodes, -// including VLOAD and VConstant must currently have count and type as -// their last two operands. -VADD, VSUB, VMUL, VSDIV, VUDIV, -VAND, VOR, VXOR, - /// VINSERT_VECTOR_ELT(VECTOR, VAL, IDX, COUNT,TYPE) - Given a vector /// VECTOR, an element ELEMENT, and a (potentially variable) index IDX, /// return an vector with the specified element of VECTOR replaced with VAL. /// COUNT and TYPE specify the type of vector, as is standard for V* nodes. VINSERT_VECTOR_ELT, +/// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR (a legal packed +/// type) with the element at IDX replaced with VAL. +INSERT_VECTOR_ELT, + +/// BINOP(LHS, RHS, COUNT,TYPE) +/// Simple abstract vector operators. Unlike the integer and floating point +/// binary operators, these nodes also take two additional operands: +/// a constant element count, and a value type node indicating the type of +/// the elements. The order is count, type, op0, op1. All vector opcodes, +/// including VLOAD and VConstant must currently have count and type as +/// their last two operands. +VADD, VSUB, VMUL, VSDIV, VUDIV, +VAND, VOR, VXOR, + // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing // an unsigned/signed value of type i[2*n], then return the top part. MULHU, MULHS, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.319 -> 1.320
SelectionDAG.cpp updated: 1.273 -> 1.274
SelectionDAGISel.cpp updated: 1.195 -> 1.196
---
Log message:
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR.
Allow*BUILD_VECTOR to take variable inputs.
---
Diffs of the changes: (+71 -57)
LegalizeDAG.cpp | 115 ---
SelectionDAG.cpp |5 --
SelectionDAGISel.cpp |8 +--
3 files changed, 71 insertions(+), 57 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.319
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.320
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.319 Sat Mar 18 18:20:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Mar 18 18:52:58 2006
@@ -452,7 +452,6 @@
case ISD::TargetFrameIndex:
case ISD::TargetConstant:
case ISD::TargetConstantFP:
- case ISD::TargetConstantVec:
case ISD::TargetConstantPool:
case ISD::TargetGlobalAddress:
case ISD::TargetExternalSymbol:
@@ -709,47 +708,6 @@
}
break;
}
- case ISD::ConstantVec:
-switch (TLI.getOperationAction(ISD::ConstantVec, Node->getValueType(0))) {
-default: assert(0 && "This action is not supported yet!");
-case TargetLowering::Custom:
- Tmp3 = TLI.LowerOperation(Result, DAG);
- if (Tmp3.Val) {
-Result = Tmp3;
-break;
- }
- // FALLTHROUGH
-case TargetLowering::Expand:
- // We assume that vector constants are not legal, and will be immediately
- // spilled to the constant pool.
- //
- // Create a ConstantPacked, and put it in the constant pool.
- MVT::ValueType VT = Node->getValueType(0);
- const Type *OpNTy =
-MVT::getTypeForValueType(Node->getOperand(0).getValueType());
- std::vector CV;
- if (MVT::isFloatingPoint(VT)) {
-for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
- double V = 0;
- if (Node->getOperand(i).getOpcode() != ISD::UNDEF)
-V = cast(Node->getOperand(i))->getValue();
- CV.push_back(ConstantFP::get(OpNTy, V));
-}
- } else {
-for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
- uint64_t V = 0;
- if (Node->getOperand(i).getOpcode() != ISD::UNDEF)
-V = cast(Node->getOperand(i))->getValue();
- CV.push_back(ConstantUInt::get(OpNTy, V));
-}
- }
- Constant *CP = ConstantPacked::get(CV);
- SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
- Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
- DAG.getSrcValue(NULL));
- break;
-}
-break;
case ISD::TokenFactor:
if (Node->getNumOperands() == 2) {
Tmp1 = LegalizeOp(Node->getOperand(0));
@@ -769,6 +727,64 @@
}
break;
+ case ISD::BUILD_VECTOR:
+switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
+ default: assert(0 && "This action is not supported yet!");
+ case TargetLowering::Custom:
+Tmp3 = TLI.LowerOperation(Result, DAG);
+if (Tmp3.Val) {
+ Result = Tmp3;
+ break;
+}
+ // FALLTHROUGH
+case TargetLowering::Expand: {
+ // We assume that built vectors are not legal, and will be
immediately
+ // spilled to memory. If the values are all constants, turn this
into a
+ // load from the constant pool.
+ bool isConstant = true;
+ for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
+ I != E; ++I) {
+if (!isa(I) && !isa(I) &&
+I->getOpcode() != ISD::UNDEF) {
+ isConstant = false;
+ break;
+}
+ }
+
+ // Create a ConstantPacked, and put it in the constant pool.
+ if (isConstant) {
+MVT::ValueType VT = Node->getValueType(0);
+const Type *OpNTy =
+ MVT::getTypeForValueType(Node->getOperand(0).getValueType());
+std::vector CV;
+for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+ if (ConstantFPSDNode *V =
+dyn_cast(Node->getOperand(i))) {
+CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
+ } else if (ConstantSDNode *V =
+ dyn_cast(Node->getOperand(i))) {
+CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
+ } else {
+assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
+CV.push_back(UndefValue::get(OpNTy));
+ }
+}
+Constant *CP = ConstantPacked::get(CV);
+SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
+Result = DAG.getLoad(VT, DAG.getEntryNode(),
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.97 -> 1.98 --- Log message: rename these nodes --- Diffs of the changes: (+3 -3) PPCISelLowering.cpp |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.97 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.98 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.97Thu Mar 16 19:40:33 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Mar 18 19:13:28 2006 @@ -179,10 +179,10 @@ setOperationAction(ISD::LOAD , MVT::v4f32, Legal); setOperationAction(ISD::ADD, MVT::v4i32, Legal); setOperationAction(ISD::LOAD , MVT::v4i32, Legal); -// FIXME: We don't support any ConstantVec's yet. We should custom expand +// FIXME: We don't support any BUILD_VECTOR's yet. We should custom expand // the ones we do! -setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand); -setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand); +setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand); +setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand); } setSetCCResultContents(ZeroOrOneSetCCResult); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.111 -> 1.112
---
Log message:
rename these nodes
---
Diffs of the changes: (+9 -9)
X86ISelLowering.cpp | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.111
llvm/lib/Target/X86/X86ISelLowering.cpp:1.112
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.111 Fri Mar 17 14:31:41 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Mar 18 19:13:28 2006
@@ -263,9 +263,9 @@
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics
-setOperationAction(ISD::ConstantVec, MVT::v8i8, Expand);
-setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand);
-setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
}
if (TM.getSubtarget().hasSSE1()) {
@@ -275,7 +275,7 @@
setOperationAction(ISD::SUB, MVT::v4f32, Legal);
setOperationAction(ISD::MUL, MVT::v4f32, Legal);
setOperationAction(ISD::LOAD , MVT::v4f32, Legal);
-setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
}
if (TM.getSubtarget().hasSSE2()) {
@@ -290,11 +290,11 @@
setOperationAction(ISD::SUB, MVT::v2f64, Legal);
setOperationAction(ISD::MUL, MVT::v2f64, Legal);
setOperationAction(ISD::LOAD , MVT::v2f64, Legal);
-setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand);
-setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand);
-setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand);
-setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
-setOperationAction(ISD::ConstantVec, MVT::v2i64, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand);
}
computeRegisterProperties();
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.320 -> 1.321
SelectionDAGISel.cpp updated: 1.196 -> 1.197
---
Log message:
implement basic support for INSERT_VECTOR_ELT.
---
Diffs of the changes: (+97 -73)
LegalizeDAG.cpp | 144 ---
SelectionDAGISel.cpp | 26 +
2 files changed, 97 insertions(+), 73 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.320
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.321
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.320 Sat Mar 18 18:52:58 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Mar 18 19:17:20 2006
@@ -729,62 +729,92 @@
case ISD::BUILD_VECTOR:
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
- default: assert(0 && "This action is not supported yet!");
- case TargetLowering::Custom:
-Tmp3 = TLI.LowerOperation(Result, DAG);
-if (Tmp3.Val) {
- Result = Tmp3;
+default: assert(0 && "This action is not supported yet!");
+case TargetLowering::Custom:
+ Tmp3 = TLI.LowerOperation(Result, DAG);
+ if (Tmp3.Val) {
+Result = Tmp3;
+break;
+ }
+ // FALLTHROUGH
+case TargetLowering::Expand: {
+ // We assume that built vectors are not legal, and will be immediately
+ // spilled to memory. If the values are all constants, turn this into a
+ // load from the constant pool.
+ bool isConstant = true;
+ for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
+ I != E; ++I) {
+if (!isa(I) && !isa(I) &&
+I->getOpcode() != ISD::UNDEF) {
+ isConstant = false;
break;
}
- // FALLTHROUGH
-case TargetLowering::Expand: {
- // We assume that built vectors are not legal, and will be
immediately
- // spilled to memory. If the values are all constants, turn this
into a
- // load from the constant pool.
- bool isConstant = true;
- for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
- I != E; ++I) {
-if (!isa(I) && !isa(I) &&
-I->getOpcode() != ISD::UNDEF) {
- isConstant = false;
- break;
-}
- }
-
- // Create a ConstantPacked, and put it in the constant pool.
- if (isConstant) {
-MVT::ValueType VT = Node->getValueType(0);
-const Type *OpNTy =
- MVT::getTypeForValueType(Node->getOperand(0).getValueType());
-std::vector CV;
-for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
- if (ConstantFPSDNode *V =
-dyn_cast(Node->getOperand(i))) {
-CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
- } else if (ConstantSDNode *V =
- dyn_cast(Node->getOperand(i))) {
-CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
- } else {
-assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
-CV.push_back(UndefValue::get(OpNTy));
- }
-}
-Constant *CP = ConstantPacked::get(CV);
-SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
-Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
- DAG.getSrcValue(NULL));
-break;
+ }
+
+ // Create a ConstantPacked, and put it in the constant pool.
+ if (isConstant) {
+MVT::ValueType VT = Node->getValueType(0);
+const Type *OpNTy =
+ MVT::getTypeForValueType(Node->getOperand(0).getValueType());
+std::vector CV;
+for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+ if (ConstantFPSDNode *V =
+dyn_cast(Node->getOperand(i))) {
+CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
+ } else if (ConstantSDNode *V =
+ dyn_cast(Node->getOperand(i))) {
+CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
+ } else {
+assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
+CV.push_back(UndefValue::get(OpNTy));
}
-
- // Otherwise, this isn't a constant entry. Allocate a sufficiently
- // aligned object on the stack, store each element into it, then load
- // the result as a vector.
- assert(0 && "Cannot lower variable BUILD_VECTOR yet!");
- abort();
- break;
}
+Constant *CP = ConstantPacked::get(CV);
+SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
+Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+ DAG.getSrcValu
[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll
Changes in directory llvm/test/Regression/CodeGen/Generic:
vector.ll updated: 1.2 -> 1.3
---
Log message:
add two new insert_element tests
---
Diffs of the changes: (+12 -0)
vector.ll | 12
1 files changed, 12 insertions(+)
Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.2
llvm/test/Regression/CodeGen/Generic/vector.ll:1.3
--- llvm/test/Regression/CodeGen/Generic/vector.ll:1.2 Sat Mar 18 18:20:03 2006
+++ llvm/test/Regression/CodeGen/Generic/vector.ll Sat Mar 18 19:27:04 2006
@@ -64,3 +64,15 @@
store %f4 %R, %f4 *%S
ret void
}
+
+void %test_constant_insert(%f4 *%S) {
+ %R = insertelement %f4 zeroinitializer, float 10.0, uint 0
+ store %f4 %R, %f4 *%S
+ ret void
+}
+
+void %test_variable_buildvector(float %F, %f4 *%S) {
+ %R = insertelement %f4 zeroinitializer, float %F, uint 0
+ store %f4 %R, %f4 *%S
+ ret void
+}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.127 -> 1.128
---
Log message:
fold insertelement(buildvector) -> buildvector if the inserted element # is
a constant. This implements test_constant_insert in CodeGen/Generic/vector.ll
---
Diffs of the changes: (+42 -0)
DAGCombiner.cpp | 42 ++
1 files changed, 42 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.127
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.128
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.127 Thu Mar 16 19:40:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Mar 18 19:27:56 2006
@@ -209,6 +209,8 @@
SDOperand visitBR_CC(SDNode *N);
SDOperand visitLOAD(SDNode *N);
SDOperand visitSTORE(SDNode *N);
+SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
+SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
@@ -640,6 +642,8 @@
case ISD::BR_CC: return visitBR_CC(N);
case ISD::LOAD: return visitLOAD(N);
case ISD::STORE: return visitSTORE(N);
+ case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
+ case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
}
return SDOperand();
}
@@ -2290,6 +2294,44 @@
return SDOperand();
}
+SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
+ SDOperand InVec = N->getOperand(0);
+ SDOperand InVal = N->getOperand(1);
+ SDOperand EltNo = N->getOperand(2);
+
+ // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
+ // vector with the inserted element.
+ if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa(EltNo)) {
+unsigned Elt = cast(EltNo)->getValue();
+std::vector Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+if (Elt < Ops.size())
+ Ops[Elt] = InVal;
+return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops);
+ }
+
+ return SDOperand();
+}
+
+SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
+ SDOperand InVec = N->getOperand(0);
+ SDOperand InVal = N->getOperand(1);
+ SDOperand EltNo = N->getOperand(2);
+ SDOperand NumElts = N->getOperand(3);
+ SDOperand EltType = N->getOperand(4);
+
+ // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
+ // vector with the inserted element.
+ if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa(EltNo)) {
+unsigned Elt = cast(EltNo)->getValue();
+std::vector Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+if (Elt < Ops.size()-2)
+ Ops[Elt] = InVal;
+return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops);
+ }
+
+ return SDOperand();
+}
+
SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand
N2){
assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC
node!");
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.321 -> 1.322
---
Log message:
Implement expand of BUILD_VECTOR containing variable elements.
This implements CodeGen/Generic/vector.ll:test_variable_buildvector
---
Diffs of the changes: (+32 -2)
LegalizeDAG.cpp | 34 --
1 files changed, 32 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.321
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.322
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.321 Sat Mar 18 19:17:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Mar 18 22:18:56 2006
@@ -779,8 +779,38 @@
// Otherwise, this isn't a constant entry. Allocate a sufficiently
// aligned object on the stack, store each element into it, then load
// the result as a vector.
- assert(0 && "Cannot lower variable BUILD_VECTOR yet!");
- abort();
+ MVT::ValueType VT = Node->getValueType(0);
+ // Create the stack frame object.
+ MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
+ unsigned ByteSize = MVT::getSizeInBits(VT)/8;
+ int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
+ SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
+
+ // Emit a store of each element to the stack slot.
+ std::vector Stores;
+ bool isLittleEndian = TLI.isLittleEndian();
+ unsigned TypeByteSize =
+MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
+ unsigned VectorSize = MVT::getSizeInBits(VT)/8;
+ // Store (in the right endianness) the elements to memory.
+ for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+unsigned Offset;
+if (isLittleEndian)
+ Offset = TypeByteSize*i;
+else
+ Offset = TypeByteSize*(e-i-1);
+
+SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
+Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
+
+Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other,
DAG.getEntryNode(),
+ Node->getOperand(i), Idx,
+ DAG.getSrcValue(NULL)));
+ }
+ SDOperand StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+
+ // Result is a load from the stack slot.
+ Result = DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
break;
}
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.td updated: 1.187 -> 1.188
---
Log message:
we don't use lmw/stmw. When we want them they are easy enough to add
---
Diffs of the changes: (+0 -6)
PPCInstrInfo.td |6 --
1 files changed, 6 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.187
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.188
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.187 Fri Mar 17 16:41:37 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sat Mar 18 22:33:37 2006
@@ -301,9 +301,6 @@
def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
"lhz $rD, $src", LdStGeneral,
[(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
-def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
- "lmw $rD, $disp($rA)", LdStLMW,
- []>;
def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
"lwz $rD, $src", LdStGeneral,
[(set GPRC:$rD, (load iaddr:$src))]>;
@@ -343,9 +340,6 @@
[(set GPRC:$rD, imm16Shifted:$imm)]>;
}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
-def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
- "stmw $rS, $disp($rA)", LdStLMW,
- []>;
def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
"stb $rS, $src", LdStGeneral,
[(truncstore GPRC:$rS, iaddr:$src, i8)]>;
___
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll
Changes in directory llvm/test/Regression/CodeGen/Generic:
vector.ll updated: 1.3 -> 1.4
---
Log message:
add another testcase, explicitly check stuff works with G5 and G3 codegen on
PPC.
---
Diffs of the changes: (+17 -1)
vector.ll | 18 +-
1 files changed, 17 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.3
llvm/test/Regression/CodeGen/Generic/vector.ll:1.4
--- llvm/test/Regression/CodeGen/Generic/vector.ll:1.3 Sat Mar 18 19:27:04 2006
+++ llvm/test/Regression/CodeGen/Generic/vector.ll Sat Mar 18 22:45:11 2006
@@ -1,5 +1,7 @@
-; RUN: llvm-as < %s | llc
; Test that vectors are scalarized/lowered correctly.
+; RUN: llvm-as < %s | llc &&
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 &&
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3
%f1 = type <1 x float>
%f2 = type <2 x float>
@@ -76,3 +78,17 @@
store %f4 %R, %f4 *%S
ret void
}
+
+;;; TEST IMPORTANT IDIOMS
+
+void %splat(%f4* %P, %f4* %Q, float %X) {
+%tmp = insertelement %f4 undef, float %X, uint 0
+%tmp2 = insertelement %f4 %tmp, float %X, uint 1
+%tmp4 = insertelement %f4 %tmp2, float %X, uint 2
+%tmp6 = insertelement %f4 %tmp4, float %X, uint 3
+ %q = load %f4* %Q
+ %R = add %f4 %q, %tmp6
+store %f4 %R, %f4* %P
+ret void
+}
+
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h ValueTypes.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.114 -> 1.115
ValueTypes.h updated: 1.22 -> 1.23
---
Log message:
improve comments, add a new MVT::getVectorBaseType method.
---
Diffs of the changes: (+71 -40)
SelectionDAGNodes.h | 14 ---
ValueTypes.h| 97 +---
2 files changed, 71 insertions(+), 40 deletions(-)
Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.114
llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.115
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.114 Sat Mar 18 18:52:25 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Sat Mar 18 23:26:45 2006
@@ -166,7 +166,12 @@
/// their last two operands.
VADD, VSUB, VMUL, VSDIV, VUDIV,
VAND, VOR, VXOR,
-
+
+/// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
+/// scalar value into the low element of the resultant vector type. The
top
+/// elements of the vector are undefined.
+SCALAR_TO_VECTOR,
+
// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
producing
// an unsigned/signed value of type i[2*n], then return the top part.
MULHU, MULHS,
@@ -281,10 +286,9 @@
// integer result type.
// ZEXTLOAD loads the integer operand and zero extends it to a larger
// integer result type.
-// EXTLOAD is used for two things: floating point extending loads, and
-// integer extending loads where it doesn't matter what the high
-// bits are set to. The code generator is allowed to codegen this
-// into whichever operation is more efficient.
+// EXTLOAD is used for three things: floating point extending loads,
+// integer extending loads [the top bits are undefined], and
vector
+// extending loads [load into low elt].
EXTLOAD, SEXTLOAD, ZEXTLOAD,
// TRUNCSTORE - This operators truncates (for integer) or rounds (for FP) a
Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.22
llvm/include/llvm/CodeGen/ValueTypes.h:1.23
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.22 Thu Mar 16 13:42:44 2006
+++ llvm/include/llvm/CodeGen/ValueTypes.h Sat Mar 18 23:26:45 2006
@@ -66,20 +66,55 @@
LAST_VALUETYPE = 24// This always remains at the end of the list.
};
+ /// MVT::isInteger - Return true if this is a simple integer, or a packed
+ /// vector integer type.
static inline bool isInteger(ValueType VT) {
return (VT >= i1 && VT <= i128) || (VT >= v8i8 && VT <= v2i64);
}
+
+ /// MVT::isFloatingPoint - Return true if this is a simple FP, or a packed
+ /// vector FP type.
static inline bool isFloatingPoint(ValueType VT) {
return (VT >= f32 && VT <= f128) || (VT >= v4f32 && VT <= v2f64);
}
+
+ /// MVT::isVector - Return true if this is a packed vector type (i.e. not
+ /// MVT::Vector).
static inline bool isVector(ValueType VT) {
-return (VT >= FIRST_VECTOR_VALUETYPE &&
-VT <= LAST_VECTOR_VALUETYPE);
+return VT >= FIRST_VECTOR_VALUETYPE && VT <= LAST_VECTOR_VALUETYPE;
}
- /// getVectorType - Returns the ValueType that represents a vector
NumElements
- /// in length, where each element is of type VT. If there is no ValueType
- /// that represents this vector, a ValueType of Other is returned.
+ /// MVT::getSizeInBits - Return the size of the specified value type in bits.
+ ///
+ static inline unsigned getSizeInBits(ValueType VT) {
+switch (VT) {
+default: assert(0 && "ValueType has no known size!");
+case MVT::i1 : return 1;
+case MVT::i8 : return 8;
+case MVT::i16 : return 16;
+case MVT::f32 :
+case MVT::i32 : return 32;
+case MVT::f64 :
+case MVT::i64 :
+case MVT::v8i8:
+case MVT::v4i16:
+case MVT::v2i32:
+case MVT::v2f32: return 64;
+case MVT::f80 : return 80;
+case MVT::f128:
+case MVT::i128:
+case MVT::v16i8:
+case MVT::v8i16:
+case MVT::v4i32:
+case MVT::v2i64:
+case MVT::v4f32:
+case MVT::v2f64: return 128;
+}
+ }
+
+ /// MVT::getVectorType - Returns the ValueType that represents a vector
+ /// NumElements in length, where each element is of type VT. If there is no
+ /// ValueType that represents this vector, a ValueType of Other is returned.
///
static inline ValueType getVectorType(ValueType VT, unsigned NumElements) {
switch (VT) {
@@ -88,19 +123,19 @@
case MVT::i8:
if (NumElements == 8) return MVT::v8i8;
if (NumElements == 16) return MVT::v16i8;
- break;
+break;
case MVT::i16:
if (NumElements == 4) return MVT::v4i16;
if (NumElements == 8) return MVT::v8i16;
- break;
+break;
case MVT::i32:
if (NumElements == 2) return MVT::v2i32;
if (NumElements == 4) return MV
[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.74 -> 1.75
---
Log message:
notes
---
Diffs of the changes: (+16 -0)
README.txt | 16
1 files changed, 16 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.74
llvm/lib/Target/PowerPC/README.txt:1.75
--- llvm/lib/Target/PowerPC/README.txt:1.74 Thu Mar 16 19:40:33 2006
+++ llvm/lib/Target/PowerPC/README.txt Sat Mar 18 23:33:30 2006
@@ -506,6 +506,7 @@
registers, to generate better spill code.
===-===
+
int foo(int N, int ***W, int **TK, int X) {
int t, i;
@@ -518,5 +519,20 @@
We generate relatively atrocious code for this loop compared to gcc.
+===-===
+
+Altivec support. The first should be a single lvx from the constant pool, the
+second should be a xor/stvx:
+void foo(void) {
+ int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
+ bar (x);
+}
+
+#include
+void foo(void) {
+ int x[8] __attribute__((aligned(128)));
+ memset (x, 0, sizeof (x));
+ bar (x);
+}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.188 -> 1.189 --- Log message: minor fixes --- Diffs of the changes: (+2 -2) PPCInstrInfo.td |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.188 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.189 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.188 Sat Mar 18 22:33:37 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sat Mar 18 23:43:01 2006 @@ -216,9 +216,9 @@ } def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", [(set GPRC:$rD, (undef))]>; -def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8", +def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8", [(set F8RC:$rD, (undef))]>; -def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4", +def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4", [(set F4RC:$rD, (undef))]>; // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.322 -> 1.323
---
Log message:
Don't bother storing undef elements of BUILD_VECTOR's
---
Diffs of the changes: (+9 -1)
LegalizeDAG.cpp | 10 +-
1 files changed, 9 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.322
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.323
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.322 Sat Mar 18 22:18:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Mar 18 23:46:04 2006
@@ -794,6 +794,9 @@
unsigned VectorSize = MVT::getSizeInBits(VT)/8;
// Store (in the right endianness) the elements to memory.
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+// Ignore undef elements.
+if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
+
unsigned Offset;
if (isLittleEndian)
Offset = TypeByteSize*i;
@@ -807,7 +810,12 @@
Node->getOperand(i), Idx,
DAG.getSrcValue(NULL)));
}
- SDOperand StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+
+ SDOperand StoreChain;
+ if (!Stores.empty())// Not all undef elements?
+StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+ else
+StoreChain = DAG.getEntryNode();
// Result is a load from the stack slot.
Result = DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
___
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll
Changes in directory llvm/test/Regression/CodeGen/Generic:
vector.ll updated: 1.4 -> 1.5
---
Log message:
add a new testcase. This insertelement should be a noop on SSE.
---
Diffs of the changes: (+6 -0)
vector.ll |6 ++
1 files changed, 6 insertions(+)
Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.4
llvm/test/Regression/CodeGen/Generic/vector.ll:1.5
--- llvm/test/Regression/CodeGen/Generic/vector.ll:1.4 Sat Mar 18 22:45:11 2006
+++ llvm/test/Regression/CodeGen/Generic/vector.ll Sat Mar 18 23:46:51 2006
@@ -79,6 +79,12 @@
ret void
}
+void %test_scalar_to_vector(float %F, %f4 *%S) {
+ %R = insertelement %f4 undef, float %F, uint 0 ;; R = scalar_to_vector F
+ store %f4 %R, %f4 *%S
+ ret void
+}
+
;;; TEST IMPORTANT IDIOMS
void %splat(%f4* %P, %f4* %Q, float %X) {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86: README.txt updated: 1.66 -> 1.67 --- Log message: Remember which tests are hurt by LSR. --- Diffs of the changes: (+4 -0) README.txt |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.66 llvm/lib/Target/X86/README.txt:1.67 --- llvm/lib/Target/X86/README.txt:1.66 Thu Mar 16 16:44:22 2006 +++ llvm/lib/Target/X86/README.txt Sun Mar 19 00:08:11 2006 @@ -629,3 +629,7 @@ dependent LICM pass or 2) makeing SelectDAG represent the whole function. //===-===// + +The following tests perform worse with LSR: + +lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp
Changes in directory llvm/lib/Target/X86:
X86TargetMachine.cpp updated: 1.108 -> 1.109
---
Log message:
Turning on LSR by default
---
Diffs of the changes: (+2 -6)
X86TargetMachine.cpp |8 ++--
1 files changed, 2 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.108
llvm/lib/Target/X86/X86TargetMachine.cpp:1.109
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.108 Thu Mar 16 15:47:42 2006
+++ llvm/lib/Target/X86/X86TargetMachine.cppSun Mar 19 00:08:49 2006
@@ -38,9 +38,6 @@
cl::desc("Disable the X86 asm printer, for use "
"when profiling the code generator."));
- cl::opt EnableX86LSR("enable-x86-lsr", cl::Hidden,
- cl::desc("Enable the X86 loop strength reduction
"
- "pass."));
// Register the target.
RegisterTarget X("x86", " IA-32 (Pentium and above)");
}
@@ -97,7 +94,7 @@
FileType != TargetMachine::ObjectFile) return true;
// Run loop strength reduction before anything else.
- if (EnableX86LSR) PM.add(createLoopStrengthReducePass(&TLInfo));
+ PM.add(createLoopStrengthReducePass(&TLInfo));
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
@@ -165,8 +162,7 @@
TM.setRelocationModel(Reloc::Static);
// Run loop strength reduction before anything else.
- if (EnableX86LSR)
-PM.add(createLoopStrengthReducePass(TM.getTargetLowering()));
+ PM.add(createLoopStrengthReducePass(TM.getTargetLowering()));
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
___
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[llvm-commits] CVS: llvm/lib/Target/README.txt
Changes in directory llvm/lib/Target: README.txt updated: 1.22 -> 1.23 --- Log message: Remind us of exit value substitution --- Diffs of the changes: (+3 -0) README.txt |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.22 llvm/lib/Target/README.txt:1.23 --- llvm/lib/Target/README.txt:1.22 Thu Mar 16 19:40:33 2006 +++ llvm/lib/Target/README.txt Sun Mar 19 00:09:23 2006 @@ -125,3 +125,6 @@ 1. The instcombiner should eliminate the type conversions. 2. The X86 backend should turn this into a rotate by one bit. +//===-===// + +Add LSR exit value substitution. It'll probably be a win for Ackermann, etc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.189 -> 1.190 --- Log message: add support for vector undef --- Diffs of the changes: (+4 -0) PPCInstrInfo.td |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.189 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.190 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.189 Sat Mar 18 23:43:01 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sun Mar 19 00:10:09 2006 @@ -220,6 +220,8 @@ [(set F8RC:$rD, (undef))]>; def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4", [(set F4RC:$rD, (undef))]>; +def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC", + [(set VRRC:$rD, (v4f32 (undef)))]>; // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the // scheduler into a branch sequence. @@ -1148,6 +1150,8 @@ def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst), (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>; +def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>; + // Same as above, but using a temporary. FIXME: implement temporaries :) /* ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.200 -> 1.201 --- Log message: Switch x86 llc-beta back to -enable-x86-fastcc now that LSR is on by default --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.200 llvm-test/Makefile.programs:1.201 --- llvm-test/Makefile.programs:1.200 Thu Mar 9 20:18:30 2006 +++ llvm-test/Makefile.programs Sun Mar 19 00:11:09 2006 @@ -197,7 +197,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -enable-x86-lsr +LLCBETAOPTION := -enable-x86-fastcc endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.98 -> 1.99 --- Log message: PPC doesn't have SCALAR_TO_VECTOR --- Diffs of the changes: (+3 -0) PPCISelLowering.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.98 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.99 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.98Sat Mar 18 19:13:28 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sun Mar 19 00:17:19 2006 @@ -183,6 +183,9 @@ // the ones we do! setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand); + +setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Expand); +setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Expand); } setSetCCResultContents(ZeroOrOneSetCCResult); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.323 -> 1.324
SelectionDAG.cpp updated: 1.274 -> 1.275
---
Log message:
Add SCALAR_TO_VECTOR support
---
Diffs of the changes: (+154 -90)
LegalizeDAG.cpp | 227 +--
SelectionDAG.cpp | 17 +++-
2 files changed, 154 insertions(+), 90 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.323
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.324
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.323 Sat Mar 18 23:46:04 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Mar 19 00:31:19 2006
@@ -160,12 +160,15 @@
void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
+ SDOperand CreateStackTemporary(MVT::ValueType VT);
+
SDOperand ExpandLibCall(const char *Name, SDNode *Node,
SDOperand &Hi);
SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
SDOperand Source);
SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
+ SDOperand ExpandBUILD_VECTOR(SDNode *Node);
SDOperand ExpandLegalINT_TO_FP(bool isSigned,
SDOperand LegalOp,
MVT::ValueType DestVT);
@@ -737,91 +740,10 @@
break;
}
// FALLTHROUGH
-case TargetLowering::Expand: {
- // We assume that built vectors are not legal, and will be immediately
- // spilled to memory. If the values are all constants, turn this into a
- // load from the constant pool.
- bool isConstant = true;
- for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
- I != E; ++I) {
-if (!isa(I) && !isa(I) &&
-I->getOpcode() != ISD::UNDEF) {
- isConstant = false;
- break;
-}
- }
-
- // Create a ConstantPacked, and put it in the constant pool.
- if (isConstant) {
-MVT::ValueType VT = Node->getValueType(0);
-const Type *OpNTy =
- MVT::getTypeForValueType(Node->getOperand(0).getValueType());
-std::vector CV;
-for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
- if (ConstantFPSDNode *V =
-dyn_cast(Node->getOperand(i))) {
-CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
- } else if (ConstantSDNode *V =
- dyn_cast(Node->getOperand(i))) {
-CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
- } else {
-assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
-CV.push_back(UndefValue::get(OpNTy));
- }
-}
-Constant *CP = ConstantPacked::get(CV);
-SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
-Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
- DAG.getSrcValue(NULL));
-break;
- }
-
- // Otherwise, this isn't a constant entry. Allocate a sufficiently
- // aligned object on the stack, store each element into it, then load
- // the result as a vector.
- MVT::ValueType VT = Node->getValueType(0);
- // Create the stack frame object.
- MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
- unsigned ByteSize = MVT::getSizeInBits(VT)/8;
- int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
- SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
-
- // Emit a store of each element to the stack slot.
- std::vector Stores;
- bool isLittleEndian = TLI.isLittleEndian();
- unsigned TypeByteSize =
-MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
- unsigned VectorSize = MVT::getSizeInBits(VT)/8;
- // Store (in the right endianness) the elements to memory.
- for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
-// Ignore undef elements.
-if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
-
-unsigned Offset;
-if (isLittleEndian)
- Offset = TypeByteSize*i;
-else
- Offset = TypeByteSize*(e-i-1);
-
-SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
-Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
-
-Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other,
DAG.getEntryNode(),
- Node->getOperand(i), Idx,
- DAG.getSrcValue(NULL)));
- }
-
- SDOperand StoreChain;
- if (!Stores.empty())// Not all undef elements?
-StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
- else
-StoreChain = DAG.getEntryNode();
-
- // Result is a load from the stack slot.
- Result = DAG.getLoad(VT,
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.324 -> 1.325
---
Log message:
Allow SCALAR_TO_VECTOR to be custom lowered.
---
Diffs of the changes: (+9 -0)
LegalizeDAG.cpp |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.324
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.325
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.324 Sun Mar 19 00:31:19 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Mar 19 00:47:21 2006
@@ -783,9 +783,18 @@
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
break;
+case TargetLowering::Custom:
+ Tmp3 = TLI.LowerOperation(Result, DAG);
+ if (Tmp3.Val) {
+Result = Tmp3;
+break;
+ }
+ // FALLTHROUGH
case TargetLowering::Expand: {
// If the target doesn't support this, store the value to a temporary
// stack slot, then EXTLOAD the vector back out.
+ // TODO: If a target doesn't support this, create a stack slot for the
+ // whole vector, then store into it, then load the whole vector.
SDOperand StackPtr =
CreateStackTemporary(Node->getOperand(0).getValueType());
SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.99 -> 1.100
PPCISelLowering.h updated: 1.26 -> 1.27
PPCInstrInfo.td updated: 1.190 -> 1.191
---
Log message:
Custom lower SCALAR_TO_VECTOR into lve*x.
---
Diffs of the changes: (+37 -9)
PPCISelLowering.cpp | 20 ++--
PPCISelLowering.h |8
PPCInstrInfo.td | 18 +++---
3 files changed, 37 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.99
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.100
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.99Sun Mar 19 00:17:19 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sun Mar 19 00:55:52 2006
@@ -184,8 +184,8 @@
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
-setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Expand);
-setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Expand);
+setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
+setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
}
setSetCCResultContents(ZeroOrOneSetCCResult);
@@ -208,6 +208,7 @@
case PPCISD::STFIWX:return "PPCISD::STFIWX";
case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
+ case PPCISD::LVE_X: return "PPCISD::LVE_X";
case PPCISD::Hi:return "PPCISD::Hi";
case PPCISD::Lo:return "PPCISD::Lo";
case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
@@ -550,6 +551,21 @@
}
return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
+ case ISD::SCALAR_TO_VECTOR: {
+// Create a stack slot that is 16-byte aligned.
+MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
+int FrameIdx = FrameInfo->CreateStackObject(16, 16);
+SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
+
+// Store the input value into Value#0 of the stack slot.
+unsigned InSize = MVT::getSizeInBits(Op.getOperand(0).getValueType())/8;
+FIdx = DAG.getNode(ISD::ADD, MVT::i32, FIdx,
+ DAG.getConstant(16-InSize, MVT::i32));
+SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+ Op.getOperand(0),
FIdx,DAG.getSrcValue(NULL));
+return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx,
+ DAG.getSrcValue(NULL));
+ }
}
return SDOperand();
}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.26
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.27
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.26 Mon Mar 13 17:20:37 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Sun Mar 19 00:55:52 2006
@@ -48,6 +48,14 @@
// three v4f32 operands and producing a v4f32 result.
VMADDFP, VNMSUBFP,
+ /// LVE_X - The PPC LVE*X instructions. The size of the element loaded
is
+ /// the size of the element type of the vector result. The element
loaded
+ /// depends on the alignment of the input pointer.
+ ///
+ /// The first operand is a token chain, the second is the address to load
+ /// the third is the SRCVALUE node.
+ LVE_X,
+
/// Hi/Lo - These represent the high and low 16-bit parts of a global
/// address respectively. These nodes have two operands, the first of
/// which must be a TargetGlobalAddress, and the second of which must be
a
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.190
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.191
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.190 Sun Mar 19 00:10:09 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sun Mar 19 00:55:52 2006
@@ -45,6 +45,8 @@
def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
+def PPClve_x: SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
+
// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
// amounts. These nodes are generated by the multi-precision shift code.
def PPCsrl: SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
@@ -451,15 +453,15 @@
def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
"ldx $rD, $src", LdStLD,
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
-def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
- "lvebx $vD, $base, $rA", LdStGeneral,
- []>;
-def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
- "lvehx $vD, $base, $rA", LdStGeneral,
+def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
+ "lvebx $vD, $src", LdStGeneral
[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp
Changes in directory llvm/utils/TableGen: CodeGenTarget.cpp updated: 1.56 -> 1.57 --- Log message: getEnumName() missed v8i8, v4i16, and v2i32 types --- Diffs of the changes: (+3 -0) CodeGenTarget.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.56 llvm/utils/TableGen/CodeGenTarget.cpp:1.57 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.56 Tue Feb 28 19:10:52 2006 +++ llvm/utils/TableGen/CodeGenTarget.cpp Sun Mar 19 01:57:34 2006 @@ -76,6 +76,9 @@ case MVT::f128: return "f128"; case MVT::Flag: return "Flag"; case MVT::isVoid:return "isVoid"; + case MVT::v8i8: return "v8i8"; + case MVT::v4i16: return "v4i16"; + case MVT::v2i32: return "v2i32"; case MVT::v16i8: return "v16i8"; case MVT::v8i16: return "v8i16"; case MVT::v4i32: return "v4i32"; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
