[llvm-commits] CVS: llvm/docs/Projects.html
Changes in directory llvm/docs: Projects.html updated: 1.21 -> 1.22 --- Log message: Fix a typo. --- Diffs of the changes: (+2 -2) Projects.html |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/docs/Projects.html diff -u llvm/docs/Projects.html:1.21 llvm/docs/Projects.html:1.22 --- llvm/docs/Projects.html:1.21Thu Mar 16 10:14:59 2006 +++ llvm/docs/Projects.html Fri Mar 17 02:04:25 2006 @@ -105,7 +105,7 @@ it specifies a relative path to the llvm/autoconf directory. LLVM_CONFIG_PROJECT. Just leave this alone. AC_CONFIG_SRCDIR. Specify a path to a file name that identifies -your project; or just leave it at Makefile.config.in +your project; or just leave it at Makefile.common.in AC_CONFIG_FILES. Do not change. AC_CONFIG_MAKEFILE. Use one of these macros for each Makefile that your project uses. This macro arranges for your makefiles to be copied @@ -453,7 +453,7 @@ mailto:[EMAIL PROTECTED]">John Criswell http://llvm.org";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/03/16 16:14:59 $ + Last modified: $Date: 2006/03/17 08:04:25 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.109 -> 1.110
---
Log message:
Disable x86 fastcc from passing args in registers
---
Diffs of the changes: (+18 -6)
X86ISelLowering.cpp | 24 ++--
1 files changed, 18 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.109
llvm/lib/Target/X86/X86ISelLowering.cpp:1.110
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.109 Thu Mar 16 23:10:20 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 17 11:27:47 2006
@@ -639,12 +639,24 @@
return VReg;
}
-enum {
- // FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments
- // to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and
- // EDX". Anything more is illegal.
- FASTCC_NUM_INT_ARGS_INREGS = 2
-};
+// FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments
+// to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and
+// EDX". Anything more is illegal.
+//
+// FIXME: The linscan register allocator currently has problem with
+// coallescing. At the time of this writing, whenever it decides to coallesce
+// a physreg with a virtreg, this increases the size of the physreg's live
+// range, and the live range cannot ever be reduced. This causes problems if
+// too many physregs are coalleced with virtregs, which can cause the register
+// allocator to wedge itself.
+//
+// This code triggers this problem more often if we pass args in registers,
+// so disable it until this is fixed.
+//
+// NOTE: this isn't marked const, so that GCC doesn't emit annoying warnings
+// about code being dead.
+//
+static unsigned FASTCC_NUM_INT_ARGS_INREGS = 0;
std::vector
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/NightlyTest.pl
Changes in directory llvm/utils:
NightlyTest.pl updated: 1.104 -> 1.105
---
Log message:
Use the tag instead of tag to get code/file/warning lists to
wrap but also still be in a fixed-width font.
---
Diffs of the changes: (+1 -1)
NightlyTest.pl |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/utils/NightlyTest.pl
diff -u llvm/utils/NightlyTest.pl:1.104 llvm/utils/NightlyTest.pl:1.105
--- llvm/utils/NightlyTest.pl:1.104 Wed Feb 8 03:08:06 2006
+++ llvm/utils/NightlyTest.pl Fri Mar 17 11:43:01 2006
@@ -151,7 +151,7 @@
sub AddPreTag { # Add pre tags around nonempty list, or convert to "none"
$_ = shift;
- if (length) { return "$_"; } else { "none"; }
+ if (length) { return "$_"; } else { "none"; }
}
sub ChangeDir { # directory, logical name
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CFrontend/2006-03-17-KnRMismatch.c
Changes in directory llvm/test/Regression/CFrontend:
2006-03-17-KnRMismatch.c added (r1.1)
---
Log message:
new testcase that broke the new f.e.
---
Diffs of the changes: (+8 -0)
2006-03-17-KnRMismatch.c |8
1 files changed, 8 insertions(+)
Index: llvm/test/Regression/CFrontend/2006-03-17-KnRMismatch.c
diff -c /dev/null llvm/test/Regression/CFrontend/2006-03-17-KnRMismatch.c:1.1
*** /dev/null Fri Mar 17 12:01:27 2006
--- llvm/test/Regression/CFrontend/2006-03-17-KnRMismatch.c Fri Mar 17
12:01:17 2006
***
*** 0
--- 1,8
+ // RUN: %llvmgcc %s -S -o -
+
+ void regnode(int op);
+
+ void regnode(op)
+ char op;
+ {
+ }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
loop-strength-reduce.ll added (r1.1)
---
Log message:
Add a lsr common loop invariant hoisting test case
---
Diffs of the changes: (+28 -0)
loop-strength-reduce.ll | 28
1 files changed, 28 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll:1.1
*** /dev/null Fri Mar 17 13:46:04 2006
--- llvm/test/Regression/CodeGen/X86/loop-strength-reduce.llFri Mar 17
13:45:54 2006
***
*** 0
--- 1,28
+ ; RUN: llvm-as < %s | llc -march=x86 -enable-x86-lsr | grep 'A(' | wc -l |
grep 1
+ ;
+ ; Make sure the common loop invariant _A(reg) is hoisted up to preheader.
+
+ %A = internal global [16 x [16 x int]] zeroinitializer, align 32
+
+ void %test(int %row, int %N) {
+ entry:
+ %N = cast int %N to uint
+ %tmp5 = setgt int %N, 0
+ br bool %tmp5, label %cond_true, label %return
+
+ cond_true:
+ %indvar = phi uint [ 0, %entry ], [ %indvar.next, %cond_true ]
+ %i.0.0 = cast uint %indvar to int
+ %tmp2 = add int %i.0.0, 1
+ %tmp = getelementptr [16 x [16 x int]]* %A, int 0, int %row, int %tmp2
+ store int 4, int* %tmp
+ %tmp5 = add int %i.0.0, 2
+ %tmp7 = getelementptr [16 x [16 x int]]* %A, int 0, int %row, int %tmp5
+ store int 5, int* %tmp7
+ %indvar.next = add uint %indvar, 1
+ %exitcond = seteq uint %indvar.next, %N
+ br bool %exitcond, label %return, label %cond_true
+
+ return:
+ ret void
+ }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopStrengthReduce.cpp updated: 1.77 -> 1.78
---
Log message:
Allow users of iv / stride to be rewritten with expression that is a multiply
of a smaller stride even if they have a common loop invariant expression part.
---
Diffs of the changes: (+83 -41)
LoopStrengthReduce.cpp | 124 -
1 files changed, 83 insertions(+), 41 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.77
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.78
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.77 Thu Mar 16
15:53:05 2006
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Fri Mar 17 13:52:23 2006
@@ -180,6 +180,8 @@
void OptimizeIndvars(Loop *L);
+unsigned CheckForIVReuse(const SCEVHandle &Stride, IVExpr &IV);
+
void StrengthReduceStridedIVUsers(const SCEVHandle &Stride,
IVUsersOfOneStride &Uses,
Loop *L, bool isOnlyStride);
@@ -858,6 +860,44 @@
}
+/// CheckForIVReuse - Returns the multiple if the stride is the multiple
+/// of a previous stride and it is a legal value for the target addressing
+/// mode scale component. This allows the users of this stride to be rewritten
+/// as prev iv * factor. It returns 1 if no reuse is possible.
+unsigned LoopStrengthReduce::CheckForIVReuse(const SCEVHandle &Stride,
+ IVExpr &IV) {
+ if (!TLI)
+return 1;
+
+ if (SCEVConstant *SC = dyn_cast(Stride)) {
+unsigned SInt = SC->getValue()->getRawValue();
+if (SInt == 1)
+ return 1;
+
+for (TargetLowering::legal_am_scale_iterator
+ I = TLI->legal_am_scale_begin(), E = TLI->legal_am_scale_end();
+ I != E; ++I) {
+ unsigned Scale = *I;
+ if (SInt >= Scale && (SInt % Scale) != 0)
+continue;
+ std::map::iterator SI =
+IVsByStride.find(SCEVUnknown::getIntegerSCEV(SInt/Scale,
Type::UIntTy));
+ if (SI == IVsByStride.end())
+continue;
+ for (std::vector::iterator II = SI->second.IVs.begin(),
+ IE = SI->second.IVs.end(); II != IE; ++II)
+// FIXME: Only handle base == 0 for now.
+if (isZero(II->Base)) {
+ IV = *II;
+ return Scale;
+}
+}
+ }
+
+ return 1;
+}
+
+
/// StrengthReduceStridedIVUsers - Strength reduce all of the users of a single
/// stride of IV. All of the users may have different starting values, and
this
/// may not be the only stride (we know it is if isOnlyStride is true).
@@ -883,7 +923,19 @@
assert(UsersToProcess.back().Base->isLoopInvariant(L) &&
"Base value is not loop invariant!");
}
-
+
+ // Check if it is possible to reuse a IV with stride that is factor of this
+ // stride. And the multiple is a number that can be encoded in the scale
+ // field of the target addressing mode.
+ PHINode *NewPHI = NULL;
+ Value *IncV = NULL;
+ IVExpr ReuseIV(Stride, NULL, NULL);
+ unsigned RewriteFactor = CheckForIVReuse(Stride, ReuseIV);
+ if (RewriteFactor > 1) {
+NewPHI = ReuseIV.PHI;
+IncV = ReuseIV.IncV;
+ }
+
// We now have a whole bunch of uses of like-strided induction variables, but
// they might all have different bases. We want to emit one PHI node for
this
// stride which we fold as many common expressions (between the IVs) into as
@@ -935,55 +987,26 @@
BasicBlock *LatchBlock = L->getLoopLatch();
- unsigned RewriteFactor = 1;
- PHINode *NewPHI = NULL;
- Value *IncV = NULL;
- // FIXME: Only handle base == 0 for now.
- if (TLI && isZero(CommonExprs)) {
-if (SCEVConstant *SC = dyn_cast(Stride)) {
- unsigned SInt = SC->getValue()->getRawValue();
- for (TargetLowering::legal_am_scale_iterator
- I = TLI->legal_am_scale_begin(), E = TLI->legal_am_scale_end();
- I != E; ++I) {
-unsigned Scale = *I;
-if ((SInt % Scale) != 0)
- continue;
-std::map::iterator SI =
-IVsByStride.find(SCEVUnknown::getIntegerSCEV(SInt/Scale,
Type::UIntTy));
-if (SI == IVsByStride.end())
- continue;
-for (std::vector::iterator II = SI->second.IVs.begin(),
- IE = SI->second.IVs.end(); II != IE; ++II)
- if (isZero(II->Base)) {
-RewriteFactor = Scale;
-NewPHI = II->PHI;
-IncV = II->IncV;
-break;
- }
-if (RewriteFactor != 1)
- break;
- }
-}
- }
-
const Type *ReplacedTy = CommonExprs->getType();
+
+ // Emit the initial base value into the loop preheader.
+ Value *CommonBaseV
+= PreheaderRewriter.expandCodeFor(CommonExprs, PreInsertPt,
+ ReplacedTy);
+
if (RewriteFactor == 1) {
// Create a new Phi for this base, and stick it in the loop he
[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.111 -> 1.112 --- Log message: add a couple of enum values --- Diffs of the changes: (+12 -1) SelectionDAGNodes.h | 13 - 1 files changed, 12 insertions(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.111 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.112 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.111 Thu Mar 16 19:40:33 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Fri Mar 17 13:53:41 2006 @@ -146,7 +146,12 @@ // are both floating point. X and the result must have the same type. // FCOPYSIGN(f32, f64) is allowed. FCOPYSIGN, + +/// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR (a legal packed +/// type) with the element at IDX replaced with VAL. +INSERT_VECTOR_ELT, +// BINOP(LHS, RHS, COUNT,TYPE) // Simple abstract vector operators. Unlike the integer and floating point // binary operators, these nodes also take two additional operands: // a constant element count, and a value type node indicating the type of @@ -156,6 +161,12 @@ VADD, VSUB, VMUL, VSDIV, VUDIV, VAND, VOR, VXOR, +/// VINSERT_VECTOR_ELT(VECTOR, VAL, IDX, COUNT,TYPE) - Given a vector +/// VECTOR, an element ELEMENT, and a (potentially variable) index IDX, +/// return an vector with the specified element of VECTOR replaced with VAL. +/// COUNT and TYPE specify the type of vector, as is standard for V* nodes. +VINSERT_VECTOR_ELT, + // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing // an unsigned/signed value of type i[2*n], then return the top part. MULHU, MULHS, @@ -168,7 +179,7 @@ // Counting operators CTTZ, CTLZ, CTPOP, -// Select +// Select(COND, TRUEVAL, FALSEVAL) SELECT, // Select with condition operator - This selects between a true value and ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.271 -> 1.272 --- Log message: add a couple enum values --- Diffs of the changes: (+3 -1) SelectionDAG.cpp |4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.271 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.272 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.271Thu Mar 16 19:40:33 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Mar 17 13:53:59 2006 @@ -2649,10 +2649,12 @@ case ISD::VADD: return "vadd"; case ISD::VSUB: return "vsub"; case ISD::VMUL: return "vmul"; - + case ISD::SETCC: return "setcc"; case ISD::SELECT: return "select"; case ISD::SELECT_CC: return "select_cc"; + case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; + case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt"; case ISD::ADDC:return "addc"; case ISD::ADDE:return "adde"; case ISD::SUBC:return "subc"; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td X86InstrInfo.td X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrFPStack.td updated: 1.3 -> 1.4
X86InstrInfo.td updated: 1.254 -> 1.255
X86InstrSSE.td updated: 1.5 -> 1.6
---
Log message:
Move some pattern fragments to the right files.
---
Diffs of the changes: (+37 -27)
X86InstrFPStack.td | 26 ++
X86InstrInfo.td| 28 +---
X86InstrSSE.td | 10 ++
3 files changed, 37 insertions(+), 27 deletions(-)
Index: llvm/lib/Target/X86/X86InstrFPStack.td
diff -u llvm/lib/Target/X86/X86InstrFPStack.td:1.3
llvm/lib/Target/X86/X86InstrFPStack.td:1.4
--- llvm/lib/Target/X86/X86InstrFPStack.td:1.3 Tue Feb 21 14:00:20 2006
+++ llvm/lib/Target/X86/X86InstrFPStack.td Fri Mar 17 13:55:52 2006
@@ -13,6 +13,32 @@
//
//===--===//
+//===--===//
+// FPStack pattern fragments
+//===--===//
+
+def fp32imm0 : PatLeaf<(f32 fpimm), [{
+ return N->isExactlyValue(+0.0);
+}]>;
+
+def fp64imm0 : PatLeaf<(f64 fpimm), [{
+ return N->isExactlyValue(+0.0);
+}]>;
+
+def fp64immneg0 : PatLeaf<(f64 fpimm), [{
+ return N->isExactlyValue(-0.0);
+}]>;
+
+def fp64imm1 : PatLeaf<(f64 fpimm), [{
+ return N->isExactlyValue(+1.0);
+}]>;
+
+def fp64immneg1 : PatLeaf<(f64 fpimm), [{
+ return N->isExactlyValue(-1.0);
+}]>;
+
+def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>;
+
// Some 'special' instructions
let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def FP_TO_INT16_IN_MEM : I<0, Pseudo,
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.254
llvm/lib/Target/X86/X86InstrInfo.td:1.255
--- llvm/lib/Target/X86/X86InstrInfo.td:1.254 Thu Mar 16 20:24:04 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Fri Mar 17 13:55:52 2006
@@ -319,36 +319,14 @@
return (unsigned)N->getValue() == (unsigned char)N->getValue();
}]>;
-def fp32imm0 : PatLeaf<(f32 fpimm), [{
- return N->isExactlyValue(+0.0);
-}]>;
-
-def fp64imm0 : PatLeaf<(f64 fpimm), [{
- return N->isExactlyValue(+0.0);
-}]>;
-
-def fp64immneg0 : PatLeaf<(f64 fpimm), [{
- return N->isExactlyValue(-0.0);
-}]>;
-
-def fp64imm1 : PatLeaf<(f64 fpimm), [{
- return N->isExactlyValue(+1.0);
-}]>;
-
-def fp64immneg1 : PatLeaf<(f64 fpimm), [{
- return N->isExactlyValue(-1.0);
-}]>;
-
// Helper fragments for loads.
def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
+
def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
-def X86loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
-def X86loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
-
def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>;
def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>;
def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>;
@@ -363,10 +341,6 @@
def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>;
def extloadi8i1: PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>;
-def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>;
-
-def X86loadpf32: PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
-def X86loadpf64: PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
//===--===//
// Instruction templates...
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.5
llvm/lib/Target/X86/X86InstrSSE.td:1.6
--- llvm/lib/Target/X86/X86InstrSSE.td:1.5 Tue Feb 21 20:26:30 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Mar 17 13:55:52 2006
@@ -14,6 +14,16 @@
//===--===//
//===--===//
+// SSE pattern fragments
+//===--===//
+
+def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
+def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
+
+def X86loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
+def X86loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
+
+//===--===//
// SSE scalar FP Instructions
//===--===//
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-comm
[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll
Changes in directory llvm/test/Regression/CodeGen/Generic:
vector.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+41 -0)
vector.ll | 41 +
1 files changed, 41 insertions(+)
Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Generic/vector.ll:1.1
*** /dev/null Fri Mar 17 14:04:50 2006
--- llvm/test/Regression/CodeGen/Generic/vector.ll Fri Mar 17 14:04:40 2006
***
*** 0
--- 1,41
+ ; RUN: llvm-as < %s | llc
+ ; Test that vectors are scalarized/lowered correctly.
+
+ %f1 = type <1 x float>
+ %f2 = type <2 x float>
+ %f4 = type <4 x float>
+ %f8 = type <8 x float>
+
+ implementation
+
+ void %test_f1(%f1 *%P, %f1* %Q, %f1 *%S) {
+ %p = load %f1 *%P
+ %q = load %f1* %Q
+ %R = add %f1 %p, %q
+ store %f1 %R, %f1 *%S
+ ret void
+ }
+
+ void %test_f2(%f2 *%P, %f2* %Q, %f2 *%S) {
+ %p = load %f2* %P
+ %q = load %f2* %Q
+ %R = add %f2 %p, %q
+ store %f2 %R, %f2 *%S
+ ret void
+ }
+
+ void %test_f4(%f4 *%P, %f4* %Q, %f4 *%S) {
+ %p = load %f4* %P
+ %q = load %f4* %Q
+ %R = add %f4 %p, %q
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_f8(%f8 *%P, %f8* %Q, %f8 *%S) {
+ %p = load %f8* %P
+ %q = load %f8* %Q
+ %R = add %f8 %p, %q
+ store %f8 %R, %f8 *%S
+ ret void
+ }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.110 -> 1.111 --- Log message: Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. --- Diffs of the changes: (+4 -0) X86ISelLowering.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.110 llvm/lib/Target/X86/X86ISelLowering.cpp:1.111 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.110 Fri Mar 17 11:27:47 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 17 14:31:41 2006 @@ -50,6 +50,10 @@ setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 setStackPointerRegisterToSaveRestore(X86::ESP); + if (!TM.getSubtarget().isTargetDarwin()) +// Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. +setUseUnderscoreSetJmpLongJmp(true); + // Add legal addressing mode scale values. addLegalAddressScale(8); addLegalAddressScale(4); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/neg.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
neg.ll added (r1.1)
---
Log message:
Add a missing testcase
---
Diffs of the changes: (+6 -0)
neg.ll |6 ++
1 files changed, 6 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/neg.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/neg.ll:1.1
*** /dev/null Fri Mar 17 16:39:55 2006
--- llvm/test/Regression/CodeGen/PowerPC/neg.ll Fri Mar 17 16:39:45 2006
***
*** 0
--- 1,6
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep neg
+
+ int %test(int %X) {
+ %Y = sub int 0, %X
+ ret int %Y
+ }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.186 -> 1.187 --- Log message: Fix subfic to match subc by default instead of sub so that it is correctly cost-modeled as producing a flag. This fixes the test I just added for neg --- Diffs of the changes: (+2 -2) PPCInstrInfo.td |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.186 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.187 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.186 Thu Mar 16 19:40:33 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Fri Mar 17 16:41:37 2006 @@ -334,7 +334,7 @@ [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), "subfic $rD, $rA, $imm", IntGeneral, - [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>; + [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm), "li $rD, $imm", IntGeneral, [(set GPRC:$rD, immSExt16:$imm)]>; @@ -1058,7 +1058,7 @@ def : Pat<(xor GPRC:$in, imm:$imm), (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; // SUBFIC -def : Pat<(subc immSExt16:$imm, GPRC:$in), +def : Pat<(sub immSExt16:$imm, GPRC:$in), (SUBFIC GPRC:$in, imm:$imm)>; // Return void support. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/CodeEmitterGen.cpp
Changes in directory llvm/utils/TableGen:
CodeEmitterGen.cpp updated: 1.43 -> 1.44
---
Log message:
Fix miscodegen of V_SET0 in PPC.
---
Diffs of the changes: (+4 -0)
CodeEmitterGen.cpp |4
1 files changed, 4 insertions(+)
Index: llvm/utils/TableGen/CodeEmitterGen.cpp
diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.43
llvm/utils/TableGen/CodeEmitterGen.cpp:1.44
--- llvm/utils/TableGen/CodeEmitterGen.cpp:1.43 Thu Jan 26 19:39:38 2006
+++ llvm/utils/TableGen/CodeEmitterGen.cpp Fri Mar 17 18:40:36 2006
@@ -112,6 +112,10 @@
NewBI->setBit(middle, BI->getBit(middle));
}
BI = NewBI;
+
+ // Update the bits in reversed order so that emitInstrOpBits will get the
+ // correct endianness.
+ R->getValue("Inst")->setValue(NewBI);
}
unsigned Value = 0;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopStrengthReduce.cpp updated: 1.78 -> 1.79
---
Log message:
Sort StrideOrder so we can process the smallest strides first. This allows
for more IV reuses.
---
Diffs of the changes: (+27 -0)
LoopStrengthReduce.cpp | 27 +++
1 files changed, 27 insertions(+)
Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.78
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.79
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.78 Fri Mar 17
13:52:23 2006
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Fri Mar 17 18:44:49 2006
@@ -1199,6 +1199,30 @@
CondUse->isUseOfPostIncrementedValue = true;
}
+namespace {
+ // Constant strides come first which in turns are sorted by their absolute
+ // values. If absolute values are the same, then positive strides comes
first.
+ // e.g.
+ // 4, -1, X, 1, 2 ==> 1, -1, 2, 4, X
+ struct StrideCompare {
+bool operator()(const SCEVHandle &LHS, const SCEVHandle &RHS) {
+ SCEVConstant *LHSC = dyn_cast(LHS);
+ SCEVConstant *RHSC = dyn_cast(RHS);
+ if (LHSC && RHSC) {
+int64_t LV = LHSC->getValue()->getSExtValue();
+int64_t RV = RHSC->getValue()->getSExtValue();
+uint64_t ALV = (LV < 0) ? -LV : LV;
+uint64_t ARV = (RV < 0) ? -RV : RV;
+if (ALV == ARV)
+ return LV > RV;
+else
+ return ALV < ARV;
+ } else
+return (LHSC && !RHSC);
+}
+ };
+}
+
void LoopStrengthReduce::runOnLoop(Loop *L) {
// First step, transform all loops nesting inside of this loop.
for (LoopInfo::iterator I = L->begin(), E = L->end(); I != E; ++I)
@@ -1241,6 +1265,9 @@
// IVsByStride keeps IVs for one particular loop.
IVsByStride.clear();
+ // Sort the StrideOrder so we process larger strides first.
+ std::stable_sort(StrideOrder.begin(), StrideOrder.end(), StrideCompare());
+
// Note: this processes each stride/type pair individually. All users passed
// into StrengthReduceStridedIVUsers have the same type AND stride. Also,
// node that we iterate over IVUsesByStride indirectly by using StrideOrder.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td X86InstrInfo.td X86InstrSSE.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86: X86InstrFPStack.td updated: 1.4 -> 1.5 X86InstrInfo.td updated: 1.255 -> 1.256 X86InstrSSE.td updated: 1.6 -> 1.7 X86RegisterInfo.cpp updated: 1.129 -> 1.130 --- Log message: Use the generic vector register classes VR64 / VR128 rather than V4F32, V8I16, etc. --- Diffs of the changes: (+247 -233) X86InstrFPStack.td | 33 X86InstrInfo.td | 39 - X86InstrSSE.td | 396 +++- X86RegisterInfo.cpp | 12 - 4 files changed, 247 insertions(+), 233 deletions(-) Index: llvm/lib/Target/X86/X86InstrFPStack.td diff -u llvm/lib/Target/X86/X86InstrFPStack.td:1.4 llvm/lib/Target/X86/X86InstrFPStack.td:1.5 --- llvm/lib/Target/X86/X86InstrFPStack.td:1.4 Fri Mar 17 13:55:52 2006 +++ llvm/lib/Target/X86/X86InstrFPStack.td Fri Mar 17 19:23:20 2006 @@ -14,6 +14,39 @@ //===--===// //===--===// +// FPStack specific DAG Nodes. +//===--===// + +def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>; +def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>; +def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, + SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; +def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, + SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; +def SDTX86Fild: SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>, + SDTCisVT<2, OtherVT>]>; +def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; + +def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet, +[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; +def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet, +[SDNPHasChain, SDNPOutFlag]>; +def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, +[SDNPHasChain]>; +def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, +[SDNPHasChain, SDNPInFlag]>; +def X86fild: SDNode<"X86ISD::FILD", SDTX86Fild, +[SDNPHasChain]>; +def X86fildflag: SDNode<"X86ISD::FILD_FLAG",SDTX86Fild, +[SDNPHasChain, SDNPOutFlag]>; +def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, +[SDNPHasChain]>; +def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, +[SDNPHasChain]>; +def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, +[SDNPHasChain]>; + +//===--===// // FPStack pattern fragments //===--===// Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.255 llvm/lib/Target/X86/X86InstrInfo.td:1.256 --- llvm/lib/Target/X86/X86InstrInfo.td:1.255 Fri Mar 17 13:55:52 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Fri Mar 17 19:23:20 2006 @@ -41,17 +41,6 @@ def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; -def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>; -def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>; - -def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, - SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; -def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, - SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; -def SDTX86Fild: SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>, - SDTCisVT<2, OtherVT>]>; -def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; - def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; def SDTX86RdTsc : SDTypeProfile<0, 0, []>; @@ -61,11 +50,6 @@ def X86shld: SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; def X86shrd: SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; -def X86fand: SDNode<"X86ISD::FAND", SDTFPBinOp, -[SDNPCommutative, SDNPAssociative]>; -def X86fxor: SDNode<"X86ISD::FXOR", SDTFPBinOp, -[SDNPCommutative, SDNPAssociative]>; - def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, [SDNPOutFlag]>; def X86test: SDNode<"X86ISD::TEST", SDTX86CmpTest, @@ -91,26 +75,6 @@ def X86call: SDNode<"X86ISD::CALL", SDT_X86Call, [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; -def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet, -[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; -def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet, -
[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.112 -> 1.113 --- Log message: Update comments. --- Diffs of the changes: (+5 -4) SelectionDAGNodes.h |9 + 1 files changed, 5 insertions(+), 4 deletions(-) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.112 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.113 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.112 Fri Mar 17 13:53:41 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Fri Mar 17 19:43:28 2006 @@ -85,9 +85,10 @@ TargetConstantPool, TargetExternalSymbol, -// Abstract version of ConstantVec with abstract Vector type. The first node -// is a constant element count, the second is a value type indicating the -// type of the elements. +// Abstract version of ConstantVec with abstract Vector type. The first N-2 +// operands are the constants to initialize the vector, the N-2nd operand +// is a constant element count, and that last operand is the value type +// indicating the type of the elements. VConstant, // CopyToReg - This node has three operands: a chain, a register number to @@ -157,7 +158,7 @@ // a constant element count, and a value type node indicating the type of // the elements. The order is count, type, op0, op1. All vector opcodes, // including VLOAD and VConstant must currently have count and type as -// their 1st and 2nd arguments. +// their last two operands. VADD, VSUB, VMUL, VSDIV, VUDIV, VAND, VOR, VXOR, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.316 -> 1.317
SelectionDAG.cpp updated: 1.272 -> 1.273
SelectionDAGISel.cpp updated: 1.193 -> 1.194
---
Log message:
Change the structure of lowering vector stuff. Note: This breaks some
things.
---
Diffs of the changes: (+318 -214)
LegalizeDAG.cpp | 429 +++
SelectionDAG.cpp |4
SelectionDAGISel.cpp | 99 +--
3 files changed, 318 insertions(+), 214 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.316
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.317
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.316 Thu Mar 16 19:40:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Mar 17 19:44:44 2006
@@ -74,12 +74,21 @@
/// us to avoid promoting the same thing more than once.
std::map PromotedNodes;
- /// ExpandedNodes - For nodes that need to be expanded, and which have more
- /// than one use, this map indicates which which operands are the expanded
- /// version of the input. This allows us to avoid expanding the same node
- /// more than once.
+ /// ExpandedNodes - For nodes that need to be expanded this map indicates
+ /// which which operands are the expanded version of the input. This allows
+ /// us to avoid expanding the same node more than once.
std::map > ExpandedNodes;
+ /// SplitNodes - For vector nodes that need to be split, this map indicates
+ /// which which operands are the split version of the input. This allows us
+ /// to avoid splitting the same node more than once.
+ std::map > SplitNodes;
+
+ /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
+ /// concrete packed types, this contains the mapping of ones we have already
+ /// processed to the result.
+ std::map PackedNodes;
+
void AddLegalizedOperand(SDOperand From, SDOperand To) {
LegalizedNodes.insert(std::make_pair(From, To));
// If someone requests legalization of the new node, return itself.
@@ -113,11 +122,40 @@
void LegalizeDAG();
private:
-
+ /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
+ /// appropriate for its type.
+ void HandleOp(SDOperand Op);
+
+ /// LegalizeOp - We know that the specified value has a legal type.
+ /// Recursively ensure that the operands have legal types, then return the
+ /// result.
SDOperand LegalizeOp(SDOperand O);
- void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
+
+ /// PromoteOp - Given an operation that produces a value in an invalid type,
+ /// promote it to compute the value into a larger type. The produced value
+ /// will have the correct bits for the low portion of the register, but no
+ /// guarantee is made about the top bits: it may be zero, sign-extended, or
+ /// garbage.
SDOperand PromoteOp(SDOperand O);
+ /// ExpandOp - Expand the specified SDOperand into its two component pieces
+ /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
+ /// the LegalizeNodes map is filled in for any results that are not expanded,
+ /// the ExpandedNodes map is filled in for any results that are expanded, and
+ /// the Lo/Hi values are returned. This applies to integer types and Vector
+ /// types.
+ void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
+
+ /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
+ /// two smaller values of MVT::Vector type.
+ void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
+
+ /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
+ /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
+ /// this is called, we know that PackedVT is the right type for the result
and
+ /// we know that this type is legal for the target.
+ SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
+
bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
@@ -149,6 +187,8 @@
};
}
+/// getScalarizedOpcode - Return the scalar opcode that corresponds to the
+/// specified vector opcode.
static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
switch (VecOp) {
default: assert(0 && "Don't know how to scalarize this opcode!");
@@ -220,23 +260,8 @@
"Error: DAG is cyclic!");
Visited.clear();
- for (unsigned i = 0, e = Order.size(); i != e; ++i) {
-SDNode *N = Order[i];
-switch (getTypeAction(N->getValueType(0))) {
-default: assert(0 && "Bad type action!");
-case Legal:
- LegalizeOp(SDOperand(N, 0));
- break;
-case Promote:
- PromoteOp(SDOperand(N, 0));
- break;
-case Expand: {
- SDOperand X, Y;
- ExpandOp(SDOperand(N, 0), X, Y);
- break;
-}
-}
- }
+ for (unsigned i = 0, e = Orde
