[llvm-commits] CVS: llvm/docs/Projects.html
Changes in directory llvm/docs: Projects.html updated: 1.20 -> 1.21 --- Log message: Fix a typo Eric van Riet Paap noticed --- Diffs of the changes: (+2 -2) Projects.html |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/docs/Projects.html diff -u llvm/docs/Projects.html:1.20 llvm/docs/Projects.html:1.21 --- llvm/docs/Projects.html:1.20Mon Mar 13 23:39:39 2006 +++ llvm/docs/Projects.html Thu Mar 16 10:14:59 2006 @@ -100,7 +100,7 @@ AC_INIT. Place the name of your project, its version number and a contact email address for your project as the arguments to this macro -AC_CONFIG_AUC_DIR. If your project isn't in the +AC_CONFIG_AUX_DIR. If your project isn't in the llvm/projects directory then you might need to adjust this so that it specifies a relative path to the llvm/autoconf directory. LLVM_CONFIG_PROJECT. Just leave this alone. @@ -453,7 +453,7 @@ mailto:[EMAIL PROTECTED]">John Criswell http://llvm.org";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/03/16 16:14:59 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicInst.h
Changes in directory llvm/include/llvm: IntrinsicInst.h updated: 1.11 -> 1.12 --- Log message: Typo. --- Diffs of the changes: (+1 -1) IntrinsicInst.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/IntrinsicInst.h diff -u llvm/include/llvm/IntrinsicInst.h:1.11 llvm/include/llvm/IntrinsicInst.h:1.12 --- llvm/include/llvm/IntrinsicInst.h:1.11 Thu Mar 9 14:01:20 2006 +++ llvm/include/llvm/IntrinsicInst.h Thu Mar 16 12:15:12 2006 @@ -1,4 +1,4 @@ -//===-- llvm/InstrinsicInst.h - Intrinsic Instruction Wrappers --*- C++ -*-===// +//===-- llvm/IntrinsicInst.h - Intrinsic Instruction Wrappers ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.167 -> 1.168
---
Log message:
Save/restore VRSAVE once per function, not once per block.
---
Diffs of the changes: (+52 -39)
PPCISelDAGToDAG.cpp | 91 +---
1 files changed, 52 insertions(+), 39 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.167
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.168
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.167 Tue Mar 14 11:56:49 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Mar 16 12:25:23 2006
@@ -39,17 +39,21 @@
/// instructions for SelectionDAG operations.
///
class PPCDAGToDAGISel : public SelectionDAGISel {
+PPCTargetMachine &TM;
PPCTargetLowering PPCLowering;
unsigned GlobalBaseReg;
public:
-PPCDAGToDAGISel(PPCTargetMachine &TM)
- : SelectionDAGISel(PPCLowering),
-PPCLowering(*TM.getTargetLowering()){}
+PPCDAGToDAGISel(PPCTargetMachine &tm)
+ : SelectionDAGISel(PPCLowering), TM(tm),
+PPCLowering(*TM.getTargetLowering()) {}
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
GlobalBaseReg = 0;
- return SelectionDAGISel::runOnFunction(Fn);
+ SelectionDAGISel::runOnFunction(Fn);
+
+ InsertVRSaveCode(Fn);
+ return true;
}
/// getI32Imm - Return a target constant with the specified value, of type
@@ -121,6 +125,8 @@
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
+void InsertVRSaveCode(Function &Fn);
+
virtual const char *getPassName() const {
return "PowerPC DAG->DAG Pattern Instruction Selection";
}
@@ -199,13 +205,19 @@
// Emit machine code to BB.
ScheduleAndEmitDAG(DAG);
-
+}
+
+/// InsertVRSaveCode - Once the entire function has been instruction selected,
+/// all virtual registers are created and all machine instructions are built,
+/// check to see if we need to save/restore VRSAVE. If so, do it.
+void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
// Check to see if this function uses vector registers, which means we have
to
// save and restore the VRSAVE register and update it with the regs we use.
//
// In this case, there will be virtual registers of vector type type created
// by the scheduler. Detect them now.
- SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
+ MachineFunction &Fn = MachineFunction::get(&F);
+ SSARegMap *RegMap = Fn.getSSARegMap();
bool HasVectorVReg = false;
for (unsigned i = MRegisterInfo::FirstVirtualRegister,
e = RegMap->getLastVirtReg()+1; i != e; ++i)
@@ -213,7 +225,8 @@
HasVectorVReg = true;
break;
}
-
+ if (!HasVectorVReg) return; // nothing to do.
+
// If we have a vector register, we want to emit code into the entry and exit
// blocks to save and restore the VRSAVE register. We do this here (instead
// of marking all vector instructions as clobbering VRSAVE) for two reasons:
@@ -223,41 +236,41 @@
// 2. This (more significantly) allows us to create a temporary virtual
//register to hold the saved VRSAVE value, allowing this temporary to be
//register allocated, instead of forcing it to be spilled to the stack.
- if (HasVectorVReg) {
-// Create two vregs - one to hold the VRSAVE register that is live-in to
the
-// function and one for the value after having bits or'd into it.
-unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
-unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
-
-MachineFunction &MF = DAG.getMachineFunction();
-MachineBasicBlock &EntryBB = *MF.begin();
-// Emit the following code into the entry block:
-// InVRSAVE = MFVRSAVE
-// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
-// MTVRSAVE UpdatedVRSAVE
-MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
-BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
-BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1,
UpdatedVRSAVE).addReg(InVRSAVE);
-BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
-
-// Find all return blocks, outputting a restore in each epilog.
-const TargetInstrInfo &TII = *DAG.getTarget().getInstrInfo();
-for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E;
++BB)
- if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
-IP = BB->end(); --IP;
-
-// Skip over all terminator instructions, which are part of the return
-// sequence.
-MachineBasicBlock::iterator I2 = IP;
-while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
- IP = I2;
-
-// Emit: MTVRSAVE InVRSave
-
[llvm-commits] CVS: llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c
Changes in directory llvm/test/Regression/CFrontend:
2006-03-16-VectorCtor.c added (r1.1)
---
Log message:
New testcase, the new CFE compiles this into insertelement instructions, the
old one crashes.
---
Diffs of the changes: (+11 -0)
2006-03-16-VectorCtor.c | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c
diff -c /dev/null llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c:1.1
*** /dev/null Thu Mar 16 12:48:01 2006
--- llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c Thu Mar 16
12:47:51 2006
***
*** 0
--- 1,11
+ // Passes with the new CFE.
+ // RUN: %llvmgcc %s -S -o -
+ // XFAIL: *
+
+ typedef int v4si __attribute__ ((__vector_size__ (16)));
+ void test(v4si *P, v4si *Q, float X) {
+ *P = (v4si){ X, X, X, X } * *Q;
+ }
+
+ v4si G = (v4si){ 0.1, 1.2, 4.2, 17.2 };
+
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.70 -> 1.71
---
Log message:
Another case we could do better on.
---
Diffs of the changes: (+11 -0)
README.txt | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.70
llvm/lib/Target/PowerPC/README.txt:1.71
--- llvm/lib/Target/PowerPC/README.txt:1.70 Tue Mar 7 18:25:47 2006
+++ llvm/lib/Target/PowerPC/README.txt Thu Mar 16 12:50:44 2006
@@ -507,3 +507,14 @@
===-===
+int foo(int N, int ***W, int **TK, int X) {
+ int t, i;
+
+ for (t = 0; t < N; ++t)
+for (i = 0; i < 4; ++i)
+ W[t / X][i][t % X] = TK[i][t];
+
+ return 5;
+}
+
+We generate relatively atrocious code for this loop compared to gcc.
\ No newline at end of file
___
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[llvm-commits] CVS: llvm-www/Features.html OpenProjects.html Oversight.html header.incl
Changes in directory llvm-www: Features.html updated: 1.15 -> 1.16 OpenProjects.html updated: 1.11 -> 1.12 Oversight.html updated: 1.4 -> 1.5 header.incl updated: 1.44 -> 1.45 --- Log message: llvm.cs -> llvm.org --- Diffs of the changes: (+0 -0) 0 files changed ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h
Changes in directory llvm/include/llvm/CodeGen:
ValueTypes.h updated: 1.21 -> 1.22
---
Log message:
Add markers for the first and last vector value type.
---
Diffs of the changes: (+6 -2)
ValueTypes.h |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.21
llvm/include/llvm/CodeGen/ValueTypes.h:1.22
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.21 Thu Mar 2 19:55:49 2006
+++ llvm/include/llvm/CodeGen/ValueTypes.h Thu Mar 16 13:42:44 2006
@@ -48,6 +48,7 @@
Vector = 13, // This is an abstract vector type, which will
// be expanded into a target vector type, or
scalars
// if no matching vector type is available.
+
v8i8 = 14, // 8 x i8
v4i16 = 15, // 4 x i16
v2i32 = 16, // 2 x i32
@@ -59,8 +60,10 @@
v2f32 = 21, // 2 x f32
v4f32 = 22, // 4 x f32
v2f64 = 23, // 2 x f64
+FIRST_VECTOR_VALUETYPE = v8i8,
+LAST_VECTOR_VALUETYPE = v2f64,
-LAST_VALUETYPE // This always remains at the end of the list.
+LAST_VALUETYPE = 24// This always remains at the end of the list.
};
static inline bool isInteger(ValueType VT) {
@@ -70,7 +73,8 @@
return (VT >= f32 && VT <= f128) || (VT >= v4f32 && VT <= v2f64);
}
static inline bool isVector(ValueType VT) {
-return (VT >= v8i8 && VT <= v2f64);
+return (VT >= FIRST_VECTOR_VALUETYPE &&
+VT <= LAST_VECTOR_VALUETYPE);
}
/// getVectorType - Returns the ValueType that represents a vector
NumElements
___
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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.46 -> 1.47
---
Log message:
set TransformToType correctly for vector types.
---
Diffs of the changes: (+8 -0)
TargetLowering.cpp |8
1 files changed, 8 insertions(+)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.46
llvm/lib/Target/TargetLowering.cpp:1.47
--- llvm/lib/Target/TargetLowering.cpp:1.46 Mon Mar 13 17:16:31 2006
+++ llvm/lib/Target/TargetLowering.cpp Thu Mar 16 13:50:01 2006
@@ -124,6 +124,14 @@
// Set MVT::Vector to always be Expanded
SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
ValueTypeActions);
+
+ // Loop over all of the legal vector value types, specifying an identity type
+ // transformation.
+ for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
+ i != MVT::LAST_VECTOR_VALUETYPE; ++i) {
+if (isTypeLegal((MVT::ValueType)i))
+ TransformToType[i] = (MVT::ValueType)i;
+ }
assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
TransformToType[MVT::f64] = MVT::f64;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.189 -> 1.190
---
Log message:
Teach CreateRegForValue how to handle vector types.
---
Diffs of the changes: (+53 -23)
SelectionDAGISel.cpp | 76 +++
1 files changed, 53 insertions(+), 23 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.189
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.190
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.189Wed Mar 15
16:19:46 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 16 13:51:18 2006
@@ -171,28 +171,8 @@
return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
}
-unsigned CreateRegForValue(const Value *V) {
- MVT::ValueType VT = TLI.getValueType(V->getType());
- // The common case is that we will only create one register for this
- // value. If we have that case, create and return the virtual register.
- unsigned NV = TLI.getNumElements(VT);
- if (NV == 1) {
-// If we are promoting this value, pick the next largest supported
type.
-return MakeReg(TLI.getTypeToTransformTo(VT));
- }
-
- // If this value is represented with multiple target registers, make sure
- // to create enough consecutive registers of the right (smaller) type.
- unsigned NT = VT-1; // Find the type to use.
- while (TLI.getNumElements((MVT::ValueType)NT) != 1)
---NT;
-
- unsigned R = MakeReg((MVT::ValueType)NT);
- for (unsigned i = 1; i != NV; ++i)
-MakeReg((MVT::ValueType)NT);
- return R;
-}
-
+unsigned CreateRegForValue(const Value *V);
+
unsigned InitializeRegForValue(const Value *V) {
unsigned &R = ValueMap[V];
assert(R == 0 && "Already initialized this value register!");
@@ -290,7 +270,57 @@
}
}
-
+/// CreateRegForValue - Allocate the appropriate number of virtual registers of
+/// the correctly promoted or expanded types. Assign these registers
+/// consecutive vreg numbers and return the first assigned number.
+unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
+ MVT::ValueType VT = TLI.getValueType(V->getType());
+
+ // The number of multiples of registers that we need, to, e.g., split up
+ // a <2 x int64> -> 4 x i32 registers.
+ unsigned NumVectorRegs = 1;
+
+ // If this is a packed type, figure out what type it will decompose into
+ // and how many of the elements it will use.
+ if (VT == MVT::Vector) {
+const PackedType *PTy = cast(V->getType());
+unsigned NumElts = PTy->getNumElements();
+MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
+
+// Divide the input until we get to a supported size. This will always
+// end with a scalar if the target doesn't support vectors.
+while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
+ NumElts >>= 1;
+ NumVectorRegs <<= 1;
+}
+VT = getVectorType(EltTy, NumElts);
+ }
+
+ // The common case is that we will only create one register for this
+ // value. If we have that case, create and return the virtual register.
+ unsigned NV = TLI.getNumElements(VT);
+ if (NV == 1) {
+// If we are promoting this value, pick the next largest supported type.
+MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
+unsigned Reg = MakeReg(PromotedType);
+// If this is a vector of supported or promoted types (e.g. 4 x i16),
+// create all of the registers.
+for (unsigned i = 1; i != NumVectorRegs; ++i)
+ MakeReg(PromotedType);
+return Reg;
+ }
+
+ // If this value is represented with multiple target registers, make sure
+ // to create enough consecutive registers of the right (smaller) type.
+ unsigned NT = VT-1; // Find the type to use.
+ while (TLI.getNumElements((MVT::ValueType)NT) != 1)
+--NT;
+
+ unsigned R = MakeReg((MVT::ValueType)NT);
+ for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
+MakeReg((MVT::ValueType)NT);
+ return R;
+}
//===--===//
/// SelectionDAGLowering - This is the common target-independent lowering
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.190 -> 1.191
---
Log message:
Add support for CopyFromReg from vector values. Note: this doesn't support
illegal vector types yet!
---
Diffs of the changes: (+119 -104)
SelectionDAGISel.cpp | 223 +++
1 files changed, 119 insertions(+), 104 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.190
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.191
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.190Thu Mar 16
13:51:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 16 13:57:50 2006
@@ -400,110 +400,7 @@
return DAG.getConstant(Val, TLI.getPointerTy());
}
- SDOperand getValue(const Value *V) {
-SDOperand &N = NodeMap[V];
-if (N.Val) return N;
-
-const Type *VTy = V->getType();
-MVT::ValueType VT = TLI.getValueType(VTy);
-if (Constant *C = const_cast(dyn_cast(V)))
- if (ConstantExpr *CE = dyn_cast(C)) {
-visit(CE->getOpcode(), *CE);
-assert(N.Val && "visit didn't populate the ValueMap!");
-return N;
- } else if (GlobalValue *GV = dyn_cast(C)) {
-return N = DAG.getGlobalAddress(GV, VT);
- } else if (isa(C)) {
-return N = DAG.getConstant(0, TLI.getPointerTy());
- } else if (isa(C)) {
-return N = DAG.getNode(ISD::UNDEF, VT);
- } else if (ConstantFP *CFP = dyn_cast(C)) {
-return N = DAG.getConstantFP(CFP->getValue(), VT);
- } else if (const PackedType *PTy = dyn_cast(VTy)) {
-unsigned NumElements = PTy->getNumElements();
-MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
-MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
-
-// Now that we know the number and type of the elements, push a
-// Constant or ConstantFP node onto the ops list for each element of
-// the packed constant.
-std::vector Ops;
-if (ConstantPacked *CP = dyn_cast(C)) {
- if (MVT::isFloatingPoint(PVT)) {
-for (unsigned i = 0; i != NumElements; ++i) {
- const ConstantFP *El = cast(CP->getOperand(i));
- Ops.push_back(DAG.getConstantFP(El->getValue(), PVT));
-}
- } else {
-for (unsigned i = 0; i != NumElements; ++i) {
- const ConstantIntegral *El =
-cast(CP->getOperand(i));
- Ops.push_back(DAG.getConstant(El->getRawValue(), PVT));
-}
- }
-} else {
- assert(isa(C) && "Unknown packed constant!");
- SDOperand Op;
- if (MVT::isFloatingPoint(PVT))
-Op = DAG.getConstantFP(0, PVT);
- else
-Op = DAG.getConstant(0, PVT);
- Ops.assign(NumElements, Op);
-}
-
-// Handle the case where we have a 1-element vector, in which
-// case we want to immediately turn it into a scalar constant.
-if (Ops.size() == 1) {
- return N = Ops[0];
-} else if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
- return N = DAG.getNode(ISD::ConstantVec, TVT, Ops);
-} else {
- // If the packed type isn't legal, then create a ConstantVec node
with
- // generic Vector type instead.
- SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
- SDOperand Typ = DAG.getValueType(PVT);
- Ops.insert(Ops.begin(), Typ);
- Ops.insert(Ops.begin(), Num);
- return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops);
-}
- } else {
-// Canonicalize all constant ints to be unsigned.
-return N =
DAG.getConstant(cast(C)->getRawValue(),VT);
- }
-
-if (const AllocaInst *AI = dyn_cast(V)) {
- std::map::iterator SI =
-FuncInfo.StaticAllocaMap.find(AI);
- if (SI != FuncInfo.StaticAllocaMap.end())
-return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
-}
-
-std::map::const_iterator VMI =
- FuncInfo.ValueMap.find(V);
-assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
-
-unsigned InReg = VMI->second;
-
-// If this type is not legal, make it so now.
-MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
-
-N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
-if (DestVT < VT) {
- // Source must be expanded. This input value is actually coming from the
- // register pair VMI->second and VMI->second+1.
- N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
- DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
-} else {
- if (DestVT > VT) { // Promotion case
-if (MVT::isFloatingPoint(VT))
- N = DAG.getNode(ISD::FP_ROUND, VT, N);
-else
- N = DAG.getNode(ISD::TRUNCATE, VT, N);
- }
-}
-
-ret
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCInstrInfo.td PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.17 -> 1.18
PPCInstrInfo.td updated: 1.183 -> 1.184
PPCRegisterInfo.cpp updated: 1.44 -> 1.45
---
Log message:
Add support for copying registers. still needed: spilling and reloading them
---
Diffs of the changes: (+7 -1)
PPCInstrInfo.cpp|2 +-
PPCInstrInfo.td |4
PPCRegisterInfo.cpp |2 ++
3 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.17
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.18
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.17 Sun Mar 5 17:49:55 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppThu Mar 16 14:03:58 2006
@@ -25,7 +25,7 @@
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
- if (oc == PPC::OR4 || oc == PPC::OR8 ||
+ if (oc == PPC::OR4 || oc == PPC::OR8 || oc == PPC::VOR ||
oc == PPC::OR4To8 || oc == PPC::OR8To4) {// or r1, r2, r2
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.183
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.184
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.183 Tue Mar 14 23:25:05 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Thu Mar 16 14:03:58 2006
@@ -1009,6 +1009,9 @@
def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vsubfp $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
+def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vor $vD, $vA, $vB", VecFP,
+ []>;
def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vxor $vD, $vA, $vB", VecFP,
[]>;
@@ -1151,6 +1154,7 @@
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
+
// Same as above, but using a temporary. FIXME: implement temporaries :)
/*
def : Pattern<(xor GPRC:$in, imm:$imm),
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.44
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.45
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.44Mon Mar 13 15:52:10 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 14:03:58 2006
@@ -110,6 +110,8 @@
BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
} else if (RC == PPC::CRRCRegisterClass) {
BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
+ } else if (RC == PPC::VRRCRegisterClass) {
+BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
std::cerr << "Attempt to copy register that is not GPR or FPR";
abort();
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.45 -> 1.46
---
Log message:
in functions that use a lot of callee saved regs, this can be more than
5 instructions away.
---
Diffs of the changes: (+1 -1)
PPCRegisterInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.45
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.45Thu Mar 16 14:03:58 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 15:31:45 2006
@@ -315,7 +315,7 @@
// Scan the first few instructions of the prolog, looking for an
UPDATE_VRSAVE
// instruction. If we find it, process it.
- for (unsigned i = 0; MBBI != MBB.end() && i < 5; ++i, ++MBBI) {
+ for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
break;
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.60 -> 1.61
---
Log message:
Added a way for TargetLowering to specify what values can be used as the
scale component of the target addressing mode.
---
Diffs of the changes: (+28 -9)
TargetLowering.h | 37 -
1 files changed, 28 insertions(+), 9 deletions(-)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.60
llvm/include/llvm/Target/TargetLowering.h:1.61
--- llvm/include/llvm/Target/TargetLowering.h:1.60 Mon Mar 13 17:15:27 2006
+++ llvm/include/llvm/Target/TargetLowering.h Thu Mar 16 15:47:42 2006
@@ -560,15 +560,6 @@
virtual bool isOperandValidForConstraint(SDOperand Op, char
ConstraintLetter);
//======//
- // Loop Strength Reduction hooks
- //
-
- /// isLegalAddressImmediate - Return true if the integer value or GlobalValue
- /// can be used as the offset of the target addressing mode.
- virtual bool isLegalAddressImmediate(int64_t V) const;
- virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
-
-
//======//
// Scheduler hooks
//
@@ -580,6 +571,34 @@
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
+
//======//
+ // Loop Strength Reduction hooks
+ //
+
+ /// isLegalAddressImmediate - Return true if the integer value or GlobalValue
+ /// can be used as the offset of the target addressing mode.
+ virtual bool isLegalAddressImmediate(int64_t V) const;
+ virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
+
+ typedef std::vector::const_iterator legal_am_scale_iterator;
+ legal_am_scale_iterator legal_am_scale_begin() const {
+return LegalAddressScales.begin();
+ }
+ legal_am_scale_iterator legal_am_scale_end() const {
+return LegalAddressScales.end();
+ }
+
+protected:
+ /// addLegalAddressScale - Add a integer (> 1) value which can be used as
+ /// scale in the target addressing mode. Note: the ordering matters so the
+ /// least efficient ones should be entered first.
+ void addLegalAddressScale(unsigned Scale) {
+LegalAddressScales.push_back(Scale);
+ }
+
+private:
+ std::vector LegalAddressScales;
+
private:
TargetMachine &TM;
const TargetData &TD;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86TargetMachine.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.105 -> 1.106 X86TargetMachine.cpp updated: 1.107 -> 1.108 --- Log message: Added a way for TargetLowering to specify what values can be used as the scale component of the target addressing mode. --- Diffs of the changes: (+12 -2) X86ISelLowering.cpp | 10 ++ X86TargetMachine.cpp |4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.105 llvm/lib/Target/X86/X86ISelLowering.cpp:1.106 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.105 Mon Mar 13 17:18:16 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 16 15:47:42 2006 @@ -49,6 +49,16 @@ setSchedulingPreference(SchedulingForRegPressure); setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 setStackPointerRegisterToSaveRestore(X86::ESP); + + // Add legal addressing mode scale values. + addLegalAddressScale(8); + addLegalAddressScale(4); + addLegalAddressScale(2); + // Enter the ones which require both scale + index last. These are more + // expensive. + addLegalAddressScale(9); + addLegalAddressScale(5); + addLegalAddressScale(3); // Set up the register classes. addRegisterClass(MVT::i8, X86::R8RegisterClass); Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.107 llvm/lib/Target/X86/X86TargetMachine.cpp:1.108 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.107 Mon Mar 13 17:20:37 2006 +++ llvm/lib/Target/X86/X86TargetMachine.cppThu Mar 16 15:47:42 2006 @@ -97,7 +97,7 @@ FileType != TargetMachine::ObjectFile) return true; // Run loop strength reduction before anything else. - if (EnableX86LSR) PM.add(createLoopStrengthReducePass(1, &TLInfo)); + if (EnableX86LSR) PM.add(createLoopStrengthReducePass(&TLInfo)); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); @@ -166,7 +166,7 @@ // Run loop strength reduction before anything else. if (EnableX86LSR) -PM.add(createLoopStrengthReducePass(1, TM.getTargetLowering())); +PM.add(createLoopStrengthReducePass(TM.getTargetLowering())); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCTargetMachine.cpp updated: 1.83 -> 1.84 --- Log message: Added a way for TargetLowering to specify what values can be used as the scale component of the target addressing mode. --- Diffs of the changes: (+2 -2) PPCTargetMachine.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.83 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.84 --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.83 Mon Mar 13 17:56:51 2006 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cppThu Mar 16 15:47:42 2006 @@ -84,7 +84,7 @@ if (FileType != TargetMachine::AssemblyFile) return true; // Run loop strength reduction before anything else. - if (!Fast) PM.add(createLoopStrengthReducePass(1, &TLInfo)); + if (!Fast) PM.add(createLoopStrengthReducePass(&TLInfo)); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); @@ -138,7 +138,7 @@ TM.setRelocationModel(Reloc::DynamicNoPIC); // Run loop strength reduction before anything else. - PM.add(createLoopStrengthReducePass(1, TM.getTargetLowering())); + PM.add(createLoopStrengthReducePass(TM.getTargetLowering())); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Transforms/Scalar.h
Changes in directory llvm/include/llvm/Transforms: Scalar.h updated: 1.61 -> 1.62 --- Log message: For each loop, keep track of all the IV expressions inserted indexed by stride. For a set of uses of the IV of a stride which is a multiple of another stride, do not insert a new IV expression. Rather, reuse the previous IV and rewrite the uses as uses of IV expression multiplied by the factor. e.g. x = 0 ...; x ++ y = 0 ...; y += 4 then use of y can be rewritten as use of 4*x for x86. --- Diffs of the changes: (+4 -8) Scalar.h | 12 1 files changed, 4 insertions(+), 8 deletions(-) Index: llvm/include/llvm/Transforms/Scalar.h diff -u llvm/include/llvm/Transforms/Scalar.h:1.61 llvm/include/llvm/Transforms/Scalar.h:1.62 --- llvm/include/llvm/Transforms/Scalar.h:1.61 Mon Mar 13 17:14:23 2006 +++ llvm/include/llvm/Transforms/Scalar.h Thu Mar 16 15:53:05 2006 @@ -132,15 +132,11 @@ //===--===// // // LoopStrengthReduce - This pass is strength reduces GEP instructions that use -// a loop's canonical induction variable as one of their indices. The -// MaxTargetAMSize is the largest element size that the target architecture -// can handle in its addressing modes. Power of two multipliers less than or -// equal to this value are not reduced. It also takes an optional second -// parameter used to consult the target machine whether certain transformations -// are profitable. +// a loop's canonical induction variable as one of their indices. It takes an +// optional parameter used to consult the target machine whether certain +// transformations are profitable. // -FunctionPass *createLoopStrengthReducePass(unsigned MaxTargetAMSize = 1, - const TargetLowering *TLI = NULL); +FunctionPass *createLoopStrengthReducePass(const TargetLowering *TLI = NULL); //===--===// // ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopStrengthReduce.cpp updated: 1.76 -> 1.77
---
Log message:
For each loop, keep track of all the IV expressions inserted indexed by
stride. For a set of uses of the IV of a stride which is a multiple
of another stride, do not insert a new IV expression. Rather, reuse the
previous IV and rewrite the uses as uses of IV expression multiplied by
the factor.
e.g.
x = 0 ...; x ++
y = 0 ...; y += 4
then use of y can be rewritten as use of 4*x for x86.
---
Diffs of the changes: (+119 -40)
LoopStrengthReduce.cpp | 159 -
1 files changed, 119 insertions(+), 40 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.76
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.77
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.76 Mon Mar 13
17:14:23 2006
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Mar 16 15:53:05 2006
@@ -76,6 +76,27 @@
}
};
+ /// IVInfo - This structure keeps track of one IV expression inserted during
+ /// StrengthReduceStridedIVUsers. It contains the base value, as well as the
+ /// PHI node and increment value created for rewrite.
+ struct IVExpr {
+SCEVHandle Base;
+PHINode*PHI;
+Value *IncV;
+
+IVExpr(const SCEVHandle &base, PHINode *phi, Value *incv)
+ : Base(base), PHI(phi), IncV(incv) {}
+ };
+
+ /// IVsOfOneStride - This structure keeps track of all IV expression inserted
+ /// during StrengthReduceStridedIVUsers for a particular stride of the IV.
+ struct IVsOfOneStride {
+std::vector IVs;
+
+void addIV(const SCEVHandle &Base, PHINode *PHI, Value *IncV) {
+ IVs.push_back(IVExpr(Base, PHI, IncV));
+}
+ };
class LoopStrengthReduce : public FunctionPass {
LoopInfo *LI;
@@ -85,14 +106,14 @@
const Type *UIntPtrTy;
bool Changed;
-/// MaxTargetAMSize - This is the maximum power-of-two scale value that the
-/// target can handle for free with its addressing modes.
-unsigned MaxTargetAMSize;
-
/// IVUsesByStride - Keep track of all uses of induction variables that we
/// are interested in. The key of the map is the stride of the access.
std::map IVUsesByStride;
+/// IVsByStride - Keep track of all IVs that have been inserted for a
+/// particular stride.
+std::map IVsByStride;
+
/// StrideOrder - An ordering of the keys in IVUsesByStride that is stable:
/// We use this to iterate over the IVUsesByStride collection without being
/// dependent on random ordering of pointers in the process.
@@ -112,8 +133,8 @@
const TargetLowering *TLI;
public:
-LoopStrengthReduce(unsigned MTAMS = 1, const TargetLowering *tli = NULL)
- : MaxTargetAMSize(MTAMS), TLI(tli) {
+LoopStrengthReduce(const TargetLowering *tli = NULL)
+ : TLI(tli) {
}
virtual bool runOnFunction(Function &) {
@@ -168,9 +189,8 @@
"Loop Strength Reduction");
}
-FunctionPass *llvm::createLoopStrengthReducePass(unsigned MaxTargetAMSize,
- const TargetLowering *TLI) {
- return new LoopStrengthReduce(MaxTargetAMSize, TLI);
+FunctionPass *llvm::createLoopStrengthReducePass(const TargetLowering *TLI) {
+ return new LoopStrengthReduce(TLI);
}
/// getCastedVersionOf - Return the specified value casted to uintptr_t.
@@ -829,6 +849,14 @@
return Result;
}
+/// isZero - returns true if the scalar evolution expression is zero.
+///
+static bool isZero(SCEVHandle &V) {
+ if (SCEVConstant *SC = dyn_cast(V))
+return SC->getValue()->getRawValue() == 0;
+ return false;
+}
+
/// StrengthReduceStridedIVUsers - Strength reduce all of the users of a single
/// stride of IV. All of the users may have different starting values, and
this
@@ -863,7 +891,8 @@
// for the strides (e.g. if we have "A+C+B" and "A+B+D" as our bases, find
// "A+B"), emit it to the preheader, then remove the expression from the
// UsersToProcess base values.
- SCEVHandle CommonExprs = RemoveCommonExpressionsFromUseBases(UsersToProcess);
+ SCEVHandle CommonExprs =
+RemoveCommonExpressionsFromUseBases(UsersToProcess);
// Next, figure out what we can represent in the immediate fields of
// instructions. If we can represent anything there, move it to the imm
@@ -891,12 +920,12 @@
isAddress, L);
}
}
-
+
// Now that we know what we need to do, insert the PHI node itself.
//
DEBUG(std::cerr << "INSERTING IV of STRIDE " << *Stride << " and BASE "
<< *CommonExprs << " :\n");
-
+
SCEVExpander Rewriter(*SE, *LI);
SCEVExpander PreheaderRewriter(*SE, *LI);
@@ -905,33 +934,68 @@
Instruction *PhiInsertBefore = L->getHeader()->begin();
BasicBlock *LatchBlock = L->getLoopLatch();
-
- // Create a new Phi for th
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.106 -> 1.107 --- Log message: Bug fix: condition inverted. --- Diffs of the changes: (+1 -1) X86ISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.106 llvm/lib/Target/X86/X86ISelLowering.cpp:1.107 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.106 Thu Mar 16 15:47:42 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 16 16:02:48 2006 @@ -2214,7 +2214,7 @@ if (RModel == Reloc::Static) return true; else if (RModel == Reloc::DynamicNoPIC) - return DarwinGVRequiresExtraLoad(GV); + return !DarwinGVRequiresExtraLoad(GV); else return false; } else ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.td
Changes in directory llvm/lib/Target/PowerPC: PPC.td updated: 1.14 -> 1.15 --- Log message: add callee saved vector regs --- Diffs of the changes: (+2 -1) PPC.td |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPC.td diff -u llvm/lib/Target/PowerPC/PPC.td:1.14 llvm/lib/Target/PowerPC/PPC.td:1.15 --- llvm/lib/Target/PowerPC/PPC.td:1.14 Sun Mar 12 23:15:10 2006 +++ llvm/lib/Target/PowerPC/PPC.td Thu Mar 16 16:07:06 2006 @@ -93,5 +93,6 @@ let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, -F30, F31, CR2, CR3, CR4, LR]; +F30, F31, CR2, CR3, CR4, V20, V21, V22, V23, V24, V25, V26, V27, V28, +V29, V30, V31, LR]; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.18 -> 1.19
PPCRegisterInfo.cpp updated: 1.46 -> 1.47
---
Log message:
teach the ppc backend how to spill/reload vector regs
---
Diffs of the changes: (+21 -1)
PPCInstrInfo.cpp|2 +-
PPCRegisterInfo.cpp | 20
2 files changed, 21 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.18
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.19
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.18 Thu Mar 16 14:03:58 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppThu Mar 16 16:24:02 2006
@@ -80,7 +80,7 @@
}
unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
- int &FrameIndex) const {
+ int &FrameIndex) const {
switch (MI->getOpcode()) {
default: break;
case PPC::LD:
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.47
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46Thu Mar 16 15:31:45 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 16:24:02 2006
@@ -50,6 +50,9 @@
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
if (SrcReg == PPC::LR) {
+// FIXME: this spills LR immediately to memory in one step. To do this, we
+// use R11, which we know cannot be used in the prolog/epilog. This is a
+// hack.
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
@@ -63,6 +66,15 @@
addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
} else if (RC == PPC::F4RCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
+ } else if (RC == PPC::VRRCRegisterClass) {
+// We don't have indexed addressing for vector loads. Emit:
+// R11 = ADDI FI#
+// Dest = LVX R0, R11
+//
+// FIXME: We use R0 here, because it isn't available for RA.
+addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+BuildMI(MBB, MI, PPC::STVX, 3)
+ .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 && "Unknown regclass!");
abort();
@@ -88,6 +100,14 @@
addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
} else if (RC == PPC::F4RCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
+ } else if (RC == PPC::VRRCRegisterClass) {
+// We don't have indexed addressing for vector loads. Emit:
+// R11 = ADDI FI#
+// Dest = LVX R0, R11
+//
+// FIXME: We use R0 here, because it isn't available for RA.
+addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 && "Unknown regclass!");
abort();
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.71 -> 1.72
---
Log message:
add a note
---
Diffs of the changes: (+8 -1)
README.txt |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.71
llvm/lib/Target/PowerPC/README.txt:1.72
--- llvm/lib/Target/PowerPC/README.txt:1.71 Thu Mar 16 12:50:44 2006
+++ llvm/lib/Target/PowerPC/README.txt Thu Mar 16 16:25:55 2006
@@ -507,6 +507,10 @@
===-===
+Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
+registers, to generate better spill code.
+
+===-===
int foo(int N, int ***W, int **TK, int X) {
int t, i;
@@ -517,4 +521,7 @@
return 5;
}
-We generate relatively atrocious code for this loop compared to gcc.
\ No newline at end of file
+We generate relatively atrocious code for this loop compared to gcc.
+
+
+
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.td updated: 1.184 -> 1.185
---
Log message:
Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
---
Diffs of the changes: (+1 -0)
PPCInstrInfo.td |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.184
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.185
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.184 Thu Mar 16 14:03:58 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Thu Mar 16 16:35:59 2006
@@ -276,6 +276,7 @@
// All calls clobber the non-callee saved registers...
Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
+
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
LR,CTR,
CR0,CR1,CR5,CR6,CR7] in {
// Convenient aliases for call instructions
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.72 -> 1.73 --- Log message: Notes on how to kill the eeevil brtwoway, and make ppc branch selector more target independant, generate better code, and be less conservative. --- Diffs of the changes: (+28 -0) README.txt | 28 1 files changed, 28 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.72 llvm/lib/Target/PowerPC/README.txt:1.73 --- llvm/lib/Target/PowerPC/README.txt:1.72 Thu Mar 16 16:25:55 2006 +++ llvm/lib/Target/PowerPC/README.txt Thu Mar 16 16:37:48 2006 @@ -18,6 +18,34 @@ This occurs in SPASS. +The power of diet coke came up with a solution to this today: + +We know the only two cases that can happen here are either: +a) we have a conditional branch followed by a fallthrough to the next BB +b) we have a conditional branch followed by an unconditional branch + +We also invented the BRTWOWAY node to model (b). + +Currently, these are modeled by the PPC_BRCOND node which is a 12-byte pseudo +that codegens to + bccinv false +true: + b truebb +false: + b falsebb + +However, realizing that for (a), we can bccinv directly to the fallthrough +block, and for (b) we will already have another unconditional branch after +the conditional branch (see SPASS case above), then we know that we don't need +BRTWOWAY at all, and can just codegen PPC_BRCOND as + +bccinv +8 +b truebb + +This will also allow us to selectively not run the ppc branch selector, by just +selecting PPC_BRCOND pseudo directly to the correct conditional branch +instruction for small functions. + ===-=== * Codegen this: ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.65 -> 1.66
---
Log message:
A new entry.
---
Diffs of the changes: (+45 -0)
README.txt | 45 +
1 files changed, 45 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.65 llvm/lib/Target/X86/README.txt:1.66
--- llvm/lib/Target/X86/README.txt:1.65 Wed Mar 8 19:39:46 2006
+++ llvm/lib/Target/X86/README.txt Thu Mar 16 16:44:22 2006
@@ -584,3 +584,48 @@
//===-===//
+%X = weak global int 0
+
+void %foo(int %N) {
+ %N = cast int %N to uint
+ %tmp.24 = setgt int %N, 0
+ br bool %tmp.24, label %no_exit, label %return
+
+no_exit:
+ %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
+ %i.0.0 = cast uint %indvar to int
+ volatile store int %i.0.0, int* %X
+ %indvar.next = add uint %indvar, 1
+ %exitcond = seteq uint %indvar.next, %N
+ br bool %exitcond, label %return, label %no_exit
+
+return:
+ ret void
+}
+
+compiles into:
+
+ .text
+ .align 4
+ .globl _foo
+_foo:
+ movl 4(%esp), %eax
+ cmpl $1, %eax
+ jl LBB_foo_4# return
+LBB_foo_1: # no_exit.preheader
+ xorl %ecx, %ecx
+LBB_foo_2: # no_exit
+ movl L_X$non_lazy_ptr, %edx
+ movl %ecx, (%edx)
+ incl %ecx
+ cmpl %eax, %ecx
+ jne LBB_foo_2 # no_exit
+LBB_foo_3: # return.loopexit
+LBB_foo_4: # return
+ ret
+
+We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
+remateralization is implemented. This can be accomplished with 1) a target
+dependent LICM pass or 2) makeing SelectDAG represent the whole function.
+
+//===-===//
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.191 -> 1.192 --- Log message: Fix a problem fully scalarizing values. --- Diffs of the changes: (+4 -1) SelectionDAGISel.cpp |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.191 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.192 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.191Thu Mar 16 13:57:50 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 16 17:05:19 2006 @@ -293,7 +293,10 @@ NumElts >>= 1; NumVectorRegs <<= 1; } -VT = getVectorType(EltTy, NumElts); +if (NumElts == 1) + VT = EltTy; +else + VT = getVectorType(EltTy, NumElts); } // The common case is that we will only create one register for this ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/tools/bugpoint/CrashDebugger.cpp
Changes in directory llvm/tools/bugpoint:
CrashDebugger.cpp updated: 1.46 -> 1.47
---
Log message:
add an assert to get a slightly better msg about this problem
---
Diffs of the changes: (+3 -0)
CrashDebugger.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/tools/bugpoint/CrashDebugger.cpp
diff -u llvm/tools/bugpoint/CrashDebugger.cpp:1.46
llvm/tools/bugpoint/CrashDebugger.cpp:1.47
--- llvm/tools/bugpoint/CrashDebugger.cpp:1.46 Sun Mar 5 16:21:36 2006
+++ llvm/tools/bugpoint/CrashDebugger.cpp Thu Mar 16 17:16:17 2006
@@ -128,6 +128,9 @@
// Convert list to set for fast lookup...
std::set Functions;
for (unsigned i = 0, e = Funcs.size(); i != e; ++i) {
+// FIXME: bugpoint should add names to all stripped symbols.
+assert(!Funcs[i]->getName().empty() &&
+ "Bugpoint doesn't work on stripped modules yet PR718!");
Function *CMF = M->getFunction(Funcs[i]->getName(),
Funcs[i]->getFunctionType());
assert(CMF && "Function not in module?!");
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.47 -> 1.48
---
Log message:
remove dead variable
---
Diffs of the changes: (+0 -2)
PPCRegisterInfo.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.47
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.48
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.47Thu Mar 16 16:24:02 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 17:52:08 2006
@@ -118,8 +118,6 @@
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
- MachineInstr *I;
-
if (RC == PPC::GPRCRegisterClass) {
BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == PPC::G8RCRegisterClass) {
___
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[llvm-commits] CVS: llvm/lib/Target/README.txt
Changes in directory llvm/lib/Target: README.txt updated: 1.21 -> 1.22 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+5 -1) README.txt |6 +- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.21 llvm/lib/Target/README.txt:1.22 --- llvm/lib/Target/README.txt:1.21 Tue Mar 14 13:31:24 2006 +++ llvm/lib/Target/README.txt Thu Mar 16 19:40:33 2006 @@ -17,7 +17,11 @@ a bunch of loads from m. It would be better to avoid the memcpy and just do loads from the static array. -===-=== +//===-===// + +Make the PPC branch selector target independant + +//===-===// Get the C front-end to expand hypot(x,y) -> llvm.sqrt(x*x+y*y) when errno and precision don't matter (ffastmath). Misc/mandel will like this. :) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.107 -> 1.108 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+0 -2) X86ISelLowering.cpp |2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.107 llvm/lib/Target/X86/X86ISelLowering.cpp:1.108 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.107 Thu Mar 16 16:02:48 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 16 19:40:33 2006 @@ -125,8 +125,6 @@ setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); setOperationAction(ISD::BRCOND , MVT::Other, Custom); - setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); - setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); setOperationAction(ISD::BR_CC, MVT::Other, Expand); setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.35 -> 1.36 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+0 -2) IA64ISelLowering.cpp |2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.35 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.36 --- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.35 Sat Mar 4 23:08:37 2006 +++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Thu Mar 16 19:40:33 2006 @@ -36,8 +36,6 @@ addRegisterClass(MVT::i1, IA64::PRRegisterClass); setOperationAction(ISD::BR_CC, MVT::Other, Expand); - setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); - setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); // ia64 uses SELECT not SELECT_CC ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.110 -> 1.111 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+0 -13) SelectionDAGNodes.h | 13 - 1 files changed, 13 deletions(-) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.110 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.111 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.110 Sat Mar 4 23:06:40 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Thu Mar 16 19:40:33 2006 @@ -302,25 +302,12 @@ // to if the condition is true. BRCOND, -// BRCONDTWOWAY - Two-way conditional branch. The first operand is the -// chain, the second is the condition, the third is the block to branch to -// if true, and the forth is the block to branch to if false. Targets -// usually do not implement this, preferring to have legalize demote the -// operation to BRCOND/BR pairs when necessary. -BRCONDTWOWAY, - // BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in // that the condition is represented as condition code, and two nodes to // compare, rather than as a combined SetCC node. The operands in order are // chain, cc, lhs, rhs, block to branch to if condition is true. BR_CC, -// BRTWOWAY_CC - Two-way conditional branch. The operands in order are -// chain, cc, lhs, rhs, block to branch to if condition is true, block to -// branch to if condition is false. Targets usually do not implement this, -// preferring to have legalize demote the operation to BRCOND/BR pairs. -BRTWOWAY_CC, - // RET - Return from function. The first operand is the chain, // and any subsequent operands are the return values for the // function. This operation can have variable number of operands. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/Sparc: SparcISelDAGToDAG.cpp updated: 1.88 -> 1.89 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+0 -2) SparcISelDAGToDAG.cpp |2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.88 llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.89 --- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.88Sat Mar 4 23:08:37 2006 +++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Mar 16 19:40:33 2006 @@ -166,8 +166,6 @@ // Sparc doesn't have BRCOND either, it has BR_CC. setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); - setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); setOperationAction(ISD::BR_CC, MVT::i32, Custom); setOperationAction(ISD::BR_CC, MVT::f32, Custom); setOperationAction(ISD::BR_CC, MVT::f64, Custom); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.126 -> 1.127
LegalizeDAG.cpp updated: 1.315 -> 1.316
SelectionDAG.cpp updated: 1.270 -> 1.271
SelectionDAGISel.cpp updated: 1.192 -> 1.193
---
Log message:
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
---
Diffs of the changes: (+5 -181)
DAGCombiner.cpp | 68
LegalizeDAG.cpp | 94 ---
SelectionDAG.cpp | 16
SelectionDAGISel.cpp |8 ++--
4 files changed, 5 insertions(+), 181 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.126
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.127
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.126 Mon Mar 13 12:37:30 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Mar 16 19:40:33 2006
@@ -206,9 +206,7 @@
SDOperand visitFNEG(SDNode *N);
SDOperand visitFABS(SDNode *N);
SDOperand visitBRCOND(SDNode *N);
-SDOperand visitBRCONDTWOWAY(SDNode *N);
SDOperand visitBR_CC(SDNode *N);
-SDOperand visitBRTWOWAY_CC(SDNode *N);
SDOperand visitLOAD(SDNode *N);
SDOperand visitSTORE(SDNode *N);
@@ -639,9 +637,7 @@
case ISD::FNEG: return visitFNEG(N);
case ISD::FABS: return visitFABS(N);
case ISD::BRCOND: return visitBRCOND(N);
- case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
case ISD::BR_CC: return visitBR_CC(N);
- case ISD::BRTWOWAY_CC:return visitBRTWOWAY_CC(N);
case ISD::LOAD: return visitLOAD(N);
case ISD::STORE: return visitSTORE(N);
}
@@ -2219,35 +2215,6 @@
return SDOperand();
}
-SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
- SDOperand Chain = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
- SDOperand N2 = N->getOperand(2);
- SDOperand N3 = N->getOperand(3);
- ConstantSDNode *N1C = dyn_cast(N1);
-
- // unconditional branch to true mbb
- if (N1C && N1C->getValue() == 1)
-return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
- // unconditional branch to false mbb
- if (N1C && N1C->isNullValue())
-return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
- // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if
- // BRTWOWAY_CC is legal on the target.
- if (N1.getOpcode() == ISD::SETCC &&
- TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
-std::vector Ops;
-Ops.push_back(Chain);
-Ops.push_back(N1.getOperand(2));
-Ops.push_back(N1.getOperand(0));
-Ops.push_back(N1.getOperand(1));
-Ops.push_back(N2);
-Ops.push_back(N3);
-return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
- }
- return SDOperand();
-}
-
// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
//
SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
@@ -2273,41 +2240,6 @@
return SDOperand();
}
-SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
- SDOperand Chain = N->getOperand(0);
- SDOperand CCN = N->getOperand(1);
- SDOperand LHS = N->getOperand(2);
- SDOperand RHS = N->getOperand(3);
- SDOperand N4 = N->getOperand(4);
- SDOperand N5 = N->getOperand(5);
-
- SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
-cast(CCN)->get(), false);
- ConstantSDNode *SCCC = dyn_cast_or_null(SCC.Val);
-
- // fold select_cc lhs, rhs, x, x, cc -> x
- if (N4 == N5)
-return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
- // fold select_cc true, x, y -> x
- if (SCCC && SCCC->getValue())
-return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
- // fold select_cc false, x, y -> y
- if (SCCC && SCCC->isNullValue())
-return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
- // fold to a simpler setcc
- if (SCC.Val && SCC.getOpcode() == ISD::SETCC) {
-std::vector Ops;
-Ops.push_back(Chain);
-Ops.push_back(SCC.getOperand(2));
-Ops.push_back(SCC.getOperand(0));
-Ops.push_back(SCC.getOperand(1));
-Ops.push_back(N4);
-Ops.push_back(N5);
-return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
- }
- return SDOperand();
-}
-
SDOperand DAGCombiner::visitLOAD(SDNode *N) {
SDOperand Chain= N->getOperand(0);
SDOperand Ptr = N->getOperand(1);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.315
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.316
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.315 Wed Mar 15 16:19:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Mar 16 19:40:33 2006
@@ -945,100 +945,6 @@
break;
}
break;
- case ISD::BRCONDTWOWAY:
-Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
-switch (getTypeAction(Node->getOperand(1).ge
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.40 -> 1.41 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+0 -2) AlphaISelLowering.cpp |2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.40 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.41 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.40Thu Mar 9 08:58:25 2006 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Thu Mar 16 19:40:33 2006 @@ -48,8 +48,6 @@ addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass); addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass); - setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); - setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); setOperationAction(ISD::BR_CC,MVT::Other, Expand); setOperationAction(ISD::SELECT_CC,MVT::Other, Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td README.txt
Changes in directory llvm/lib/Target/PowerPC:
PPCBranchSelector.cpp updated: 1.21 -> 1.22
PPCISelDAGToDAG.cpp updated: 1.168 -> 1.169
PPCISelLowering.cpp updated: 1.96 -> 1.97
PPCInstrInfo.td updated: 1.185 -> 1.186
README.txt updated: 1.73 -> 1.74
---
Log message:
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
---
Diffs of the changes: (+11 -80)
PPCBranchSelector.cpp |8 ++--
PPCISelDAGToDAG.cpp | 38 --
PPCISelLowering.cpp |5 ++---
PPCInstrInfo.td |3 +--
README.txt| 37 ++---
5 files changed, 11 insertions(+), 80 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.21
llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.22
--- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.21 Wed Feb 8 13:33:26 2006
+++ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp Thu Mar 16 19:40:33 2006
@@ -48,10 +48,10 @@
static unsigned getNumBytesForInstruction(MachineInstr *MI) {
switch (MI->getOpcode()) {
case PPC::COND_BRANCH:
-// while this will be 4 most of the time, if we emit 12 it is just a
+// while this will be 4 most of the time, if we emit 8 it is just a
// minor pessimization that saves us from having to worry about
// keeping the offsets up to date later when we emit long branch glue.
-return 12;
+return 8;
case PPC::IMPLICIT_DEF_GPR: // no asm emitted
case PPC::IMPLICIT_DEF_F4: // no asm emitted
case PPC::IMPLICIT_DEF_F8: // no asm emitted
@@ -102,7 +102,6 @@
// long branch:
// bInverseCC $PC+8
// b .L_TARGET_MBB
- // b .L_FALLTHROUGH_MBB
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
++MFI) {
MachineBasicBlock *MBB = MFI;
@@ -123,8 +122,6 @@
// 3. fallthrough MBB
MachineBasicBlock *trueMBB =
MBBI->getOperand(2).getMachineBasicBlock();
-MachineBasicBlock *falseMBB =
- MBBI->getOperand(3).getMachineBasicBlock();
int Displacement = OffsetMap[trueMBB] - ByteCount;
unsigned Opcode = MBBI->getOperand(1).getImmedValue();
@@ -136,7 +133,6 @@
} else {
BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addSImm(8);
BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(trueMBB);
- BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(falseMBB);
}
// Erase the psuedo COND_BRANCH instruction, and then back up the
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.168
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.169
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.168 Thu Mar 16 12:25:23 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Mar 16 19:40:33 2006
@@ -1105,44 +1105,14 @@
N2, N3, getI32Imm(BROpc));
return;
}
- case ISD::BR_CC:
- case ISD::BRTWOWAY_CC: {
+ case ISD::BR_CC: {
SDOperand Chain;
Select(Chain, N->getOperand(0));
-MachineBasicBlock *Dest =
- cast(N->getOperand(4))->getBasicBlock();
ISD::CondCode CC = cast(N->getOperand(1))->get();
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
-
-// If this is a two way branch, then grab the fallthrough basic block
-// argument and build a PowerPC branch pseudo-op, suitable for long branch
-// conversion if necessary by the branch selection pass. Otherwise, emit a
-// standard conditional branch.
-if (N->getOpcode() == ISD::BRTWOWAY_CC) {
- SDOperand CondTrueBlock = N->getOperand(4);
- SDOperand CondFalseBlock = N->getOperand(5);
- unsigned Opc = getBCCForSetCC(CC);
- SDOperand CB =
-SDOperand(CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
-CondCode, getI32Imm(Opc),
-CondTrueBlock, CondFalseBlock,
-Chain), 0);
- Result = CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB);
-} else {
- // Iterate to the next basic block
- ilist::iterator It = BB;
- ++It;
-
- // If the fallthrough path is off the end of the function, which would be
- // undefined behavior, set it to be the same as the current block because
- // we have nothing better to set it to, and leaving it alone will cause
- // the PowerPC Branch Selection pass to crash.
- if (It == BB->getParent()->end()) It = Dest;
- Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
-getI32Imm(getBCCForSetCC(CC)),
-N->getOperand(4),
CurDAG->getBasicBlock(It),
-Chain);
-}
+Result = CurDAG->SelectNodeT
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.253 -> 1.254
---
Log message:
- Nuke 16-bit SBB instructions. We'll never use them.
- Nuke a bogus comment.
---
Diffs of the changes: (+0 -21)
X86InstrInfo.td | 21 -
1 files changed, 21 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.253
llvm/lib/Target/X86/X86InstrInfo.td:1.254
--- llvm/lib/Target/X86/X86InstrInfo.td:1.253 Tue Mar 7 17:34:23 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Thu Mar 16 20:24:04 2006
@@ -1784,7 +1784,6 @@
[(set R32:$dst, (add R32:$src1, imm:$src2))]>;
}
-// FIXME: move ADD16ri8 above ADD16ri to optimize for space.
def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
"add{w} {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>,
@@ -1926,39 +1925,19 @@
def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
"sbb{b} {$src2, $dst|$dst, $src2}",
[(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
- def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}",
- [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
- OpSize;
def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
[(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
- def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i16i8imm :$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}",
- [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
- OpSize;
def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
[(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
}
-def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
-"sbb{b} {$src2, $dst|$dst, $src2}",
-[(set R8:$dst, (sube R8:$src1, imm:$src2))]>;
-def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
-"sbb{w} {$src2, $dst|$dst, $src2}",
-[(set R16:$dst, (sube R16:$src1, imm:$src2))]>, OpSize;
-
def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (sube R32:$src1, (load addr:$src2)))]>;
def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (sube R32:$src1, imm:$src2))]>;
-
-def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (sube R16:$src1, i16immSExt8:$src2))]>,
- OpSize;
def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
"sbb{l} {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (sube R32:$src1, i32immSExt8:$src2))]>;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.127 -> 1.128 --- Log message: Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g. ADD32ri8. --- Diffs of the changes: (+18 -6) X86RegisterInfo.cpp | 24 ++-- 1 files changed, 18 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.127 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.128 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.127 Fri Feb 24 19:37:02 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Mar 16 20:25:01 2006 @@ -221,39 +221,49 @@ case X86::ADD8rr:return MakeMRInst(X86::ADD8mr , FrameIndex, MI); case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI); case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI); -case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI); -case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI); case X86::ADD8ri:return MakeMIInst(X86::ADD8mi , FrameIndex, MI); case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI); case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI); +case X86::ADD16ri8: return MakeMIInst(X86::ADD16mi8,FrameIndex, MI); +case X86::ADD32ri8: return MakeMIInst(X86::ADD32mi8,FrameIndex, MI); +case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI); +case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI); +case X86::ADC32ri8: return MakeMIInst(X86::ADC32mi8,FrameIndex, MI); case X86::SUB8rr:return MakeMRInst(X86::SUB8mr , FrameIndex, MI); case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI); case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI); -case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI); -case X86::SBB8ri:return MakeMIInst(X86::SBB8mi, FrameIndex, MI); -case X86::SBB16ri: return MakeMIInst(X86::SBB16mi, FrameIndex, MI); -case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI); case X86::SUB8ri:return MakeMIInst(X86::SUB8mi , FrameIndex, MI); case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI); case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI); +case X86::SUB16ri8: return MakeMIInst(X86::SUB16mi8,FrameIndex, MI); +case X86::SUB32ri8: return MakeMIInst(X86::SUB32mi8,FrameIndex, MI); +case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI); +case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI); +case X86::SBB32ri8: return MakeMIInst(X86::SBB32mi8,FrameIndex, MI); case X86::AND8rr:return MakeMRInst(X86::AND8mr , FrameIndex, MI); case X86::AND16rr: return MakeMRInst(X86::AND16mr, FrameIndex, MI); case X86::AND32rr: return MakeMRInst(X86::AND32mr, FrameIndex, MI); case X86::AND8ri:return MakeMIInst(X86::AND8mi , FrameIndex, MI); case X86::AND16ri: return MakeMIInst(X86::AND16mi, FrameIndex, MI); case X86::AND32ri: return MakeMIInst(X86::AND32mi, FrameIndex, MI); +case X86::AND16ri8: return MakeMIInst(X86::AND16mi8,FrameIndex, MI); +case X86::AND32ri8: return MakeMIInst(X86::AND32mi8,FrameIndex, MI); case X86::OR8rr: return MakeMRInst(X86::OR8mr , FrameIndex, MI); case X86::OR16rr:return MakeMRInst(X86::OR16mr, FrameIndex, MI); case X86::OR32rr:return MakeMRInst(X86::OR32mr, FrameIndex, MI); case X86::OR8ri: return MakeMIInst(X86::OR8mi , FrameIndex, MI); case X86::OR16ri:return MakeMIInst(X86::OR16mi, FrameIndex, MI); case X86::OR32ri:return MakeMIInst(X86::OR32mi, FrameIndex, MI); +case X86::OR16ri8: return MakeMIInst(X86::OR16mi8, FrameIndex, MI); +case X86::OR32ri8: return MakeMIInst(X86::OR32mi8, FrameIndex, MI); case X86::XOR8rr:return MakeMRInst(X86::XOR8mr , FrameIndex, MI); case X86::XOR16rr: return MakeMRInst(X86::XOR16mr, FrameIndex, MI); case X86::XOR32rr: return MakeMRInst(X86::XOR32mr, FrameIndex, MI); case X86::XOR8ri:return MakeMIInst(X86::XOR8mi , FrameIndex, MI); case X86::XOR16ri: return MakeMIInst(X86::XOR16mi, FrameIndex, MI); case X86::XOR32ri: return MakeMIInst(X86::XOR32mi, FrameIndex, MI); +case X86::XOR16ri8: return MakeMIInst(X86::XOR16mi8,FrameIndex, MI); +case X86::XOR32ri8: return MakeMIInst(X86::XOR32mi8,FrameIndex, MI); case X86::SHL8rCL: return MakeMInst( X86::SHL8mCL ,FrameIndex, MI); case X86::SHL16rCL: return MakeMInst( X86::SHL16mCL,FrameIndex, MI); case X86::SHL32rCL: return MakeMInst( X86::SHL32mCL,FrameIndex, MI); @@ -392,6 +402,8 @@ case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI); case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI); case X86::IMUL32rri: return MakeRMIInst
[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.128 -> 1.129
---
Log message:
Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
---
Diffs of the changes: (+9 -0)
X86RegisterInfo.cpp |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.128
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.129
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.128 Thu Mar 16 20:25:01 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Mar 16 20:36:22 2006
@@ -160,6 +160,11 @@
return 0;
}
+static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
+MachineInstr *MI) {
+ return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addZImm(0);
+}
+
static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
const MachineOperand& op = MI->getOperand(0);
@@ -328,6 +333,10 @@
case X86::CMP8ri:return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
+// Alias instructions
+case X86::MOV8r0:return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
+case X86::MOV16r0: return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
+case X86::MOV32r0: return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
// Alias scalar SSE instructions
case X86::FsMOVAPSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
case X86::FsMOVAPDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.108 -> 1.109
---
Log message:
Parameterize the number of integer arguments to pass in registers
---
Diffs of the changes: (+27 -17)
X86ISelLowering.cpp | 44 +++-
1 files changed, 27 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.108
llvm/lib/Target/X86/X86ISelLowering.cpp:1.109
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.108 Thu Mar 16 19:40:33 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 16 23:10:20 2006
@@ -639,6 +639,13 @@
return VReg;
}
+enum {
+ // FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments
+ // to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and
+ // EDX". Anything more is illegal.
+ FASTCC_NUM_INT_ARGS_INREGS = 2
+};
+
std::vector
X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
@@ -660,7 +667,7 @@
// 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
// used).
unsigned NumIntRegs = 0;
-
+
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
{
MVT::ValueType ObjectVT = getValueType(I->getType());
unsigned ArgIncrement = 4;
@@ -671,7 +678,7 @@
default: assert(0 && "Unhandled argument type!");
case MVT::i1:
case MVT::i8:
- if (NumIntRegs < 2) {
+ if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
if (!I->use_empty()) {
unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
X86::R8RegisterClass);
@@ -688,7 +695,7 @@
ObjSize = 1;
break;
case MVT::i16:
- if (NumIntRegs < 2) {
+ if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
if (!I->use_empty()) {
unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
X86::R16RegisterClass);
@@ -701,9 +708,9 @@
ObjSize = 2;
break;
case MVT::i32:
- if (NumIntRegs < 2) {
+ if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
if (!I->use_empty()) {
- unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
+ unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
X86::R32RegisterClass);
ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
DAG.setRoot(ArgValue.getValue(1));
@@ -714,7 +721,7 @@
ObjSize = 4;
break;
case MVT::i64:
- if (NumIntRegs == 0) {
+ if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) {
if (!I->use_empty()) {
unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
@@ -725,9 +732,9 @@
ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
}
-NumIntRegs = 2;
+NumIntRegs += 2;
break;
- } else if (NumIntRegs == 1) {
+ } else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) {
if (!I->use_empty()) {
unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
@@ -742,7 +749,7 @@
ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
}
ArgOffset += 4;
-NumIntRegs = 2;
+NumIntRegs = FASTCC_NUM_INT_ARGS_INREGS;
break;
}
ObjSize = ArgIncrement = 8;
@@ -826,7 +833,7 @@
case MVT::i8:
case MVT::i16:
case MVT::i32:
- if (NumIntRegs < 2) {
+ if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
++NumIntRegs;
break;
}
@@ -835,11 +842,11 @@
NumBytes += 4;
break;
case MVT::i64:
- if (NumIntRegs == 0) {
-NumIntRegs = 2;
+ if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) {
+NumIntRegs += 2;
break;
- } else if (NumIntRegs == 1) {
-NumIntRegs = 2;
+ } else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) {
+NumIntRegs = FASTCC_NUM_INT_ARGS_INREGS;
NumBytes += 4;
break;
}
@@ -872,7 +879,7 @@
case MVT::i8:
case MVT::i16:
case MVT::i32:
- if (NumIntRegs < 2) {
+ if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
RegValuesToPass.push_back(Args[i].first);
++NumIntRegs;
break;
@@ -888,14 +895,17 @@
break;
}
case MVT::i64:
- if (NumIntRegs < 2) {// Can pass part of it in regs?
+ // Can pass (at least) part of it in regs?
+ if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
Args[i].first, DAG.getConstant(1,
MVT::i32));
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
[llvm-commits] CVS: llvm/lib/VMCore/Makefile
Changes in directory llvm/lib/VMCore: Makefile updated: 1.11 -> 1.12 --- Log message: Two fixes: 1. Allow building of Intrinsics.gen to work for srcdir != objdir 2. Add a rule for installation of Intrinsics.gen. --- Diffs of the changes: (+5 -1) Makefile |6 +- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/VMCore/Makefile diff -u llvm/lib/VMCore/Makefile:1.11 llvm/lib/VMCore/Makefile:1.12 --- llvm/lib/VMCore/Makefile:1.11 Mon Mar 13 11:57:31 2006 +++ llvm/lib/VMCore/MakefileFri Mar 17 00:27:06 2006 @@ -18,7 +18,11 @@ include $(LEVEL)/Makefile.common -$(LEVEL)/include/llvm/Intrinsics.gen: $(LEVEL)/include/llvm/Intrinsics.td $(TBLGEN) +GENFILE:=$(PROJ_SRC_ROOT)/include/llvm/Intrinsics.gen + +$(GENFILE): $(PROJ_SRC_ROOT)/include/llvm/Intrinsics.td $(TBLGEN) $(Echo) Building Intrinsics.gen from Intrinsics.td $(Verb) $(TableGen) $< -o $@ -gen-intrinsic +install-local:: $(GENFILE) + $(DataInstall) $(GENFILE) $(PROJ_includedir)/llvm/Intrinsics.gen ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/GenerateReport.pl
Changes in directory llvm-test:
GenerateReport.pl updated: 1.27 -> 1.28
---
Log message:
Add the ability for reports to request custom hilighting of columns to
make it easier to browse reports :)
---
Diffs of the changes: (+38 -13)
GenerateReport.pl | 51 ++-
1 files changed, 38 insertions(+), 13 deletions(-)
Index: llvm-test/GenerateReport.pl
diff -u llvm-test/GenerateReport.pl:1.27 llvm-test/GenerateReport.pl:1.28
--- llvm-test/GenerateReport.pl:1.27Wed Apr 27 15:12:30 2005
+++ llvm-test/GenerateReport.pl Fri Mar 17 00:54:41 2006
@@ -96,6 +96,11 @@
open(REPORTDESC, $ReportFN) or
die "Couldn't open report description '$ReportFN'!";
+# HilightColumns - Filled in by the report if desired in HTML mode. This
+# contains a column number if the HTML version of the output should highlight a
+# cell in green/red if it is gt/lt 1.0 by a significant margin.
+my %HilightColumns;
+
my @LatexColumns; # Filled in by report if it supports Latex mode
my %LatexColumnFormat; # Filled in by report if supports latex mode
my @Graphs;# Filled in by the report if supports graph mode
@@ -201,27 +206,47 @@
if ($HTML) {
sub printCell {
my $Str = shift;
+my $ColNo = shift;
+my $IsWhite = shift;
+my $Attrs = "";
if ($Str eq '|') {
- print "";
+ $Attrs = " bgcolor='black' width='1'";
+ $Str = "";
} else {
- #print "$Str\n";
- print "$Str\n";
-}; "";
- }
- sub printLine {
-#print "\n";
+ # If the user requested that we highlight this column, check to see what
+ # number it is. If it is > 1.05, we color it green, < 0.95 we use red.
+ # If it's not a number, ignore it.
+ if ($HilightColumns{$ColNo}) {
+if ($Str =~ m/^([0-9]+).?[0-9.]*$/) {
+ if ($Str <= 0.85) {
+$Attrs = " bgcolor='#FF7070'";
+ } elsif ($Str <= 0.95) {
+$Attrs = " bgcolor='#FF'";
+ } elsif ($Str >= 1.15) {
+$Attrs = " bgcolor='#80FF80'";
+ } elsif ($Str >= 1.05) {
+$Attrs = " bgcolor='#CCFFCC'";
+ }
+}
+
+if (!$IsWhite && $Attrs eq "") {
+ # If it's not already white, make it white now.
+ $Attrs = " bgcolor=white";
+}
+ }
+};
+print "$Str";
+"";
}
print "\n";
print "\n";
map {
-#print "";
$_ = "$_"
- if $_ ne "|"; printCell $_
+ if $_ ne "|";
+printCell($_, -1)
} @Header;
- #print "";
print "\n";
- #print "" x ([EMAIL PROTECTED]);
print "\n";
my $RowCount = 0;
foreach $Row (@Values) {
@@ -229,8 +254,8 @@
$IsWhite = ++$RowCount <= 2;
print "\n";
$RowCount = 0 if ($RowCount > 3);
-map { printLine($IsWhite); printCell $_ } @$Row;
-printLine($IsWhite);
+my $ColCount = 0;
+map { printCell($_, $ColCount++, $IsWhite); } @$Row;
print "\n\n";
}
print "\n\n";
___
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[llvm-commits] CVS: llvm-test/TEST.nightly.report
Changes in directory llvm-test:
TEST.nightly.report updated: 1.38 -> 1.39
---
Log message:
Add a new LLC/LLCBETA column, to make it easier to track LLC BETA
hilight the ratio columns with red/green to make it easy to tell at a glance
if we're winning or losing.
---
Diffs of the changes: (+24 -7)
TEST.nightly.report | 31 ---
1 files changed, 24 insertions(+), 7 deletions(-)
Index: llvm-test/TEST.nightly.report
diff -u llvm-test/TEST.nightly.report:1.38 llvm-test/TEST.nightly.report:1.39
--- llvm-test/TEST.nightly.report:1.38 Wed Nov 2 10:15:15 2005
+++ llvm-test/TEST.nightly.report Fri Mar 17 01:06:34 2006
@@ -22,8 +22,8 @@
sub GCCCBERatio {
my ($Cols, $Col) = @_;
- my $GCC = $Cols->[$Col-5];
- my $CBE = $Cols->[$Col-4];
+ my $GCC = $Cols->[$Col-6];
+ my $CBE = $Cols->[$Col-5];
return "n/a" if ($GCC eq "*" or $CBE eq "*");
return sprintf("%3.2f", $GCC/$CBE) if ($GCC >= 0.1 and $CBE >= 0.1);
return "-";
@@ -31,8 +31,8 @@
sub GCCLLCRatio {
my ($Cols, $Col) = @_;
- my $GCC = $Cols->[$Col-6];
- my $LLC = $Cols->[$Col-4];
+ my $GCC = $Cols->[$Col-7];
+ my $LLC = $Cols->[$Col-5];
return "n/a" if ($GCC eq "*" or $LLC eq "*");
return sprintf("%3.2f", $GCC/$LLC) if ($GCC >= 0.1 and $LLC >= 0.1);
return "-";
@@ -40,13 +40,28 @@
sub GCCLLC_BETARatio {
my ($Cols, $Col) = @_;
- my $GCC = $Cols->[$Col-7];
- my $LLC_BETA = $Cols->[$Col-4];
+ my $GCC = $Cols->[$Col-8];
+ my $LLC_BETA = $Cols->[$Col-5];
return "n/a" if ($GCC eq "*" or $LLC_BETA eq "*");
return sprintf("%3.2f", $GCC/$LLC_BETA) if ($GCC >= 0.1 and $LLC_BETA >=
0.1);
return "-";
}
+sub LLCLLC_BETARatio { # LLC/LLC-BETA
+ my ($Cols, $Col) = @_;
+ my $LLC = $Cols->[$Col-7];
+ my $LLC_BETA = $Cols->[$Col-6];
+ return "n/a" if ($LLC eq "*" or $LLC_BETA eq "*");
+ return sprintf("%3.2f", $LLC/$LLC_BETA) if ($LLC >= 0.1 and $LLC_BETA >=
0.1);
+ return "-";
+}
+
+# highlight the RATIO columns with green/red.
+$HilightColumns{14} = 1;
+$HilightColumns{15} = 1;
+$HilightColumns{16} = 1;
+$HilightColumns{17} = 1;
+
# These are the columns for the report. The first entry is the header for the
# column, the second is the regex to use to match the value. Empty list create
# separators, and closures may be put in for custom processing.
@@ -66,7 +81,9 @@
["LLC" , 'TEST-RESULT-llc-time: program\s*([.0-9m:]+)', \&FormatTime],
["LLC-BETA" , 'TEST-RESULT-llc-beta-time:
program\s*([.0-9m:]+)',\&FormatTime],
["JIT" , 'TEST-RESULT-jit-time: program\s*([.0-9m:]+)', \&FormatTime],
+ [],
["GCC/CBE" , \&GCCCBERatio],
["GCC/LLC" , \&GCCLLCRatio],
- ["GCC/LLC-BETA" , \&GCCLLC_BETARatio]
+ ["GCC/LLC-BETA" , \&GCCLLC_BETARatio],
+ ["LLC/LLC-BETA" , \&LLCLLC_BETARatio]
);
___
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[llvm-commits] CVS: llvm/lib/VMCore/Makefile
Changes in directory llvm/lib/VMCore: Makefile updated: 1.12 -> 1.13 --- Log message: Fix use of LEVEL. --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/VMCore/Makefile diff -u llvm/lib/VMCore/Makefile:1.12 llvm/lib/VMCore/Makefile:1.13 --- llvm/lib/VMCore/Makefile:1.12 Fri Mar 17 00:27:06 2006 +++ llvm/lib/VMCore/MakefileFri Mar 17 01:39:44 2006 @@ -9,7 +9,7 @@ LEVEL = ../.. LIBRARYNAME = LLVMCore -BUILT_SOURCES = $(LEVEL)/include/llvm/Intrinsics.gen +BUILT_SOURCES = $(PROJ_SRC_ROOT)/include/llvm/Intrinsics.gen include $(LEVEL)/Makefile.config ifeq ($(ARCH),Alpha) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
