[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.9 -> 1.10
---
Log message:
Move the available queue to being inside the ListSchedule method, since it
bounds its lifetime.
---
Diffs of the changes: (+15 -10)
ScheduleDAGList.cpp | 25 +++--
1 files changed, 15 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.9
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.10
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.9 Fri Mar 3
00:23:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Sun Mar 5 14:21:55 2006
@@ -164,8 +164,6 @@
private:
// SDNode to SUnit mapping (many to one).
std::map SUnitMap;
- // Available queue.
- std::priority_queue, ls_rr_sort> Available;
// The schedule.
std::vector Sequence;
// Current scheduling cycle.
@@ -173,6 +171,9 @@
// First and last SUnit created.
SUnit *HeadSUnit, *TailSUnit;
+ typedef std::priority_queue, ls_rr_sort>
+AvailableQueueTy;
+
public:
ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
const TargetMachine &tm)
@@ -194,8 +195,8 @@
private:
SUnit *NewSUnit(SDNode *N);
- void ReleasePred(SUnit *PredSU, bool isChain = false);
- void ScheduleNode(SUnit *SU);
+ void ReleasePred(AvailableQueueTy &Avail,SUnit *PredSU, bool isChain =
false);
+ void ScheduleNode(AvailableQueueTy &Avail, SUnit *SU);
int CalcNodePriority(SUnit *SU);
void CalculatePriorities();
void ListSchedule();
@@ -220,7 +221,8 @@
/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
/// the Available queue is the count reaches zero. Also update its cycle bound.
-void ScheduleDAGList::ReleasePred(SUnit *PredSU, bool isChain) {
+void ScheduleDAGList::ReleasePred(AvailableQueueTy &Available,
+ SUnit *PredSU, bool isChain) {
SDNode *PredNode = PredSU->Node;
// FIXME: the distance between two nodes is not always == the predecessor's
@@ -251,7 +253,7 @@
/// ScheduleNode - Add the node to the schedule. Decrement the pending count of
/// its predecessors. If a predecessor pending count is zero, add it to the
/// Available queue.
-void ScheduleDAGList::ScheduleNode(SUnit *SU) {
+void ScheduleDAGList::ScheduleNode(AvailableQueueTy &Available, SUnit *SU) {
DEBUG(std::cerr << "*** Scheduling: ");
DEBUG(SU->dump(&DAG, false));
@@ -261,13 +263,13 @@
// Bottom up: release predecessors
for (std::set::iterator I1 = SU->Preds.begin(),
E1 = SU->Preds.end(); I1 != E1; ++I1) {
-ReleasePred(*I1);
+ReleasePred(Available, *I1);
SU->NumPredsLeft--;
SU->Priority1--;
}
for (std::set::iterator I2 = SU->ChainPreds.begin(),
E2 = SU->ChainPreds.end(); I2 != E2; ++I2)
-ReleasePred(*I2, true);
+ReleasePred(Available, *I2, true);
CurrCycle++;
}
@@ -280,7 +282,10 @@
/// ListSchedule - The main loop of list scheduling.
void ScheduleDAGList::ListSchedule() {
- // Add root to Available queue
+ // Available queue.
+ AvailableQueueTy Available;
+
+ // Add root to Available queue.
SUnit *Root = SUnitMap[DAG.getRoot().Val];
Available.push(Root);
@@ -300,7 +305,7 @@
for (unsigned i = 0, e = NotReady.size(); i != e; ++i)
Available.push(NotReady[i]);
-ScheduleNode(CurrNode);
+ScheduleNode(Available, CurrNode);
}
// Add entry node last
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.10 -> 1.11
---
Log message:
Add a new scheduling type. This is, of course, a hack. Proper factoring
will come later.
---
Diffs of the changes: (+8 -3)
ScheduleDAG.h | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.10
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.11
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.10Fri Feb 24 12:53:51 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Sun Mar 5 15:08:06 2006
@@ -34,17 +34,16 @@
typedef std::vector NIVector;
typedef std::vector::iterator NIIterator;
-
// Scheduling heuristics
enum SchedHeuristics {
defaultScheduling, // Let the target specify its preference.
noScheduling, // No scheduling, emit breath first sequence.
simpleScheduling, // Two pass, min. critical path, max. utilization.
simpleNoItinScheduling, // Same as above exact using generic latency.
-listSchedulingBURR // Bottom up reg reduction list scheduling.
+listSchedulingBURR, // Bottom up reg reduction list scheduling.
+listSchedulingG5// G5-specific scheduler. FIXME: parameterize
better
};
-
//======//
///
/// Node group - This struct is used to manage flagged node groups.
@@ -359,6 +358,12 @@
/// reduction list scheduler.
ScheduleDAG* createBURRListDAGScheduler(SelectionDAG &DAG,
MachineBasicBlock *BB);
+
+ /// createTDG5ListDAGScheduler - This creates a top-down list scheduler for
+ /// the PowerPC G5. FIXME: pull the priority function out into the PPC
+ /// backend!
+ ScheduleDAG* createTDG5ListDAGScheduler(SelectionDAG &DAG,
+ MachineBasicBlock *BB);
}
#endif
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.179 -> 1.180
ScheduleDAGList.cpp updated: 1.10 -> 1.11
---
Log message:
Split the list scheduler into top-down and bottom-up pieces. The priority
function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.
---
Diffs of the changes: (+185 -43)
ScheduleDAGList.cpp | 222 +--
SelectionDAGISel.cpp |6 +
2 files changed, 185 insertions(+), 43 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.179
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.180
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.179Sat Mar 4
23:09:38 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Mar 5 15:10:33 2006
@@ -76,6 +76,8 @@
"except using generic latency"),
clEnumValN(listSchedulingBURR, "list-burr",
"Bottom up register reduction list scheduling"),
+ clEnumValN(listSchedulingG5, "list-g5",
+ "Scheduling for the PowerPC G5"),
clEnumValEnd));
} // namespace
@@ -2470,6 +2472,10 @@
break;
case listSchedulingBURR:
SL = createBURRListDAGScheduler(DAG, BB);
+break;
+ case listSchedulingG5:
+SL = createTDG5ListDAGScheduler(DAG, BB);
+break;
}
BB = SL->Run();
delete SL;
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.10
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.11
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.10 Sun Mar 5
14:21:55 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Sun Mar 5 15:10:33 2006
@@ -73,15 +73,16 @@
}
if (All) {
-std::cerr << "# preds left : " << NumPredsLeft << "\n";
-std::cerr << "# succs left : " << NumSuccsLeft << "\n";
-std::cerr << "# chain preds left : " << NumChainPredsLeft << "\n";
-std::cerr << "# chain succs left : " << NumChainSuccsLeft << "\n";
-std::cerr << "Latency: " << Latency << "\n";
-std::cerr << "Priority : " << Priority1 << " , " << Priority2 <<
"\n";
+std::cerr << " # preds left : " << NumPredsLeft << "\n";
+std::cerr << " # succs left : " << NumSuccsLeft << "\n";
+std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
+std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
+std::cerr << " Latency: " << Latency << "\n";
+std::cerr << " Priority : " << Priority1 << " , "
+ << Priority2 << "\n";
if (Preds.size() != 0) {
- std::cerr << "Predecessors :\n";
+ std::cerr << " Predecessors:\n";
for (std::set::const_iterator I = Preds.begin(),
E = Preds.end(); I != E; ++I) {
std::cerr << "";
@@ -89,7 +90,7 @@
}
}
if (ChainPreds.size() != 0) {
- std::cerr << "Chained Preds :\n";
+ std::cerr << " Chained Preds:\n";
for (std::set::const_iterator I = ChainPreds.begin(),
E = ChainPreds.end(); I != E; ++I) {
std::cerr << "";
@@ -97,7 +98,7 @@
}
}
if (Succs.size() != 0) {
- std::cerr << "Successors:\n";
+ std::cerr << " Successors:\n";
for (std::set::const_iterator I = Succs.begin(),
E = Succs.end(); I != E; ++I) {
std::cerr << "";
@@ -105,7 +106,7 @@
}
}
if (ChainSuccs.size() != 0) {
- std::cerr << "Chained succs :\n";
+ std::cerr << " Chained succs:\n";
for (std::set::const_iterator I = ChainSuccs.begin(),
E = ChainSuccs.end(); I != E; ++I) {
std::cerr << "";
@@ -171,14 +172,18 @@
// First and last SUnit created.
SUnit *HeadSUnit, *TailSUnit;
+ /// isBottomUp - This is true if the scheduling problem is bottom-up, false
if
+ /// it is top-down.
+ bool isBottomUp;
+
typedef std::priority_queue, ls_rr_sort>
AvailableQueueTy;
public:
ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
- const TargetMachine &tm)
+ const TargetMachine &tm, bool isbottomup)
: ScheduleDAG(listSchedulingBURR, dag, bb, tm),
- CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL) {};
+ CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL), isBottomUp(isbottomup) {}
~ScheduleDAGList() {
SUnit *SU = HeadSUnit;
@@ -196,10 +201,13 @@
private:
SUnit *NewSUnit(SDNode *N);
void ReleasePred(AvailableQueueTy &Avail,SUnit *PredSU, bool isChain =
false);
- void ScheduleNode(AvailableQueueTy &Avail, SUnit *SU);
+ void ReleaseSucc(AvailableQueueTy &Avail,SUnit *SuccSU, bool isChain =
false);
+ void ScheduleNodeBottomUp(AvailableQueueTy &Avail, SUnit *SU);
+ void Schedule
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.11 -> 1.12
---
Log message:
Breathe some life into a comment.
---
Diffs of the changes: (+1 -1)
ScheduleDAG.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.11
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.12
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.11Sun Mar 5 15:08:06 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Sun Mar 5 15:20:20 2006
@@ -37,7 +37,7 @@
// Scheduling heuristics
enum SchedHeuristics {
defaultScheduling, // Let the target specify its preference.
-noScheduling, // No scheduling, emit breath first sequence.
+noScheduling, // No scheduling, emit breadth first sequence.
simpleScheduling, // Two pass, min. critical path, max. utilization.
simpleNoItinScheduling, // Same as above exact using generic latency.
listSchedulingBURR, // Bottom up reg reduction list scheduling.
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.267 -> 1.268
---
Log message:
Fix VC++ compilation error.
---
Diffs of the changes: (+5 -0)
SelectionDAG.cpp |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.267
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.268
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.267Sat Mar 4
23:30:57 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Mar 5 15:43:37 2006
@@ -29,6 +29,11 @@
#include
using namespace llvm;
+#ifdef _MSC_VER
+#include
+#define copysign _copysign
+#endif
+
static bool isCommutativeBinOp(unsigned Opcode) {
switch (Opcode) {
case ISD::ADD:
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[llvm-commits] CVS: llvm/tools/bugpoint/CrashDebugger.cpp
Changes in directory llvm/tools/bugpoint:
CrashDebugger.cpp updated: 1.45 -> 1.46
---
Log message:
For transforms the behave differently if main goes away, add an option to
prevent bugpoint from removing main
---
Diffs of the changes: (+13 -0)
CrashDebugger.cpp | 13 +
1 files changed, 13 insertions(+)
Index: llvm/tools/bugpoint/CrashDebugger.cpp
diff -u llvm/tools/bugpoint/CrashDebugger.cpp:1.45
llvm/tools/bugpoint/CrashDebugger.cpp:1.46
--- llvm/tools/bugpoint/CrashDebugger.cpp:1.45 Mon Aug 1 21:16:17 2005
+++ llvm/tools/bugpoint/CrashDebugger.cpp Sun Mar 5 16:21:36 2006
@@ -27,10 +27,18 @@
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Utils/Cloning.h"
#include "llvm/Support/FileUtilities.h"
+#include "llvm/Support/CommandLine.h"
#include
#include
using namespace llvm;
+namespace {
+ cl::opt
+ KeepMain("keep-main",
+ cl::desc("Force function reduction to keep main"),
+ cl::init(false));
+}
+
namespace llvm {
class ReducePassList : public ListReducer {
BugDriver &BD;
@@ -109,6 +117,11 @@
}
bool ReduceCrashingFunctions::TestFuncs(std::vector &Funcs) {
+
+ //if main isn't present, claim there is no problem
+ if (KeepMain && find(Funcs.begin(), Funcs.end(),
BD.getProgram()->getMainFunction()) == Funcs.end())
+return false;
+
// Clone the program to try hacking it apart...
Module *M = CloneModule(BD.getProgram());
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[llvm-commits] CVS: llvm-poolalloc/Regressions/2006-03-05.vaargCall.ll
Changes in directory llvm-poolalloc/Regressions:
2006-03-05.vaargCall.ll added (r1.1)
---
Log message:
a call to vaarg function fails in pc
---
Diffs of the changes: (+406 -0)
2006-03-05.vaargCall.ll | 406
1 files changed, 406 insertions(+)
Index: llvm-poolalloc/Regressions/2006-03-05.vaargCall.ll
diff -c /dev/null llvm-poolalloc/Regressions/2006-03-05.vaargCall.ll:1.1
*** /dev/null Sun Mar 5 16:19:56 2006
--- llvm-poolalloc/Regressions/2006-03-05.vaargCall.ll Sun Mar 5 16:19:46 2006
***
*** 0
--- 1,406
+ ; ModuleID = 'bugpoint-reduced-simplified.bc'
+ target endian = little
+ target pointersize = 64
+ target triple = "alphaev6-unknown-linux-gnu"
+ deplibs = [ "c", "crtend" ]
+ %struct.arg_list = type { int, %struct.arg_list* }
+ %typedef.YYSTYPE = type { sbyte*, sbyte, int, %struct.arg_list* }
+ %yyv = external global [150 x %typedef.YYSTYPE] ; <[150 x
%typedef.YYSTYPE]*> [#uses=1]
+ %.str_11 = external global [26 x sbyte] ; <[26 x sbyte]*>
[#uses=0]
+
+ implementation ; Functions:
+
+ void %warn(int, ...) {
+ entry:
+ ret void
+ }
+
+ fastcc void %lookup(sbyte* %name) {
+ entry:
+ br bool false, label %then.0, label %no_exit.i
+
+ no_exit.i:; preds = %entry
+ ret void
+
+ then.0: ; preds = %entry
+ tail call void (int, ...)* %warn( int 0, sbyte* %name )
+ ret void
+ }
+
+ fastcc void %addbyte() {
+ entry:
+ ret void
+ }
+
+ void %main() {
+ entry:
+ switch int 0, label %switchexit [
+int -1, label %loopexit
+int 118, label %label.5
+int 115, label %label.4
+int 119, label %label.3
+int 105, label %label.2
+int 108, label %label.1
+int 99, label %label.0
+ ]
+
+ label.0: ; preds = %entry
+ ret void
+
+ label.1: ; preds = %entry
+ ret void
+
+ label.2: ; preds = %entry
+ ret void
+
+ label.3: ; preds = %entry
+ ret void
+
+ label.4: ; preds = %entry
+ ret void
+
+ label.5: ; preds = %entry
+ ret void
+
+ switchexit: ; preds = %entry
+ ret void
+
+ loopexit: ; preds = %entry
+ %tmp.11.i = getelementptr %typedef.YYSTYPE* getelementptr ([150 x
%typedef.YYSTYPE]* %yyv, long 0, long -1), long 1, uint 0 ;
[#uses=2]
+ br bool false, label %yydefault.preheader.i, label %endif.1.i2
+
+ yystack.i:; preds = %endif.15.i
+ ret void
+
+ endif.1.i2: ; preds = %loopexit
+ ret void
+
+ yydefault.preheader.i:; preds = %loopexit
+ switch short 0, label %endif.12.i [
+short -2, label %then.7.i
+short 0, label %then.12.i
+ ]
+
+ then.7.i: ; preds = %yydefault.preheader.i
+ ret void
+
+ then.12.i:; preds = %yydefault.preheader.i
+ ret void
+
+ endif.12.i: ; preds = %yydefault.preheader.i
+ br bool false, label %endif.15.i, label %then.15.i
+
+ then.15.i:; preds = %endif.12.i
+ ret void
+
+ endif.15.i: ; preds = %endif.12.i
+ switch int 0, label %yystack.i [
+int 97, label %label.86.i
+int 96, label %label.85.i
+int 95, label %label.84.i
+int 94, label %label.83.i
+int 93, label %label.82.i
+int 92, label %label.81.i
+int 91, label %label.80.i
+int 90, label %label.79.i
+int 89, label %label.78.i
+int 88, label %label.77.i
+int 87, label %label.76.i
+int 86, label %label.75.i
+int 85, label %label.74.i
+int 84, label %label.73.i
+int 83, label %label.72.i
+int 82, label %label.71.i
+int 81, label %label.70.i
+int 80, label %label.69.i
+int 79, label %label.68.i
+int 78, label %label.67.i
+int 77, label %label.66.i
+int 76, label %label.61.i
+int 75, label %label.60.i
+int 74, label %label.59.i
+int 73, label %label.58.i
+int 72, label %label.57.i
+int 71, label %label.56.i
+int 70, label %label.55.i
+int 69, label %label.54.i
+int 68, label %label.53.i
+int 67, label %label.52.i
+int 65, label %label.51.i
+int 64, label %label.50.i
+int 63, label %label.49.i
+int 62, label %label.48.i
+int 61, label %label.47.i
+int 59, label %label.46.i
+int 54, label %la
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.11 -> 1.12
---
Log message:
Add basic hazard recognizer support. noop insertion isn't complete yet though.
---
Diffs of the changes: (+104 -15)
ScheduleDAGList.cpp | 119 +---
1 files changed, 104 insertions(+), 15 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.11
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.12
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.11 Sun Mar 5
15:10:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Sun Mar 5 16:45:01 2006
@@ -160,6 +160,52 @@
}
};
+
+/// HazardRecognizer - This determines whether or not an instruction can be
+/// issued this cycle, and whether or not a noop needs to be inserted to handle
+/// the hazard.
+namespace {
+ class HazardRecognizer {
+ public:
+virtual ~HazardRecognizer() {}
+
+enum HazardType {
+ NoHazard, // This instruction can be emitted at this cycle.
+ Hazard,// This instruction can't be emitted at this cycle.
+ NoopHazard,// This instruction can't be emitted, and needs noops.
+};
+
+/// getHazardType - Return the hazard type of emitting this node. There
are
+/// three possible results. Either:
+/// * NoHazard: it is legal to issue this instruction on this cycle.
+/// * Hazard: issuing this instruction would stall the machine. If some
+/// other instruction is available, issue it first.
+/// * NoopHazard: issuing this instruction would break the program. If
+/// some other instruction can be issued, do so, otherwise issue a
noop.
+virtual HazardType getHazardType(SDNode *Node) {
+ return NoHazard;
+}
+
+/// EmitInstruction - This callback is invoked when an instruction is
+/// emitted, to advance the hazard state.
+virtual void EmitInstruction(SDNode *Node) {
+}
+
+/// AdvanceCycle - This callback is invoked when no instructions can be
+/// issued on this cycle without a hazard. This should increment the
+/// internal state of the hazard recognizer so that previously "Hazard"
+/// instructions will now not be hazards.
+virtual void AdvanceCycle() {
+}
+
+/// EmitNoop - This callback is invoked when a noop was added to the
+/// instruction stream.
+virtual void EmitNoop() {
+}
+ };
+}
+
+
/// ScheduleDAGList - List scheduler.
class ScheduleDAGList : public ScheduleDAG {
private:
@@ -176,14 +222,21 @@
/// it is top-down.
bool isBottomUp;
+ /// HazardRec - The hazard recognizer to use.
+ HazardRecognizer *HazardRec;
+
typedef std::priority_queue, ls_rr_sort>
AvailableQueueTy;
public:
ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
- const TargetMachine &tm, bool isbottomup)
+ const TargetMachine &tm, bool isbottomup,
+ HazardRecognizer *HR = 0)
: ScheduleDAG(listSchedulingBURR, dag, bb, tm),
- CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL), isBottomUp(isbottomup) {}
+ CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL), isBottomUp(isbottomup) {
+ if (HR == 0) HR = new HazardRecognizer();
+HazardRec = HR;
+}
~ScheduleDAGList() {
SUnit *SU = HeadSUnit;
@@ -192,6 +245,8 @@
delete SU;
SU = NextSU;
}
+
+delete HazardRec;
}
void Schedule();
@@ -411,7 +466,8 @@
// Emit the entry node first.
SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
ScheduleNodeTopDown(Available, Entry);
-
+ HazardRec->EmitInstruction(Entry->Node);
+
// All leaves to Available queue.
for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
// It is available if it has no predecessors.
@@ -423,23 +479,46 @@
// priority. If it is not ready put it back. Schedule the node.
std::vector NotReady;
while (!Available.empty()) {
-SUnit *CurrNode = Available.top();
-Available.pop();
-
-// FIXME: when priorities make sense, reenable this.
-while (0 && !isReady(CurrNode, CurrCycle)) {
- NotReady.push_back(CurrNode);
- CurrNode = Available.top();
- Available.pop();
-}
+SUnit *FoundNode = 0;
+bool HasNoopHazards = false;
+do {
+ SUnit *CurrNode = Available.top();
+ Available.pop();
+ HazardRecognizer::HazardType HT =
+HazardRec->getHazardType(CurrNode->Node);
+ if (HT == HazardRecognizer::NoHazard) {
+FoundNode = CurrNode;
+break;
+ }
+
+ // Remember if this is a noop hazard.
+ HasNoopHazards |= HT == HazardRecognizer::NoopHazard;
+
+ NotReady.push_back(CurrNode);
+} while (!Available.empty());
+
// Add the nodes that aren't ready back onto the available list.
while (!NotReady.empty()) {
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.12 -> 1.13
---
Log message:
Implement G5HazardRecognizer as a trivial thing that wants 5 cycles between
copyfromreg nodes. Clearly useful!
---
Diffs of the changes: (+42 -2)
ScheduleDAGList.cpp | 44 ++--
1 files changed, 42 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.12
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.13
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.12 Sun Mar 5
16:45:01 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Sun Mar 5 17:13:56 2006
@@ -19,6 +19,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
+#include "llvm/ADT/Statistic.h"
#include
#include
#include
@@ -27,6 +28,8 @@
using namespace llvm;
namespace {
+ Statistic<> NumNoops ("scheduler", "Number of noops inserted");
+ Statistic<> NumStalls("scheduler", "Number of pipeline stalls");
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or a
/// group of nodes flagged together.
@@ -511,13 +514,17 @@
} else if (!HasNoopHazards) {
// Otherwise, we have a pipeline stall, but no other problem, just
advance
// the current cycle and try again.
+ DEBUG(std::cerr << "*** Advancing cycle, no work to do");
HazardRec->AdvanceCycle();
+ ++NumStalls;
} else {
// Otherwise, we have no instructions to issue and we have instructions
// that will fault if we don't do this right. This is the case for
// processors without pipeline interlocks and other cases.
+ DEBUG(std::cerr << "*** Emitting noop");
HazardRec->EmitNoop();
// FIXME: Add a noop to the schedule!!
+ ++NumNoops;
}
}
@@ -731,11 +738,44 @@
}
/// G5HazardRecognizer - A hazard recognizer for the PowerPC G5 processor.
-/// FIXME: Implement
/// FIXME: Move to the PowerPC backend.
class G5HazardRecognizer : public HazardRecognizer {
+ // Totally bogus hazard recognizer, used to test noop insertion. This
requires
+ // a noop between copyfromreg's.
+ unsigned EmittedCopyFromReg;
public:
- G5HazardRecognizer() {}
+ G5HazardRecognizer() {
+EmittedCopyFromReg = 0;
+ }
+
+ virtual HazardType getHazardType(SDNode *Node) {
+if (Node->getOpcode() == ISD::CopyFromReg && EmittedCopyFromReg)
+ return NoopHazard;
+return NoHazard;
+ }
+
+ /// EmitInstruction - This callback is invoked when an instruction is
+ /// emitted, to advance the hazard state.
+ virtual void EmitInstruction(SDNode *Node) {
+if (Node->getOpcode() == ISD::CopyFromReg) {
+ EmittedCopyFromReg = 5;
+} else if (EmittedCopyFromReg) {
+ --EmittedCopyFromReg;
+}
+ }
+
+ /// AdvanceCycle - This callback is invoked when no instructions can be
+ /// issued on this cycle without a hazard. This should increment the
+ /// internal state of the hazard recognizer so that previously "Hazard"
+ /// instructions will now not be hazards.
+ virtual void AdvanceCycle() {
+ }
+
+ /// EmitNoop - This callback is invoked when a noop was added to the
+ /// instruction stream.
+ virtual void EmitNoop() {
+--EmittedCopyFromReg;
+ }
};
___
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.58 -> 1.59
---
Log message:
custom lowered nodes are legal too
---
Diffs of the changes: (+2 -1)
TargetLowering.h |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.58
llvm/include/llvm/Target/TargetLowering.h:1.59
--- llvm/include/llvm/Target/TargetLowering.h:1.58 Fri Mar 3 00:58:59 2006
+++ llvm/include/llvm/Target/TargetLowering.h Sun Mar 5 17:49:19 2006
@@ -192,7 +192,8 @@
/// isOperationLegal - Return true if the specified operation is legal on
this
/// target.
bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
-return getOperationAction(Op, VT) == Legal;
+return getOperationAction(Op, VT) == Legal ||
+ getOperationAction(Op, VT) == Custom;
}
/// getTypeToPromoteTo - If the action for this operation is to promote, this
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.12 -> 1.13
---
Log message:
add an emitnoop method
---
Diffs of the changes: (+6 -2)
ScheduleDAG.h |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.12
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.13
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.12Sun Mar 5 15:20:20 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Sun Mar 5 17:50:42 2006
@@ -308,14 +308,18 @@
/// EmitNode - Generate machine code for an node and needed dependencies.
///
void EmitNode(NodeInfo *NI);
-
+
+/// EmitNoop - Emit a noop instruction.
+///
+void EmitNoop();
+
/// EmitAll - Emit all nodes in schedule sorted order.
///
void EmitAll();
/// Schedule - Order nodes according to selected style.
///
-virtual void Schedule() {};
+virtual void Schedule() {}
/// printNI - Print node info.
///
___
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h
Changes in directory llvm/include/llvm/Target:
TargetInstrInfo.h updated: 1.83 -> 1.84
---
Log message:
add a hook to insert a noop
---
Diffs of the changes: (+7 -0)
TargetInstrInfo.h |7 +++
1 files changed, 7 insertions(+)
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.83
llvm/include/llvm/Target/TargetInstrInfo.h:1.84
--- llvm/include/llvm/Target/TargetInstrInfo.h:1.83 Thu Feb 2 14:11:55 2006
+++ llvm/include/llvm/Target/TargetInstrInfo.h Sun Mar 5 17:48:51 2006
@@ -273,6 +273,13 @@
return MI;
}
+ /// insertNoop - Insert a noop into the instruction stream at the specified
+ /// point.
+ virtual void insertNoop(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
+assert(0 && "Target didn't implement insertNoop!");
+abort();
+ }
//-
// Code generation support for creating individual machine instructions
___
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[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/add.ll
Changes in directory llvm/test/Regression/Transforms/InstCombine:
add.ll updated: 1.29 -> 1.30
---
Log message:
new testcase I forgot to check in earlier
---
Diffs of the changes: (+7 -0)
add.ll |7 +++
1 files changed, 7 insertions(+)
Index: llvm/test/Regression/Transforms/InstCombine/add.ll
diff -u llvm/test/Regression/Transforms/InstCombine/add.ll:1.29
llvm/test/Regression/Transforms/InstCombine/add.ll:1.30
--- llvm/test/Regression/Transforms/InstCombine/add.ll:1.29 Sat Mar 4
00:02:36 2006
+++ llvm/test/Regression/Transforms/InstCombine/add.ll Sun Mar 5 17:53:04 2006
@@ -220,3 +220,10 @@
%D = sub int %C, 20
ret int %D
}
+
+int %test32(int %A) {
+ %B = add int %A, 4
+ %C = shl int %B, ubyte 2
+ %D = sub int %C, 16
+ ret int %D
+}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.14 -> 1.15 --- Log message: Comment fixes --- Diffs of the changes: (+2 -2) ScheduleDAGList.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.14 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.15 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.14 Sun Mar 5 17:51:47 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Sun Mar 5 17:59:20 2006 @@ -214,7 +214,7 @@ private: // SDNode to SUnit mapping (many to one). std::map SUnitMap; - // The schedule. Null SUnit*'s represend noop instructions. + // The schedule. Null SUnit*'s represent noop instructions. std::vector Sequence; // Current scheduling cycle. unsigned CurrCycle; @@ -523,7 +523,7 @@ // processors without pipeline interlocks and other cases. DEBUG(std::cerr << "*** Emitting noop"); HazardRec->EmitNoop(); - Sequence.push_back(0); // NULL SUnit -> noop + Sequence.push_back(0); // NULL SUnit* -> noop ++NumNoops; } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.268 -> 1.269
---
Log message:
Don't depend on the C99 copysign function, implement it ourselves.
---
Diffs of the changes: (+17 -7)
SelectionDAG.cpp | 24 +---
1 files changed, 17 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.268
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.269
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.268Sun Mar 5
15:43:37 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Mar 5 17:57:58 2006
@@ -29,11 +29,6 @@
#include
using namespace llvm;
-#ifdef _MSC_VER
-#include
-#define copysign _copysign
-#endif
-
static bool isCommutativeBinOp(unsigned Opcode) {
switch (Opcode) {
case ISD::ADD:
@@ -1255,8 +1250,23 @@
case ISD::FREM :
if (C2) return getConstantFP(fmod(C1, C2), VT);
break;
- case ISD::FCOPYSIGN:
-return getConstantFP(copysign(C1, C2), VT);
+ case ISD::FCOPYSIGN: {
+union {
+ double F;
+ uint64_t I;
+} u1;
+union {
+ double F;
+ int64_t I;
+} u2;
+u1.F = C1;
+u2.F = C2;
+if (u2.I < 0) // Sign bit of RHS set?
+ u1.I |= 1ULL << 63; // Set the sign bit of the LHS.
+else
+ u1.I &= (1ULL << 63)-1; // Clear the sign bit of the LHS.
+return getConstantFP(u1.F, VT);
+ }
default: break;
}
} else { // Cannonicalize constant to RHS if commutative
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.71 -> 1.72
ScheduleDAGList.cpp updated: 1.13 -> 1.14
---
Log message:
When a hazard recognizer needs noops to be inserted, do so. This represents
noops as null pointers in the instruction sequence.
---
Diffs of the changes: (+19 -10)
ScheduleDAG.cpp |4
ScheduleDAGList.cpp | 25 +++--
2 files changed, 19 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.71
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.72
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.71 Sat Feb 25 03:53:49 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Sun Mar 5 17:51:47 2006
@@ -370,6 +370,10 @@
NI->VRBase = VRBase;
}
+void ScheduleDAG::EmitNoop() {
+ TII->insertNoop(*BB, BB->end());
+}
+
/// EmitAll - Emit all nodes in schedule sorted order.
///
void ScheduleDAG::EmitAll() {
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.13
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.14
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.13 Sun Mar 5
17:13:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Sun Mar 5 17:51:47 2006
@@ -214,7 +214,7 @@
private:
// SDNode to SUnit mapping (many to one).
std::map SUnitMap;
- // The schedule.
+ // The schedule. Null SUnit*'s represend noop instructions.
std::vector Sequence;
// Current scheduling cycle.
unsigned CurrCycle;
@@ -523,7 +523,7 @@
// processors without pipeline interlocks and other cases.
DEBUG(std::cerr << "*** Emitting noop");
HazardRec->EmitNoop();
- // FIXME: Add a noop to the schedule!!
+ Sequence.push_back(0); // NULL SUnit -> noop
++NumNoops;
}
}
@@ -688,21 +688,26 @@
/// EmitSchedule - Emit the machine code in scheduled order.
void ScheduleDAGList::EmitSchedule() {
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
-SDNode *N;
-SUnit *SU = Sequence[i];
-for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++) {
- N = SU->FlaggedNodes[j];
- EmitNode(getNI(N));
+if (SUnit *SU = Sequence[i]) {
+ for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++) {
+SDNode *N = SU->FlaggedNodes[j];
+EmitNode(getNI(N));
+ }
+ EmitNode(getNI(SU->Node));
+} else {
+ // Null SUnit* is a noop.
+ EmitNoop();
}
-EmitNode(getNI(SU->Node));
}
}
/// dump - dump the schedule.
void ScheduleDAGList::dump() const {
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
-SUnit *SU = Sequence[i];
-SU->dump(&DAG, false);
+if (SUnit *SU = Sequence[i])
+ SU->dump(&DAG, false);
+else
+ std::cerr << " NOOP \n";
}
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCInstrInfo.h PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.16 -> 1.17
PPCInstrInfo.h updated: 1.11 -> 1.12
PPCInstrInfo.td updated: 1.178 -> 1.179
---
Log message:
implement TII::insertNoop
---
Diffs of the changes: (+8 -1)
PPCInstrInfo.cpp |5 +
PPCInstrInfo.h |3 +++
PPCInstrInfo.td |1 -
3 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.16
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.17
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.16 Thu Feb 2 15:07:50 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppSun Mar 5 17:49:55 2006
@@ -146,3 +146,8 @@
MI->getOperand(5).setImmedValue((MB-1) & 31);
return MI;
}
+
+void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
+ BuildMI(MBB, MI, PPC::NOP, 0);
+}
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.h
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.h:1.11
llvm/lib/Target/PowerPC/PPCInstrInfo.h:1.12
--- llvm/lib/Target/PowerPC/PPCInstrInfo.h:1.11 Thu Feb 2 14:16:12 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.h Sun Mar 5 17:49:55 2006
@@ -46,6 +46,9 @@
// rotate amt is zero. We also have to munge the immediates a bit.
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
+ virtual void insertNoop(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const;
+
static unsigned invertPPCBranchOpcode(unsigned Opcode) {
switch (Opcode) {
default: assert(0 && "Unknown PPC branch opcode!");
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.178
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.179
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.178 Tue Feb 28 23:50:56 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sun Mar 5 17:49:55 2006
@@ -229,7 +229,6 @@
i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
}
-
let isTerminator = 1, noResults = 1 in {
let isReturn = 1 in
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h SelectionDAGISel.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.13 -> 1.14
SelectionDAGISel.h updated: 1.9 -> 1.10
---
Log message:
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
targets can implement them. Make the top-down scheduler non-g5-specific.
---
Diffs of the changes: (+57 -6)
ScheduleDAG.h | 58 +++--
SelectionDAGISel.h |5
2 files changed, 57 insertions(+), 6 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.13
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.14
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.13Sun Mar 5 17:50:42 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Sun Mar 5 18:20:29 2006
@@ -41,7 +41,53 @@
simpleScheduling, // Two pass, min. critical path, max. utilization.
simpleNoItinScheduling, // Same as above exact using generic latency.
listSchedulingBURR, // Bottom up reg reduction list scheduling.
-listSchedulingG5// G5-specific scheduler. FIXME: parameterize
better
+listSchedulingTD// Top-down list scheduler.
+ };
+
+ /// HazardRecognizer - This determines whether or not an instruction can be
+ /// issued this cycle, and whether or not a noop needs to be inserted to
handle
+ /// the hazard.
+ class HazardRecognizer {
+ public:
+virtual ~HazardRecognizer();
+
+enum HazardType {
+ NoHazard, // This instruction can be emitted at this cycle.
+ Hazard,// This instruction can't be emitted at this cycle.
+ NoopHazard,// This instruction can't be emitted, and needs noops.
+};
+
+/// StartBasicBlock - This is called when a new basic block is started.
+///
+virtual void StartBasicBlock() {}
+
+/// getHazardType - Return the hazard type of emitting this node. There
are
+/// three possible results. Either:
+/// * NoHazard: it is legal to issue this instruction on this cycle.
+/// * Hazard: issuing this instruction would stall the machine. If some
+/// other instruction is available, issue it first.
+/// * NoopHazard: issuing this instruction would break the program. If
+/// some other instruction can be issued, do so, otherwise issue a
noop.
+virtual HazardType getHazardType(SDNode *Node) {
+ return NoHazard;
+}
+
+/// EmitInstruction - This callback is invoked when an instruction is
+/// emitted, to advance the hazard state.
+virtual void EmitInstruction(SDNode *Node) {
+}
+
+/// AdvanceCycle - This callback is invoked when no instructions can be
+/// issued on this cycle without a hazard. This should increment the
+/// internal state of the hazard recognizer so that previously "Hazard"
+/// instructions will now not be hazards.
+virtual void AdvanceCycle() {
+}
+
+/// EmitNoop - This callback is invoked when a noop was added to the
+/// instruction stream.
+virtual void EmitNoop() {
+}
};
//======//
@@ -363,11 +409,11 @@
ScheduleDAG* createBURRListDAGScheduler(SelectionDAG &DAG,
MachineBasicBlock *BB);
- /// createTDG5ListDAGScheduler - This creates a top-down list scheduler for
- /// the PowerPC G5. FIXME: pull the priority function out into the PPC
- /// backend!
- ScheduleDAG* createTDG5ListDAGScheduler(SelectionDAG &DAG,
- MachineBasicBlock *BB);
+ /// createTDListDAGScheduler - This creates a top-down list scheduler with
+ /// the specified hazard recognizer.
+ ScheduleDAG* createTDListDAGScheduler(SelectionDAG &DAG,
+MachineBasicBlock *BB,
+HazardRecognizer &HR);
}
#endif
Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.9
llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.10
--- llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.9Thu Feb 23 20:12:52 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGISel.hSun Mar 5 18:20:29 2006
@@ -28,6 +28,7 @@
class MachineInstr;
class TargetLowering;
class FunctionLoweringInfo;
+ class HazardRecognizer;
/// SelectionDAGISel - This is the common base class used for
SelectionDAG-based
/// pattern-matching instruction selectors.
@@ -61,6 +62,10 @@
return true;
}
+ /// GetTargetHazardRecognizer - Return the hazard recognizer to use for this
+ /// target when scheduling the DAG.
+ virtual HazardRecognizer &GetTargetHazardRecognizer();
+
protected:
/// Pick a safe ordering and emit instructions for each target node in the
/// graph.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.180 -> 1.181
ScheduleDAGList.cpp updated: 1.15 -> 1.16
---
Log message:
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
---
Diffs of the changes: (+32 -112)
ScheduleDAGList.cpp | 130 ---
SelectionDAGISel.cpp | 14 +++--
2 files changed, 32 insertions(+), 112 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.180
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.181
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.180Sun Mar 5
15:10:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Mar 5 18:22:00 2006
@@ -76,8 +76,8 @@
"except using generic latency"),
clEnumValN(listSchedulingBURR, "list-burr",
"Bottom up register reduction list scheduling"),
- clEnumValN(listSchedulingG5, "list-g5",
- "Scheduling for the PowerPC G5"),
+ clEnumValN(listSchedulingTD, "list-td",
+ "Top-down list scheduler"),
clEnumValEnd));
} // namespace
@@ -2473,14 +2473,20 @@
case listSchedulingBURR:
SL = createBURRListDAGScheduler(DAG, BB);
break;
- case listSchedulingG5:
-SL = createTDG5ListDAGScheduler(DAG, BB);
+ case listSchedulingTD:
+SL = createTDListDAGScheduler(DAG, BB, GetTargetHazardRecognizer());
break;
}
BB = SL->Run();
delete SL;
}
+HazardRecognizer &SelectionDAGISel::
+GetTargetHazardRecognizer() {
+ static HazardRecognizer DefaultRecognizer;
+ return DefaultRecognizer;
+}
+
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
void SelectionDAGISel::
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.15
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.16
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.15 Sun Mar 5
17:59:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Sun Mar 5 18:22:00 2006
@@ -164,51 +164,6 @@
};
-/// HazardRecognizer - This determines whether or not an instruction can be
-/// issued this cycle, and whether or not a noop needs to be inserted to handle
-/// the hazard.
-namespace {
- class HazardRecognizer {
- public:
-virtual ~HazardRecognizer() {}
-
-enum HazardType {
- NoHazard, // This instruction can be emitted at this cycle.
- Hazard,// This instruction can't be emitted at this cycle.
- NoopHazard,// This instruction can't be emitted, and needs noops.
-};
-
-/// getHazardType - Return the hazard type of emitting this node. There
are
-/// three possible results. Either:
-/// * NoHazard: it is legal to issue this instruction on this cycle.
-/// * Hazard: issuing this instruction would stall the machine. If some
-/// other instruction is available, issue it first.
-/// * NoopHazard: issuing this instruction would break the program. If
-/// some other instruction can be issued, do so, otherwise issue a
noop.
-virtual HazardType getHazardType(SDNode *Node) {
- return NoHazard;
-}
-
-/// EmitInstruction - This callback is invoked when an instruction is
-/// emitted, to advance the hazard state.
-virtual void EmitInstruction(SDNode *Node) {
-}
-
-/// AdvanceCycle - This callback is invoked when no instructions can be
-/// issued on this cycle without a hazard. This should increment the
-/// internal state of the hazard recognizer so that previously "Hazard"
-/// instructions will now not be hazards.
-virtual void AdvanceCycle() {
-}
-
-/// EmitNoop - This callback is invoked when a noop was added to the
-/// instruction stream.
-virtual void EmitNoop() {
-}
- };
-}
-
-
/// ScheduleDAGList - List scheduler.
class ScheduleDAGList : public ScheduleDAG {
private:
@@ -226,7 +181,7 @@
bool isBottomUp;
/// HazardRec - The hazard recognizer to use.
- HazardRecognizer *HazardRec;
+ HazardRecognizer &HazardRec;
typedef std::priority_queue, ls_rr_sort>
AvailableQueueTy;
@@ -234,11 +189,10 @@
public:
ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
const TargetMachine &tm, bool isbottomup,
- HazardRecognizer *HR = 0)
+ HazardRecognizer &HR)
: ScheduleDAG(listSchedulingBURR, dag, bb, tm),
- CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL), isBottomUp(isbottomup) {
- if (HR == 0) HR = new HazardRecognizer();
-HazardRec = HR;
+ CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL), isBottomUp(isbottomup),
+ HazardRec(HR
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.16 -> 1.17
---
Log message:
Remove SUnit::Priority1: it is re-calculated on demand as number of live
range to be generated.
---
Diffs of the changes: (+25 -35)
ScheduleDAGList.cpp | 60 +---
1 files changed, 25 insertions(+), 35 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.16
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.17
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.16 Sun Mar 5
18:22:00 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Mar 6 00:08:54 2006
@@ -44,8 +44,7 @@
int NumSuccsLeft; // # of succs not scheduled.
int NumChainPredsLeft; // # of chain preds not scheduled.
int NumChainSuccsLeft; // # of chain succs not scheduled.
- int Priority1; // Scheduling priority 1.
- int Priority2; // Scheduling priority 2.
+ int SethiUllman;// Sethi Ullman number.
bool isTwoAddress; // Is a two-address instruction.
bool isDefNUseOperand; // Is a def&use operand.
unsigned Latency; // Node latency.
@@ -56,7 +55,7 @@
SUnit(SDNode *node)
: Node(node), NumPredsLeft(0), NumSuccsLeft(0),
NumChainPredsLeft(0), NumChainSuccsLeft(0),
- Priority1(INT_MIN), Priority2(INT_MIN),
+ SethiUllman(INT_MIN),
isTwoAddress(false), isDefNUseOperand(false),
Latency(0), CycleBound(0), Slot(0), Next(NULL) {}
@@ -81,8 +80,7 @@
std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
std::cerr << " Latency: " << Latency << "\n";
-std::cerr << " Priority : " << Priority1 << " , "
- << Priority2 << "\n";
+std::cerr << " SethiUllman: " << SethiUllman << "\n";
if (Preds.size() != 0) {
std::cerr << " Predecessors:\n";
@@ -140,10 +138,11 @@
RBonus++;
}
-int LPriority1 = left ->Priority1 - LBonus;
-int RPriority1 = right->Priority1 - RBonus;
-int LPriority2 = left ->Priority2 + LBonus;
-int RPriority2 = right->Priority2 + RBonus;
+// Priority1 is just the number of live range genned.
+int LPriority1 = left ->NumPredsLeft - LBonus;
+int RPriority1 = right->NumPredsLeft - RBonus;
+int LPriority2 = left ->SethiUllman + LBonus;
+int RPriority2 = right->SethiUllman + RBonus;
// Favor floaters (i.e. node with no non-passive predecessors):
// e.g. MOV32ri.
@@ -155,7 +154,7 @@
else if (LPriority1 == RPriority1)
if (LPriority2 < RPriority2)
return true;
-else if (LPriority1 == RPriority1)
+else if (LPriority2 == RPriority2)
if (left->CycleBound > right->CycleBound)
return true;
@@ -249,10 +248,9 @@
// interrupt model (drain vs. freeze).
PredSU->CycleBound = std::max(PredSU->CycleBound, CurrCycle +
PredSU->Latency);
- if (!isChain) {
+ if (!isChain)
PredSU->NumSuccsLeft--;
-PredSU->Priority1++;
- } else
+ else
PredSU->NumChainSuccsLeft--;
#ifndef NDEBUG
@@ -281,10 +279,9 @@
// interrupt model (drain vs. freeze).
SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurrCycle +
SuccSU->Latency);
- if (!isChain) {
+ if (!isChain)
SuccSU->NumPredsLeft--;
-SuccSU->Priority1++; // FIXME: ??
- } else
+ else
SuccSU->NumChainPredsLeft--;
#ifndef NDEBUG
@@ -316,7 +313,6 @@
E1 = SU->Preds.end(); I1 != E1; ++I1) {
ReleasePred(Available, *I1);
SU->NumPredsLeft--;
-SU->Priority1--;
}
for (std::set::iterator I2 = SU->ChainPreds.begin(),
E2 = SU->ChainPreds.end(); I2 != E2; ++I2)
@@ -341,7 +337,6 @@
E1 = SU->Succs.end(); I1 != E1; ++I1) {
ReleaseSucc(Available, *I1);
SU->NumSuccsLeft--;
-SU->Priority1--; // FIXME: what is this??
}
for (std::set::iterator I2 = SU->ChainSuccs.begin(),
E2 = SU->ChainSuccs.end(); I2 != E2; ++I2)
@@ -501,39 +496,34 @@
}
-/// CalcNodePriority - Priority1 is just the number of live range genned -
-/// number of live range killed. Priority2 is the Sethi Ullman number. It
-/// returns Priority2 since it is calculated recursively.
-/// Smaller number is the higher priority for Priority2. Reverse is true for
-/// Priority1.
+/// CalcNodePriority - Priority is the Sethi Ullman number.
+/// Smaller number is the higher priority.
int ScheduleDAGList::CalcNodePriority(SUnit *SU) {
- if (SU->Priority2 != INT_MIN)
-return SU->Priority2;
-
- SU->Priority1 = SU->NumPredsLeft - SU->NumSuccsLeft;
+ if (SU->SethiUllman != INT_MIN)
+return SU->SethiUllman;
if (SU->Preds.size() == 0) {
-SU->Priority2 = 1;
+
[llvm-commits] CVS: llvm/tools/llvm-ld/llvm-ld.cpp
Changes in directory llvm/tools/llvm-ld: llvm-ld.cpp updated: 1.29 -> 1.30 --- Log message: Make sure command line options are parsed before we try to add the LibPath (-L options) to TheLinker. Problem noticed by Wink Saville. --- Diffs of the changes: (+4 -4) llvm-ld.cpp |8 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/tools/llvm-ld/llvm-ld.cpp diff -u llvm/tools/llvm-ld/llvm-ld.cpp:1.29 llvm/tools/llvm-ld/llvm-ld.cpp:1.30 --- llvm/tools/llvm-ld/llvm-ld.cpp:1.29 Mon Jan 9 21:14:40 2006 +++ llvm/tools/llvm-ld/llvm-ld.cpp Mon Mar 6 00:38:19 2006 @@ -406,14 +406,14 @@ progname = sys::Path(argv[0]).getBasename(); Linker TheLinker(progname, OutputFilename, Verbose); -// Set up the library paths for the Linker -TheLinker.addPaths(LibPaths); -TheLinker.addSystemPaths(); - // Parse the command line options cl::ParseCommandLineOptions(argc, argv, " llvm linker\n"); sys::PrintStackTraceOnErrorSignal(); +// Set up the library paths for the Linker +TheLinker.addPaths(LibPaths); +TheLinker.addSystemPaths(); + // Remove any consecutive duplicates of the same library... Libraries.erase(std::unique(Libraries.begin(), Libraries.end()), Libraries.end()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.17 -> 1.18
---
Log message:
Remove some code that doesn't make sense
---
Diffs of the changes: (+5 -12)
ScheduleDAGList.cpp | 17 +
1 files changed, 5 insertions(+), 12 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.17
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.18
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.17 Mon Mar 6
00:08:54 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Mar 6 01:31:44 2006
@@ -120,8 +120,6 @@
/// Sorting functions for the Available queue.
struct ls_rr_sort : public std::binary_function {
bool operator()(const SUnit* left, const SUnit* right) const {
-bool LFloater = (left ->Preds.size() == 0);
-bool RFloater = (right->Preds.size() == 0);
int LBonus = (int)left ->isDefNUseOperand;
int RBonus = (int)right->isDefNUseOperand;
@@ -144,19 +142,14 @@
int LPriority2 = left ->SethiUllman + LBonus;
int RPriority2 = right->SethiUllman + RBonus;
-// Favor floaters (i.e. node with no non-passive predecessors):
-// e.g. MOV32ri.
-if (!LFloater && RFloater)
+if (LPriority1 > RPriority1)
return true;
-else if (LFloater == RFloater)
- if (LPriority1 > RPriority1)
+else if (LPriority1 == RPriority1)
+ if (LPriority2 < RPriority2)
return true;
- else if (LPriority1 == RPriority1)
-if (LPriority2 < RPriority2)
+ else if (LPriority2 == RPriority2)
+if (left->CycleBound > right->CycleBound)
return true;
-else if (LPriority2 == RPriority2)
- if (left->CycleBound > right->CycleBound)
-return true;
return false;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGPrinter.cpp updated: 1.30 -> 1.31
---
Log message:
print arbitrary constant pool entries
---
Diffs of the changes: (+9 -0)
SelectionDAGPrinter.cpp |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.30
llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.31
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.30 Tue Nov 29
20:04:11 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Sun Mar 5
03:38:03 2006
@@ -13,6 +13,7 @@
#include "llvm/Constants.h"
#include "llvm/Function.h"
+#include "llvm/Assembly/Writer.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/MRegisterInfo.h"
@@ -22,6 +23,7 @@
#include "llvm/ADT/StringExtras.h"
#include "llvm/Config/config.h"
#include
+#include
using namespace llvm;
namespace llvm {
@@ -81,6 +83,13 @@
} else if (const ConstantPoolSDNode *CP =
dyn_cast(Node)){
if (ConstantFP *CFP = dyn_cast(CP->get()))
Op += "<" + ftostr(CFP->getValue()) + ">";
+else if (ConstantInt *CI = dyn_cast(CP->get()))
+ Op += "<" + utostr(CI->getZExtValue()) + ">";
+else {
+ std::ostringstream SS;
+ WriteAsOperand(SS, CP->get(), false);
+ Op += "<" + SS.str() + ">";
+}
} else if (const BasicBlockSDNode *BBDN = dyn_cast(Node)) {
Op = "BB: ";
const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
___
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.194 -> 1.195 --- Log message: Added -fomit-frame-pointer to TARGET_CFLAGS for Darwin --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.194 llvm-test/Makefile.programs:1.195 --- llvm-test/Makefile.programs:1.194 Mon Feb 27 00:52:04 2006 +++ llvm-test/Makefile.programs Sun Mar 5 03:40:01 2006 @@ -204,7 +204,7 @@ endif ifeq ($(OS),Darwin) -TARGET_CFLAGS := -mdynamic-no-pic +TARGET_CFLAGS := -mdynamic-no-pic -fomit-frame-pointer endif # Given a version of the entire program linked together into a single unit of ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.43 -> 1.44
---
Log message:
Do not fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1),
we want to canonicalize the other way.
---
Diffs of the changes: (+0 -18)
TargetLowering.cpp | 18 --
1 files changed, 18 deletions(-)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.43
llvm/lib/Target/TargetLowering.cpp:1.44
--- llvm/lib/Target/TargetLowering.cpp:1.43 Fri Mar 3 00:58:59 2006
+++ llvm/lib/Target/TargetLowering.cpp Sun Mar 5 13:52:57 2006
@@ -580,24 +580,6 @@
CountTrailingZeros_64(~KnownZero2));
KnownZero = (1ULL << KnownZeroOut) - 1;
KnownOne = 0;
-
- SDOperand SH = Op.getOperand(0);
- // fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1)
- if (KnownZero && SH.getOpcode() == ISD::SHL && SH.Val->hasOneUse() &&
- Op.Val->hasOneUse()) {
-if (ConstantSDNode *SA = dyn_cast(SH.getOperand(1))) {
- MVT::ValueType VT = Op.getValueType();
- unsigned ShiftAmt = SA->getValue();
- uint64_t AddAmt = AA->getValue();
- uint64_t AddShr = AddAmt >> ShiftAmt;
- if (AddAmt == (AddShr << ShiftAmt)) {
-SDOperand ADD = TLO.DAG.getNode(ISD::ADD, VT, SH.getOperand(0),
-TLO.DAG.getConstant(AddShr, VT));
-SDOperand SHL = TLO.DAG.getNode(ISD::SHL, VT,
ADD,SH.getOperand(1));
-return TLO.CombineTo(Op, SHL);
- }
-}
- }
}
break;
case ISD::SUB:
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.122 -> 1.123 --- Log message: Reinstate this now that the offending opposite xform has been removed. --- Diffs of the changes: (+7 -0) DAGCombiner.cpp |7 +++ 1 files changed, 7 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.122 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.123 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.122 Sun Mar 5 01:30:16 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Mar 5 13:53:55 2006 @@ -1454,6 +1454,13 @@ if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) return DAG.getNode(ISD::AND, VT, N0.getOperand(0), DAG.getConstant(~0ULL << N1C->getValue(), VT)); + // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1
[llvm-commits] CVS: llvm/lib/Target/README.txt
Changes in directory llvm/lib/Target: README.txt updated: 1.12 -> 1.13 --- Log message: add a note --- Diffs of the changes: (+4 -0) README.txt |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.12 llvm/lib/Target/README.txt:1.13 --- llvm/lib/Target/README.txt:1.12 Sat Mar 4 17:33:44 2006 +++ llvm/lib/Target/README.txt Sun Mar 5 14:00:08 2006 @@ -102,3 +102,7 @@ This would be a win on ppc32, but not x86 or ppc64. //===-===// + +Shrink: (setlt (loadi32 P), 0) -> (setlt (loadi8 Phi), 0) + +//===-===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
