[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelPattern.cpp updated: 1.200 -> 1.201
---
Log message:
Loosen up these checks to allow direct uses of ESP
---
Diffs of the changes: (+12 -4)
X86ISelPattern.cpp | 16
1 files changed, 12 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.200
llvm/lib/Target/X86/X86ISelPattern.cpp:1.201
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.200Sun Jan 22 17:37:17 2006
+++ llvm/lib/Target/X86/X86ISelPattern.cpp Wed Jan 25 02:00:36 2006
@@ -2903,13 +2903,21 @@
if (OrigDest.getOpcode() == ISD::CopyFromReg) {
OrigOffset = 0;
assert(cast(OrigDest.getOperand(1))->getReg() == X86::ESP);
- } else {
+ } else if (OrigDest.getOpcode() == ISD::ADD &&
+ isa(OrigDest.getOperand(1)) &&
+ OrigDest.getOperand(0).getOpcode() == ISD::CopyFromReg &&
+
cast(OrigDest.getOperand(0).getOperand(1))->getReg()
+ == X86::ESP) {
+// We expect only (ESP+C)
+OrigOffset = cast(OrigDest.getOperand(1))->getValue();
+ } else if (OrigDest.getOpcode() == ISD::Register) {
// We expect only (ESP+C)
+OrigOffset = 0;
+ } else {
assert(OrigDest.getOpcode() == ISD::ADD &&
isa(OrigDest.getOperand(1)) &&
- OrigDest.getOperand(0).getOpcode() == ISD::CopyFromReg &&
- cast(OrigDest.getOperand(0).getOperand(1))->getReg()
- == X86::ESP);
+ OrigDest.getOperand(0).getOpcode() == ISD::Register &&
+ cast(OrigDest.getOperand(0))->getReg() == X86::ESP);
OrigOffset = cast(OrigDest.getOperand(1))->getValue();
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.54 -> 1.55
---
Log message:
Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it.
---
Diffs of the changes: (+10 -2)
X86ISelLowering.cpp | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.54
llvm/lib/Target/X86/X86ISelLowering.cpp:1.55
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.54Tue Jan 24 00:14:44 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Jan 25 03:05:09 2006
@@ -1696,9 +1696,14 @@
// If the X86ISD::SETCC has more than one use, then it's probably better
// to use a test instead of duplicating the X86ISD::CMP (for register
// pressure reason).
+ // FIXME: Check number of live Op0 uses since we are in the middle of
+ // legalization process.
if (Op0.hasOneUse() && Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
CC = Op0.getOperand(0);
Cond = Op0.getOperand(1);
+// Make a copy as flag result cannot be used by more than one.
+Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
+ Cond.getOperand(0), Cond.getOperand(1));
addTest =
isFPStack && !hasFPCMov(cast(CC)->getSignExtended());
} else
@@ -1742,11 +1747,14 @@
// If the X86ISD::SETCC has more than one use, then it's probably better
// to use a test instead of duplicating the X86ISD::CMP (for register
// pressure reason).
+ // FIXME: Check number of live Cond uses since we are in the middle of
+ // legalization process.
if (Cond.hasOneUse() && Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
CC = Cond.getOperand(0);
+Cond = Cond.getOperand(1);
+// Make a copy as flag result cannot be used by more than one.
Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
- Cond.getOperand(1).getOperand(0),
- Cond.getOperand(1).getOperand(1));
+ Cond.getOperand(0), Cond.getOperand(1));
} else
addTest = true;
} else if (Cond.getOpcode() == ISD::SETCC) {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.34 -> 1.35
---
Log message:
Add a enum to specify target scheduling preference: SchedulingForLatency or
SchedulingForRegPressure. Added corresponding methods to set / get the value.
---
Diffs of the changes: (+19 -0)
TargetLowering.h | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.34
llvm/include/llvm/Target/TargetLowering.h:1.35
--- llvm/include/llvm/Target/TargetLowering.h:1.34 Fri Jan 13 11:47:52 2006
+++ llvm/include/llvm/Target/TargetLowering.h Wed Jan 25 03:09:02 2006
@@ -70,6 +70,11 @@
ZeroOrNegativeOneSetCCResult, // SetCC returns a sign extended result.
};
+ enum SchedPreference {
+SchedulingForLatency, // Scheduling for shortest total latency.
+SchedulingForRegPressure, // Scheduling for lowest register pressure.
+ };
+
TargetLowering(TargetMachine &TM);
virtual ~TargetLowering();
@@ -102,6 +107,11 @@
/// result register.
SetCCResultValue getSetCCResultContents() const { return
SetCCResultContents;}
+ /// getSchedulingPreference - Return target scheduling preference.
+ SchedPreference getSchedulingPreference() const {
+return SchedPreferenceInfo;
+ }
+
/// getRegClassFor - Return the register class that should be used for the
/// specified value type. This may only be called on legal types.
TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
@@ -261,6 +271,11 @@
/// setcc operation in a register.
void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty;
}
+ /// setSchedulingPreference - Specify the target scheduling preference.
+ void setSchedulingPreference(SchedPreference Pref) {
+SchedPreferenceInfo = Pref;
+ }
+
/// setShiftAmountFlavor - Describe how the target handles out of range shift
/// amounts.
void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
@@ -453,6 +468,10 @@
/// SetCCResultContents - Information about the contents of the high-bits in
/// the result of a setcc comparison operation.
SetCCResultValue SetCCResultContents;
+
+ /// SchedPreferenceInfo - The target scheduling preference: shortest possible
+ /// total cycles or lowest register usage.
+ SchedPreference SchedPreferenceInfo;
/// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and
/// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.135 -> 1.136
---
Log message:
If scheduler choice is the default (-sched=default), use target scheduling
preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.
---
Diffs of the changes: (+10 -2)
SelectionDAGISel.cpp | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.135
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.136
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.135Mon Jan 23
07:34:04 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jan 25 03:12:57 2006
@@ -59,8 +59,10 @@
ISHeuristic(
"sched",
cl::desc("Choose scheduling style"),
-cl::init(noScheduling),
+cl::init(defaultScheduling),
cl::values(
+ clEnumValN(defaultScheduling, "default",
+ "Target preferred scheduling style"),
clEnumValN(noScheduling, "none",
"No scheduling: breadth first sequencing"),
clEnumValN(simpleScheduling, "simple",
@@ -69,7 +71,7 @@
clEnumValN(simpleNoItinScheduling, "simple-noitin",
"Simple two pass scheduling: Same as simple "
"except using generic latency"),
- clEnumValN(listSchedulingBURR, "list-BURR",
+ clEnumValN(listSchedulingBURR, "list-burr",
"Bottom up register reduction list scheduling"),
clEnumValEnd));
} // namespace
@@ -1772,6 +1774,12 @@
switch (ISHeuristic) {
default: assert(0 && "Unrecognized scheduling heuristic");
+ case defaultScheduling:
+if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
+ SL = createSimpleDAGScheduler(noScheduling, DAG, BB);
+else /* TargetLowering::SchedulingForRegPressure */
+ SL = createBURRListDAGScheduler(DAG, BB);
+break;
case noScheduling:
case simpleScheduling:
case simpleNoItinScheduling:
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.55 -> 1.56 --- Log message: X86 prefer scheduling for reduced register pressure. --- Diffs of the changes: (+1 -0) X86ISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.55 llvm/lib/Target/X86/X86ISelLowering.cpp:1.56 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.55Wed Jan 25 03:05:09 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Jan 25 03:15:17 2006 @@ -39,6 +39,7 @@ setShiftAmountType(MVT::i8); setSetCCResultType(MVT::i8); setSetCCResultContents(ZeroOrOneSetCCResult); + setSchedulingPreference(SchedulingForRegPressure); setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 setStackPointerRegisterToSaveRestore(X86::ESP); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.25 -> 1.26 --- Log message: Default scheduling preference is SchedulingForLatency. --- Diffs of the changes: (+1 -0) IA64ISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.25 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.26 --- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.25 Fri Jan 20 14:24:31 2006 +++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Wed Jan 25 03:15:54 2006 @@ -93,6 +93,7 @@ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); + setSchedulingPreference(SchedulingForLatency); setStackPointerRegisterToSaveRestore(IA64::r12); computeRegisterProperties(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.68 -> 1.69 --- Log message: Default scheduling preference is SchedulingForLatency. --- Diffs of the changes: (+1 -0) PPCISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.68 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.69 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.68Wed Jan 18 13:42:35 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Jan 25 03:15:54 2006 @@ -144,6 +144,7 @@ } setSetCCResultContents(ZeroOrOneSetCCResult); + setSchedulingPreference(SchedulingForLatency); setStackPointerRegisterToSaveRestore(PPC::R1); computeRegisterProperties(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.56 -> 1.57 --- Log message: Default scheduling preference is SchedulingForLatency. --- Diffs of the changes: (+1 -0) SparcV8ISelDAGToDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp diff -u llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.56 llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.57 --- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.56Thu Jan 19 01:22:29 2006 +++ llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp Wed Jan 25 03:15:54 2006 @@ -166,6 +166,7 @@ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); + setSchedulingPreference(SchedulingForLatency); setStackPointerRegisterToSaveRestore(V8::O6); computeRegisterProperties(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.4 -> 1.5
---
Log message:
Some minor scheduler changes.
---
Diffs of the changes: (+9 -4)
ScheduleDAG.h | 13 +
1 files changed, 9 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.4
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.5
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.4 Mon Jan 23 02:26:10 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Wed Jan 25 03:07:50 2006
@@ -37,6 +37,7 @@
// Scheduling heuristics
enum SchedHeuristics {
+defaultScheduling, // Let the target specify its preference.
noScheduling, // No scheduling, emit breath first sequence.
simpleScheduling, // Two pass, min. critical path, max. utilization.
simpleNoItinScheduling, // Same as above exact using generic latency.
@@ -51,6 +52,8 @@
class NodeGroup {
private:
NIVector Members;// Group member nodes
+NodeInfo *Top;
+NodeInfo *Bottom;
NodeInfo *Dominator; // Node with highest latency
unsigned Latency;// Total latency of the group
int Pending;// Number of visits pending before
@@ -58,10 +61,12 @@
public:
// Ctor.
-NodeGroup() : Dominator(NULL), Pending(0) {}
+NodeGroup() : Top(NULL), Bottom(NULL), Dominator(NULL), Pending(0) {}
// Accessors
inline void setDominator(NodeInfo *D) { Dominator = D; }
+inline NodeInfo *getTop() { return Top; }
+inline NodeInfo *getBottom() { return Bottom; }
inline NodeInfo *getDominator() { return Dominator; }
inline void setLatency(unsigned L) { Latency = L; }
inline unsigned getLatency() { return Latency; }
@@ -94,7 +99,7 @@
class NodeInfo {
private:
int Pending;// Number of visits pending before
-//adding to order
+ // adding to order
public:
SDNode*Node; // DAG node
InstrStage*StageBegin;// First stage in itinerary
@@ -279,7 +284,7 @@
/// isPassiveNode - Return true if the node is a non-scheduled leaf.
///
-bool isPassiveNode(SDNode *Node) {
+static bool isPassiveNode(SDNode *Node) {
if (isa(Node)) return true;
if (isa(Node)) return true;
if (isa(Node)) return true;
@@ -316,7 +321,7 @@
void dump(const char *tag) const;
-void dump() const;
+virtual void dump() const;
private:
/// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.57 -> 1.58
---
Log message:
Keep track of bottom / top element of a set of flagged nodes.
---
Diffs of the changes: (+6 -1)
ScheduleDAG.cpp |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.57
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.58
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.57 Mon Jan 23 01:01:07 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Wed Jan 25 03:13:41 2006
@@ -86,7 +86,7 @@
if (Op.getValueType() != MVT::Flag) break;
// Add to node group
NodeGroup::Add(getNI(Op.Val), NI);
- // Let evryone else know
+ // Let everyone else know
HasGroups = true;
}
}
@@ -464,6 +464,7 @@
// Merge the two lists
DGroup->group_insert(DGroup->group_end(),
UGroup->group_begin(), UGroup->group_end());
+DGroup->Bottom = UGroup->Bottom;
} else if (DGroup) {
// Make user member of definers group
U->Group = DGroup;
@@ -476,6 +477,7 @@
DGroup->addPending(-CountInternalUses(DNI, U));
}
DGroup->group_push_back(U);
+DGroup->Bottom = U;
} else if (UGroup) {
// Make definer member of users group
D->Group = UGroup;
@@ -488,11 +490,14 @@
UGroup->addPending(-CountInternalUses(D, UNI));
}
UGroup->group_insert(UGroup->group_begin(), D);
+UGroup->Top= D;
} else {
D->Group = U->Group = DGroup = new NodeGroup();
DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
CountInternalUses(D, U));
DGroup->group_push_back(D);
DGroup->group_push_back(U);
+DGroup->Top= D;
+DGroup->Bottom = U;
}
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.1 -> 1.2
---
Log message:
Bottom up register usage reducing list scheduler.
---
Diffs of the changes: (+451 -21)
ScheduleDAGList.cpp | 472 +---
1 files changed, 451 insertions(+), 21 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.1
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.2
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.1 Mon Jan 23
02:26:10 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Wed Jan 25 03:14:32 2006
@@ -1,4 +1,4 @@
-//===-- ScheduleDAGSimple.cpp - Implement a list scheduler for isel DAG
---===//
+//=== ScheduleDAGList.cpp - Implement a list scheduler for isel DAG
---===//
//
// The LLVM Compiler Infrastructure
//
@@ -18,44 +18,474 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
-#include
+#include "llvm/Support/Debug.h"
+#include
+#include
+#include
#include
using namespace llvm;
+namespace {
-namespace llvm {
-/// Sorting functions for ready queue.
-struct LSSortPred : public std::binary_function {
- bool operator()(const SDOperand* left, const SDOperand* right) const {
-return true;
+/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or a
+/// group of nodes flagged together.
+struct SUnit {
+ SDNode *Node; // Representative node.
+ std::vector FlaggedNodes; // All nodes flagged to Node.
+ std::vector Preds; // All real predecessors.
+ std::vector ChainPreds;// All chain predecessors.
+ std::vector Succs; // All real successors.
+ std::vector ChainSuccs;// All chain successors.
+ int NumPredsLeft; // # of preds not scheduled.
+ int NumSuccsLeft; // # of succs not scheduled.
+ int Priority1; // Scheduling priority 1.
+ int Priority2; // Scheduling priority 2.
+ unsigned Latency; // Node latency.
+ unsigned CycleBound;// Upper/lower cycle to be scheduled at.
+ unsigned Slot; // Cycle node is scheduled at.
+
+ SUnit(SDNode *node)
+: Node(node), NumPredsLeft(0), NumSuccsLeft(0),
+ Priority1(INT_MIN), Priority2(INT_MIN), Latency(0),
+ CycleBound(0), Slot(0) {}
+
+ void dump(const SelectionDAG *G, bool All=true) const;
+};
+
+void SUnit::dump(const SelectionDAG *G, bool All) const {
+ std::cerr << "SU: ";
+ Node->dump(G);
+ std::cerr << "\n";
+ if (All) {
+std::cerr << "# preds left : " << NumPredsLeft << "\n";
+std::cerr << "# succs left : " << NumSuccsLeft << "\n";
+std::cerr << "Latency : " << Latency << "\n";
+std::cerr << "Priority : " << Priority1 << " , " << Priority2 << "\n";
+ }
+
+ if (FlaggedNodes.size() != 0) {
+if (All)
+ std::cerr << "Flagged nodes :\n";
+for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
+ std::cerr << " ";
+ FlaggedNodes[i]->dump(G);
+ std::cerr << "\n";
+}
+ }
+
+ if (All) {
+if (Preds.size() != 0) {
+ std::cerr << "Predecessors :\n";
+ for (unsigned i = 0, e = Preds.size(); i != e; i++) {
+std::cerr << "";
+Preds[i]->dump(G);
+std::cerr << "\n";
+ }
+}
+if (ChainPreds.size() != 0) {
+ std::cerr << "Chained Preds :\n";
+ for (unsigned i = 0, e = ChainPreds.size(); i != e; i++) {
+std::cerr << "";
+ChainPreds[i]->dump(G);
+std::cerr << "\n";
+ }
+}
+if (Succs.size() != 0) {
+ std::cerr << "Successors:\n";
+ for (unsigned i = 0, e = Succs.size(); i != e; i++) {
+std::cerr << "";
+Succs[i]->dump(G);
+std::cerr << "\n";
+ }
+}
+if (ChainSuccs.size() != 0) {
+ std::cerr << "Chained succs :\n";
+ for (unsigned i = 0, e = ChainSuccs.size(); i != e; i++) {
+std::cerr << "";
+ChainSuccs[i]->dump(G);
+std::cerr << "\n";
+ }
+}
+ }
+}
+
+/// Sorting functions for the Available queue.
+struct ls_rr_sort : public std::binary_function {
+ bool operator()(const SUnit* left, const SUnit* right) const {
+if (left->Priority1 > right->Priority1) {
+ return true;
+} else if (left->Priority1 == right->Priority1) {
+ unsigned lf = left->FlaggedNodes.size();
+ unsigned rf = right->FlaggedNodes.size();
+ if (lf > rf)
+return true;
+ else if (lf == rf) {
+if (left->Priority2 > right->Priority2)
+ return true;
+else if (left->Priority2 == right->Priority2) {
+ if (left->CycleBound > right->CycleBound)
+return true;
+ else
+return left->Node->getNodeDepth() < right->Node->getNodeDep
[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp
Changes in directory llvm/lib/Bytecode/Reader:
Reader.cpp updated: 1.185 -> 1.186
---
Log message:
Make it even more portable.
---
Diffs of the changes: (+1 -1)
Reader.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Bytecode/Reader/Reader.cpp
diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.185
llvm/lib/Bytecode/Reader/Reader.cpp:1.186
--- llvm/lib/Bytecode/Reader/Reader.cpp:1.185 Tue Jan 24 20:40:10 2006
+++ llvm/lib/Bytecode/Reader/Reader.cpp Wed Jan 25 11:18:50 2006
@@ -79,7 +79,7 @@
inline void BytecodeReader::align32() {
if (hasAlignment) {
BufPtr Save = At;
-At = (const unsigned char *)((size_t)(At+3) & (~3UL));
+At = (const unsigned char *)((intptr_t)(At+3) & (~3UL));
if (At > Save)
if (Handler) Handler->handleAlignment(At - Save);
if (At > BlockEnd)
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.16 -> 1.17
---
Log message:
Make it even more portable.
---
Diffs of the changes: (+1 -1)
DwarfWriter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.16
llvm/lib/CodeGen/DwarfWriter.cpp:1.17
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.16 Tue Jan 24 20:40:10 2006
+++ llvm/lib/CodeGen/DwarfWriter.cppWed Jan 25 11:18:50 2006
@@ -645,7 +645,7 @@
#ifndef NDEBUG
void DIEAbbrev::print(std::ostream &O) {
O << "Abbreviation @"
- << std::hex << (size_t)this << std::dec
+ << std::hex << (intptr_t)this << std::dec
<< " "
<< TagString(Tag)
<< " "
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.2 -> 1.3
---
Log message:
Fix VC++ compilation error.
---
Diffs of the changes: (+1 -1)
ScheduleDAGList.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.2
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.3
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.2 Wed Jan 25
03:14:32 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Wed Jan 25 11:17:49 2006
@@ -341,7 +341,7 @@
}
void ScheduleDAGList::BuildSchedUnits() {
- for (unsigned i = 0, N = NodeCount; i < N; i++) {
+ for (unsigned i = 0, NC = NodeCount; i < NC; i++) {
NodeInfo *NI = &Info[i];
SDNode *N = NI->Node;
if (!isPassiveNode(N)) {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen: SelectionDAG.h updated: 1.87 -> 1.88 SelectionDAGNodes.h updated: 1.93 -> 1.94 --- Log message: First part of bug 680: http://llvm.cs.uiuc.edu/PR680 : Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything else. --- Diffs of the changes: (+18 -0) SelectionDAG.h |5 + SelectionDAGNodes.h | 13 + 2 files changed, 18 insertions(+) Index: llvm/include/llvm/CodeGen/SelectionDAG.h diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.87 llvm/include/llvm/CodeGen/SelectionDAG.h:1.88 --- llvm/include/llvm/CodeGen/SelectionDAG.h:1.87 Mon Jan 23 15:51:14 2006 +++ llvm/include/llvm/CodeGen/SelectionDAG.hWed Jan 25 12:21:52 2006 @@ -278,6 +278,11 @@ Ops.push_back(False); return getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); } + + /// getVAArg - VAArg produces a result and token chain, and takes a pointer + /// and a source value as input. + SDOperand getVAArg(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr, + SDOperand SV); /// getLoad - Loads are not normal binary operators: their result type is not /// determined by their operands, and they produce a value AND a token chain. Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.93 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.94 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.93 Mon Jan 23 23:47:05 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Wed Jan 25 12:21:52 2006 @@ -335,6 +335,19 @@ // target and not touched by the DAG optimizers. CALLSEQ_START, // Beginning of a call sequence CALLSEQ_END,// End of a call sequence + +// VAARG - VAARG has three operands: an input chain, a pointer, and a +// SRCVALUE. It returns a pair of values: the vaarg value and a new chain. +VAARG, + +// VACOPY - VACOPY has five operands: an input chain, a destination pointer, +// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the +// source. +VACOPY, + +// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, a +// pointer, and a SRCVALUE. +VAEND, VASTART, // SRCVALUE - This corresponds to a Value*, and is used to associate memory // locations with their value. This allows one use alias analysis ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.69 -> 1.70
PPCISelLowering.h updated: 1.14 -> 1.15
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
---
Diffs of the changes: (+14 -41)
PPCISelLowering.cpp | 48 ++--
PPCISelLowering.h |7 ---
2 files changed, 14 insertions(+), 41 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.69
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.70
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.69Wed Jan 25 03:15:54 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Jan 25 12:21:52 2006
@@ -110,7 +110,13 @@
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ // VASTART needs to be custom lowered to use the VarArgsFrameIndex
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
+
// Use the default implementation.
+ setOperationAction(ISD::VAARG , MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
@@ -427,6 +433,14 @@
// resolution stub.
return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
}
+ case ISD::VASTART: {
+// vastart just stores the address of the VarArgsFrameIndex slot into the
+// memory location argument.
+// FIXME: Replace MVT::i32 with PointerTy
+SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
+return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
+ Op.getOperand(1), Op.getOperand(2));
+ }
}
return SDOperand();
}
@@ -846,40 +860,6 @@
return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
-SDOperand PPCTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
- Value *VAListV, SelectionDAG &DAG) {
- // vastart just stores the address of the VarArgsFrameIndex slot into the
- // memory location argument.
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
- return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
- DAG.getSrcValue(VAListV));
-}
-
-std::pair
-PPCTargetLowering::LowerVAArg(SDOperand Chain,
- SDOperand VAListP, Value *VAListV,
- const Type *ArgTy, SelectionDAG &DAG) {
- MVT::ValueType ArgVT = getValueType(ArgTy);
-
- SDOperand VAList =
-DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
- SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
- unsigned Amt;
- if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
-Amt = 4;
- else {
-assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
- "Other types should have been promoted for varargs!");
-Amt = 8;
- }
- VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
- DAG.getConstant(Amt, VAList.getValueType()));
- Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- VAList, VAListP, DAG.getSrcValue(VAListV));
- return std::make_pair(Result, Chain);
-}
-
-
std::pair PPCTargetLowering::
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
SelectionDAG &DAG) {
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.14
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.15
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.14 Mon Jan 9 17:52:17 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Wed Jan 25 12:21:52 2006
@@ -94,13 +94,6 @@
virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
SelectionDAG &DAG);
-virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
- Value *VAListV, SelectionDAG &DAG);
-
-virtual std::pair
- LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
- const Type *ArgTy, SelectionDAG &DAG);
-
virtual std::pair
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned
Depth,
SelectionDAG &DAG);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp AlphaISelLowering.h
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.28 -> 1.29
AlphaISelLowering.h updated: 1.11 -> 1.12
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
---
Diffs of the changes: (+70 -83)
AlphaISelLowering.cpp | 144 --
AlphaISelLowering.h |9 ---
2 files changed, 70 insertions(+), 83 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.28
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.29
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.28Mon Jan 23 15:56:07 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jan 25 12:21:52 2006
@@ -368,79 +368,6 @@
return std::make_pair(RetVal, Chain);
}
-SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
-Value *VAListV, SelectionDAG &DAG)
{
- // vastart stores the address of the VarArgsBase and VarArgsOffset
- SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
- SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
- DAG.getSrcValue(VAListV));
- SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
- DAG.getConstant(8, MVT::i64));
- return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
- DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
- DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
-}
-
-std::pair AlphaTargetLowering::
-LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
- const Type *ArgTy, SelectionDAG &DAG) {
- SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
- DAG.getSrcValue(VAListV));
- SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
- DAG.getConstant(8, MVT::i64));
- SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
-Tmp, DAG.getSrcValue(VAListV, 8),
MVT::i32);
- SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
- if (ArgTy->isFloatingPoint())
- {
-//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
- SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
-DAG.getConstant(8*6, MVT::i64));
- SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
- DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
- DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
- }
-
- SDOperand Result;
- if (ArgTy == Type::IntTy)
-Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
-DataPtr, DAG.getSrcValue(NULL), MVT::i32);
- else if (ArgTy == Type::UIntTy)
-Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
-DataPtr, DAG.getSrcValue(NULL), MVT::i32);
- else
-Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
- DAG.getSrcValue(NULL));
-
- SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
-DAG.getConstant(8, MVT::i64));
- SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
- Result.getValue(1), NewOffset,
- Tmp, DAG.getSrcValue(VAListV, 8),
- DAG.getValueType(MVT::i32));
- Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
-
- return std::make_pair(Result, Update);
-}
-
-SDOperand AlphaTargetLowering::
-LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
-Value *DestV, SelectionDAG &DAG) {
- SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
- DAG.getSrcValue(SrcV));
- SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
- Val, DestP, DAG.getSrcValue(DestV));
- SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
- DAG.getConstant(8, MVT::i64));
- Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
- DAG.getSrcValue(SrcV, 8), MVT::i32);
- SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
- DAG.getConstant(8, MVT::i64));
- return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
- Val, NPD, DAG.getSrcValue(DestV, 8),
- DAG.getValueType(MVT::i32));
-}
-
void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
{
BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
@@ -680,8 +607,77 @@
ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
return DAG.getNode(Opc, VTS, ARGS);
}
+ case ISD::VAARG: {
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.56 -> 1.57
X86ISelLowering.h updated: 1.15 -> 1.16
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
---
Diffs of the changes: (+15 -41)
X86ISelLowering.cpp | 50 +++---
X86ISelLowering.h |6 --
2 files changed, 15 insertions(+), 41 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.56
llvm/lib/Target/X86/X86ISelLowering.cpp:1.57
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.56Wed Jan 25 03:15:17 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Jan 25 12:21:52 2006
@@ -169,7 +169,13 @@
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
- // Expand to the default code.
+ // VASTART needs to be custom lowered to use the VarArgsFrameIndex
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
+
+ // Use the default implementation.
+ setOperationAction(ISD::VAARG , MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
@@ -641,40 +647,6 @@
}
}
-SDOperand
-X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
-Value *VAListV, SelectionDAG &DAG) {
- // vastart just stores the address of the VarArgsFrameIndex slot.
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
- return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
- DAG.getSrcValue(VAListV));
-}
-
-
-std::pair
-X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
- Value *VAListV, const Type *ArgTy,
- SelectionDAG &DAG) {
- MVT::ValueType ArgVT = getValueType(ArgTy);
- SDOperand Val = DAG.getLoad(MVT::i32, Chain,
- VAListP, DAG.getSrcValue(VAListV));
- SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
- DAG.getSrcValue(NULL));
- unsigned Amt;
- if (ArgVT == MVT::i32)
-Amt = 4;
- else {
-assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
- "Other types should have been promoted for varargs!");
-Amt = 8;
- }
- Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
-DAG.getConstant(Amt, Val.getValueType()));
- Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Val, VAListP, DAG.getSrcValue(VAListV));
- return std::make_pair(Result, Chain);
-}
-
//===--===//
//Fast Calling Convention implementation
//===--===//
@@ -1898,6 +1870,14 @@
DAG.getSrcValue(NULL));
return Result;
}
+ case ISD::VASTART: {
+// vastart just stores the address of the VarArgsFrameIndex slot into the
+// memory location argument.
+// FIXME: Replace MVT::i32 with PointerTy
+SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
+return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
+ Op.getOperand(1), Op.getOperand(2));
+ }
}
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.15
llvm/lib/Target/X86/X86ISelLowering.h:1.16
--- llvm/lib/Target/X86/X86ISelLowering.h:1.15 Thu Jan 12 16:54:21 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Wed Jan 25 12:21:52 2006
@@ -195,12 +195,6 @@
virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
SelectionDAG &DAG);
-virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
- Value *VAListV, SelectionDAG &DAG);
-virtual std::pair
-LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
- const Type *ArgTy, SelectionDAG &DAG);
-
virtual std::pair
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
SelectionDAG &DAG);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.276 -> 1.277
SelectionDAG.cpp updated: 1.243 -> 1.244
SelectionDAGISel.cpp updated: 1.136 -> 1.137
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
---
Diffs of the changes: (+192 -67)
LegalizeDAG.cpp | 157 +--
SelectionDAG.cpp | 33 --
SelectionDAGISel.cpp | 69 +-
3 files changed, 192 insertions(+), 67 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.276
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.277
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.276 Mon Jan 23 23:48:21 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 25 12:21:52 2006
@@ -1115,13 +1115,12 @@
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Custom: {
- SDOperand Op = DAG.getLoad(Node->getValueType(0),
- Tmp1, Tmp2, Node->getOperand(2));
+ SDOperand Op = DAG.getLoad(VT, Tmp1, Tmp2, Node->getOperand(2));
SDOperand Tmp = TLI.LowerOperation(Op, DAG);
if (Tmp.Val) {
Result = LegalizeOp(Tmp);
-// Since loads produce two values, make sure to remember that we
legalized
-// both of them.
+// Since loads produce two values, make sure to remember that we
+// legalized both of them.
AddLegalizedOperand(SDOperand(Node, 0), Result);
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
@@ -1131,8 +1130,7 @@
case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0) ||
Tmp2 != Node->getOperand(1))
-Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
- Node->getOperand(2));
+Result = DAG.getLoad(VT, Tmp1, Tmp2, Node->getOperand(2));
else
Result = SDOperand(Node, 0);
@@ -,6 +2220,140 @@
}
break;
+ case ISD::VAARG: {
+Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
+Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
+
+MVT::ValueType VT = Node->getValueType(0);
+switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
+default: assert(0 && "This action is not supported yet!");
+case TargetLowering::Custom: {
+ SDOperand Op = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
+ SDOperand Tmp = TLI.LowerOperation(Op, DAG);
+ if (Tmp.Val) {
+Result = LegalizeOp(Tmp);
+break;
+ }
+ // FALLTHROUGH if the target thinks it is legal.
+}
+case TargetLowering::Legal:
+ if (Tmp1 != Node->getOperand(0) ||
+ Tmp2 != Node->getOperand(1))
+Result = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
+ else
+Result = SDOperand(Node, 0);
+ break;
+case TargetLowering::Expand: {
+ SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
+ Node->getOperand(2));
+ // Increment the pointer, VAList, to the next vaarg
+ Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
+ DAG.getConstant(MVT::getSizeInBits(VT)/8,
+ TLI.getPointerTy()));
+ // Store the incremented VAList to the legalized pointer
+ Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3,
Tmp2,
+ Node->getOperand(2));
+ // Load the actual argument out of the pointer VAList
+ Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
+ Result = LegalizeOp(Result);
+ break;
+}
+}
+// Since VAARG produces two values, make sure to remember that we
+// legalized both of them.
+AddLegalizedOperand(SDOperand(Node, 0), Result);
+AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+return Result.getValue(Op.ResNo);
+ }
+
+ case ISD::VACOPY:
+Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
+Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
+Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
+
+switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
+default: assert(0 && "This action is not supported yet!");
+case TargetLowering::Custom: {
+ SDOperand Op = DAG.getNode(ISD::VACOPY, MVT::Other, Tmp1, Tmp2, Tmp3,
+ Node->getOperand(3), Node->getOperand(4));
+ SDOperand Tmp = TLI.LowerOperation(Op, DAG);
+ if (Tmp.Val) {
+Result = LegalizeOp(Tmp);
+break;
+ }
+ // FALLTHROUGH if the target thinks it is legal.
+}
[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.35 -> 1.36 --- Log message: First part of bug 680: http://llvm.cs.uiuc.edu/PR680 : Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything else. --- Diffs of the changes: (+0 -25) TargetLowering.h | 25 - 1 files changed, 25 deletions(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.35 llvm/include/llvm/Target/TargetLowering.h:1.36 --- llvm/include/llvm/Target/TargetLowering.h:1.35 Wed Jan 25 03:09:02 2006 +++ llvm/include/llvm/Target/TargetLowering.h Wed Jan 25 12:21:52 2006 @@ -366,31 +366,6 @@ virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, SelectionDAG &DAG); - /// LowerVAStart - This lowers the llvm.va_start intrinsic. If not - /// implemented, this method prints a message and aborts. This method should - /// return the modified chain value. Note that VAListPtr* correspond to the - /// llvm.va_start operand. - virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, - Value *VAListV, SelectionDAG &DAG); - - /// LowerVAEnd - This lowers llvm.va_end and returns the resultant chain. If - /// not implemented, this defaults to a noop. - virtual SDOperand LowerVAEnd(SDOperand Chain, SDOperand LP, Value *LV, - SelectionDAG &DAG); - - /// LowerVACopy - This lowers llvm.va_copy and returns the resultant chain. - /// If not implemented, this defaults to loading a pointer from the input and - /// storing it to the output. - virtual SDOperand LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, -SDOperand DestP, Value *DestV, -SelectionDAG &DAG); - - /// LowerVAArg - This lowers the vaarg instruction. If not implemented, this - /// prints a message and aborts. - virtual std::pair - LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, - const Type *ArgTy, SelectionDAG &DAG); - /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or /// llvm.frameaddress (depending on the value of the first argument). The /// return values are the result pointer and the resultant token chain. If ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.57 -> 1.58
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
---
Diffs of the changes: (+18 -37)
SparcV8ISelDAGToDAG.cpp | 55 +++-
1 files changed, 18 insertions(+), 37 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.57
llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.58
--- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.57Wed Jan 25
03:15:54 2006
+++ llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp Wed Jan 25 12:21:52 2006
@@ -66,11 +66,6 @@
virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
SelectionDAG &DAG);
-virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
- Value *VAListV, SelectionDAG &DAG);
-virtual std::pair
- LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
- const Type *ArgTy, SelectionDAG &DAG);
virtual std::pair
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned
Depth,
SelectionDAG &DAG);
@@ -161,9 +156,15 @@
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
- // Expand these to their default code.
- setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ // VASTART needs to be custom lowered to use the VarArgsFrameIndex
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
+
+ // Use the default implementation.
+ setOperationAction(ISD::VAARG , MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
setSchedulingPreference(SchedulingForLatency);
@@ -602,35 +603,6 @@
return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
-SDOperand SparcV8TargetLowering::
-LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
- SelectionDAG &DAG) {
-
- SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
- DAG.getRegister(V8::I6, MVT::i32),
- DAG.getConstant(VarArgsFrameOffset,
MVT::i32));
- return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset,
- VAListP, DAG.getSrcValue(VAListV));
-}
-
-std::pair SparcV8TargetLowering::
-LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
- const Type *ArgTy, SelectionDAG &DAG) {
- // Load the pointer out of the valist.
- SDOperand Ptr = DAG.getLoad(MVT::i32, Chain,
- VAListP, DAG.getSrcValue(VAListV));
- MVT::ValueType ArgVT = getValueType(ArgTy);
- SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1),
- Ptr, DAG.getSrcValue(NULL));
- // Increment the pointer.
- Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr,
-DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32));
- // Store it back to the valist.
- Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr,
- VAListP, DAG.getSrcValue(VAListV));
- return std::make_pair(Val, Chain);
-}
-
std::pair SparcV8TargetLowering::
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
SelectionDAG &DAG) {
@@ -714,6 +686,15 @@
return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
DAG.getConstant(CC, MVT::i32), CompareFlag);
}
+ case ISD::VASTART: {
+// vastart just stores the address of the VarArgsFrameIndex slot into the
+// memory location argument.
+SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
+ DAG.getRegister(V8::I6, MVT::i32),
+ DAG.getConstant(VarArgsFrameOffset,
MVT::i32));
+return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
+ Op.getOperand(1), Op.getOperand(2));
+ }
}
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp IA64ISelLowering.h
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.26 -> 1.27
IA64ISelLowering.h updated: 1.5 -> 1.6
---
Log message:
First part of bug 680: http://llvm.cs.uiuc.edu/PR680 :
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
---
Diffs of the changes: (+28 -42)
IA64ISelLowering.cpp | 63 ++-
IA64ISelLowering.h |7 -
2 files changed, 28 insertions(+), 42 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.26
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.27
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.26 Wed Jan 25 03:15:54 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Wed Jan 25 12:21:52 2006
@@ -89,6 +89,13 @@
setOperationAction(ISD::ROTR , MVT::i64 , Expand);
setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev
+ // VASTART needs to be custom lowered to use the VarArgsFrameIndex
+ setOperationAction(ISD::VAARG , MVT::Other, Custom);
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
+
+ // Use the default implementation.
+ setOperationAction(ISD::VACOPY, MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
@@ -569,41 +576,6 @@
// return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, MVT::Other, Copy, Chain,
InFlag);
}
-SDOperand
-IA64TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
- Value *VAListV, SelectionDAG &DAG) {
- // vastart just stores the address of the VarArgsFrameIndex slot.
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
- return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR,
- VAListP, DAG.getSrcValue(VAListV));
-}
-
-std::pair IA64TargetLowering::
-LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
- const Type *ArgTy, SelectionDAG &DAG) {
-
- MVT::ValueType ArgVT = getValueType(ArgTy);
- SDOperand Val = DAG.getLoad(MVT::i64, Chain,
- VAListP, DAG.getSrcValue(VAListV));
- SDOperand Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), Val,
- DAG.getSrcValue(NULL));
- unsigned Amt;
- if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
-Amt = 8;
- else {
-assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
- "Other types should have been promoted for varargs!");
-Amt = 8;
- }
- Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
-DAG.getConstant(Amt, Val.getValueType()));
- Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Val, VAListP, DAG.getSrcValue(VAListV));
- return std::make_pair(Result, Chain);
-}
-
-
-
std::pair IA64TargetLowering::
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
SelectionDAG &DAG) {
@@ -631,5 +603,26 @@
// and then just emit a 'ret' instruction
return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, Chain);
}
+ case ISD::VAARG: {
+MVT::ValueType VT = getPointerTy();
+SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
+ Op.getOperand(2));
+// Increment the pointer, VAList, to the next vaarg
+SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
+ DAG.getConstant(MVT::getSizeInBits(VT)/8,
+ VT));
+// Store the incremented VAList to the legalized pointer
+VAIncr = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), VAIncr,
+ Op.getOperand(1), Op.getOperand(2));
+// Load the actual argument out of the pointer VAList
+return DAG.getLoad(VT, VAIncr, VAList, DAG.getSrcValue(0));
+ }
+ case ISD::VASTART: {
+// vastart just stores the address of the VarArgsFrameIndex slot into the
+// memory location argument.
+SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
+return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
+ Op.getOperand(1), Op.getOperand(2));
+ }
}
}
Index: llvm/lib/Target/IA64/IA64ISelLowering.h
diff -u llvm/lib/Target/IA64/IA64ISelLowering.h:1.5
llvm/lib/Target/IA64/IA64ISelLowering.h:1.6
--- llvm/lib/Target/IA64/IA64ISelLowering.h:1.5 Fri Jan 20 14:24:31 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.h Wed Jan 25 12:21:52 2006
@@ -76,13 +76,6 @@
/// (currently, only "ret void")
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
-virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
-
[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.18 -> 1.19
---
Log message:
Set SchedulingForLatency to be the default scheduling preference for all.
---
Diffs of the changes: (+1 -0)
TargetLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.18
llvm/lib/Target/TargetLowering.cpp:1.19
--- llvm/lib/Target/TargetLowering.cpp:1.18 Wed Dec 21 17:14:54 2005
+++ llvm/lib/Target/TargetLowering.cpp Wed Jan 25 12:52:42 2006
@@ -32,6 +32,7 @@
UseUnderscoreSetJmpLongJmp = false;
IntDivIsCheap = false;
Pow2DivIsCheap = false;
+ SchedPreferenceInfo = SchedulingForLatency;
}
TargetLowering::~TargetLowering() {}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.27 -> 1.28 --- Log message: Set SchedulingForLatency to be the default scheduling preference for all. --- Diffs of the changes: (+0 -1) IA64ISelLowering.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.27 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.28 --- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.27 Wed Jan 25 12:21:52 2006 +++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Wed Jan 25 12:52:42 2006 @@ -100,7 +100,6 @@ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); - setSchedulingPreference(SchedulingForLatency); setStackPointerRegisterToSaveRestore(IA64::r12); computeRegisterProperties(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.5 -> 1.6
---
Log message:
No need to keep track of top and bottom nodes in a group since the vector is
already in order. Thanks Jim for pointing it out.
---
Diffs of the changes: (+3 -5)
ScheduleDAG.h |8 +++-
1 files changed, 3 insertions(+), 5 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.5
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.6
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.5 Wed Jan 25 03:07:50 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Wed Jan 25 12:54:24 2006
@@ -52,8 +52,6 @@
class NodeGroup {
private:
NIVector Members;// Group member nodes
-NodeInfo *Top;
-NodeInfo *Bottom;
NodeInfo *Dominator; // Node with highest latency
unsigned Latency;// Total latency of the group
int Pending;// Number of visits pending before
@@ -61,12 +59,12 @@
public:
// Ctor.
-NodeGroup() : Top(NULL), Bottom(NULL), Dominator(NULL), Pending(0) {}
+NodeGroup() : Dominator(NULL), Pending(0) {}
// Accessors
inline void setDominator(NodeInfo *D) { Dominator = D; }
-inline NodeInfo *getTop() { return Top; }
-inline NodeInfo *getBottom() { return Bottom; }
+inline NodeInfo *getTop() { return Members[0]; }
+inline NodeInfo *getBottom() { return Members[Members.size()-1]; }
inline NodeInfo *getDominator() { return Dominator; }
inline void setLatency(unsigned L) { Latency = L; }
inline unsigned getLatency() { return Latency; }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Module.h
Changes in directory llvm/include/llvm:
Module.h updated: 1.68 -> 1.69
---
Log message:
Change inline asms to be uniqued like constants, not embedded in a Module.
---
Diffs of the changes: (+0 -31)
Module.h | 31 ---
1 files changed, 31 deletions(-)
Index: llvm/include/llvm/Module.h
diff -u llvm/include/llvm/Module.h:1.68 llvm/include/llvm/Module.h:1.69
--- llvm/include/llvm/Module.h:1.68 Mon Jan 23 22:12:40 2006
+++ llvm/include/llvm/Module.h Wed Jan 25 12:55:37 2006
@@ -21,7 +21,6 @@
#include "llvm/Function.h"
#include "llvm/GlobalVariable.h"
-#include "llvm/InlineAsm.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/Support/DataTypes.h"
@@ -46,19 +45,11 @@
static void destroySentinel(GlobalVariable *GV) { delete GV; }
static iplist &getList(Module *M);
};
-template<> struct ilist_traits
-: public SymbolTableListTraits {
- // createSentinel is used to create a node that marks the end of the list.
- static InlineAsm *createSentinel();
- static void destroySentinel(InlineAsm *GV) { delete GV; }
- static iplist &getList(Module *M);
-};
class Module {
public:
typedef iplist GlobalListType;
typedef iplist FunctionListType;
- typedef iplist InlineAsmListType;
typedef SetVector LibraryListType;
// Global Variable iterators.
@@ -69,10 +60,6 @@
typedef FunctionListType::iterator iterator;
typedef FunctionListType::const_iterator const_iterator;
- // Inline Asm iterators.
- typedef InlineAsmListType::iterator inlineasm_iterator;
- typedef InlineAsmListType::const_iterator const_inlineasm_iterator;
-
// Library list iterators.
typedef LibraryListType::const_iterator lib_iterator;
@@ -82,7 +69,6 @@
private:
GlobalListType GlobalList; // The Global Variables in the module
FunctionListType FunctionList; // The Functions in the module
- InlineAsmListType InlineAsmList; // The inline asm objects in the module.
LibraryListType LibraryList; // The Libraries needed by the module
std::string GlobalScopeAsm;// Inline Asm at global scope.
SymbolTable *SymTab; // Symbol Table for the module
@@ -193,8 +179,6 @@
GlobalListType &getGlobalList() { return GlobalList; }
const FunctionListType &getFunctionList() const { return FunctionList; }
FunctionListType &getFunctionList() { return FunctionList; }
- const InlineAsmListType &getInlineAsmList() const { return InlineAsmList; }
-InlineAsmListType &getInlineAsmList() { return InlineAsmList; }
/// getSymbolTable() - Get access to the symbol table for the module, where
/// global variables and functions are identified.
@@ -222,21 +206,6 @@
size_t size() const { return FunctionList.size(); }
boolempty() const { return FunctionList.empty(); }
- // Inline Asm list interface
- inlineasm_iterator inlineasm_begin() {
-return InlineAsmList.begin();
- }
- const_inlineasm_iterator inlineasm_begin() const {
-return InlineAsmList.begin();
- }
- inlineasm_iterator inlineasm_end() {
-return InlineAsmList.end();
- }
- const_inlineasm_iterator inlineasm_end() const {
-return InlineAsmList.end();
- }
- bool inlineasm_empty() const { return InlineAsmList.empty(); }
-
//======//
// List of dependent library access functions
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/InlineAsm.h
Changes in directory llvm/include/llvm:
InlineAsm.h updated: 1.2 -> 1.3
---
Log message:
Change inline asms to be uniqued like constants, not embedded in a Module.
---
Diffs of the changes: (+12 -33)
InlineAsm.h | 45 -
1 files changed, 12 insertions(+), 33 deletions(-)
Index: llvm/include/llvm/InlineAsm.h
diff -u llvm/include/llvm/InlineAsm.h:1.2 llvm/include/llvm/InlineAsm.h:1.3
--- llvm/include/llvm/InlineAsm.h:1.2 Mon Jan 23 22:41:48 2006
+++ llvm/include/llvm/InlineAsm.h Wed Jan 25 12:55:19 2006
@@ -8,7 +8,8 @@
//===--===//
//
// This class represents the inline asm strings, which are Value*'s that are
-// used as the callee operand of call instructions.
+// used as the callee operand of call instructions. InlineAsm's are uniqued
+// like constants, and created via InlineAsm::get(...).
//
//===--===//
@@ -23,35 +24,24 @@
class PointerType;
class FunctionType;
class Module;
-template struct ilist_traits;
-template class SymbolTableListTraits;
class InlineAsm : public Value {
- friend class SymbolTableListTraits >;
InlineAsm(const InlineAsm &); // do not implement
void operator=(const InlineAsm&); // do not implement
- void setParent(Module *Parent);
- InlineAsm *Prev, *Next;
- void setNext(InlineAsm *N) { Next = N; }
- void setPrev(InlineAsm *N) { Prev = N; }
-InlineAsm *getNext() { return Next; }
- const InlineAsm *getNext() const { return Next; }
-InlineAsm *getPrev() { return Prev; }
- const InlineAsm *getPrev() const { return Prev; }
-
- Module *Parent;
std::string AsmString, Constraints;
- bool AsmHasSideEffects;
-public:
+ bool HasSideEffects;
+
InlineAsm(const FunctionType *Ty, const std::string &AsmString,
-const std::string &Constraints, bool hasSideEffects,
-const std::string &Name = "", Module *ParentModule = 0);
+const std::string &Constraints, bool hasSideEffects);
+public:
+
+ /// InlineAsm::get - Return the the specified uniqued inline asm string.
+ ///
+ static InlineAsm *get(const FunctionType *Ty, const std::string &AsmString,
+const std::string &Constraints, bool hasSideEffects);
- bool getHasSideEffects() const { return AsmHasSideEffects; }
- void setSideEffects(bool X) { AsmHasSideEffects = X; }
+ bool hasSideEffects() const { return HasSideEffects; }
/// getType - InlineAsm's are always pointers.
///
@@ -63,17 +53,6 @@
///
const FunctionType *getFunctionType() const;
- /// getParent - Get the module that this global value is contained inside
- /// of...
- Module *getParent() { return Parent; }
- const Module *getParent() const { return Parent; }
-
-
- /// removeFromParent/eraseFromParent - Unlink and unlink/delete this object
- /// from the module it is embedded into.
- void removeFromParent();
- void eraseFromParent();
-
virtual void print(std::ostream &O) const { print(O, 0); }
void print(std::ostream &OS, AssemblyAnnotationWriter *AAW) const;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.70 -> 1.71 --- Log message: Set SchedulingForLatency to be the default scheduling preference for all. --- Diffs of the changes: (+0 -1) PPCISelLowering.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.70 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.71 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.70Wed Jan 25 12:21:52 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Jan 25 12:52:42 2006 @@ -150,7 +150,6 @@ } setSetCCResultContents(ZeroOrOneSetCCResult); - setSchedulingPreference(SchedulingForLatency); setStackPointerRegisterToSaveRestore(PPC::R1); computeRegisterProperties(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.58 -> 1.59
---
Log message:
No need to keep track of top and bottom nodes in a group since the vector is
already in order. Thanks Jim for pointing it out.
---
Diffs of the changes: (+0 -5)
ScheduleDAG.cpp |5 -
1 files changed, 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.58
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.59
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.58 Wed Jan 25 03:13:41 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Wed Jan 25 12:54:24 2006
@@ -464,7 +464,6 @@
// Merge the two lists
DGroup->group_insert(DGroup->group_end(),
UGroup->group_begin(), UGroup->group_end());
-DGroup->Bottom = UGroup->Bottom;
} else if (DGroup) {
// Make user member of definers group
U->Group = DGroup;
@@ -477,7 +476,6 @@
DGroup->addPending(-CountInternalUses(DNI, U));
}
DGroup->group_push_back(U);
-DGroup->Bottom = U;
} else if (UGroup) {
// Make definer member of users group
D->Group = UGroup;
@@ -490,14 +488,11 @@
UGroup->addPending(-CountInternalUses(D, UNI));
}
UGroup->group_insert(UGroup->group_begin(), D);
-UGroup->Top= D;
} else {
D->Group = U->Group = DGroup = new NodeGroup();
DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
CountInternalUses(D, U));
DGroup->group_push_back(D);
DGroup->group_push_back(U);
-DGroup->Top= D;
-DGroup->Bottom = U;
}
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/External/SPEC/CINT2000/252.eon/Makefile
Changes in directory llvm-test/External/SPEC/CINT2000/252.eon: Makefile updated: 1.12 -> 1.13 --- Log message: eon doesn't need exceptions --- Diffs of the changes: (+2 -0) Makefile |2 ++ 1 files changed, 2 insertions(+) Index: llvm-test/External/SPEC/CINT2000/252.eon/Makefile diff -u llvm-test/External/SPEC/CINT2000/252.eon/Makefile:1.12 llvm-test/External/SPEC/CINT2000/252.eon/Makefile:1.13 --- llvm-test/External/SPEC/CINT2000/252.eon/Makefile:1.12 Tue Aug 2 14:09:44 2005 +++ llvm-test/External/SPEC/CINT2000/252.eon/Makefile Wed Jan 25 12:57:56 2006 @@ -9,6 +9,8 @@ include $(LEVEL)/Makefile.config +CFLAGS += -fno-exceptions + ifeq ($(ARCH),PowerPC) CPPFLAGS += -DFMAX_IS_DOUBLE endif ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.19 -> 1.20 --- Log message: initialize an instance var, apparently I forgot to commit this long ago --- Diffs of the changes: (+1 -0) TargetLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.19 llvm/lib/Target/TargetLowering.cpp:1.20 --- llvm/lib/Target/TargetLowering.cpp:1.19 Wed Jan 25 12:52:42 2006 +++ llvm/lib/Target/TargetLowering.cpp Wed Jan 25 12:57:15 2006 @@ -32,6 +32,7 @@ UseUnderscoreSetJmpLongJmp = false; IntDivIsCheap = false; Pow2DivIsCheap = false; + StackPointerRegisterToSaveRestore = 0; SchedPreferenceInfo = SchedulingForLatency; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp InlineAsm.cpp Module.cpp
Changes in directory llvm/lib/VMCore:
AsmWriter.cpp updated: 1.189 -> 1.190
InlineAsm.cpp updated: 1.1 -> 1.2
Module.cpp updated: 1.63 -> 1.64
---
Log message:
Change inline asms to be uniqued like constants, not embedded in a Module.
---
Diffs of the changes: (+6 -43)
AsmWriter.cpp |4 +---
InlineAsm.cpp | 28 +---
Module.cpp| 17 -
3 files changed, 6 insertions(+), 43 deletions(-)
Index: llvm/lib/VMCore/AsmWriter.cpp
diff -u llvm/lib/VMCore/AsmWriter.cpp:1.189 llvm/lib/VMCore/AsmWriter.cpp:1.190
--- llvm/lib/VMCore/AsmWriter.cpp:1.189 Mon Jan 23 22:13:11 2006
+++ llvm/lib/VMCore/AsmWriter.cpp Wed Jan 25 12:57:27 2006
@@ -21,6 +21,7 @@
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
+#include "llvm/InlineAsm.h"
#include "llvm/Instruction.h"
#include "llvm/Instructions.h"
#include "llvm/Module.h"
@@ -1270,9 +1271,6 @@
}
void InlineAsm::print(std::ostream &o, AssemblyAnnotationWriter *AAW) const {
- SlotMachine SlotTable(getParent());
- AssemblyWriter W(o, SlotTable, getParent(), AAW);
-
assert(0 && "Inline asm printing unimplemented!");
//W.write(this);
}
Index: llvm/lib/VMCore/InlineAsm.cpp
diff -u llvm/lib/VMCore/InlineAsm.cpp:1.1 llvm/lib/VMCore/InlineAsm.cpp:1.2
--- llvm/lib/VMCore/InlineAsm.cpp:1.1 Mon Jan 23 22:13:11 2006
+++ llvm/lib/VMCore/InlineAsm.cpp Wed Jan 25 12:57:27 2006
@@ -18,33 +18,15 @@
using namespace llvm;
InlineAsm::InlineAsm(const FunctionType *Ty, const std::string &asmString,
- const std::string &constraints, bool hasSideEffects,
- const std::string &name, Module *ParentModule)
- : Value(PointerType::get(Ty), Value::InlineAsmVal, name),
-Parent(0), AsmString(asmString), Constraints(constraints),
-AsmHasSideEffects(hasSideEffects) {
+ const std::string &constraints, bool hasSideEffects)
+ : Value(PointerType::get(Ty), Value::InlineAsmVal), AsmString(asmString),
+Constraints(constraints), HasSideEffects(hasSideEffects) {
LeakDetector::addGarbageObject(this);
- if (ParentModule)
-ParentModule->getInlineAsmList().push_back(this);
+ // FIXME: do various checks on the constraint string and type.
+
}
const FunctionType *InlineAsm::getFunctionType() const {
return cast(getType()->getElementType());
}
-
-void InlineAsm::setParent(Module *parent) {
- if (getParent())
-LeakDetector::addGarbageObject(this);
- Parent = parent;
- if (getParent())
-LeakDetector::removeGarbageObject(this);
-}
-
-void InlineAsm::removeFromParent() {
- getParent()->getInlineAsmList().remove(this);
-}
-
-void InlineAsm::eraseFromParent() {
- getParent()->getInlineAsmList().erase(this);
-}
Index: llvm/lib/VMCore/Module.cpp
diff -u llvm/lib/VMCore/Module.cpp:1.63 llvm/lib/VMCore/Module.cpp:1.64
--- llvm/lib/VMCore/Module.cpp:1.63 Mon Jan 23 22:13:11 2006
+++ llvm/lib/VMCore/Module.cpp Wed Jan 25 12:57:27 2006
@@ -44,30 +44,17 @@
return Ret;
}
-InlineAsm *ilist_traits::createSentinel() {
- InlineAsm *Ret = new InlineAsm(FunctionType::get(Type::VoidTy,
-std::vector(), false), "", "",
- false);
- // This should not be garbage monitored.
- LeakDetector::removeGarbageObject(Ret);
- return Ret;
-}
-
iplist &ilist_traits::getList(Module *M) {
return M->getFunctionList();
}
iplist &ilist_traits::getList(Module *M) {
return M->getGlobalList();
}
-iplist &ilist_traits::getList(Module *M) {
- return M->getInlineAsmList();
-}
// Explicit instantiations of SymbolTableListTraits since some of the methods
// are not in the public header file.
template class SymbolTableListTraits;
template class SymbolTableListTraits;
-template class SymbolTableListTraits;
//===--===//
// Primitive Module methods.
@@ -79,8 +66,6 @@
FunctionList.setParent(this);
GlobalList.setItemParent(this);
GlobalList.setParent(this);
- InlineAsmList.setItemParent(this);
- InlineAsmList.setParent(this);
SymTab = new SymbolTable();
}
@@ -90,8 +75,6 @@
GlobalList.setParent(0);
FunctionList.clear();
FunctionList.setParent(0);
- InlineAsmList.clear();
- InlineAsmList.setParent(0);
LibraryList.clear();
delete SymTab;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.58 -> 1.59 --- Log message: Set SchedulingForLatency to be the default scheduling preference for all. --- Diffs of the changes: (+0 -1) SparcV8ISelDAGToDAG.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp diff -u llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.58 llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.59 --- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.58Wed Jan 25 12:21:52 2006 +++ llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp Wed Jan 25 12:52:42 2006 @@ -167,7 +167,6 @@ setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); - setSchedulingPreference(SchedulingForLatency); setStackPointerRegisterToSaveRestore(V8::O6); computeRegisterProperties(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/InlineAsm.h
Changes in directory llvm/include/llvm:
InlineAsm.h updated: 1.3 -> 1.4
---
Log message:
add some useful accessors :)
---
Diffs of the changes: (+3 -0)
InlineAsm.h |3 +++
1 files changed, 3 insertions(+)
Index: llvm/include/llvm/InlineAsm.h
diff -u llvm/include/llvm/InlineAsm.h:1.3 llvm/include/llvm/InlineAsm.h:1.4
--- llvm/include/llvm/InlineAsm.h:1.3 Wed Jan 25 12:55:19 2006
+++ llvm/include/llvm/InlineAsm.h Wed Jan 25 13:58:26 2006
@@ -52,6 +52,9 @@
/// getFunctionType - InlineAsm's are always pointers to functions.
///
const FunctionType *getFunctionType() const;
+
+ const std::string &getAsmString() const { return AsmString; }
+ const std::string &getConstraintString() const { return Constraints; }
virtual void print(std::ostream &O) const { print(O, 0); }
void print(std::ostream &OS, AssemblyAnnotationWriter *AAW) const;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.3 -> 1.4 --- Log message: Don't break the optimized build (by incorrect placement of #endif) --- Diffs of the changes: (+1 -1) ScheduleDAGList.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.3 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.4 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.3 Wed Jan 25 11:17:49 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Wed Jan 25 15:49:13 2006 @@ -270,8 +270,8 @@ std::cerr << " has not been scheduled!\n"; assert(0); } -#endif } +#endif // Reverse the order if it is bottom up. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.29 -> 1.30 --- Log message: make things compile again --- Diffs of the changes: (+4 -0) AlphaISelLowering.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.29 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.30 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.29Wed Jan 25 12:21:52 2006 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jan 25 15:54:38 2006 @@ -137,6 +137,10 @@ setOperationAction(ISD::ConstantPool, MVT::i64, Custom); setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom); + setOperationAction(ISD::VASTART, MVT::Other, Custom); + setOperationAction(ISD::VAEND, MVT::Other, Custom); + setOperationAction(ISD::VACOPY, MVT::Other, Custom); + setStackPointerRegisterToSaveRestore(Alpha::R30); addLegalFPImmediate(+0.0); //F31 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-poolalloc/lib/PoolAllocate/AccessTrace.cpp PointerCompress.cpp PoolAllocate.cpp PoolOptimize.cpp TransformFunctionBody.cpp
Changes in directory llvm-poolalloc/lib/PoolAllocate:
AccessTrace.cpp updated: 1.3 -> 1.4
PointerCompress.cpp updated: 1.64 -> 1.65
PoolAllocate.cpp updated: 1.122 -> 1.123
PoolOptimize.cpp updated: 1.5 -> 1.6
TransformFunctionBody.cpp updated: 1.49 -> 1.50
---
Log message:
silence some gcc warnings
---
Diffs of the changes: (+29 -26)
AccessTrace.cpp |4 ++--
PointerCompress.cpp |8
PoolAllocate.cpp | 17 +
PoolOptimize.cpp | 24 +---
TransformFunctionBody.cpp |2 +-
5 files changed, 29 insertions(+), 26 deletions(-)
Index: llvm-poolalloc/lib/PoolAllocate/AccessTrace.cpp
diff -u llvm-poolalloc/lib/PoolAllocate/AccessTrace.cpp:1.3
llvm-poolalloc/lib/PoolAllocate/AccessTrace.cpp:1.4
--- llvm-poolalloc/lib/PoolAllocate/AccessTrace.cpp:1.3 Wed May 18 14:56:28 2005
+++ llvm-poolalloc/lib/PoolAllocate/AccessTrace.cpp Wed Jan 25 16:07:36 2006
@@ -61,9 +61,9 @@
VoidPtrTy = PointerType::get(Type::SByteTy);
AccessTraceInitFn = M.getOrInsertFunction("poolaccesstraceinit",
-Type::VoidTy,0);
+Type::VoidTy,NULL);
PoolAccessTraceFn = M.getOrInsertFunction("poolaccesstrace", Type::VoidTy,
-VoidPtrTy, VoidPtrTy, 0);
+VoidPtrTy, VoidPtrTy, NULL);
}
void PoolAccessTrace::InstrumentAccess(Instruction *I, Value *Ptr,
Index: llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp
diff -u llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp:1.64
llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp:1.65
--- llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp:1.64Tue Jan 24
14:41:19 2006
+++ llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp Wed Jan 25 16:07:36 2006
@@ -899,7 +899,7 @@
const DSGraph *CG = 0;
Function *Callee = CI.getCalledFunction();
if (Callee)
-if (FI = PtrComp.getPoolAlloc()->getFuncInfoOrClone(*Callee))
+if ((FI = PtrComp.getPoolAlloc()->getFuncInfoOrClone(*Callee)))
CG = &PtrComp.getGraphForFunc(FI);
if (!Callee) {
@@ -1415,11 +1415,11 @@
const Type *PoolDescPtrTy = PointerType::get(ArrayType::get(VoidPtrTy, 16));
PoolInitPC = M.getOrInsertFunction("poolinit_pc", VoidPtrTy, PoolDescPtrTy,
- Type::UIntTy, Type::UIntTy, 0);
+ Type::UIntTy, Type::UIntTy, NULL);
PoolDestroyPC = M.getOrInsertFunction("pooldestroy_pc", Type::VoidTy,
-PoolDescPtrTy, 0);
+PoolDescPtrTy, NULL);
PoolAllocPC = M.getOrInsertFunction("poolalloc_pc", SCALARUINTTYPE,
- PoolDescPtrTy, Type::UIntTy, 0);
+ PoolDescPtrTy, Type::UIntTy, NULL);
// FIXME: Need bumppointer versions as well as realloc??/memalign??
}
Index: llvm-poolalloc/lib/PoolAllocate/PoolAllocate.cpp
diff -u llvm-poolalloc/lib/PoolAllocate/PoolAllocate.cpp:1.122
llvm-poolalloc/lib/PoolAllocate/PoolAllocate.cpp:1.123
--- llvm-poolalloc/lib/PoolAllocate/PoolAllocate.cpp:1.122 Tue Jan 24
14:41:19 2006
+++ llvm-poolalloc/lib/PoolAllocate/PoolAllocate.cppWed Jan 25 16:07:36 2006
@@ -182,37 +182,38 @@
// Get poolinit function.
PoolInit = CurModule->getOrInsertFunction("poolinit", Type::VoidTy,
PoolDescPtrTy, Type::UIntTy,
-Type::UIntTy, 0);
+Type::UIntTy, NULL);
// Get pooldestroy function.
PoolDestroy = CurModule->getOrInsertFunction("pooldestroy", Type::VoidTy,
- PoolDescPtrTy, 0);
+ PoolDescPtrTy, NULL);
// The poolalloc function.
PoolAlloc = CurModule->getOrInsertFunction("poolalloc",
VoidPtrTy, PoolDescPtrTy,
- Type::UIntTy, 0);
+ Type::UIntTy, NULL);
// The poolrealloc function.
PoolRealloc = CurModule->getOrInsertFunction("poolrealloc",
VoidPtrTy, PoolDescPtrTy,
- VoidPtrTy, Type::UIntTy, 0);
+ VoidPtrTy, Type::UIntTy, NULL);
// The poolmemalign function.
PoolMemAlign = CurModule->getOrInsertFunction("poolmemalign",
VoidPtrTy, PoolDescPtrTy,
-Type::UIntTy, Type::UIntTy, 0);
+Type::UIntTy, Type::UIntTy,
+NULL);
// Get the poolfree function.
PoolFree = CurModule->getOrI
[llvm-commits] CVS: llvm/include/llvm/InlineAsm.h
Changes in directory llvm/include/llvm:
InlineAsm.h updated: 1.4 -> 1.5
---
Log message:
add another method
---
Diffs of the changes: (+7 -0)
InlineAsm.h |7 +++
1 files changed, 7 insertions(+)
Index: llvm/include/llvm/InlineAsm.h
diff -u llvm/include/llvm/InlineAsm.h:1.4 llvm/include/llvm/InlineAsm.h:1.5
--- llvm/include/llvm/InlineAsm.h:1.4 Wed Jan 25 13:58:26 2006
+++ llvm/include/llvm/InlineAsm.h Wed Jan 25 16:10:35 2006
@@ -59,6 +59,13 @@
virtual void print(std::ostream &O) const { print(O, 0); }
void print(std::ostream &OS, AssemblyAnnotationWriter *AAW) const;
+ /// Verify - This static method can be used by the parser to check to see if
+ /// the specified constraint string is legal for the type. This returns true
+ /// if legal, false if not.
+ ///
+ static bool Verify(const FunctionType *Ty, const std::string &Constraints);
+
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const InlineAsm *) { return true; }
static inline bool classof(const Value *V) {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/AsmParser/Lexer.l llvmAsmParser.y ParserInternals.h
Changes in directory llvm/lib/AsmParser:
Lexer.l updated: 1.70 -> 1.71
llvmAsmParser.y updated: 1.248 -> 1.249
ParserInternals.h updated: 1.42 -> 1.43
---
Log message:
Parse inline asm objects
---
Diffs of the changes: (+56 -3)
Lexer.l |1 +
ParserInternals.h | 27 +--
llvmAsmParser.y | 31 ++-
3 files changed, 56 insertions(+), 3 deletions(-)
Index: llvm/lib/AsmParser/Lexer.l
diff -u llvm/lib/AsmParser/Lexer.l:1.70 llvm/lib/AsmParser/Lexer.l:1.71
--- llvm/lib/AsmParser/Lexer.l:1.70 Mon Jan 23 18:40:17 2006
+++ llvm/lib/AsmParser/Lexer.l Wed Jan 25 16:26:43 2006
@@ -214,6 +214,7 @@
section { return SECTION; }
module { return MODULE; }
asm { return ASM_TOK; }
+sideeffect { return SIDEEFFECT; }
cc { return CC_TOK; }
ccc { return CCC_TOK; }
Index: llvm/lib/AsmParser/llvmAsmParser.y
diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.248
llvm/lib/AsmParser/llvmAsmParser.y:1.249
--- llvm/lib/AsmParser/llvmAsmParser.y:1.248Mon Jan 23 22:14:29 2006
+++ llvm/lib/AsmParser/llvmAsmParser.y Wed Jan 25 16:26:43 2006
@@ -14,6 +14,7 @@
%{
#include "ParserInternals.h"
#include "llvm/CallingConv.h"
+#include "llvm/InlineAsm.h"
#include "llvm/Instructions.h"
#include "llvm/Module.h"
#include "llvm/SymbolTable.h"
@@ -316,6 +317,17 @@
ThrowException("Constant expression type different from required type!");
return D.ConstantValue;
+ case ValID::InlineAsmVal: {// Inline asm expression
+const PointerType *PTy = dyn_cast(Ty);
+const FunctionType *FTy =
+ PTy ? dyn_cast(PTy->getElementType()) : 0;
+if (!FTy || !InlineAsm::Verify(FTy, D.IAD->Constraints))
+ ThrowException("Invalid type for asm constraint string!");
+InlineAsm *IA = InlineAsm::get(FTy, D.IAD->AsmString, D.IAD->Constraints,
+ D.IAD->HasSideEffects);
+D.destroy(); // Free InlineAsmDescriptor.
+return IA;
+ }
default:
assert(0 && "Unhandled case!");
return 0;
@@ -932,6 +944,7 @@
%typeGlobalType // GLOBAL or CONSTANT?
%typeOptVolatile // 'volatile' or not
%typeOptTailCall // TAIL CALL or plain CALL.
+%typeOptSideEffect // 'sideeffect' or not.
%typeOptLinkage
%type BigOrLittle
@@ -967,7 +980,7 @@
%token DECLARE GLOBAL CONSTANT SECTION VOLATILE
%token TO DOTDOTDOT NULL_TOK UNDEF CONST INTERNAL LINKONCE WEAK APPENDING
%token OPAQUE NOT EXTERNAL TARGET TRIPLE ENDIAN POINTERSIZE LITTLE BIG ALIGN
-%token DEPLIBS CALL TAIL ASM_TOK MODULE
+%token DEPLIBS CALL TAIL ASM_TOK MODULE SIDEEFFECT
%token CC_TOK CCC_TOK FASTCC_TOK COLDCC_TOK
%type OptCallingConv
@@ -1831,6 +1844,13 @@
//Rules to match Basic Blocks
//===--===//
+OptSideEffect : /* empty */ {
+$$ = false;
+ }
+ | SIDEEFFECT {
+$$ = true;
+ };
+
ConstValueRef : ESINT64VAL {// A reference to a direct constant
$$ = ValID::create($1);
}
@@ -1881,6 +1901,15 @@
}
| ConstExpr {
$$ = ValID::create($1);
+ }
+ | ASM_TOK OptSideEffect STRINGCONSTANT ',' STRINGCONSTANT {
+char *End = UnEscapeLexed($3, true);
+std::string AsmStr = std::string($3, End);
+End = UnEscapeLexed($5, true);
+std::string Constraints = std::string($5, End);
+$$ = ValID::createInlineAsm(AsmStr, Constraints, $2);
+free($3);
+free($5);
};
// SymbolicValueRef - Reference to one of two ways of symbolically refering to
Index: llvm/lib/AsmParser/ParserInternals.h
diff -u llvm/lib/AsmParser/ParserInternals.h:1.42
llvm/lib/AsmParser/ParserInternals.h:1.43
--- llvm/lib/AsmParser/ParserInternals.h:1.42 Wed Dec 21 11:53:02 2005
+++ llvm/lib/AsmParser/ParserInternals.hWed Jan 25 16:26:43 2006
@@ -72,6 +72,17 @@
throw ParseException(CurFilename, message, LineNo);
}
+/// InlineAsmDescriptor - This is a simple class that holds info about inline
+/// asm blocks, for use by ValID.
+struct InlineAsmDescriptor {
+ std::string AsmString, Constraints;
+ bool HasSideEffects;
+
+ InlineAsmDescriptor(const std::string &as, const std::string &c, bool HSE)
+: AsmString(as), Constraints(c), HasSideEffects(HSE) {}
+};
+
+
// ValID - Represents a reference of a definition of some sort. This may
either
// be a numeric reference or a symbolic (%var) reference. This is just a
// discriminated union.
@@ -82,7 +93,7 @@
struct ValID {
enum {
NumberVal, NameVal, ConstSIntVal, ConstUIntVal, ConstFPVal, ConstNullVal,
-ConstUndefVal, ConstZeroVal, ConstantVal,
+ConstUndefVal, ConstZeroVal, ConstantVal, InlineAsmVal
} Type;
union {
@@ -92,6 +103,7 @@
uint64_t UConstPool64;// Unsigned constant pool reference.
double ConstPoolFP; // Floating point constant pool reference
Constant *
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.30 -> 1.31 --- Log message: forgot one --- Diffs of the changes: (+1 -0) AlphaISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.30 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.31 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.30Wed Jan 25 15:54:38 2006 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jan 25 16:28:07 2006 @@ -140,6 +140,7 @@ setOperationAction(ISD::VASTART, MVT::Other, Custom); setOperationAction(ISD::VAEND, MVT::Other, Custom); setOperationAction(ISD::VACOPY, MVT::Other, Custom); + setOperationAction(ISD::VAARG, MVT::Other, Custom); setStackPointerRegisterToSaveRestore(Alpha::R30); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp InlineAsm.cpp
Changes in directory llvm/lib/VMCore:
AsmWriter.cpp updated: 1.190 -> 1.191
InlineAsm.cpp updated: 1.2 -> 1.3
---
Log message:
Print InlineAsm objects
---
Diffs of the changes: (+27 -9)
AsmWriter.cpp | 16
InlineAsm.cpp | 20 +++-
2 files changed, 27 insertions(+), 9 deletions(-)
Index: llvm/lib/VMCore/AsmWriter.cpp
diff -u llvm/lib/VMCore/AsmWriter.cpp:1.190 llvm/lib/VMCore/AsmWriter.cpp:1.191
--- llvm/lib/VMCore/AsmWriter.cpp:1.190 Wed Jan 25 12:57:27 2006
+++ llvm/lib/VMCore/AsmWriter.cpp Wed Jan 25 16:26:05 2006
@@ -556,9 +556,18 @@
Out << getLLVMName(V->getName());
else {
const Constant *CV = dyn_cast(V);
-if (CV && !isa(CV))
+if (CV && !isa(CV)) {
WriteConstantInt(Out, CV, PrintName, TypeTable, Machine);
-else {
+} else if (const InlineAsm *IA = dyn_cast(V)) {
+ Out << "asm ";
+ if (IA->hasSideEffects())
+Out << "sideeffect ";
+ Out << '"';
+ PrintEscapedString(IA->getAsmString(), Out);
+ Out << "\", \"";
+ PrintEscapedString(IA->getConstraintString(), Out);
+ Out << '"';
+} else {
int Slot;
if (Machine) {
Slot = Machine->getSlot(V);
@@ -1271,8 +1280,7 @@
}
void InlineAsm::print(std::ostream &o, AssemblyAnnotationWriter *AAW) const {
- assert(0 && "Inline asm printing unimplemented!");
- //W.write(this);
+ WriteAsOperand(o, this, true, true, 0);
}
void BasicBlock::print(std::ostream &o, AssemblyAnnotationWriter *AAW) const {
Index: llvm/lib/VMCore/InlineAsm.cpp
diff -u llvm/lib/VMCore/InlineAsm.cpp:1.2 llvm/lib/VMCore/InlineAsm.cpp:1.3
--- llvm/lib/VMCore/InlineAsm.cpp:1.2 Wed Jan 25 12:57:27 2006
+++ llvm/lib/VMCore/InlineAsm.cpp Wed Jan 25 16:26:05 2006
@@ -13,20 +13,30 @@
#include "llvm/InlineAsm.h"
#include "llvm/DerivedTypes.h"
-#include "llvm/Module.h"
-#include "llvm/Support/LeakDetector.h"
using namespace llvm;
+// NOTE: when memoizing the function type, we have to be careful to handle the
+// case when the type gets refined.
+
+InlineAsm *InlineAsm::get(const FunctionType *Ty, const std::string &AsmString,
+ const std::string &Constraints, bool hasSideEffects)
{
+ // FIXME: memoize!
+ return new InlineAsm(Ty, AsmString, Constraints, hasSideEffects);
+}
+
InlineAsm::InlineAsm(const FunctionType *Ty, const std::string &asmString,
const std::string &constraints, bool hasSideEffects)
: Value(PointerType::get(Ty), Value::InlineAsmVal), AsmString(asmString),
Constraints(constraints), HasSideEffects(hasSideEffects) {
- LeakDetector::addGarbageObject(this);
- // FIXME: do various checks on the constraint string and type.
-
+ // Do various checks on the constraint string and type.
+ assert(Verify(Ty, constraints) && "Function type not legal for
constraints!");
}
const FunctionType *InlineAsm::getFunctionType() const {
return cast(getType()->getElementType());
}
+
+bool InlineAsm::Verify(const FunctionType *Ty, const std::string &Constraints)
{
+ return true;
+}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp Reader.h
Changes in directory llvm/lib/Bytecode/Reader:
Reader.cpp updated: 1.186 -> 1.187
Reader.h updated: 1.26 -> 1.27
---
Log message:
add bc reader/writer support for inline asm
---
Diffs of the changes: (+33 -10)
Reader.cpp | 39 +++
Reader.h |4 ++--
2 files changed, 33 insertions(+), 10 deletions(-)
Index: llvm/lib/Bytecode/Reader/Reader.cpp
diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.186
llvm/lib/Bytecode/Reader/Reader.cpp:1.187
--- llvm/lib/Bytecode/Reader/Reader.cpp:1.186 Wed Jan 25 11:18:50 2006
+++ llvm/lib/Bytecode/Reader/Reader.cpp Wed Jan 25 17:08:15 2006
@@ -22,6 +22,7 @@
#include "llvm/BasicBlock.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
+#include "llvm/InlineAsm.h"
#include "llvm/Instructions.h"
#include "llvm/SymbolTable.h"
#include "llvm/Bytecode/Format.h"
@@ -1404,7 +1405,7 @@
}
/// Parse a single constant value
-Constant *BytecodeReader::ParseConstantValue(unsigned TypeID) {
+Value *BytecodeReader::ParseConstantPoolValue(unsigned TypeID) {
// We must check for a ConstantExpr before switching by type because
// a ConstantExpr can be of any type, and has no explicit value.
//
@@ -1412,11 +1413,32 @@
unsigned isExprNumArgs = read_vbr_uint();
if (isExprNumArgs) {
-// 'undef' is encoded with 'exprnumargs' == 1.
-if (!hasNoUndefValue)
- if (--isExprNumArgs == 0)
+if (!hasNoUndefValue) {
+ // 'undef' is encoded with 'exprnumargs' == 1.
+ if (isExprNumArgs == 1)
return UndefValue::get(getType(TypeID));
+ // Inline asm is encoded with exprnumargs == ~0U.
+ if (isExprNumArgs == ~0U) {
+std::string AsmStr = read_str();
+std::string ConstraintStr = read_str();
+unsigned Flags = read_vbr_uint();
+
+const PointerType *PTy = dyn_cast(getType(TypeID));
+const FunctionType *FTy =
+ PTy ? dyn_cast(PTy->getElementType()) : 0;
+
+if (!FTy || !InlineAsm::Verify(FTy, ConstraintStr))
+ error("Invalid constraints for inline asm");
+if (Flags & ~1U)
+ error("Invalid flags for inline asm");
+bool HasSideEffects = Flags & 1;
+return InlineAsm::get(FTy, AsmStr, ConstraintStr, HasSideEffects);
+ }
+
+ --isExprNumArgs;
+}
+
// FIXME: Encoding of constant exprs could be much more compact!
std::vector ArgVec;
ArgVec.reserve(isExprNumArgs);
@@ -1695,9 +1717,9 @@
ParseStringConstants(NumEntries, Tab);
} else {
for (unsigned i = 0; i < NumEntries; ++i) {
-Constant *C = ParseConstantValue(Typ);
-assert(C && "ParseConstantValue returned NULL!");
-unsigned Slot = insertValue(C, Typ, Tab);
+Value *V = ParseConstantPoolValue(Typ);
+assert(V && "ParseConstantPoolValue returned NULL!");
+unsigned Slot = insertValue(V, Typ, Tab);
// If we are reading a function constant table, make sure that we
adjust
// the slot number to be the real global constant number.
@@ -1705,7 +1727,8 @@
if (&Tab != &ModuleValues && Typ < ModuleValues.size() &&
ModuleValues[Typ])
Slot += ModuleValues[Typ]->size();
-ResolveReferencesToConstant(C, Typ, Slot);
+if (Constant *C = dyn_cast(V))
+ ResolveReferencesToConstant(C, Typ, Slot);
}
}
}
Index: llvm/lib/Bytecode/Reader/Reader.h
diff -u llvm/lib/Bytecode/Reader/Reader.h:1.26
llvm/lib/Bytecode/Reader/Reader.h:1.27
--- llvm/lib/Bytecode/Reader/Reader.h:1.26 Thu Jan 19 00:57:58 2006
+++ llvm/lib/Bytecode/Reader/Reader.h Wed Jan 25 17:08:15 2006
@@ -229,8 +229,8 @@
void ParseConstantPool(ValueTable& Values, TypeListTy& Types,
bool isFunction);
- /// @brief Parse a single constant value
- Constant* ParseConstantValue(unsigned TypeID);
+ /// @brief Parse a single constant pool value
+ Value *ParseConstantPoolValue(unsigned TypeID);
/// @brief Parse a block of types constants
void ParseTypes(TypeListTy &Tab, unsigned NumEntries);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Bytecode/Writer/SlotCalculator.cpp SlotCalculator.h Writer.cpp WriterInternals.h
Changes in directory llvm/lib/Bytecode/Writer:
SlotCalculator.cpp updated: 1.72 -> 1.73
SlotCalculator.h updated: 1.22 -> 1.23
Writer.cpp updated: 1.118 -> 1.119
WriterInternals.h updated: 1.26 -> 1.27
---
Log message:
add bc reader/writer support for inline asm
---
Diffs of the changes: (+41 -24)
SlotCalculator.cpp | 25 -
SlotCalculator.h | 14 +++---
Writer.cpp | 22 +++---
WriterInternals.h |4 +++-
4 files changed, 41 insertions(+), 24 deletions(-)
Index: llvm/lib/Bytecode/Writer/SlotCalculator.cpp
diff -u llvm/lib/Bytecode/Writer/SlotCalculator.cpp:1.72
llvm/lib/Bytecode/Writer/SlotCalculator.cpp:1.73
--- llvm/lib/Bytecode/Writer/SlotCalculator.cpp:1.72Sat Jun 18 13:34:51 2005
+++ llvm/lib/Bytecode/Writer/SlotCalculator.cpp Wed Jan 25 17:08:15 2006
@@ -18,6 +18,7 @@
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
+#include "llvm/InlineAsm.h"
#include "llvm/Instructions.h"
#include "llvm/Module.h"
#include "llvm/SymbolTable.h"
@@ -27,7 +28,6 @@
#include "llvm/ADT/STLExtras.h"
#include
#include
-
using namespace llvm;
#if 0
@@ -181,11 +181,13 @@
SC_DEBUG("Inserting function constants:\n");
for (Module::const_iterator F = TheModule->begin(), E = TheModule->end();
F != E; ++F) {
-for (const_inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I){
- for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
-if (isa(I->getOperand(op)) &&
-!isa(I->getOperand(op)))
- getOrCreateSlot(I->getOperand(op));
+for (const_inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) {
+ for (User::const_op_iterator OI = I->op_begin(), E = I->op_end();
+ OI != E; ++OI) {
+if ((isa(*OI) && !isa(*OI)) ||
+isa(*OI))
+ getOrCreateSlot(*OI);
+ }
getOrCreateSlot(I->getType());
}
processSymbolTableConstants(&F->getSymbolTable());
@@ -286,7 +288,7 @@
for(Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); I !=
E; ++I)
getOrCreateSlot(I);
- if ( !ModuleContainsAllFunctionConstants ) {
+ if (!ModuleContainsAllFunctionConstants) {
// Iterate over all of the instructions in the function, looking for
// constant values that are referenced. Add these to the value pools
// before any nonconstant values. This will be turned into the constant
@@ -295,12 +297,9 @@
// Emit all of the constants that are being used by the instructions in
// the function...
-constant_iterator CI = constant_begin(F);
-constant_iterator CE = constant_end(F);
-while ( CI != CE ) {
- this->getOrCreateSlot(*CI);
- ++CI;
-}
+for (constant_iterator CI = constant_begin(F), CE = constant_end(F);
+ CI != CE; ++CI)
+ getOrCreateSlot(*CI);
// If there is a symbol table, it is possible that the user has names for
// constants that are not being used. In this case, we will have problems
Index: llvm/lib/Bytecode/Writer/SlotCalculator.h
diff -u llvm/lib/Bytecode/Writer/SlotCalculator.h:1.22
llvm/lib/Bytecode/Writer/SlotCalculator.h:1.23
--- llvm/lib/Bytecode/Writer/SlotCalculator.h:1.22 Thu Apr 21 16:48:46 2005
+++ llvm/lib/Bytecode/Writer/SlotCalculator.h Wed Jan 25 17:08:15 2006
@@ -74,9 +74,9 @@
SlotCalculator(const SlotCalculator &); // DO NOT IMPLEMENT
void operator=(const SlotCalculator &); // DO NOT IMPLEMENT
public:
- SlotCalculator(const Module *M );
+ SlotCalculator(const Module *M);
// Start out in incorp state
- SlotCalculator(const Function *F );
+ SlotCalculator(const Function *F);
/// getSlot - Return the slot number of the specified value in it's type
/// plane. This returns < 0 on error!
@@ -146,19 +146,19 @@
// they haven't been inserted already, they get inserted, otherwise
// they are ignored.
//
- int getOrCreateSlot(const Value *D);
- int getOrCreateSlot(const Type* T);
+ int getOrCreateSlot(const Value *V);
+ int getOrCreateSlot(const Type *T);
// insertValue - Insert a value into the value table... Return the
// slot that it occupies, or -1 if the declaration is to be ignored
// because of the IgnoreNamedNodes flag.
//
int insertValue(const Value *D, bool dontIgnore = false);
- int insertType(const Type* T, bool dontIgnore = false );
+ int insertType(const Type *T, bool dontIgnore = false);
// doInsertValue - Small helper function to be called only be insertVal.
- int doInsertValue(const Value *D);
- int doInsertType(const Type*T);
+ int doInsertValue(const Value *V);
+ int doInsertType(const Type *T);
// processModule - Process all of the module level function declarations and
// types that are available.
Index: llvm/lib/Bytecode/Writer/Writer.cpp
diff -u llvm/lib/Bytecode/Writer/Writer.cpp:1.118
llvm/lib/Bytecode/Writer/Writer.cpp:1.119
--- llvm/lib/Bytecode/Writer/Writer.cpp:1.118
[llvm-commits] CVS: llvm/docs/BytecodeFormat.html
Changes in directory llvm/docs: BytecodeFormat.html updated: 1.49 -> 1.50 --- Log message: update the bytecode format guide for the encoding of inline asm. --- Diffs of the changes: (+62 -10) BytecodeFormat.html | 72 1 files changed, 62 insertions(+), 10 deletions(-) Index: llvm/docs/BytecodeFormat.html diff -u llvm/docs/BytecodeFormat.html:1.49 llvm/docs/BytecodeFormat.html:1.50 --- llvm/docs/BytecodeFormat.html:1.49 Mon Jan 23 17:38:09 2006 +++ llvm/docs/BytecodeFormat.html Wed Jan 25 17:31:53 2006 @@ -1275,16 +1275,21 @@ + -Constant Field +Simple Constant Pool +Entries + -Constants come in many shapes and flavors. The sections that follow -define the format for each of them. All constants start with a Constant pool entries come in many shapes and flavors. The sections that +follow define the format for each of them. All constants start with a uint32_vbr encoded integer that provides the number of operands for the constant. For primitive, structure, and -array constants, this will always be zero since those types of -constants have no operands. In this case, we have the following field -definitions: +array constants, this will always be zero to indicate that the form of the +constant is solely determined by its type. In this case, we have the following +field definitions, based on type: + Bool. This is written as an uint32_vbr of value 1U or 0U. @@ -1303,12 +1308,59 @@ field values of the structure. + + + +Undef Entries + + When the number of operands to the constant is one, we have an 'undef' value of the specified type. + + + +Inline Assembler Entries + + +Inline Assembler entries are stored in the constant pool, though they are not + officially LLVM constants. These entries are marked with a value of + "4294967295" (all ones) for the number of operands. They are encoded as + follows: + + + + + Type + Field Description + + + string + The asm string. + + + string + The constraints string. + + + uint32_vbr + Flags + + + + +Currently, the only defined flag, the low bit, indicates whether or not the + inline assembler has side effects. + + + + +Constant Expression Entries + + -When the number of operands to the constant is greater than one, we have a -constant expression and its field format is provided in the table below, and the -number is equal to the number of operands+1. +Otherwise, we have a constant expression. The format of the constant +expression is specified in the table below, and the number is equal to the +number of operands+1. @@ -2096,7 +2148,7 @@ mailto:[EMAIL PROTECTED]">Reid Spencer and mailto:[EMAIL PROTECTED]">Chris Lattner http://llvm.cs.uiuc.edu";>The LLVM Compiler Infrastructure -Last modified: $Date: 2006/01/23 23:38:09 $ +Last modified: $Date: 2006/01/25 23:31:53 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.31 -> 1.32 --- Log message: oops --- Diffs of the changes: (+1 -1) AlphaISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.31 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.32 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.31Wed Jan 25 16:28:07 2006 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jan 25 17:33:32 2006 @@ -138,7 +138,7 @@ setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom); setOperationAction(ISD::VASTART, MVT::Other, Custom); - setOperationAction(ISD::VAEND, MVT::Other, Custom); + setOperationAction(ISD::VAEND, MVT::Other, Expand); setOperationAction(ISD::VACOPY, MVT::Other, Custom); setOperationAction(ISD::VAARG, MVT::Other, Custom); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Feature/inlineasm.ll
Changes in directory llvm/test/Feature:
inlineasm.ll updated: 1.2 -> 1.3
---
Log message:
new tests for actual inline asm expressions
---
Diffs of the changes: (+8 -2)
inlineasm.ll | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
Index: llvm/test/Feature/inlineasm.ll
diff -u llvm/test/Feature/inlineasm.ll:1.2 llvm/test/Feature/inlineasm.ll:1.3
--- llvm/test/Feature/inlineasm.ll:1.2 Mon Jan 23 18:37:20 2006
+++ llvm/test/Feature/inlineasm.ll Wed Jan 25 17:49:54 2006
@@ -1,8 +1,14 @@
-; RUN: llvm-as %s -o - | llvm-dis > Output/t1.ll
-; RUN: llvm-as Output/t1.ll -o - | llvm-dis > Output/t2.ll
+; RUN: llvm-as %s -o /dev/null -f &&
+; RUN: llvm-as %s -o - | llvm-dis > Output/t1.ll &&
+; RUN: llvm-as Output/t1.ll -o - | llvm-dis > Output/t2.ll &&
; RUN: diff Output/t1.ll Output/t2.ll
module asm "this is an inline asm block"
module asm "this is another inline asm block"
+int %test() {
+ %X = call int asm "tricky here $0, $1", "=r,r"(int 4)
+ call void asm sideeffect "eieio", ""()
+ ret int %X
+}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/LangRef.html
Changes in directory llvm/docs: LangRef.html updated: 1.133 -> 1.134 --- Log message: document the syntax of inline asm --- Diffs of the changes: (+56 -1) LangRef.html | 57 - 1 files changed, 56 insertions(+), 1 deletion(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.133 llvm/docs/LangRef.html:1.134 --- llvm/docs/LangRef.html:1.133Mon Jan 23 18:37:10 2006 +++ llvm/docs/LangRef.html Wed Jan 25 17:47:57 2006 @@ -55,6 +55,11 @@ Constant Expressions + Other Values + + Inline Assembler Expressions + + Instruction Reference Terminator Instructions @@ -1145,6 +1150,56 @@ + Other Values + + + + +Inline Assembler Expressions + + + + + +LLVM supports inline assembler expressions (as opposed to +Module-Level Inline Assembly) through the use of a special value. This +value represents the inline assembler as a string (containing the instructions +to emit), a list of operand constraints (stored as a string), and a flag that +indicates whether or not the inline asm expression has side effects. An example +inline assembler expression is: + + + + int(int) asm "bswap $0", "=r,r" + + + +Inline assembler expressions may only be used as the callee operand of +a call instruction. Thus, typically we have: + + + + %X = call int asm "bswap $0", "=r,r"(int %Y) + + + +Inline asms with side effects not visible in the constraint list must be marked +as having side effects. This is done through the use of the +'sideeffect' keyword, like so: + + + + call void asm sideeffect "eieio", ""() + + +TODO: The format of the asm and constraints string still need to be +documented here. Constraints on what can be done (e.g. duplication, moving, etc +need to be documented). + + + + + Instruction Reference @@ -3679,7 +3734,7 @@ mailto:[EMAIL PROTECTED]">Chris Lattner http://llvm.cs.uiuc.edu";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/01/24 00:37:10 $ + Last modified: $Date: 2006/01/25 23:47:57 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/Verifier.cpp
Changes in directory llvm/lib/VMCore:
Verifier.cpp updated: 1.145 -> 1.146
---
Log message:
Make sure the only user of InlineAsm's are direct calls.
---
Diffs of the changes: (+4 -0)
Verifier.cpp |4
1 files changed, 4 insertions(+)
Index: llvm/lib/VMCore/Verifier.cpp
diff -u llvm/lib/VMCore/Verifier.cpp:1.145 llvm/lib/VMCore/Verifier.cpp:1.146
--- llvm/lib/VMCore/Verifier.cpp:1.145 Wed Jan 18 19:20:03 2006
+++ llvm/lib/VMCore/Verifier.cppWed Jan 25 18:08:45 2006
@@ -47,6 +47,7 @@
#include "llvm/Module.h"
#include "llvm/ModuleProvider.h"
#include "llvm/DerivedTypes.h"
+#include "llvm/InlineAsm.h"
#include "llvm/Instructions.h"
#include "llvm/Intrinsics.h"
#include "llvm/PassManager.h"
@@ -663,6 +664,9 @@
!EF->dominates(&BB->getParent()->getEntryBlock(), PredBB),
"Instruction does not dominate all uses!", Op, &I);
}
+} else if (isa(I.getOperand(i))) {
+ Assert1(i == 0 && isa(I),
+ "Cannot take the address of an inline asm!", &I);
}
}
InstsInThisBlock.insert(&I);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.141 -> 1.142
---
Log message:
Incoming (and optional) flag bugs. They may be embedded inside a inner node of
a pattern. Also, nodes which take incoming flag should not be folded if it has
more than one use.
---
Diffs of the changes: (+56 -30)
DAGISelEmitter.cpp | 86 ++---
1 files changed, 56 insertions(+), 30 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.141
llvm/utils/TableGen/DAGISelEmitter.cpp:1.142
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.141Tue Jan 24 14:46:50 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Wed Jan 25 18:22:25 2006
@@ -1909,6 +1909,7 @@
unsigned OpNo = 0;
bool NodeHasChain = NodeHasProperty(N, SDNodeInfo::SDNPHasChain, ISE);
bool HasChain = PatternHasProperty(N, SDNodeInfo::SDNPHasChain, ISE);
+bool EmittedCheck = false;
if (HasChain) {
if (NodeHasChain)
OpNo = 1;
@@ -1916,6 +1917,7 @@
const SDNodeInfo &CInfo = ISE.getSDNodeInfo(N->getOperator());
OS << " if (!" << RootName << ".hasOneUse()) goto P"
<< PatternNo << "Fail; // Multiple uses of actual result?\n";
+EmittedCheck = true;
if (NodeHasChain)
OS << " if (CodeGenMap.count(" << RootName
<< ".getValue(" << CInfo.getNumResults() << "))) goto P"
@@ -1927,6 +1929,20 @@
}
}
+// Don't fold any node which reads or writes a flag and has multiple uses.
+// FIXME: we really need to separate the concepts of flag and "glue". Those
+// real flag results, e.g. X86CMP output, can have multiple uses.
+if (!EmittedCheck &&
+(PatternHasProperty(N, SDNodeInfo::SDNPInFlag, ISE) ||
+ PatternHasProperty(N, SDNodeInfo::SDNPOptInFlag, ISE) ||
+ PatternHasProperty(N, SDNodeInfo::SDNPOutFlag, ISE))) {
+ if (!isRoot) {
+const SDNodeInfo &CInfo = ISE.getSDNodeInfo(N->getOperator());
+OS << " if (!" << RootName << ".hasOneUse()) goto P"
+ << PatternNo << "Fail; // Multiple uses of actual result?\n";
+ }
+}
+
for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
OS << " SDOperand " << RootName << OpNo << " = "
<< RootName << ".getOperand(" << OpNo << ");\n";
@@ -2116,19 +2132,21 @@
const DAGInstruction &Inst = ISE.getInstruction(Op);
bool HasImpInputs = Inst.getNumImpOperands() > 0;
bool HasImpResults = Inst.getNumImpResults() > 0;
- bool HasOptInFlag = isRoot &&
-NodeHasProperty(Pattern, SDNodeInfo::SDNPOptInFlag, ISE);
+ bool HasOptInFlag = isRoot &&
+PatternHasProperty(Pattern, SDNodeInfo::SDNPOptInFlag, ISE);
bool HasInFlag = isRoot &&
-NodeHasProperty(Pattern, SDNodeInfo::SDNPInFlag, ISE);
- bool HasOutFlag = HasImpResults ||
+PatternHasProperty(Pattern, SDNodeInfo::SDNPInFlag, ISE);
+ bool NodeHasOutFlag = HasImpResults ||
(isRoot && PatternHasProperty(Pattern, SDNodeInfo::SDNPOutFlag, ISE));
bool NodeHasChain =
NodeHasProperty(Pattern, SDNodeInfo::SDNPHasChain, ISE);
bool HasChain = II.hasCtrlDep ||
(isRoot && PatternHasProperty(Pattern, SDNodeInfo::SDNPHasChain, ISE));
- if (HasOutFlag || HasInFlag || HasOptInFlag || HasImpInputs)
+ if (HasInFlag || NodeHasOutFlag || HasOptInFlag || HasImpInputs)
OS << " SDOperand InFlag = SDOperand(0, 0);\n";
+ if (HasOptInFlag)
+OS << " bool HasOptInFlag = false;\n";
// How many results is this pattern expected to produce?
unsigned NumExpectedResults = 0;
@@ -2173,16 +2191,8 @@
bool ChainEmitted = HasChain;
if (HasChain)
OS << " Chain = Select(Chain);\n";
- if (HasImpInputs)
-EmitCopyToRegs(Pattern, "N", ChainEmitted, true);
- if (HasInFlag || HasOptInFlag) {
-unsigned FlagNo = (unsigned) NodeHasChain + Pattern->getNumChildren();
-if (HasOptInFlag)
- OS << " if (N.getNumOperands() == " << FlagNo+1 << ") ";
-else
- OS << " ";
-OS << "InFlag = Select(N.getOperand(" << FlagNo << "));\n";
- }
+ if (HasInFlag || HasOptInFlag || HasImpInputs)
+EmitInFlagSelectCode(Pattern, "N", ChainEmitted, true);
unsigned NumResults = Inst.getNumResults();
unsigned ResNo = TmpNo++;
@@ -2191,7 +2201,7 @@
<< II.Namespace << "::" << II.TheDef->getName();
if (N->getTypeNum(0) != MVT::isVoid)
OS << ", MVT::" << getEnumName(N->getTypeNum(0));
-if (HasOutFlag)
+if (NodeHasOutFlag)
OS << ", MVT::Flag";
unsigned LastOp = 0;
@@ -2205,11 +2215,11 @@
OS << " Chain = Tmp" << LastOp << ".getValue("
<< NumResults << ");\n";
}
- } else if (HasCh
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td X86RegisterInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.217 -> 1.218
X86RegisterInfo.td updated: 1.27 -> 1.28
---
Log message:
Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
SDNPOutFlag, and SDNPOptInFlag instead.
---
Diffs of the changes: (+222 -259)
X86InstrInfo.td| 474 -
X86RegisterInfo.td |7
2 files changed, 222 insertions(+), 259 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.217
llvm/lib/Target/X86/X86InstrInfo.td:1.218
--- llvm/lib/Target/X86/X86InstrInfo.td:1.217 Mon Jan 23 23:17:12 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Wed Jan 25 18:29:36 2006
@@ -21,19 +21,17 @@
[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
SDTCisInt<0>, SDTCisInt<3>]>;
-def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisSameAs<1,
2>]>;
+def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
-def SDTX86Cmov: SDTypeProfile<1, 4,
+def SDTX86Cmov: SDTypeProfile<1, 3,
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
- SDTCisVT<3, i8>, SDTCisVT<4, FlagVT>]>;
+ SDTCisVT<3, i8>]>;
-def SDTX86BrCond : SDTypeProfile<0, 3,
- [SDTCisVT<0, OtherVT>,
- SDTCisVT<1, i8>, SDTCisVT<2, FlagVT>]>;
-
-def SDTX86SetCC : SDTypeProfile<1, 2,
- [SDTCisVT<0, i8>, SDTCisVT<1, i8>,
- SDTCisVT<2, FlagVT>]>;
+def SDTX86BrCond : SDTypeProfile<0, 2,
+ [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
+
+def SDTX86SetCC : SDTypeProfile<1, 1,
+ [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
@@ -70,15 +68,17 @@
def X86shld: SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
def X86shrd: SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
-def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>;
-def X86test: SDNode<"X86ISD::TEST", SDTX86CmpTest, []>;
+def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
+[SDNPOutFlag]>;
+def X86test: SDNode<"X86ISD::TEST", SDTX86CmpTest,
+[SDNPOutFlag]>;
def X86cmov: SDNode<"X86ISD::CMOV", SDTX86Cmov,
-[SDNPOutFlag]>;
+[SDNPInFlag, SDNPOutFlag]>;
def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
-[SDNPHasChain]>;
+[SDNPHasChain, SDNPInFlag]>;
def X86setcc : SDNode<"X86ISD::SETCC",SDTX86SetCC,
-[SDNPOutFlag]>;
+[SDNPInFlag, SDNPOutFlag]>;
def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
[SDNPHasChain, SDNPOptInFlag]>;
@@ -411,13 +411,11 @@
def CMOV_FR32 : I<0, Pseudo,
(ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
"#CMOV_FR32 PSEUDO!",
-[(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
- STATUS))]>;
+[(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
def CMOV_FR64 : I<0, Pseudo,
(ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
"#CMOV_FR64 PSEUDO!",
-[(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
- STATUS))]>;
+[(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
}
let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
@@ -466,39 +464,39 @@
def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
def JE : IBr<0x84, (ops brtarget:$dst), "je $dst",
- [(X86brcond bb:$dst, X86_COND_E, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_E)]>, TB;
def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst",
- [(X86brcond bb:$dst, X86_COND_NE, STATUS)]>, Imp<[STATUS],[]>,
TB;
+ [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst",
- [(X86brcond bb:$dst, X86_COND_L, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_L)]>, TB;
def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst",
- [(X86brcond bb:$dst, X86_COND_LE, STATUS)]>, Imp<[STATUS],[]>,
TB;
+ [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst",
- [(X86brcond bb:$dst, X86_COND_G, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_G)]>, TB;
def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst",
- [(X86brcond bb:$dst, X86_CO
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.6 -> 1.7
---
Log message:
Duh.
---
Diffs of the changes: (+2 -2)
ScheduleDAG.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.6
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.7
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.6 Wed Jan 25 12:54:24 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Wed Jan 25 18:28:35 2006
@@ -63,8 +63,8 @@
// Accessors
inline void setDominator(NodeInfo *D) { Dominator = D; }
-inline NodeInfo *getTop() { return Members[0]; }
-inline NodeInfo *getBottom() { return Members[Members.size()-1]; }
+inline NodeInfo *getTop() { return Members.front(); }
+inline NodeInfo *getBottom() { return Members.back(); }
inline NodeInfo *getDominator() { return Dominator; }
inline void setLatency(unsigned L) { Latency = L; }
inline unsigned getLatency() { return Latency; }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.4 -> 1.5
---
Log message:
Clean up some code; improve efficiency; and fixed a potential bug involving
chain successors.
---
Diffs of the changes: (+126 -149)
ScheduleDAGList.cpp | 275 +++-
1 files changed, 126 insertions(+), 149 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.4
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.5
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.4 Wed Jan 25
15:49:13 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Wed Jan 25 18:30:29 2006
@@ -32,10 +32,10 @@
struct SUnit {
SDNode *Node; // Representative node.
std::vector FlaggedNodes; // All nodes flagged to Node.
- std::vector Preds; // All real predecessors.
- std::vector ChainPreds;// All chain predecessors.
- std::vector Succs; // All real successors.
- std::vector ChainSuccs;// All chain successors.
+ std::vector Preds; // All real predecessors.
+ std::vector ChainPreds;// All chain predecessors.
+ std::vector Succs; // All real successors.
+ std::vector ChainSuccs;// All chain successors.
int NumPredsLeft; // # of preds not scheduled.
int NumSuccsLeft; // # of succs not scheduled.
int Priority1; // Scheduling priority 1.
@@ -43,67 +43,60 @@
unsigned Latency; // Node latency.
unsigned CycleBound;// Upper/lower cycle to be scheduled at.
unsigned Slot; // Cycle node is scheduled at.
+ SUnit *Next;
SUnit(SDNode *node)
: Node(node), NumPredsLeft(0), NumSuccsLeft(0),
Priority1(INT_MIN), Priority2(INT_MIN), Latency(0),
- CycleBound(0), Slot(0) {}
+ CycleBound(0), Slot(0), Next(NULL) {}
void dump(const SelectionDAG *G, bool All=true) const;
};
void SUnit::dump(const SelectionDAG *G, bool All) const {
- std::cerr << "SU: ";
+ std::cerr << "SU: ";
Node->dump(G);
std::cerr << "\n";
- if (All) {
-std::cerr << "# preds left : " << NumPredsLeft << "\n";
-std::cerr << "# succs left : " << NumSuccsLeft << "\n";
-std::cerr << "Latency : " << Latency << "\n";
-std::cerr << "Priority : " << Priority1 << " , " << Priority2 << "\n";
- }
-
if (FlaggedNodes.size() != 0) {
-if (All)
- std::cerr << "Flagged nodes :\n";
for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
- std::cerr << " ";
+ std::cerr << "";
FlaggedNodes[i]->dump(G);
std::cerr << "\n";
}
}
if (All) {
+std::cerr << "# preds left : " << NumPredsLeft << "\n";
+std::cerr << "# succs left : " << NumSuccsLeft << "\n";
+std::cerr << "Latency : " << Latency << "\n";
+std::cerr << "Priority : " << Priority1 << " , " << Priority2 << "\n";
+
if (Preds.size() != 0) {
std::cerr << "Predecessors :\n";
for (unsigned i = 0, e = Preds.size(); i != e; i++) {
std::cerr << "";
-Preds[i]->dump(G);
-std::cerr << "\n";
+Preds[i]->dump(G, false);
}
}
if (ChainPreds.size() != 0) {
std::cerr << "Chained Preds :\n";
for (unsigned i = 0, e = ChainPreds.size(); i != e; i++) {
std::cerr << "";
-ChainPreds[i]->dump(G);
-std::cerr << "\n";
+ChainPreds[i]->dump(G, false);
}
}
if (Succs.size() != 0) {
std::cerr << "Successors:\n";
for (unsigned i = 0, e = Succs.size(); i != e; i++) {
std::cerr << "";
-Succs[i]->dump(G);
-std::cerr << "\n";
+Succs[i]->dump(G, false);
}
}
if (ChainSuccs.size() != 0) {
std::cerr << "Chained succs :\n";
for (unsigned i = 0, e = ChainSuccs.size(); i != e; i++) {
std::cerr << "";
-ChainSuccs[i]->dump(G);
-std::cerr << "\n";
+ChainSuccs[i]->dump(G, false);
}
}
}
@@ -146,21 +139,21 @@
std::vector Sequence;
// Current scheduling cycle.
unsigned CurrCycle;
+ // First and last SUnit created.
+ SUnit *HeadSUnit, *TailSUnit;
public:
ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
const TargetMachine &tm)
-: ScheduleDAG(listSchedulingBURR, dag, bb, tm), CurrCycle(0) {};
+: ScheduleDAG(listSchedulingBURR, dag, bb, tm),
+ CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL) {};
~ScheduleDAGList() {
-for (std::map::iterator I = SUnitMap.begin(),
- E = SUnitMap.end(); I != E; ++I) {
- SUnit *SU = I->second;
- // Multiple SDNode* can point to one SUnit. Do ref counting, sort of.
- if (SU->FlaggedNodes.size() == 0)
-delete SU;
- else
-SU->FlaggedNodes.pop_back();
+SUnit *SU
[llvm-commits] CVS: llvm/lib/VMCore/InlineAsm.cpp
Changes in directory llvm/lib/VMCore:
InlineAsm.cpp updated: 1.3 -> 1.4
---
Log message:
parse and verify the constraint string.
---
Diffs of the changes: (+68 -0)
InlineAsm.cpp | 68 ++
1 files changed, 68 insertions(+)
Index: llvm/lib/VMCore/InlineAsm.cpp
diff -u llvm/lib/VMCore/InlineAsm.cpp:1.3 llvm/lib/VMCore/InlineAsm.cpp:1.4
--- llvm/lib/VMCore/InlineAsm.cpp:1.3 Wed Jan 25 16:26:05 2006
+++ llvm/lib/VMCore/InlineAsm.cpp Wed Jan 25 18:48:33 2006
@@ -13,6 +13,7 @@
#include "llvm/InlineAsm.h"
#include "llvm/DerivedTypes.h"
+#include
using namespace llvm;
// NOTE: when memoizing the function type, we have to be careful to handle the
@@ -37,6 +38,73 @@
return cast(getType()->getElementType());
}
+/// Verify - Verify that the specified constraint string is reasonable for the
+/// specified function type, and otherwise validate the constraint string.
bool InlineAsm::Verify(const FunctionType *Ty, const std::string &Constraints)
{
+ if (Ty->isVarArg()) return false;
+
+ unsigned NumOutputs = 0, NumInputs = 0, NumClobbers = 0;
+
+ // Scan the constraints string.
+ for (std::string::const_iterator I = Constraints.begin(),
+ E = Constraints.end(); I != E; ) {
+if (*I == ',') return false; // Empty constraint like ",,"
+
+// Parse the prefix.
+enum {
+ isInput,// 'x'
+ isOutput, // '=x'
+ isIndirectOutput, // '==x'
+ isClobber, // '~x'
+} ConstraintType = isInput;
+
+if (*I == '~') {
+ ConstraintType = isClobber;
+ ++I;
+} else if (*I == '=') {
+ ++I;
+ if (I != E && *I == '=') {
+ConstraintType = isIndirectOutput;
+++I;
+ } else {
+ConstraintType = isOutput;
+ }
+}
+
+if (I == E) return false; // Just a prefix, like "==" or "~".
+
+switch (ConstraintType) {
+case isOutput:
+ if (NumInputs || NumClobbers) return false; // outputs come first.
+ ++NumOutputs;
+ break;
+case isInput:
+case isIndirectOutput:
+ if (NumClobbers) return false; // inputs before clobbers.
+ ++NumInputs;
+ break;
+case isClobber:
+ ++NumClobbers;
+ break;
+}
+
+// Parse the id. We accept [a-zA-Z0-9] currently.
+while (I != E && isalnum(*I)) ++I;
+
+// If we reached the end of the ID, we must have the end of the string or a
+// comma, which we skip now.
+if (I != E) {
+ if (*I != ',') return false;
+ ++I;
+ if (I == E) return false;// don't allow "xyz,"
+}
+ }
+
+ if (NumOutputs > 1) return false; // Only one result allowed.
+
+ if ((Ty->getReturnType() != Type::VoidTy) != NumOutputs)
+return false; // NumOutputs = 1 iff has a result type.
+
+ if (Ty->getNumParams() != NumInputs) return false;
return true;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Utils/ValueMapper.cpp
Changes in directory llvm/lib/Transforms/Utils:
ValueMapper.cpp updated: 1.20 -> 1.21
---
Log message:
teach the cloner to handle inline asms
---
Diffs of the changes: (+1 -9)
ValueMapper.cpp | 10 +-
1 files changed, 1 insertion(+), 9 deletions(-)
Index: llvm/lib/Transforms/Utils/ValueMapper.cpp
diff -u llvm/lib/Transforms/Utils/ValueMapper.cpp:1.20
llvm/lib/Transforms/Utils/ValueMapper.cpp:1.21
--- llvm/lib/Transforms/Utils/ValueMapper.cpp:1.20 Thu Apr 21 18:45:34 2005
+++ llvm/lib/Transforms/Utils/ValueMapper.cpp Wed Jan 25 19:55:22 2006
@@ -16,8 +16,6 @@
#include "llvm/Constants.h"
#include "llvm/GlobalValue.h"
#include "llvm/Instruction.h"
-#include
-
using namespace llvm;
Value *llvm::MapValue(const Value *V, std::map &VM) {
@@ -32,7 +30,7 @@
if (Constant *C = const_cast(dyn_cast(V))) {
if (isa(C) || isa(C) ||
isa(C) || isa(C) ||
-isa(C))
+isa(C) || isa(V))
return VMSlot = C; // Primitive constants map directly
else if (ConstantArray *CA = dyn_cast(C)) {
for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i) {
@@ -112,12 +110,6 @@
for (unsigned op = 0, E = I->getNumOperands(); op != E; ++op) {
const Value *Op = I->getOperand(op);
Value *V = MapValue(Op, ValueMap);
-#ifndef NDEBUG
-if (!V) {
- std::cerr << "Val = \n" << *Op << "Addr = " << (void*)Op;
- std::cerr << "\nInst = " << *I;
-}
-#endif
assert(V && "Referenced value not in value map!");
I->setOperand(op, V);
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Value.h
Changes in directory llvm/include/llvm:
Value.h updated: 1.82 -> 1.83
---
Log message:
Allow use of isa(X) without #including InlineAsm.h
---
Diffs of the changes: (+4 -0)
Value.h |4
1 files changed, 4 insertions(+)
Index: llvm/include/llvm/Value.h
diff -u llvm/include/llvm/Value.h:1.82 llvm/include/llvm/Value.h:1.83
--- llvm/include/llvm/Value.h:1.82 Mon Jan 23 22:12:40 2006
+++ llvm/include/llvm/Value.h Wed Jan 25 19:54:21 2006
@@ -31,6 +31,7 @@
class GlobalValue;
class Function;
class GlobalVariable;
+class InlineAsm;
class SymbolTable;
//===--===//
@@ -213,6 +214,9 @@
template <> inline bool isa_impl(const Value &Val) {
return Val.getValueType() == Value::ArgumentVal;
}
+template <> inline bool isa_impl(const Value &Val) {
+ return Val.getValueType() == Value::InlineAsmVal;
+}
template <> inline bool isa_impl(const Value &Val) {
return Val.getValueType() >= Value::InstructionVal;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.57 -> 1.58
---
Log message:
When trying to fold X86::SETCC into a Select, make a copy if it has more than
one use. This allows more CMOV instructions.
---
Diffs of the changes: (+22 -6)
X86ISelLowering.cpp | 28 ++--
1 files changed, 22 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.57
llvm/lib/Target/X86/X86ISelLowering.cpp:1.58
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.57Wed Jan 25 12:21:52 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Jan 25 20:13:10 2006
@@ -1669,9 +1669,17 @@
// If the X86ISD::SETCC has more than one use, then it's probably better
// to use a test instead of duplicating the X86ISD::CMP (for register
// pressure reason).
- // FIXME: Check number of live Op0 uses since we are in the middle of
- // legalization process.
- if (Op0.hasOneUse() && Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
+ if (Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
+if (!Op0.hasOneUse()) {
+ std::vector Tys;
+ for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
+Tys.push_back(Op0.Val->getValueType(i));
+ std::vector Ops;
+ for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
+Ops.push_back(Op0.getOperand(i));
+ Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
+}
+
CC = Op0.getOperand(0);
Cond = Op0.getOperand(1);
// Make a copy as flag result cannot be used by more than one.
@@ -1720,9 +1728,17 @@
// If the X86ISD::SETCC has more than one use, then it's probably better
// to use a test instead of duplicating the X86ISD::CMP (for register
// pressure reason).
- // FIXME: Check number of live Cond uses since we are in the middle of
- // legalization process.
- if (Cond.hasOneUse() && Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
+ if (Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
+if (!Cond.hasOneUse()) {
+ std::vector Tys;
+ for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
+Tys.push_back(Cond.Val->getValueType(i));
+ std::vector Ops;
+ for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
+Ops.push_back(Cond.getOperand(i));
+ Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops);
+}
+
CC = Cond.getOperand(0);
Cond = Cond.getOperand(1);
// Make a copy as flag result cannot be used by more than one.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.142 -> 1.143 --- Log message: Add a FIXME comment. --- Diffs of the changes: (+1 -0) DAGISelEmitter.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.142 llvm/utils/TableGen/DAGISelEmitter.cpp:1.143 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.142Wed Jan 25 18:22:25 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Wed Jan 25 20:13:31 2006 @@ -1932,6 +1932,7 @@ // Don't fold any node which reads or writes a flag and has multiple uses. // FIXME: we really need to separate the concepts of flag and "glue". Those // real flag results, e.g. X86CMP output, can have multiple uses. +// FIXME: If the incoming flag is optional. Then it is ok to fold it. if (!EmittedCheck && (PatternHasProperty(N, SDNodeInfo::SDNPInFlag, ISE) || PatternHasProperty(N, SDNodeInfo::SDNPOptInFlag, ISE) || ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/InlineAsm.h
Changes in directory llvm/include/llvm:
InlineAsm.h updated: 1.5 -> 1.6
---
Log message:
add methods for constraint parsing
---
Diffs of the changes: (+19 -0)
InlineAsm.h | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/include/llvm/InlineAsm.h
diff -u llvm/include/llvm/InlineAsm.h:1.5 llvm/include/llvm/InlineAsm.h:1.6
--- llvm/include/llvm/InlineAsm.h:1.5 Wed Jan 25 16:10:35 2006
+++ llvm/include/llvm/InlineAsm.h Wed Jan 25 20:21:42 2006
@@ -17,6 +17,7 @@
#define LLVM_INLINEASM_H
#include "llvm/Value.h"
+#include
namespace llvm {
@@ -65,6 +66,24 @@
///
static bool Verify(const FunctionType *Ty, const std::string &Constraints);
+ // Constraint String Parsing
+ enum ConstraintPrefix {
+isInput,// 'x'
+isOutput, // '=x'
+isIndirectOutput, // '==x'
+isClobber, // '~x'
+ };
+
+ /// ParseConstraints - Split up the constraint string into the specific
+ /// constraints and their prefixes. If this returns an empty vector, and if
+ /// the constraint string itself isn't empty, there was an error parsing.
+ static std::vector >
+ParseConstraints(const std::string &ConstraintString);
+
+ std::vector >
+ ParseConstraints() const {
+return ParseConstraints(Constraints);
+ }
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const InlineAsm *) { return true; }
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/InlineAsm.cpp
Changes in directory llvm/lib/VMCore:
InlineAsm.cpp updated: 1.4 -> 1.5
---
Log message:
add method for constraint parsing
---
Diffs of the changes: (+50 -29)
InlineAsm.cpp | 79 --
1 files changed, 50 insertions(+), 29 deletions(-)
Index: llvm/lib/VMCore/InlineAsm.cpp
diff -u llvm/lib/VMCore/InlineAsm.cpp:1.4 llvm/lib/VMCore/InlineAsm.cpp:1.5
--- llvm/lib/VMCore/InlineAsm.cpp:1.4 Wed Jan 25 18:48:33 2006
+++ llvm/lib/VMCore/InlineAsm.cpp Wed Jan 25 20:21:59 2006
@@ -38,25 +38,17 @@
return cast(getType()->getElementType());
}
-/// Verify - Verify that the specified constraint string is reasonable for the
-/// specified function type, and otherwise validate the constraint string.
-bool InlineAsm::Verify(const FunctionType *Ty, const std::string &Constraints)
{
- if (Ty->isVarArg()) return false;
-
- unsigned NumOutputs = 0, NumInputs = 0, NumClobbers = 0;
+std::vector >
+InlineAsm::ParseConstraints(const std::string &Constraints) {
+ std::vector > Result;
// Scan the constraints string.
for (std::string::const_iterator I = Constraints.begin(),
- E = Constraints.end(); I != E; ) {
-if (*I == ',') return false; // Empty constraint like ",,"
+ E = Constraints.end(); I != E; ) {
+if (*I == ',') { Result.clear(); break; } // Empty constraint like ",,"
// Parse the prefix.
-enum {
- isInput,// 'x'
- isOutput, // '=x'
- isIndirectOutput, // '==x'
- isClobber, // '~x'
-} ConstraintType = isInput;
+ConstraintPrefix ConstraintType = isInput;
if (*I == '~') {
ConstraintType = isClobber;
@@ -71,9 +63,49 @@
}
}
-if (I == E) return false; // Just a prefix, like "==" or "~".
+if (I == E) { Result.clear(); break; } // Just a prefix, like "==" or "~".
+
+std::string::const_iterator IdStart = I;
+
+// Parse the id. We accept [a-zA-Z0-9] currently.
+while (I != E && isalnum(*I)) ++I;
+
+if (IdStart == I) {// Requires more than just a prefix
+ Result.clear();
+ break;
+}
+
+// Remember this constraint.
+Result.push_back(std::make_pair(ConstraintType, std::string(IdStart, I)));
-switch (ConstraintType) {
+// If we reached the end of the ID, we must have the end of the string or a
+// comma, which we skip now.
+if (I != E) {
+ if (*I != ',') { Result.clear(); break; }
+ ++I;
+ if (I == E) { Result.clear(); break; }// don't allow "xyz,"
+}
+ }
+
+ return Result;
+}
+
+
+/// Verify - Verify that the specified constraint string is reasonable for the
+/// specified function type, and otherwise validate the constraint string.
+bool InlineAsm::Verify(const FunctionType *Ty, const std::string &ConstStr) {
+ if (Ty->isVarArg()) return false;
+
+ std::vector >
+ Constraints = ParseConstraints(ConstStr);
+
+ // Error parsing constraints.
+ if (Constraints.empty() && !ConstStr.empty()) return false;
+
+ unsigned NumOutputs = 0, NumInputs = 0, NumClobbers = 0;
+
+ for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
+switch (Constraints[i].first) {
case isOutput:
if (NumInputs || NumClobbers) return false; // outputs come first.
++NumOutputs;
@@ -87,20 +119,9 @@
++NumClobbers;
break;
}
-
-// Parse the id. We accept [a-zA-Z0-9] currently.
-while (I != E && isalnum(*I)) ++I;
-
-// If we reached the end of the ID, we must have the end of the string or a
-// comma, which we skip now.
-if (I != E) {
- if (*I != ',') return false;
- ++I;
- if (I == E) return false;// don't allow "xyz,"
-}
}
-
- if (NumOutputs > 1) return false; // Only one result allowed.
+
+ if (NumOutputs > 1) return false; // Only one result allowed so far.
if ((Ty->getReturnType() != Type::VoidTy) != NumOutputs)
return false; // NumOutputs = 1 iff has a result type.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.cpp updated: 1.19 -> 1.20
---
Log message:
Work around some x86 Darwin assembler bugs
---
Diffs of the changes: (+26 -0)
X86ATTAsmPrinter.cpp | 26 ++
1 files changed, 26 insertions(+)
Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.19
llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.20
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.19 Sun Jan 22 17:37:17 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cppWed Jan 25 20:27:43 2006
@@ -220,6 +220,32 @@
///
void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
++EmittedInsts;
+ // This works around some Darwin assembler bugs.
+ if (forDarwin) {
+switch (MI->getOpcode()) {
+case X86::REP_MOVSB:
+ O << "rep/movsb (%esi),(%edi)\n";
+ return;
+case X86::REP_MOVSD:
+ O << "rep/movsl (%esi),(%edi)\n";
+ return;
+case X86::REP_MOVSW:
+ O << "rep/movsw (%esi),(%edi)\n";
+ return;
+case X86::REP_STOSB:
+ O << "rep/stosb\n";
+ return;
+case X86::REP_STOSD:
+ O << "rep/stosl\n";
+ return;
+case X86::REP_STOSW:
+ O << "rep/stosw\n";
+ return;
+default:
+ break;
+}
+ }
+
// Call the autogenerated instruction printer routines.
printInstruction(MI);
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
Evan,
I don't know anything about this stuff, but looking at the pattern, it
seems a mistake may have been made? Consider these:
On Wed, 2006-01-25 at 20:27 -0600, Evan Cheng wrote:
> void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
>++EmittedInsts;
> + // This works around some Darwin assembler bugs.
> + if (forDarwin) {
> +switch (MI->getOpcode()) {
> +case X86::REP_MOVSB:
> + O << "rep/movsb (%esi),(%edi)\n";
> + return;
REP_MOVSB = rep/movsb
> +case X86::REP_MOVSD:
> + O << "rep/movsl (%esi),(%edi)\n";
> + return;
REP_MOVSD != rep/movsl
is this a mistake?
> +case X86::REP_MOVSW:
> + O << "rep/movsw (%esi),(%edi)\n";
> + return;
> +case X86::REP_STOSB:
> + O << "rep/stosb\n";
> + return;
> +case X86::REP_STOSD:
> + O << "rep/stosl\n";
> + return;
and this one?
> +case X86::REP_STOSW:
> + O << "rep/stosw\n";
> + return;
> +default:
> + break;
> +}
> + }
Reid.
signature.asc
Description: This is a digitally signed message part
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
No, it's correct. Some assemblers prefer 'd' for double-word, some
'l' for long-word. This just works around some inconsistency in the
Apple assembler.
Evan
On Jan 25, 2006, at 6:38 PM, Reid Spencer wrote:
Evan,
I don't know anything about this stuff, but looking at the pattern, it
seems a mistake may have been made? Consider these:
On Wed, 2006-01-25 at 20:27 -0600, Evan Cheng wrote:
void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr
*MI) {
++EmittedInsts;
+ // This works around some Darwin assembler bugs.
+ if (forDarwin) {
+switch (MI->getOpcode()) {
+case X86::REP_MOVSB:
+ O << "rep/movsb (%esi),(%edi)\n";
+ return;
REP_MOVSB = rep/movsb
+case X86::REP_MOVSD:
+ O << "rep/movsl (%esi),(%edi)\n";
+ return;
REP_MOVSD != rep/movsl
is this a mistake?
+case X86::REP_MOVSW:
+ O << "rep/movsw (%esi),(%edi)\n";
+ return;
+case X86::REP_STOSB:
+ O << "rep/stosb\n";
+ return;
+case X86::REP_STOSD:
+ O << "rep/stosl\n";
+ return;
and this one?
+case X86::REP_STOSW:
+ O << "rep/stosw\n";
+ return;
+default:
+ break;
+}
+ }
Reid.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrFormats.td AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrFormats.td updated: 1.24 -> 1.25
AlphaInstrInfo.td updated: 1.108 -> 1.109
---
Log message:
minor renaming
---
Diffs of the changes: (+16 -16)
AlphaInstrFormats.td |2 +-
AlphaInstrInfo.td| 30 +++---
2 files changed, 16 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.24
llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.25
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.24 Wed Jan 25 21:22:07 2006
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td Wed Jan 25 21:24:15 2006
@@ -90,7 +90,7 @@
let Inst{20-0} = disp;
}
let isBranch = 1, isTerminator = 1 in
-class BFormDG opcode, string asmstr, list pattern>
+class BForm opcode, string asmstr, list pattern>
: InstAlpha {
let Pattern = pattern;
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.108
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.109
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.108 Wed Jan 25 21:22:07 2006
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Wed Jan 25 21:24:15 2006
@@ -764,21 +764,21 @@
def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)]>;
//Branches, int
-def BEQ : BFormDG<0x39, "beq $RA,$DISP",
- [(brcond (seteq GPRC:$RA, 0), bb:$DISP)]>;
-def BGE : BFormDG<0x3E, "bge $RA,$DISP",
- [(brcond (setge GPRC:$RA, 0), bb:$DISP)]>;
-def BGT : BFormDG<0x3F, "bgt $RA,$DISP",
- [(brcond (setgt GPRC:$RA, 0), bb:$DISP)]>;
-def BLBC : BFormDG<0x38, "blbc $RA,$DISP", []>; //TODO: Low bit clear
-def BLBS : BFormDG<0x3C, "blbs $RA,$DISP",
- [(brcond (and GPRC:$RA, 1), bb:$DISP)]>;
-def BLE : BFormDG<0x3B, "ble $RA,$DISP",
- [(brcond (setle GPRC:$RA, 0), bb:$DISP)]>;
-def BLT : BFormDG<0x3A, "blt $RA,$DISP",
- [(brcond (setlt GPRC:$RA, 0), bb:$DISP)]>;
-def BNE : BFormDG<0x3D, "bne $RA,$DISP",
- [(brcond (setne GPRC:$RA, 0), bb:$DISP)]>;
+def BEQ : BForm<0x39, "beq $RA,$DISP",
+ [(brcond (seteq GPRC:$RA, 0), bb:$DISP)]>;
+def BGE : BForm<0x3E, "bge $RA,$DISP",
+ [(brcond (setge GPRC:$RA, 0), bb:$DISP)]>;
+def BGT : BForm<0x3F, "bgt $RA,$DISP",
+ [(brcond (setgt GPRC:$RA, 0), bb:$DISP)]>;
+def BLBC : BForm<0x38, "blbc $RA,$DISP", []>; //TODO: Low bit clear
+def BLBS : BForm<0x3C, "blbs $RA,$DISP",
+ [(brcond (and GPRC:$RA, 1), bb:$DISP)]>;
+def BLE : BForm<0x3B, "ble $RA,$DISP",
+ [(brcond (setle GPRC:$RA, 0), bb:$DISP)]>;
+def BLT : BForm<0x3A, "blt $RA,$DISP",
+ [(brcond (setlt GPRC:$RA, 0), bb:$DISP)]>;
+def BNE : BForm<0x3D, "bne $RA,$DISP",
+ [(brcond (setne GPRC:$RA, 0), bb:$DISP)]>;
//Branches, float
def FBEQ : FBForm<0x31, "fbeq $RA,$DISP",
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrFormats.td AlphaInstrInfo.td AlphaRegisterInfo.cpp
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrFormats.td updated: 1.23 -> 1.24
AlphaInstrInfo.td updated: 1.107 -> 1.108
AlphaRegisterInfo.cpp updated: 1.32 -> 1.33
---
Log message:
allow R28 to be used for frame calculations without entirely removing it from
circulation
---
Diffs of the changes: (+4 -21)
AlphaInstrFormats.td | 19 +--
AlphaInstrInfo.td |4 ++--
AlphaRegisterInfo.cpp |2 +-
3 files changed, 4 insertions(+), 21 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.23
llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.24
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.23 Mon Jan 16 15:22:38 2006
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td Wed Jan 25 21:22:07 2006
@@ -45,6 +45,7 @@
let Pattern = pattern;
let isStore = store;
let isLoad = load;
+ let Defs = [R28]; //We may use this for frame index calculations, so reserve
it here
bits<5> Ra;
bits<16> disp;
@@ -54,16 +55,7 @@
let Inst{20-16} = Rb;
let Inst{15-0} = disp;
}
-class MFormAlt opcode, string asmstr>
-: InstAlphaAlt {
- bits<5> Ra;
- bits<16> disp;
- bits<5> Rb;
- let Inst{25-21} = Ra;
- let Inst{20-16} = Rb;
- let Inst{15-0} = disp;
-}
class MfcForm opcode, bits<16> fc, string asmstr>
: InstAlpha {
bits<5> Ra;
@@ -85,15 +77,6 @@
}
//3.3.2
-let isBranch = 1, isTerminator = 1 in
-class BForm opcode, string asmstr>
-: InstAlpha {
- bits<5> Ra;
- bits<21> disp;
-
- let Inst{25-21} = Ra;
- let Inst{20-0} = disp;
-}
def target : Operand {}
let isBranch = 1, isTerminator = 1 in
class BFormD opcode, string asmstr, list pattern>
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.107
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.108
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.107 Mon Jan 23 15:51:33 2006
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Wed Jan 25 21:22:07 2006
@@ -576,8 +576,8 @@
//load address, rellocated gpdist form
let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
-def LDAg : MFormAlt<0x08, "lda $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
-def LDAHg : MFormAlt<0x09, "ldah $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
+def LDAg : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", []>; //Load
address
+def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", []>; //Load
address
}
//Load quad, rellocated literal form
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.32
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.33
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.32Tue Jan 24 19:51:08 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Wed Jan 25 21:22:07 2006
@@ -257,7 +257,7 @@
" for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
if (Offset > IMM_HIGH || Offset < IMM_LOW) {
-std::cerr << "Unconditionally using R28 for evil purposes\n";
+DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: "
<< Offset << "\n");
//so in this case, we need to use a temporary register, and move the
original
//inst off the SP/FP
//fix up the old:
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp SparcV8Subtarget.h Makefile SparcV8.td SparcV8TargetMachine.cpp SparcV8TargetMachine.h
Changes in directory llvm/lib/Target/SparcV8:
SparcV8Subtarget.cpp added (r1.1)
SparcV8Subtarget.h added (r1.1)
Makefile updated: 1.12 -> 1.13
SparcV8.td updated: 1.6 -> 1.7
SparcV8TargetMachine.cpp updated: 1.37 -> 1.38
SparcV8TargetMachine.h updated: 1.9 -> 1.10
---
Log message:
Add trivial subtarget support
---
Diffs of the changes: (+86 -1)
Makefile |2 +-
SparcV8.td | 16
SparcV8Subtarget.cpp | 27 +++
SparcV8Subtarget.h | 38 ++
SparcV8TargetMachine.cpp |1 +
SparcV8TargetMachine.h |3 +++
6 files changed, 86 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp:1.1
*** /dev/null Thu Jan 26 00:51:31 2006
--- llvm/lib/Target/SparcV8/SparcV8Subtarget.cppThu Jan 26 00:51:21 2006
***
*** 0
--- 1,27
+ //===- SparcV8Subtarget.cpp - SPARC Subtarget Information
-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file implements the SPARC specific subclass of TargetSubtarget.
+ //
+
//===--===//
+
+ #include "SparcV8Subtarget.h"
+ #include "SparcV8GenSubtarget.inc"
+ using namespace llvm;
+
+ SparcV8Subtarget::SparcV8Subtarget(const Module &M, const std::string &FS) {
+ // Determine default and user specified characteristics
+ std::string CPU = "generic";
+
+ // FIXME: autodetect host here!
+
+ // Parse features string.
+ ParseSubtargetFeatures(FS, CPU);
+
+ };
\ No newline at end of file
Index: llvm/lib/Target/SparcV8/SparcV8Subtarget.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8Subtarget.h:1.1
*** /dev/null Thu Jan 26 00:51:33 2006
--- llvm/lib/Target/SparcV8/SparcV8Subtarget.h Thu Jan 26 00:51:21 2006
***
*** 0
--- 1,38
+ //=-- SparcV8Subtarget.h - Define Subtarget for the SPARC -*- C++
-*--//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file declares the SPARC specific subclass of TargetSubtarget.
+ //
+
//===--===//
+
+ #ifndef SPARC_SUBTARGET_H
+ #define SPARC_SUBTARGET_H
+
+ #include "llvm/Target/TargetSubtarget.h"
+ #include
+
+ namespace llvm {
+ class Module;
+
+ class SparcV8Subtarget : public TargetSubtarget {
+ bool Is64Bit;
+ public:
+ SparcV8Subtarget(const Module &M, const std::string &FS);
+
+ bool is64Bit() const { return Is64Bit; }
+
+ /// ParseSubtargetFeatures - Parses features string setting specified
+ /// subtarget options. Definition of function is auto generated by tblgen.
+ void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+
+ };
+
+ } // end namespace llvm
+
+ #endif
Index: llvm/lib/Target/SparcV8/Makefile
diff -u llvm/lib/Target/SparcV8/Makefile:1.12
llvm/lib/Target/SparcV8/Makefile:1.13
--- llvm/lib/Target/SparcV8/Makefile:1.12 Sat Dec 17 01:47:01 2005
+++ llvm/lib/Target/SparcV8/MakefileThu Jan 26 00:51:21 2006
@@ -14,7 +14,7 @@
BUILT_SOURCES = SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc \
-SparcV8GenDAGISel.inc
+SparcV8GenDAGISel.inc SparcV8GenSubtarget.inc
include $(LEVEL)/Makefile.common
Index: llvm/lib/Target/SparcV8/SparcV8.td
diff -u llvm/lib/Target/SparcV8/SparcV8.td:1.6
llvm/lib/Target/SparcV8/SparcV8.td:1.7
--- llvm/lib/Target/SparcV8/SparcV8.td:1.6 Thu Dec 9 22:48:57 2004
+++ llvm/lib/Target/SparcV8/SparcV8.td Thu Jan 26 00:51:21 2006
@@ -17,6 +17,14 @@
include "../Target.td"
//===--===//
+// PowerPC Subtarget features.
+//
+
+def Feature64Bit : SubtargetFeature<"64bit", "bool", "Is64Bit",
+"Enable 64-bit instructions">;
+
+
+//===--===//
// Register File Description
//===--===//
@@ -37,6 +45,14 @@
}
//===--===//
+// SPARC processors supported.
+//===
[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8.td SparcV8ISelDAGToDAG.cpp SparcV8Subtarget.cpp SparcV8Subtarget.h
Changes in directory llvm/lib/Target/SparcV8:
SparcV8.td updated: 1.7 -> 1.8
SparcV8ISelDAGToDAG.cpp updated: 1.59 -> 1.60
SparcV8Subtarget.cpp updated: 1.1 -> 1.2
SparcV8Subtarget.h updated: 1.1 -> 1.2
---
Log message:
Rest of subtarget support, remove references to ppc
---
Diffs of the changes: (+38 -14)
SparcV8.td | 34 +++---
SparcV8ISelDAGToDAG.cpp |8
SparcV8Subtarget.cpp|2 +-
SparcV8Subtarget.h |8 ++--
4 files changed, 38 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8.td
diff -u llvm/lib/Target/SparcV8/SparcV8.td:1.7
llvm/lib/Target/SparcV8/SparcV8.td:1.8
--- llvm/lib/Target/SparcV8/SparcV8.td:1.7 Thu Jan 26 00:51:21 2006
+++ llvm/lib/Target/SparcV8/SparcV8.td Thu Jan 26 01:22:22 2006
@@ -17,12 +17,18 @@
include "../Target.td"
//===--===//
-// PowerPC Subtarget features.
+// SPARC Subtarget features.
//
-def Feature64Bit : SubtargetFeature<"64bit", "bool", "Is64Bit",
-"Enable 64-bit instructions">;
-
+def FeatureV9
+ : SubtargetFeature<"v9", "bool", "IsV9",
+ "Enable SPARC-V9 instructions">;
+def FeatureV8Deprecated
+ : SubtargetFeature<"deprecated-v8", "bool", "V8DeprecatedInsts",
+ "Enable deprecated V8 instructions in V9 mode">;
+def FeatureVIS
+ : SubtargetFeature<"vis", "bool", "IsVIS",
+ "Enable UltraSPARC Visual Instruction Set extensions">;
//===--===//
// Register File Description
@@ -48,9 +54,23 @@
// SPARC processors supported.
//===--===//
-def : Processor<"generic", NoItineraries, []>;
-def : Processor<"v8", NoItineraries, []>;
-def : Processor<"v9", NoItineraries, [Feature64Bit]>;
+class Proc Features>
+ : Processor;
+
+def : Proc<"generic", []>;
+def : Proc<"v8", []>;
+def : Proc<"supersparc", []>;
+def : Proc<"sparclite", []>;
+def : Proc<"f934",[]>;
+def : Proc<"hypersparc", []>;
+def : Proc<"sparclite86x",[]>;
+def : Proc<"sparclet",[]>;
+def : Proc<"tsc701", []>;
+def : Proc<"v9", [FeatureV9]>;
+def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
+
//===--===//
// Declare the target which we are implementing
Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.59
llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.60
--- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.59Wed Jan 25
12:52:42 2006
+++ llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp Thu Jan 26 01:22:22 2006
@@ -795,7 +795,7 @@
//===--===//
//======//
-/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
+/// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine
/// instructions for SelectionDAG operations.
///
namespace {
@@ -816,7 +816,7 @@
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
virtual const char *getPassName() const {
-return "PowerPC DAG->DAG Pattern Instruction Selection";
+return "SparcV8 DAG->DAG Pattern Instruction Selection";
}
// Include the pieces autogenerated from the target description.
@@ -1011,8 +1011,8 @@
}
-/// createPPCISelDag - This pass converts a legalized DAG into a
-/// PowerPC-specific DAG, ready for instruction scheduling.
+/// createSparcV8ISelDag - This pass converts a legalized DAG into a
+/// SPARC-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
return new SparcV8DAGToDAGISel(TM);
Index: llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp:1.1
llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp:1.2
--- llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp:1.1Thu Jan 26 00:51:21 2006
+++ llvm/lib/Target/SparcV8/SparcV8Subtarget.cppThu Jan 26 01:22:22 2006
@@ -24,4 +24,4 @@
// Parse features string.
ParseSubtargetFeatures(FS, CPU);
-};
\ No newline at end of file
+};
Index: llvm/lib/Target/SparcV8/SparcV8Subtarget.h
diff -u llvm/lib/Target/SparcV8/SparcV8Subtarget.h:1.1
llvm/lib/Target/SparcV8/SparcV8Subtarget.h:1.2
--- llvm/lib/Target/SparcV8/SparcV8Subtarget.h:1.1 Thu Jan 26 00:51:21 2006
+++ llvm/lib/Target/SparcV8/SparcV8Subtarget.h Thu Jan 26 01:22:22 2006
@@ -21,11 +21,15 @@
class Module;
class
