[llvm-commits] CVS: llvm/test/Regression/Transforms/ScalarRepl/2005-12-14-UnionPromoteCrash.ll
Changes in directory llvm/test/Regression/Transforms/ScalarRepl:
2005-12-14-UnionPromoteCrash.ll added (r1.1)
---
Log message:
new (undefined) testcase, distilled from 126.gcc that scalarrepl crashes on
---
Diffs of the changes: (+34 -0)
2005-12-14-UnionPromoteCrash.ll | 34 ++
1 files changed, 34 insertions(+)
Index:
llvm/test/Regression/Transforms/ScalarRepl/2005-12-14-UnionPromoteCrash.ll
diff -c /dev/null
llvm/test/Regression/Transforms/ScalarRepl/2005-12-14-UnionPromoteCrash.ll:1.1
*** /dev/null Wed Dec 14 11:23:30 2005
--- llvm/test/Regression/Transforms/ScalarRepl/2005-12-14-UnionPromoteCrash.ll
Wed Dec 14 11:23:20 2005
***
*** 0
--- 1,34
+ ; RUN: llvm-as < %s | opt -scalarrepl -disable-output
+ target endian = big
+ target pointersize = 32
+ %struct.rtx_def = type { [2 x ubyte], int, [1 x %union.rtunion_def] }
+ %union.rtunion_def = type { uint }
+
+ implementation ; Functions:
+
+ void %find_reloads() {
+ entry:
+ %c_addr.i = alloca sbyte; [#uses=1]
+ switch uint 0, label %return [
+uint 36, label %label.7
+uint 34, label %label.7
+uint 41, label %label.5
+ ]
+
+ label.5: ; preds = %entry
+ ret void
+
+ label.7: ; preds = %entry, %entry
+ br bool false, label %then.4, label %switchexit.0
+
+ then.4: ; preds = %label.7
+ %tmp.0.i = cast sbyte* %c_addr.i to int*;
[#uses=1]
+ store int 44, int* %tmp.0.i
+ ret void
+
+ switchexit.0: ; preds = %label.7
+ ret void
+
+ return: ; preds = %entry
+ ret void
+ }
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
Changes in directory llvm/lib/Transforms/Scalar:
ScalarReplAggregates.cpp updated: 1.33 -> 1.34
---
Log message:
Fix Transforms/ScalarRepl/2005-12-14-UnionPromoteCrash.ll, a crash on undefined
behavior in 126.gcc on big-endian systems.
---
Diffs of the changes: (+2 -2)
ScalarReplAggregates.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
diff -u llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.33
llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.34
--- llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.33Mon Dec 12
01:19:13 2005
+++ llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Dec 14 11:23:59 2005
@@ -539,7 +539,7 @@
if (LoadInst *LI = dyn_cast(User)) {
// The load is a bit extract from NewAI shifted right by Offset bits.
Value *NV = new LoadInst(NewAI, LI->getName(), LI);
- if (Offset)
+ if (Offset && Offset < NV->getType()->getPrimitiveSizeInBits())
NV = new ShiftInst(Instruction::Shr, NV,
ConstantUInt::get(Type::UByteTy, Offset),
LI->getName(), LI);
@@ -563,7 +563,7 @@
SV = new CastInst(SV, SV->getType()->getUnsignedVersion(),
SV->getName(), SI);
SV = new CastInst(SV, Old->getType(), SV->getName(), SI);
-if (Offset)
+if (Offset && Offset < SV->getType()->getPrimitiveSizeInBits())
SV = new ShiftInst(Instruction::Shl, SV,
ConstantUInt::get(Type::UByteTy, Offset),
SV->getName()+".adj", SI);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.66 -> 1.67
---
Log message:
Fix the (zext (zextload)) case to trigger, similarly for sign extends.
Allow (zext (truncate)) to apply after legalize if the target supports
AND (which all do).
This compiles
short %foo() {
%tmp.0 = load ubyte* %X ; [#uses=1]
%tmp.3 = cast ubyte %tmp.0 to short ; [#uses=1]
ret short %tmp.3
}
to:
_foo:
movzbl _X, %eax
ret
instead of:
_foo:
movzbl _X, %eax
movzbl %al, %eax
ret
thanks to Evan for pointing this out.
---
Diffs of the changes: (+28 -7)
DAGCombiner.cpp | 35 ---
1 files changed, 28 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.66
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.67
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.66 Wed Dec 14 01:58:38 2005
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Dec 14 13:05:06 2005
@@ -1543,9 +1543,6 @@
// fold (sext (sext x)) -> (sext x)
if (N0.getOpcode() == ISD::SIGN_EXTEND)
return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
- // fold (sext (sextload x)) -> (sextload x)
- if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType())
-return N0;
// fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() ==
VT&&
(!AfterLegalize ||
@@ -1562,6 +1559,20 @@
ExtLoad.getValue(1));
return SDOperand();
}
+
+ // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
+ // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
+ if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
+ N0.hasOneUse()) {
+SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
+N0.getOperand(1), N0.getOperand(2),
+N0.getOperand(3));
+WorkList.push_back(N);
+CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+ ExtLoad.getValue(1));
+return SDOperand();
+ }
+
return SDOperand();
}
@@ -1576,12 +1587,9 @@
// fold (zext (zext x)) -> (zext x)
if (N0.getOpcode() == ISD::ZERO_EXTEND)
return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
- // fold (zext (zextload x)) -> (zextload x)
- if (N0.getOpcode() == ISD::ZEXTLOAD && VT == N0.getValueType())
-return N0;
// fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() ==
VT&&
- !AfterLegalize)
+ (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType(
return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
// fold (zext (load x)) -> (zext (truncate (zextload x)))
if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
@@ -1593,6 +1601,19 @@
ExtLoad.getValue(1));
return SDOperand();
}
+
+ // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
+ // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
+ if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
+ N0.hasOneUse()) {
+SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
+N0.getOperand(1), N0.getOperand(2),
+N0.getOperand(3));
+WorkList.push_back(N);
+CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+ ExtLoad.getValue(1));
+return SDOperand();
+ }
return SDOperand();
}
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[llvm-commits] CVS: llvm/tools/gccld/gccld.cpp
Changes in directory llvm/tools/gccld:
gccld.cpp updated: 1.105 -> 1.106
---
Log message:
Remove -start-group and -end-group no-op options, accidentally committed
in last patch.
---
Diffs of the changes: (+0 -5)
gccld.cpp |5 -
1 files changed, 5 deletions(-)
Index: llvm/tools/gccld/gccld.cpp
diff -u llvm/tools/gccld/gccld.cpp:1.105 llvm/tools/gccld/gccld.cpp:1.106
--- llvm/tools/gccld/gccld.cpp:1.105Tue Dec 13 14:00:37 2005
+++ llvm/tools/gccld/gccld.cpp Wed Dec 14 13:08:51 2005
@@ -107,11 +107,6 @@
CO5("eh-frame-hdr", cl::Hidden, cl::desc("Compatibility option: ignored"));
cl::opt
CO6("h", cl::Hidden, cl::desc("Compatibility option: ignored"));
- cl::opt
- CO7("start-group", cl::Hidden, cl::desc("Compatibility option: ignored"));
- cl::opt
- CO8("end-group", cl::Hidden, cl::desc("Compatibility option: ignored"));
-
cl::alias A0("s", cl::desc("Alias for --strip-all"),
cl::aliasopt(Strip));
cl::alias A1("S", cl::desc("Alias for --strip-debug"),
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/extend.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
extend.ll added (r1.1)
---
Log message:
new testcase, each function should have one extension instr in it
---
Diffs of the changes: (+19 -0)
extend.ll | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/extend.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/extend.ll:1.1
*** /dev/null Wed Dec 14 13:24:18 2005
--- llvm/test/Regression/CodeGen/X86/extend.ll Wed Dec 14 13:24:08 2005
***
*** 0
--- 1,19
+ ; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep movzx | wc
-l | grep 1
+ ; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep movsx | wc
-l | grep 1
+
+ %G1 = internal global ubyte 0 ; [#uses=1]
+ %G2 = internal global sbyte 0 ; [#uses=1]
+
+ implementation ; Functions:
+
+ short %test1() { ;; one zext
+ %tmp.0 = load ubyte* %G1; [#uses=1]
+ %tmp.3 = cast ubyte %tmp.0 to short ; [#uses=1]
+ ret short %tmp.3
+ }
+
+ short %test2() { ;; one sext
+ %tmp.0 = load sbyte* %G2; [#uses=1]
+ %tmp.3 = cast sbyte %tmp.0 to short ; [#uses=1]
+ ret short %tmp.3
+ }
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.67 -> 1.68 --- Log message: When folding loads into ops, immediately replace uses of the op with the load. This reduces number of worklist iterations and avoid missing optimizations depending on folding of things into sext_inreg nodes (which aren't supported by all targets). Tested by Regression/CodeGen/X86/extend.ll:test2 --- Diffs of the changes: (+6 -6) DAGCombiner.cpp | 12 ++-- 1 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.67 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.68 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.67 Wed Dec 14 13:05:06 2005 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Dec 14 13:25:30 2005 @@ -1554,7 +1554,7 @@ SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), N0.getOperand(1), N0.getOperand(2), N0.getValueType()); -WorkList.push_back(N); +CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); return SDOperand(); @@ -1567,7 +1567,7 @@ SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0), N0.getOperand(1), N0.getOperand(2), N0.getOperand(3)); -WorkList.push_back(N); +CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); return SDOperand(); @@ -1596,7 +1596,7 @@ SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), N0.getOperand(1), N0.getOperand(2), N0.getValueType()); -WorkList.push_back(N); +CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); return SDOperand(); @@ -1609,7 +1609,7 @@ SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0), N0.getOperand(1), N0.getOperand(2), N0.getOperand(3)); -WorkList.push_back(N); +CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); return SDOperand(); @@ -1673,7 +1673,7 @@ SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), N0.getOperand(1), N0.getOperand(2), EVT); -WorkList.push_back(N); +CombineTo(N, ExtLoad); CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); return SDOperand(); } @@ -1684,7 +1684,7 @@ SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), N0.getOperand(1), N0.getOperand(2), EVT); -WorkList.push_back(N); +CombineTo(N, ExtLoad); CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); return SDOperand(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.22 -> 1.23 --- Log message: Fixed extload type profile. The 4th operand is a ValueType node with type OtherVT, it cannot be compare to type of 1st operand which is an integer type. --- Diffs of the changes: (+1 -2) TargetSelectionDAG.td |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.22 llvm/lib/Target/TargetSelectionDAG.td:1.23 --- llvm/lib/Target/TargetSelectionDAG.td:1.22 Tue Dec 13 20:21:01 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Dec 14 13:40:54 2005 @@ -151,8 +151,7 @@ ]>; def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, - SDTCisVTSmallerThanOp<3, 0> + SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/tools/bugpoint/Miscompilation.cpp
Changes in directory llvm/tools/bugpoint: Miscompilation.cpp updated: 1.73 -> 1.74 --- Log message: Fix printing of the instructions. --- Diffs of the changes: (+1 -1) Miscompilation.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/tools/bugpoint/Miscompilation.cpp diff -u llvm/tools/bugpoint/Miscompilation.cpp:1.73 llvm/tools/bugpoint/Miscompilation.cpp:1.74 --- llvm/tools/bugpoint/Miscompilation.cpp:1.73 Tue Dec 6 14:51:30 2005 +++ llvm/tools/bugpoint/Miscompilation.cpp Wed Dec 14 16:01:07 2005 @@ -862,7 +862,7 @@ std::cout << " gcc " << SharedObject << " " << TestModuleBC << ".s -o " << TestModuleBC << ".exe"; #if defined (HAVE_LINK_R) -std::cout << "-Wl,-R."; +std::cout << " -Wl,-R."; #endif std::cout << "\n"; std::cout << " " << TestModuleBC << ".exe"; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Target.td TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
Target.td updated: 1.64 -> 1.65
TargetSelectionDAG.td updated: 1.23 -> 1.24
---
Log message:
Added support to specify predicates.
---
Diffs of the changes: (+17 -2)
Target.td | 14 ++
TargetSelectionDAG.td |5 +++--
2 files changed, 17 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.64 llvm/lib/Target/Target.td:1.65
--- llvm/lib/Target/Target.td:1.64 Sun Dec 4 02:13:17 2005
+++ llvm/lib/Target/Target.td Wed Dec 14 16:02:59 2005
@@ -127,6 +127,7 @@
//
include "../TargetSchedule.td"
+class Predicate; // Forward def
//===--===//
// Instruction set description - These classes correspond to the C++ classes in
@@ -149,6 +150,10 @@
list Uses = []; // Default to using no non-operand registers
list Defs = []; // Default to modifying no non-operand registers
+ // Predicates - List of predicates which will be turned into isel matching
+ // code.
+ list Predicates = [];
+
// These bits capture information about the high-level semantics of the
// instruction.
bit isReturn = 0; // Is this instruction a return instruction?
@@ -168,6 +173,15 @@
InstrItinClass Itinerary; // Execution steps used for scheduling.
}
+/// Predicates - These are extra conditionals which are turned into instruction
+/// selector matching code. Currently each predicate is just a string.
+class Predicate {
+ string CondString = cond;
+}
+
+class Requires preds> {
+ list Predicates = preds;
+}
/// ops definition - This is just a simple marker used to identify the operands
/// list for an instruction. This should be used like this:
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.23
llvm/lib/Target/TargetSelectionDAG.td:1.24
--- llvm/lib/Target/TargetSelectionDAG.td:1.23 Wed Dec 14 13:40:54 2005
+++ llvm/lib/Target/TargetSelectionDAG.td Wed Dec 14 16:02:59 2005
@@ -382,8 +382,9 @@
//
class Pattern resultInstrs> {
- dag PatternToMatch = patternToMatch;
- list ResultInstrs = resultInstrs;
+ dag PatternToMatch = patternToMatch;
+ list ResultInstrs = resultInstrs;
+ list Predicates = []; // See class Instruction in Target.td.
}
// Pat - A simple (but common) form of a pattern, which produces a simple
result
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp DAGISelEmitter.h
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.98 -> 1.99
DAGISelEmitter.h updated: 1.44 -> 1.45
---
Log message:
Added support to specify predicates.
---
Diffs of the changes: (+89 -40)
DAGISelEmitter.cpp | 111 ++---
DAGISelEmitter.h | 18 +++-
2 files changed, 89 insertions(+), 40 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.98
llvm/utils/TableGen/DAGISelEmitter.cpp:1.99
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.98 Tue Dec 13 20:21:57 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Wed Dec 14 16:02:59 2005
@@ -1300,11 +1300,13 @@
if (!SrcPattern->canPatternMatch(Reason, *this))
I->error("Instruction can never match: " + Reason);
+Record *Instr = II->first;
TreePatternNode *DstPattern = TheInst.getResultPattern();
-PatternsToMatch.push_back(std::make_pair(SrcPattern, DstPattern));
+PatternsToMatch.
+ push_back(PatternToMatch(Instr->getValueAsListInit("Predicates"),
+ SrcPattern, DstPattern));
if (PatternHasCtrlDep(Pattern, *this)) {
- Record *Instr = II->first;
CodeGenInstruction &InstInfo = Target.getInstruction(Instr->getName());
InstInfo.hasCtrlDep = true;
}
@@ -1356,8 +1358,10 @@
if (!Pattern->getOnlyTree()->canPatternMatch(Reason, *this))
Pattern->error("Pattern can never match: " + Reason);
-PatternsToMatch.push_back(std::make_pair(Pattern->getOnlyTree(),
- Result->getOnlyTree()));
+PatternsToMatch.
+ push_back(PatternToMatch(Patterns[i]->getValueAsListInit("Predicates"),
+ Pattern->getOnlyTree(),
+ Result->getOnlyTree()));
}
}
@@ -1565,7 +1569,7 @@
//
for (unsigned i = 0, e = PatternsToMatch.size(); i != e; ++i) {
std::vector Variants;
-GenerateVariantsOf(PatternsToMatch[i].first, Variants, *this);
+GenerateVariantsOf(PatternsToMatch[i].getSrcPattern(), Variants, *this);
assert(!Variants.empty() && "Must create at least original variant!");
Variants.erase(Variants.begin()); // Remove the original pattern.
@@ -1574,7 +1578,7 @@
continue;
DEBUG(std::cerr << "FOUND VARIANTS OF: ";
- PatternsToMatch[i].first->dump();
+ PatternsToMatch[i].getSrcPattern()->dump();
std::cerr << "\n");
for (unsigned v = 0, e = Variants.size(); v != e; ++v) {
@@ -1588,7 +1592,7 @@
bool AlreadyExists = false;
for (unsigned p = 0, e = PatternsToMatch.size(); p != e; ++p) {
// Check to see if this variant already exists.
-if (Variant->isIsomorphicTo(PatternsToMatch[p].first)) {
+if (Variant->isIsomorphicTo(PatternsToMatch[p].getSrcPattern())) {
DEBUG(std::cerr << " *** ALREADY EXISTS, ignoring variant.\n");
AlreadyExists = true;
break;
@@ -1598,8 +1602,9 @@
if (AlreadyExists) continue;
// Otherwise, add it to the list of patterns we have.
- PatternsToMatch.push_back(std::make_pair(Variant,
- PatternsToMatch[i].second));
+ PatternsToMatch.
+push_back(PatternToMatch(PatternsToMatch[i].getPredicates(),
+ Variant, PatternsToMatch[i].getDstPattern()));
}
DEBUG(std::cerr << "\n");
@@ -1685,15 +1690,16 @@
PatternSortingPredicate(DAGISelEmitter &ise) : ISE(ise) {};
DAGISelEmitter &ISE;
- bool operator()(DAGISelEmitter::PatternToMatch *LHS,
- DAGISelEmitter::PatternToMatch *RHS) {
-unsigned LHSSize = getPatternSize(LHS->first, ISE);
-unsigned RHSSize = getPatternSize(RHS->first, ISE);
+ bool operator()(PatternToMatch *LHS,
+ PatternToMatch *RHS) {
+unsigned LHSSize = getPatternSize(LHS->getSrcPattern(), ISE);
+unsigned RHSSize = getPatternSize(RHS->getSrcPattern(), ISE);
if (LHSSize > RHSSize) return true; // LHS -> bigger -> less cost
if (LHSSize < RHSSize) return false;
// If the patterns have equal complexity, compare generated instruction
cost
-return getResultPatternCost(LHS->second)
second);
+return getResultPatternCost(LHS->getDstPattern()) <
+ getResultPatternCost(RHS->getDstPattern());
}
};
@@ -1725,8 +1731,12 @@
private:
DAGISelEmitter &ISE;
- // LHS of the pattern being matched
- TreePatternNode *LHS;
+ // Predicates.
+ ListInit *Predicates;
+ // Instruction selector pattern.
+ TreePatternNode *Pattern;
+ // Matched instruction.
+ TreePatternNode *Instruction;
unsigned PatternNo;
std::ostream &OS;
// Node to name mapping
@@ -1738,16 +1748,39 @@
unsigned TmpNo;
public:
- PatternCodeEmitter(DAGISelEmitter &ise, TreePatternNode *lhs,
+ PatternCodeEmitter(DAGISelEmitter &ise, ListInit *preds,
+ TreePat
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.157 -> 1.158 --- Log message: Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS. --- Diffs of the changes: (+11 -4) PPCInstrInfo.td | 15 +++ 1 files changed, 11 insertions(+), 4 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.157 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.158 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.157 Tue Dec 13 18:34:09 2005 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Wed Dec 14 16:07:12 2005 @@ -166,6 +166,9 @@ let PrintMethod = "printcrbitm"; } +//===--===// +// PowerPC Instruction Predicate Definitions. +def FPContractions : Predicate<"!NoExcessFPPrecision">; //===--===// // PowerPC Instruction Definitions. @@ -719,22 +722,26 @@ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), - F8RC:$FRB))]>; + F8RC:$FRB))]>, +Requires<[FPContractions]>; def FMADDS : AForm_1<59, 29, (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), - F4RC:$FRB))]>; + F4RC:$FRB))]>, +Requires<[FPContractions]>; def FMSUB : AForm_1<63, 28, (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), - F8RC:$FRB))]>; + F8RC:$FRB))]>, +Requires<[FPContractions]>; def FMSUBS : AForm_1<59, 28, (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), - F4RC:$FRB))]>; + F4RC:$FRB))]>, +Requires<[FPContractions]>; def FNMADD : AForm_1<63, 31, (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp
Changes in directory llvm/lib/Target/X86: X86ISelPattern.cpp updated: 1.188 -> 1.189 --- Log message: Fixed a typo: line 2323: MOVSX16rm8 -> MOVZX16rm8. This was the cause fo 12/14/2005 hbd failure. --- Diffs of the changes: (+1 -1) X86ISelPattern.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.188 llvm/lib/Target/X86/X86ISelPattern.cpp:1.189 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.188Sun Dec 4 00:03:50 2005 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Wed Dec 14 16:28:18 2005 @@ -2332,7 +2332,7 @@ case MVT::i16: assert(cast(Node->getOperand(3))->getVT() <= MVT::i8 && "Bad zero extend!"); - addFullAddress(BuildMI(BB, X86::MOVSX16rm8, 5, Result), AM); + addFullAddress(BuildMI(BB, X86::MOVZX16rm8, 5, Result), AM); break; case MVT::i8: assert(cast(Node->getOperand(3))->getVT() == MVT::i1 && ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/fma.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
fma.ll updated: 1.4 -> 1.5
---
Log message:
Add a case for float just to make sure the patterns for both precisions
are matching
---
Diffs of the changes: (+7 -1)
fma.ll |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/PowerPC/fma.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/fma.ll:1.4
llvm/test/Regression/CodeGen/PowerPC/fma.ll:1.5
--- llvm/test/Regression/CodeGen/PowerPC/fma.ll:1.4 Thu May 12 16:06:05 2005
+++ llvm/test/Regression/CodeGen/PowerPC/fma.ll Wed Dec 14 16:51:13 2005
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | egrep 'fn?madd|fn?msub' | wc -l |
grep 7
+; RUN: llvm-as < %s | llc -march=ppc32 | egrep 'fn?madd|fn?msub' | wc -l |
grep 8
double %test_FMADD1(double %A, double %B, double %C) {
%D = mul double %A, %B
@@ -38,3 +38,9 @@
%F = sub double -0.0, %E
ret double %F
}
+float %test_FNMSUBS(float %A, float %B, float %C) {
+ %D = mul float %A, %B
+ %E = sub float %D, %C
+ %F = sub float -0.0, %E
+ ret float %F
+}
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.140 -> 1.141
PPCInstrInfo.td updated: 1.158 -> 1.159
---
Log message:
Use the new predicate support that Evan Cheng added to remove some code
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
---
Diffs of the changes: (+24 -57)
PPCISelDAGToDAG.cpp | 47 ---
PPCInstrInfo.td | 34 --
2 files changed, 24 insertions(+), 57 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.140
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.141
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.140 Fri Dec 9 20:36:00 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Dec 14 16:54:33 2005
@@ -885,53 +885,6 @@
CurDAG->getTargetFrameIndex(FI, MVT::i32),
getI32Imm(0));
}
- case ISD::FADD: {
-MVT::ValueType Ty = N->getValueType(0);
-if (!NoExcessFPPrecision) { // Match FMA ops
- if (N->getOperand(0).getOpcode() == ISD::FMUL &&
- N->getOperand(0).Val->hasOneUse()) {
-++FusedFP; // Statistic
-return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD
:PPC::FMADDS,
-Ty, Select(N->getOperand(0).getOperand(0)),
-Select(N->getOperand(0).getOperand(1)),
-Select(N->getOperand(1)));
- } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
- N->getOperand(1).hasOneUse()) {
-++FusedFP; // Statistic
-return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD
:PPC::FMADDS,
-Ty, Select(N->getOperand(1).getOperand(0)),
-Select(N->getOperand(1).getOperand(1)),
-Select(N->getOperand(0)));
- }
-}
-
-// Other cases are autogenerated.
-break;
- }
- case ISD::FSUB: {
-MVT::ValueType Ty = N->getValueType(0);
-
-if (!NoExcessFPPrecision) { // Match FMA ops
- if (N->getOperand(0).getOpcode() == ISD::FMUL &&
- N->getOperand(0).Val->hasOneUse()) {
-++FusedFP; // Statistic
-return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB:PPC::FMSUBS,
-Ty, Select(N->getOperand(0).getOperand(0)),
-Select(N->getOperand(0).getOperand(1)),
-Select(N->getOperand(1)));
- } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
- N->getOperand(1).Val->hasOneUse()) {
-++FusedFP; // Statistic
-return CurDAG->SelectNodeTo(N, Ty == MVT::f64
?PPC::FNMSUB:PPC::FNMSUBS,
-Ty, Select(N->getOperand(1).getOperand(0)),
-Select(N->getOperand(1).getOperand(1)),
-Select(N->getOperand(0)));
- }
-}
-
-// Other cases are autogenerated.
-break;
- }
case ISD::SDIV: {
// FIXME: since this depends on the setting of the carry flag from the
srawi
//we should really be making notes about that for the scheduler.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.158
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.159
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.158 Wed Dec 14 16:07:12 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Wed Dec 14 16:54:33 2005
@@ -168,7 +168,7 @@
//===--===//
// PowerPC Instruction Predicate Definitions.
-def FPContractions : Predicate<"!NoExcessFPPrecision">;
+def FPContractions : Predicate<"NoExcessFPPrecision">;
//===--===//
// PowerPC Instruction Definitions.
@@ -746,22 +746,26 @@
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
[(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
-
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.141 -> 1.142
---
Log message:
Remove a now unused statistic.
---
Diffs of the changes: (+0 -1)
PPCISelDAGToDAG.cpp |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.141
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.142
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.141 Wed Dec 14 16:54:33 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Dec 14 16:56:16 2005
@@ -29,7 +29,6 @@
using namespace llvm;
namespace {
- Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
//======//
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.166 -> 1.167
---
Log message:
Use MOV8rm to load 1 bit value.
---
Diffs of the changes: (+3 -0)
X86InstrInfo.td |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.166
llvm/lib/Target/X86/X86InstrInfo.td:1.167
--- llvm/lib/Target/X86/X86InstrInfo.td:1.166 Tue Dec 13 20:22:27 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Wed Dec 14 18:59:17 2005
@@ -431,6 +431,9 @@
"mov{l} {$src, $dst|$dst, $src}",
[(store R32:$src, addr:$dst)]>;
+// Handling 1 bit load
+def : Pat<(i1 (load addr:$src)), (MOV8rm addr:$src)>;
+
//===--===//
// Fixed-Register Multiplication and Division Instructions...
//
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.10 -> 1.11
---
Log message:
Handling zero extension of 1 bit value.
---
Diffs of the changes: (+128 -17)
X86ISelDAGToDAG.cpp | 145 +---
1 files changed, 128 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.10
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.11
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.10Mon Dec 12 15:49:40 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Dec 14 19:02:48 2005
@@ -22,6 +22,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
#include "llvm/ADT/Statistic.h"
+#include
using namespace llvm;
//===--===//
@@ -95,6 +96,8 @@
private:
SDOperand Select(SDOperand N);
+bool isFoldableLoad(SDOperand Op, SDOperand OtherOp,
+bool FloatPromoteOk = false);
bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp);
@@ -359,36 +362,144 @@
return false;
}
-SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
- SDNode *N = Op.Val;
- MVT::ValueType OpVT = N->getValueType(0);
+/// NodeTransitivelyUsesValue - Return true if N or any of its uses uses Op.
+/// The DAG cannot have cycles in it, by definition, so the visited set is not
+/// needed to prevent infinite loops. The DAG CAN, however, have unbounded
+/// reuse, so it prevents exponential cases.
+///
+static bool NodeTransitivelyUsesValue(SDOperand N, SDOperand Op,
+ std::set &Visited) {
+ if (N == Op) return true;// Found it.
+ SDNode *Node = N.Val;
+ if (Node->getNumOperands() == 0 || // Leaf?
+ Node->getNodeDepth() <= Op.getNodeDepth()) return false; // Can't find
it?
+ if (!Visited.insert(Node).second) return false; // Already visited?
+
+ // Recurse for the first N-1 operands.
+ for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
+if (NodeTransitivelyUsesValue(Node->getOperand(i), Op, Visited))
+ return true;
+
+ // Tail recurse for the last operand.
+ return NodeTransitivelyUsesValue(Node->getOperand(0), Op, Visited);
+}
+
+/// isFoldableLoad - Return true if this is a load instruction that can safely
+/// be folded into an operation that uses it.
+bool X86DAGToDAGISel::isFoldableLoad(SDOperand Op, SDOperand OtherOp,
+ bool FloatPromoteOk) {
+ if (Op.getOpcode() == ISD::LOAD) {
+// FIXME: currently can't fold constant pool indexes.
+if (isa(Op.getOperand(1)))
+ return false;
+ } else if (FloatPromoteOk && Op.getOpcode() == ISD::EXTLOAD &&
+ cast(Op.getOperand(3))->getVT() == MVT::f32) {
+// FIXME: currently can't fold constant pool indexes.
+if (isa(Op.getOperand(1)))
+ return false;
+ } else {
+return false;
+ }
+
+ // If this load has already been emitted, we clearly can't fold it.
+ assert(Op.ResNo == 0 && "Not a use of the value of the load?");
+ if (CodeGenMap.count(Op.getValue(1))) return false;
+ assert(!CodeGenMap.count(Op.getValue(0)) &&
+ "Value in map but not token chain?");
+ assert(!CodeGenMap.count(Op.getValue(1)) &&
+ "Token lowered but value not in map?");
+
+ // If there is not just one use of its value, we cannot fold.
+ if (!Op.Val->hasNUsesOfValue(1, 0)) return false;
+
+ // Finally, we cannot fold the load into the operation if this would induce a
+ // cycle into the resultant dag. To check for this, see if OtherOp (the
other
+ // operand of the operation we are folding the load into) can possible use
the
+ // chain node defined by the load.
+ if (OtherOp.Val && !Op.Val->hasNUsesOfValue(0, 1)) { // Has uses of chain?
+std::set Visited;
+if (NodeTransitivelyUsesValue(OtherOp, Op.getValue(1), Visited))
+ return false;
+ }
+ return true;
+}
+
+SDOperand X86DAGToDAGISel::Select(SDOperand N) {
+ SDNode *Node = N.Val;
+ MVT::ValueType NVT = Node->getValueType(0);
unsigned Opc;
- if (N->getOpcode() >= ISD::BUILTIN_OP_END)
-return Op; // Already selected.
+ if (Node->getOpcode() >= ISD::BUILTIN_OP_END)
+return N; // Already selected.
- switch (N->getOpcode()) {
+ switch (Node->getOpcode()) {
default: break;
case ISD::SHL:
- if (ConstantSDNode *CN = dyn_cast(N->getOperand(1))) {
+ if (ConstantSDNode *CN = dyn_cast(Node->getOperand(1))) {
if (CN->getValue() == 1) {
// X = SHL Y, 1 -> X = ADD Y, Y
- switch (OpVT) {
+ switch (NVT) {
default: assert(0 && "Cannot shift this type!");
case MVT::i8: Opc = X86::ADD8rr; break;
case MVT::i16: Opc = X86::ADD16rr; break;
case MVT::i32:
