[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.5 -> 1.6 --- Log message: X86 doesn't support sextinreg for 8-bit things either. --- Diffs of the changes: (+1 -0) X86ISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.5 llvm/lib/Target/X86/X86ISelLowering.cpp:1.6 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.5 Tue Nov 29 00:16:21 2005 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Dec 7 11:59:14 2005 @@ -88,6 +88,7 @@ setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.63 -> 1.64 --- Log message: Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or if the target supports the resultant sextinreg --- Diffs of the changes: (+3 -1) DAGCombiner.cpp |4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.63 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.64 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.63 Wed Dec 7 01:11:03 2005 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Dec 7 12:02:05 2005 @@ -1547,7 +1547,9 @@ if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType()) return N0; // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. - if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT) + if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& + (!AfterLegalize || + TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType( return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), DAG.getValueType(N0.getValueType())); // fold (sext (load x)) -> (sextload x) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c
Changes in directory llvm-gcc/gcc:
llvm-expand.c updated: 1.120 -> 1.121
---
Log message:
Minor simplification to the EH code: CleanupsCanThrow is always the inverse
of isExceptionEdge. Eliminate it in favor of !isExceptionEdge
---
Diffs of the changes: (+28 -41)
llvm-expand.c | 69 +++---
1 files changed, 28 insertions(+), 41 deletions(-)
Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.120 llvm-gcc/gcc/llvm-expand.c:1.121
--- llvm-gcc/gcc/llvm-expand.c:1.120Sun Dec 4 22:49:21 2005
+++ llvm-gcc/gcc/llvm-expand.c Wed Dec 7 13:35:10 2005
@@ -48,7 +48,6 @@
static void llvm_expand_constructor(llvm_function *Fn, tree exp,
llvm_value *Dest, int isVolatile);
static void llvm_expand_goto_internal(llvm_function *Fn, llvm_basicblock
*label,
- int CleanupsCanThrow,
int isExceptionEdge);
static llvm_constant *llvm_expand_constant_expr(tree exp, llvm_type *ReqType);
static llvm_constant *llvm_decode_string_constant(tree exp, unsigned Len,
@@ -638,10 +637,6 @@
/* The LLVM basic block that this is jumping to. */
llvm_basicblock *target_bb;
- /* Information about what happens if a cleanup expression throws an
exception.
- See llvm_expand_goto_internal for information about this flag. */
- int CleanupsCanThrow : 1;
-
/* Information about whether this goto is part of an exception propagation.
* If so, cleanups which are only supposed to be run on exception exits are
* expanded.
@@ -770,9 +765,8 @@
void llvm_fixup_list_dump(llvm_function *Fn) {
llvm_goto_fixup *f = Fn->ExpandInfo->GotoFixupList;
for (; f; f = f->next) {
-fprintf(stderr, "Fixup [%p]: to bb %%%s cct: %s iee: %s cleanups: %p"
+fprintf(stderr, "Fixup [%p]: to bb %%%s iee: %s cleanups: %p"
" containing_block: %p\n", (void*)f, D2V(f->target_bb)->Name,
-f->CleanupsCanThrow ? "Yes" : "No",
f->isExceptionEdge ? "Yes" : "No",
(void*)f->cleanup_list, (void*)f->containing_block);
}
@@ -784,13 +778,11 @@
*/
static llvm_basicblock *
llvm_get_existing_fixup(llvm_function *Fn, llvm_basicblock *BB,
-int CleanupsCanThrow, int isExceptionEdge,
-tree cleanups) {
+int isExceptionEdge, tree cleanups) {
llvm_goto_fixup *fixup;
for (fixup = Fn->ExpandInfo->GotoFixupList; fixup; fixup = fixup->next)
if (fixup->target_bb == BB &&
fixup->cleanup_list == cleanups &&
-fixup->CleanupsCanThrow == CleanupsCanThrow &&
fixup->isExceptionEdge == isExceptionEdge) {
llvm_basicblock *FixupBrBlock = fixup->BranchBlock;
@@ -835,14 +827,14 @@
*/
static int llvm_expand_cleanups(llvm_function *Fn, tree *list,
llvm_instruction *TheBranch,
-int CleanupsCanThrow, int isExceptionEdge) {
+int isExceptionEdge) {
int CleanupIsDead = 0;
tree OrigList = *list;
assert(TheBranch->Opcode == O_Br && TheBranch->NumOperands == 1 &&
"Cleanups only support for unconditional branches!");
- if (!CleanupsCanThrow)
+ if (isExceptionEdge)
Fn->ExpandInfo->ThrownExceptionsCallTerminate++;
while (*list) {
@@ -870,8 +862,8 @@
*/
llvm_basicblock *DestBB = V2BB(TheBranch->Operands[0]);
llvm_basicblock *Existing = llvm_get_existing_fixup(Fn, DestBB,
- CleanupsCanThrow,
- isExceptionEdge, *list);
+ isExceptionEdge,
+ *list);
if (Existing) {
TheBranch->Operands[0] = D2V(Existing);
CleanupIsDead = 1;
@@ -883,7 +875,7 @@
/* Restore input list to what it was when llvm_expand_cleanups was invoked */
*list = OrigList;
- if (!CleanupsCanThrow)
+ if (isExceptionEdge)
Fn->ExpandInfo->ThrownExceptionsCallTerminate--;
return CleanupIsDead;
@@ -931,7 +923,6 @@
DeleteThisFixup = llvm_expand_cleanups(Fn,
&thisblock->x.block.cleanups,
f->BranchInst,
- f->CleanupsCanThrow,
f->isExceptionEdge);
thisblock->x.block.cleanups = SavedCleanups;
@@ -989,7 +980,7 @@
/* Now that we have handled this binding level for the goto, check to see
* if it became equal to an existing fixup.
*/
- LastBlock = llvm_get_existing_fixup(Fn, f->target_bb,
f->CleanupsCanThrow,
+ LastBlock = llvm_get_existing_fixup(Fn, f->target_bb,
f->isExceptionEdge, newcleanups);
i
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.223 -> 1.224
SelectionDAGISel.cpp updated: 1.111 -> 1.112
---
Log message:
Fix a crash where ConstantVec nodes were being generated with the wrong
type when the target did not support them. Also teach Legalize how to
expand ConstantVecs.
This allows us to generate
_test:
lwz r2, 12(r3)
lwz r4, 8(r3)
lwz r5, 4(r3)
lwz r6, 0(r3)
addi r2, r2, 4
addi r4, r4, 3
addi r5, r5, 2
addi r6, r6, 1
stw r2, 12(r3)
stw r4, 8(r3)
stw r5, 4(r3)
stw r6, 0(r3)
blr
For:
void %test(%v4i *%P) {
%T = load %v4i* %P
%S = add %v4i %T,
store %v4i %S, %v4i * %P
ret void
}
On PowerPC.
---
Diffs of the changes: (+30 -2)
LegalizeDAG.cpp | 22 ++
SelectionDAGISel.cpp | 10 --
2 files changed, 30 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.223
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.224
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.223 Tue Dec 6 00:18:55 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Dec 7 13:48:11 2005
@@ -3159,6 +3159,28 @@
Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
break;
}
+ case ISD::ConstantVec: {
+unsigned NumElements = Node->getNumOperands();
+// If we only have two elements left in the constant vector, just break it
+// apart into the two scalar constants it contains. Otherwise, bisect the
+// ConstantVec, and return each half as a new ConstantVec.
+// FIXME: this is hard coded as big endian, it may have to change to
support
+// SSE and Alpha MVI
+if (NumElements == 2) {
+ Hi = Node->getOperand(0);
+ Lo = Node->getOperand(1);
+} else {
+ NumElements /= 2;
+ std::vector LoOps, HiOps;
+ for (unsigned I = 0, E = NumElements; I < E; ++I) {
+HiOps.push_back(Node->getOperand(I));
+LoOps.push_back(Node->getOperand(I+NumElements));
+ }
+ Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps);
+ Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps);
+}
+break;
+ }
case ISD::BUILD_PAIR:
// Legalize both operands. FIXME: in the future we should handle the case
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.111
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.112
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.111Tue Dec 6
00:18:55 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Dec 7 13:48:11 2005
@@ -318,9 +318,15 @@
}
// Handle the case where we have a 1-element vector, in which
// case we want to immediately turn it into a scalar constant.
-if (Ops.size() == 1)
+if (Ops.size() == 1) {
return N = Ops[0];
-return N = DAG.getNode(ISD::ConstantVec, TVT, Ops);
+} else if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
+ return N = DAG.getNode(ISD::ConstantVec, TVT, Ops);
+} else {
+ // If the packed type isn't legal, then create a ConstantVec node
with
+ // generic Vector type instead.
+ return N = DAG.getNode(ISD::ConstantVec, MVT::Vector, Ops);
+}
} else {
// Canonicalize all constant ints to be unsigned.
return N =
DAG.getConstant(cast(C)->getRawValue(),VT);
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.75 -> 1.76
---
Log message:
Added support for ComplexPattern. These are patterns that require C++ pattern
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple
operands, e.g. X86 addressing mode returns 4.
---
Diffs of the changes: (+49 -10)
SelectionDAG.h | 59 +++--
1 files changed, 49 insertions(+), 10 deletions(-)
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.75
llvm/include/llvm/CodeGen/SelectionDAG.h:1.76
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.75 Wed Nov 30 18:18:45 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.hWed Dec 7 20:00:35 2005
@@ -327,16 +327,6 @@
SDOperand Op1, SDOperand Op2) {
return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2);
}
- SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
- MVT::ValueType VT2, SDOperand Op1, SDOperand Op2) {
-std::vector ResultTys;
-ResultTys.push_back(VT1);
-ResultTys.push_back(VT2);
-std::vector Ops;
-Ops.push_back(Op1);
-Ops.push_back(Op2);
-return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
- }
SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
SDOperand Op1, SDOperand Op2, SDOperand Op3) {
return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3);
@@ -355,6 +345,55 @@
std::vector &Ops) {
return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops);
}
+ SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
+ MVT::ValueType VT2, SDOperand Op1, SDOperand Op2) {
+std::vector ResultTys;
+ResultTys.push_back(VT1);
+ResultTys.push_back(VT2);
+std::vector Ops;
+Ops.push_back(Op1);
+Ops.push_back(Op2);
+return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
+ }
+ SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
+ MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
+ SDOperand Op3) {
+std::vector ResultTys;
+ResultTys.push_back(VT1);
+ResultTys.push_back(VT2);
+std::vector Ops;
+Ops.push_back(Op1);
+Ops.push_back(Op2);
+Ops.push_back(Op3);
+return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
+ }
+ SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
+ MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
+ SDOperand Op3, SDOperand Op4) {
+std::vector ResultTys;
+ResultTys.push_back(VT1);
+ResultTys.push_back(VT2);
+std::vector Ops;
+Ops.push_back(Op1);
+Ops.push_back(Op2);
+Ops.push_back(Op3);
+Ops.push_back(Op4);
+return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
+ }
+ SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
+ MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
+ SDOperand Op3, SDOperand Op4, SDOperand Op5) {
+std::vector ResultTys;
+ResultTys.push_back(VT1);
+ResultTys.push_back(VT2);
+std::vector Ops;
+Ops.push_back(Op1);
+Ops.push_back(Op2);
+Ops.push_back(Op3);
+Ops.push_back(Op4);
+Ops.push_back(Op5);
+return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
+ }
SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, std::vector &Ops) {
std::vector ResultTys;
___
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[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp CodeGenTarget.h DAGISelEmitter.cpp DAGISelEmitter.h
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.47 -> 1.48
CodeGenTarget.h updated: 1.21 -> 1.22
DAGISelEmitter.cpp updated: 1.85 -> 1.86
DAGISelEmitter.h updated: 1.39 -> 1.40
---
Log message:
Added support for ComplexPattern. These are patterns that require C++ pattern
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple
operands, e.g. X86 addressing mode returns 4.
---
Diffs of the changes: (+171 -47)
CodeGenTarget.cpp |9 ++
CodeGenTarget.h| 17 +
DAGISelEmitter.cpp | 165 -
DAGISelEmitter.h | 27 +---
4 files changed, 171 insertions(+), 47 deletions(-)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.47
llvm/utils/TableGen/CodeGenTarget.cpp:1.48
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.47 Sun Dec 4 02:18:16 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp Wed Dec 7 20:00:36 2005
@@ -330,3 +330,12 @@
throw "Instruction '" + TheDef->getName() +
"' does not have an operand named '$" + Name + "'!";
}
+
+//===--===//
+// ComplexPattern implementation
+//
+ComplexPattern::ComplexPattern(Record *R) {
+ NumOperands = R->getValueAsInt("NumOperands");
+ SelectFunc= R->getValueAsString("SelectFunc");
+ MatchingNodes = R->getValueAsListOfDefs("MatchingNodes");
+}
Index: llvm/utils/TableGen/CodeGenTarget.h
diff -u llvm/utils/TableGen/CodeGenTarget.h:1.21
llvm/utils/TableGen/CodeGenTarget.h:1.22
--- llvm/utils/TableGen/CodeGenTarget.h:1.21Sun Dec 4 20:35:08 2005
+++ llvm/utils/TableGen/CodeGenTarget.h Wed Dec 7 20:00:36 2005
@@ -157,6 +157,23 @@
bool isLittleEndianEncoding() const;
};
+/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
+/// tablegen class in TargetSelectionDAG.td
+class ComplexPattern {
+ unsigned NumOperands;
+ std::string SelectFunc;
+ std::vector MatchingNodes;
+public:
+ ComplexPattern() : NumOperands(0) {};
+ ComplexPattern(Record *R);
+
+ unsigned getNumOperands() const { return NumOperands; }
+ const std::string &getSelectFunc() const { return SelectFunc; }
+ const std::vector &getMatchingNodes() const {
+return MatchingNodes;
+ }
+};
+
} // End llvm namespace
#endif
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.85
llvm/utils/TableGen/DAGISelEmitter.cpp:1.86
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.85 Mon Dec 5 17:08:55 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Wed Dec 7 20:00:36 2005
@@ -477,6 +477,9 @@
} else if (R->isSubClassOf("ValueType") || R->isSubClassOf("CondCode")) {
// Using a VTSDNode or CondCodeSDNode.
return MVT::Other;
+ } else if (R->isSubClassOf("ComplexPattern")) {
+const CodeGenTarget &T = TP.getDAGISelEmitter().getTargetInfo();
+return T.getPointerType();
} else if (R->getName() == "node") {
// Placeholder.
return MVT::isUnknown;
@@ -609,7 +612,7 @@
for (unsigned i = 0, e = getNumChildren(); i != e; ++i)
if (!getChild(i)->canPatternMatch(Reason, ISE))
return false;
-
+
// If this node is a commutative operator, check that the LHS isn't an
// immediate.
const SDNodeInfo &NodeInfo = ISE.getSDNodeInfo(getOperator());
@@ -833,6 +836,13 @@
}
}
+void DAGISelEmitter::ParseComplexPatterns() {
+ std::vector AMs =
Records.getAllDerivedDefinitions("ComplexPattern");
+ while (!AMs.empty()) {
+ComplexPatterns.insert(std::make_pair(AMs.back(), AMs.back()));
+AMs.pop_back();
+ }
+}
/// ParsePatternFragments - Parse all of the PatFrag definitions in the .td
@@ -1204,9 +1214,10 @@
if (InVal->isLeaf() &&
dynamic_cast(InVal->getLeafValue())) {
Record *InRec = static_cast(InVal->getLeafValue())->getDef();
-if (CGI.OperandList[i].Rec != InRec)
+if (CGI.OperandList[i].Rec != InRec &&
+!InRec->isSubClassOf("ComplexPattern"))
I->error("Operand $" + OpName +
- "'s register class disagrees between the operand and
pattern");
+ "'s register class disagrees between the operand and
pattern");
}
Operands.push_back(CGI.OperandList[i].Rec);
@@ -1586,22 +1597,59 @@
}
+// NodeIsComplexPattern - return true if N is a leaf node and a subclass of
+// ComplexPattern.
+static bool NodeIsComplexPattern(TreePatternNode *N)
+{
+ return (N->isLeaf() &&
+ dynamic_cast(N->getLeafValue()) &&
+ static_cast(N->getLeafValue())->getDef()->
+ isSubClassOf("ComplexPattern"));
+}
+
+// NodeGetComplexPattern - return the pointer to the ComplexPattern if N
+// is a leaf node and a subclass of ComplexPattern, else it returns NULL.
+static const ComplexPattern *NodeGetComplexPattern(TreePatternNode *N,
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.6 -> 1.7
X86InstrInfo.td updated: 1.148 -> 1.149
---
Log message:
* Added intelligence to X86 LEA addressing mode matching routine so it returns
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
---
Diffs of the changes: (+103 -84)
X86ISelDAGToDAG.cpp | 158 +++-
X86InstrInfo.td | 29 +
2 files changed, 103 insertions(+), 84 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.6
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.7
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.6 Wed Nov 30 18:43:55 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Dec 7 20:01:35 2005
@@ -36,6 +36,7 @@
enum {
RegBase,
FrameIndexBase,
+ ConstantPoolBase
} BaseType;
struct {// This is really a union, discriminated by BaseType!
@@ -94,8 +95,11 @@
private:
SDOperand Select(SDOperand N);
-void SelectAddress(SDOperand N, X86ISelAddressMode &AM);
bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
+bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
+SDOperand &Index, SDOperand &Disp);
+bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
+ SDOperand &Index, SDOperand &Disp);
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
@@ -130,23 +134,6 @@
ScheduleAndEmitDAG(DAG);
}
-/// SelectAddress - Pattern match the maximal addressing mode for this node.
-void X86DAGToDAGISel::SelectAddress(SDOperand N, X86ISelAddressMode &AM) {
- MatchAddress(N, AM);
-
- if (AM.BaseType == X86ISelAddressMode::RegBase) {
-if (AM.Base.Reg.Val)
- AM.Base.Reg = Select(AM.Base.Reg);
-else
- AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
- }
- if (!AM.IndexReg.Val) {
-AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
- } else {
-AM.IndexReg = Select(AM.IndexReg);
- }
-}
-
/// FIXME: copied from X86ISelPattern.cpp
/// MatchAddress - Add the specified node to the specified addressing mode,
/// returning true if it cannot be done. This just pattern matches for the
@@ -161,6 +148,17 @@
return false;
}
break;
+
+ case ISD::ConstantPool:
+if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
+ if (ConstantPoolSDNode *CP = dyn_cast(N)) {
+AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
+AM.Base.Reg = CurDAG->getTargetConstantPool(CP->get(), MVT::i32);
+return false;
+ }
+}
+break;
+
case ISD::GlobalAddress:
if (AM.GV == 0) {
GlobalValue *GV = cast(N)->getGlobal();
@@ -177,9 +175,11 @@
}
}
break;
+
case ISD::Constant:
AM.Disp += cast(N)->getValue();
return false;
+
case ISD::SHL:
if (AM.IndexReg.Val == 0 && AM.Scale == 1)
if (ConstantSDNode *CN = dyn_cast(N.Val->getOperand(1)))
{
@@ -204,6 +204,7 @@
}
}
break;
+
case ISD::MUL:
// X*[3,5,9] -> X+X*[2,4,8]
if (AM.IndexReg.Val == 0 && AM.BaseType == X86ISelAddressMode::RegBase &&
@@ -266,6 +267,67 @@
return false;
}
+/// SelectAddr - returns true if it is able pattern match an addressing mode.
+/// It returns the operands which make up the maximal addressing mode it can
+/// match by reference.
+bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand
&Scale,
+ SDOperand &Index, SDOperand &Disp) {
+ X86ISelAddressMode AM;
+ if (!MatchAddress(N, AM)) {
+if (AM.BaseType == X86ISelAddressMode::RegBase) {
+ if (AM.Base.Reg.Val)
+AM.Base.Reg = Select(AM.Base.Reg);
+ else
+AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
+}
+if (AM.IndexReg.Val)
+ AM.IndexReg = Select(AM.IndexReg);
+else
+ AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
+
+Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
+ CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
+Scale = getI8Imm (AM.Scale);
+Index = AM.IndexReg;
+Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
+ : getI32Imm(AM.Disp);
+return true;
+ }
+ return false;
+}
+
+static bool isRegister0(SDOperand Op)
+{
+ if (RegisterSDNode *R = dyn_cast(Op))
+return (R->getReg() == 0);
+ return false;
+}
+
+/// SelectLEAAddr - it calls SelectAddr and determines if the maximal
addressing
+/// mode it matches can be cost effectively emitted as an LEA instruction.
+/// For X86, it always is unless it's just a (Reg + const).
+bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand
&Scale,
+SDOperand &Index, SDOperand &Disp) {
+ if (SelectAddr(N, Base, Scale, Index, D
[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp CodeGenTarget.h DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.48 -> 1.49
CodeGenTarget.h updated: 1.22 -> 1.23
DAGISelEmitter.cpp updated: 1.86 -> 1.87
---
Log message:
* Added an explicit type field to ComplexPattern.
* Renamed MatchingNodes to RootNodes.
---
Diffs of the changes: (+12 -9)
CodeGenTarget.cpp |8 +---
CodeGenTarget.h|8 +---
DAGISelEmitter.cpp |5 ++---
3 files changed, 12 insertions(+), 9 deletions(-)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.48
llvm/utils/TableGen/CodeGenTarget.cpp:1.49
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.48 Wed Dec 7 20:00:36 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp Wed Dec 7 20:14:08 2005
@@ -335,7 +335,9 @@
// ComplexPattern implementation
//
ComplexPattern::ComplexPattern(Record *R) {
- NumOperands = R->getValueAsInt("NumOperands");
- SelectFunc= R->getValueAsString("SelectFunc");
- MatchingNodes = R->getValueAsListOfDefs("MatchingNodes");
+ Ty = ::getValueType(R->getValueAsDef("Ty"));
+ NumOperands = R->getValueAsInt("NumOperands");
+ SelectFunc = R->getValueAsString("SelectFunc");
+ RootNodes = R->getValueAsListOfDefs("RootNodes");
}
+
Index: llvm/utils/TableGen/CodeGenTarget.h
diff -u llvm/utils/TableGen/CodeGenTarget.h:1.22
llvm/utils/TableGen/CodeGenTarget.h:1.23
--- llvm/utils/TableGen/CodeGenTarget.h:1.22Wed Dec 7 20:00:36 2005
+++ llvm/utils/TableGen/CodeGenTarget.h Wed Dec 7 20:14:08 2005
@@ -160,17 +160,19 @@
/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
/// tablegen class in TargetSelectionDAG.td
class ComplexPattern {
+ MVT::ValueType Ty;
unsigned NumOperands;
std::string SelectFunc;
- std::vector MatchingNodes;
+ std::vector RootNodes;
public:
ComplexPattern() : NumOperands(0) {};
ComplexPattern(Record *R);
+ MVT::ValueType getValueType() const { return Ty; }
unsigned getNumOperands() const { return NumOperands; }
const std::string &getSelectFunc() const { return SelectFunc; }
- const std::vector &getMatchingNodes() const {
-return MatchingNodes;
+ const std::vector &getRootNodes() const {
+return RootNodes;
}
};
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.86
llvm/utils/TableGen/DAGISelEmitter.cpp:1.87
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.86 Wed Dec 7 20:00:36 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Wed Dec 7 20:14:08 2005
@@ -478,8 +478,7 @@
// Using a VTSDNode or CondCodeSDNode.
return MVT::Other;
} else if (R->isSubClassOf("ComplexPattern")) {
-const CodeGenTarget &T = TP.getDAGISelEmitter().getTargetInfo();
-return T.getPointerType();
+return TP.getDAGISelEmitter().getComplexPattern(R).getValueType();
} else if (R->getName() == "node") {
// Placeholder.
return MVT::isUnknown;
@@ -2256,7 +2255,7 @@
dynamic_cast(Node->getLeafValue())) {
PatternsByOpcode[getSDNodeNamed("imm")].push_back(&PatternsToMatch[i]);
} else if ((CP = NodeGetComplexPattern(Node, *this))) {
-std::vector OpNodes = CP->getMatchingNodes();
+std::vector OpNodes = CP->getRootNodes();
for (unsigned j = 0, e = OpNodes.size(); j != e; j++) {
PatternsByOpcode[OpNodes[j]].insert(PatternsByOpcode[OpNodes[j]].begin(),
&PatternsToMatch[i]);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.149 -> 1.150 --- Log message: Added explicit type field to ComplexPattern. --- Diffs of the changes: (+2 -2) X86InstrInfo.td |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.149 llvm/lib/Target/X86/X86InstrInfo.td:1.150 --- llvm/lib/Target/X86/X86InstrInfo.td:1.149 Wed Dec 7 20:01:35 2005 +++ llvm/lib/Target/X86/X86InstrInfo.td Wed Dec 7 20:15:07 2005 @@ -47,8 +47,8 @@ def brtarget : Operand; // Define X86 specific addressing mode. -def addr: ComplexPattern<4, "SelectAddr", []>; -def leaaddr : ComplexPattern<4, "SelectLEAAddr", [add]>; +def addr: ComplexPattern; +def leaaddr : ComplexPattern; // Format specifies the encoding used by the instruction. This is part of the // ad-hoc solution used to emit machine instruction encodings by our machine ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.12 -> 1.13
---
Log message:
Added support for ComplexPattern.
---
Diffs of the changes: (+21 -0)
TargetSelectionDAG.td | 21 +
1 files changed, 21 insertions(+)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.12
llvm/lib/Target/TargetSelectionDAG.td:1.13
--- llvm/lib/Target/TargetSelectionDAG.td:1.12 Sun Dec 4 20:37:26 2005
+++ llvm/lib/Target/TargetSelectionDAG.td Wed Dec 7 22:28:48 2005
@@ -131,6 +131,10 @@
SDTCisInt<0>, SDTCisInt<1>
]>;
+def SDTLoad : SDTypeProfile<1, 1, [ // load
+ SDTCisInt<1>
+]>;
+
//===--===//
// Selection DAG Node Properties.
//
@@ -220,6 +224,8 @@
def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>;
+def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
+
//===--===//
// Selection DAG Condition Codes
@@ -349,3 +355,18 @@
// not needing a full list.
class Pat : Pattern;
+//===--===//
+// Complex pattern definitions.
+//
+// Complex patterns, e.g. X86 addressing mode, requires pattern matching code
+// in C++. NumOperands is the number of operands returned by the select
function;
+// SelectFunc is the name of the function used to pattern match the max.
pattern;
+// RootNodes are the list of possible root nodes of the sub-dags to match.
+// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr",
[add]>;
+//
+class ComplexPattern roots =
[]> {
+ ValueType Ty = ty;
+ int NumOperands = numops;
+ string SelectFunc = fn;
+ list RootNodes = roots;
+}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.39 -> 1.40
---
Log message:
Add another important case we miss
---
Diffs of the changes: (+19 -0)
README.txt | 19 +++
1 files changed, 19 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.39
llvm/lib/Target/PowerPC/README.txt:1.40
--- llvm/lib/Target/PowerPC/README.txt:1.39 Thu Nov 17 12:26:56 2005
+++ llvm/lib/Target/PowerPC/README.txt Thu Dec 8 01:13:28 2005
@@ -222,3 +222,22 @@
instruction to avoid a copy AFTER the 2-addr instruction. The 2-addr pass
currently only commutes to avoid inserting a copy BEFORE the two addr instr.
+===-===
+
+Compile offsets from allocas:
+
+int *%test() {
+%X = alloca { int, int }
+%Y = getelementptr {int,int}* %X, int 0, uint 1
+ret int* %Y
+}
+
+into a single add, not two:
+
+_test:
+addi r2, r1, -8
+addi r3, r2, 4
+blr
+
+--> important for C++.
+
___
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