[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaISelDAGToDAG.cpp updated: 1.11 -> 1.12 --- Log message: fix constant pool loads --- Diffs of the changes: (+1 -1) AlphaISelDAGToDAG.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.11 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.12 --- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.11Wed Nov 30 19:53:10 2005 +++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Mon Dec 5 11:51:02 2005 @@ -281,7 +281,7 @@ ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val); SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64); Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg()); - return CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp); + return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, CPI, Tmp); } break; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopStrengthReduce.cpp updated: 1.70 -> 1.71
---
Log message:
getRawValue zero extens for unsigned values, use getsextvalue so that we
know that small negative values fit into the immediate field of addressing
modes.
---
Diffs of the changes: (+3 -3)
LoopStrengthReduce.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.70
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.71
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.70 Fri Oct 21
00:45:41 2005
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Dec 5 12:23:57 2005
@@ -560,9 +560,9 @@
// FIXME: Look at the target to decide if &GV is a legal constant immediate.
if (SCEVConstant *SC = dyn_cast(V)) {
// PPC allows a sign-extended 16-bit immediate field.
-if ((int64_t)SC->getValue()->getRawValue() > -(1 << 16) &&
-(int64_t)SC->getValue()->getRawValue() < (1 << 16)-1)
- return true;
+int64_t V = SC->getValue()->getSExtValue();
+if (V > -(1 << 16) && V < (1 << 16)-1)
+return true;
return false;
}
___
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.12 -> 1.13
AlphaInstrInfo.td updated: 1.76 -> 1.77
---
Log message:
move this over to the dag
---
Diffs of the changes: (+9 -10)
AlphaISelDAGToDAG.cpp |8
AlphaInstrInfo.td | 11 +--
2 files changed, 9 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.12
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.13
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.12Mon Dec 5 11:51:02 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Mon Dec 5 14:50:53 2005
@@ -247,14 +247,6 @@
CurDAG->getTargetExternalSymbol(cast(N)->getSymbol(),
MVT::i64),
getGlobalBaseReg());
- case ISD::CALLSEQ_START:
- case ISD::CALLSEQ_END: {
-unsigned Amt = cast(N->getOperand(1))->getValue();
-unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
- Alpha::ADJUSTSTACKDOWN : Alpha::ADJUSTSTACKUP;
-return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
-getI64Imm(Amt), Select(N->getOperand(0)));
- }
case ISD::RET: {
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
SDOperand InFlag;
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.76
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.77
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.76Wed Nov 30 11:11:20 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Mon Dec 5 14:50:53 2005
@@ -26,6 +26,11 @@
def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_", SDTFPUnaryOp, []>;
+// These are target-independent nodes, but have target-specific formats.
+def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
+def callseq_start : SDNode<"ISD::CALLSEQ_START",
SDT_AlphaCallSeq,[SDNPHasChain]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END",
SDT_AlphaCallSeq,[SDNPHasChain]>;
+
//
//Paterns for matching
@@ -99,8 +104,10 @@
[(set F8RC:$RA, (undef))]>;
def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf", []>;
-def ADJUSTSTACKUP : PseudoInstAlpha<(ops variable_ops), "ADJUP", []>;
-def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops variable_ops), "ADJDOWN", []>;
+def ADJUSTSTACKUP : PseudoInstAlpha<(ops s64imm:$amt), "ADJUP",
+[(callseq_start imm:$amt)]>;
+def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops s64imm:$amt), "ADJDOWN",
+[(callseq_end imm:$amt)]>;
def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$TARGET:\n", []>;
def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n",[]>;
def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k,
s64imm:$m),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.147 -> 1.148
---
Log message:
Remove unnecessary let hasCtrlDep=1 now it can be inferred.
---
Diffs of the changes: (+25 -27)
X86InstrInfo.td | 52 +---
1 files changed, 25 insertions(+), 27 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.147
llvm/lib/Target/X86/X86InstrInfo.td:1.148
--- llvm/lib/Target/X86/X86InstrInfo.td:1.147 Sun Dec 4 20:40:25 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Dec 5 17:09:43 2005
@@ -193,13 +193,13 @@
//
// Return instructions.
-let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep=1 in
+let isTerminator = 1, isReturn = 1, isBarrier = 1 in
def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
-let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep=1 in
+let isTerminator = 1, isReturn = 1, isBarrier = 1 in
def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
// All branches are RawFrm, Void, Branch, and Terminators
-let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in
+let isBranch = 1, isTerminator = 1 in
class IBr opcode, dag ops, string asm, list pattern> :
I;
@@ -332,30 +332,28 @@
def IN32ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
"in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
-let hasCtrlDep=1 in {
- def OUT8rr : I<0xEE, RawFrm, (ops),
- "out{b} {%al, %dx|%DX, %AL}",
- [(writeport AL, DX)]>, Imp<[DX, AL], []>;
- def OUT16rr : I<0xEF, RawFrm, (ops),
- "out{w} {%ax, %dx|%DX, %AX}",
- [(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize;
- def OUT32rr : I<0xEF, RawFrm, (ops),
- "out{l} {%eax, %dx|%DX, %EAX}",
- [(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
-
- def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
- "out{b} {%al, $port|$port, %AL}",
- [(writeport AL, (i16 immZExt8:$port))]>,
- Imp<[AL], []>;
- def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
- "out{w} {%ax, $port|$port, %AX}",
- [(writeport AX, (i16 immZExt8:$port))]>,
- Imp<[AX], []>, OpSize;
- def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
- "out{l} {%eax, $port|$port, %EAX}",
- [(writeport EAX, (i16 immZExt8:$port))]>,
- Imp<[EAX], []>;
-}
+def OUT8rr : I<0xEE, RawFrm, (ops),
+"out{b} {%al, %dx|%DX, %AL}",
+[(writeport AL, DX)]>, Imp<[DX, AL], []>;
+def OUT16rr : I<0xEF, RawFrm, (ops),
+"out{w} {%ax, %dx|%DX, %AX}",
+[(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize;
+def OUT32rr : I<0xEF, RawFrm, (ops),
+"out{l} {%eax, %dx|%DX, %EAX}",
+[(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
+
+def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
+ "out{b} {%al, $port|$port, %AL}",
+ [(writeport AL, (i16 immZExt8:$port))]>,
+ Imp<[AL], []>;
+def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
+ "out{w} {%ax, $port|$port, %AX}",
+ [(writeport AX, (i16 immZExt8:$port))]>,
+ Imp<[AX], []>, OpSize;
+def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
+ "out{l} {%eax, $port|$port, %EAX}",
+ [(writeport EAX, (i16 immZExt8:$port))]>,
+ Imp<[EAX], []>;
//===--===//
// Move Instructions...
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.84 -> 1.85
---
Log message:
* Infer instruction property hasCtrlDep from pattern if it has one.
* Fixed a bug related to hasCtrlDep property use.
---
Diffs of the changes: (+50 -31)
DAGISelEmitter.cpp | 81 -
1 files changed, 50 insertions(+), 31 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.84
llvm/utils/TableGen/DAGISelEmitter.cpp:1.85
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.84 Sun Dec 4 20:36:37 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Mon Dec 5 17:08:55 2005
@@ -1045,6 +1045,34 @@
}
}
+/// NodeHasChain - return true if TreePatternNode has the property
+/// 'hasChain', meaning it reads a ctrl-flow chain operand and writes
+/// a chain result.
+static bool NodeHasChain(TreePatternNode *N, DAGISelEmitter &ISE)
+{
+ if (N->isLeaf()) return false;
+ Record *Operator = N->getOperator();
+ if (!Operator->isSubClassOf("SDNode")) return false;
+
+ const SDNodeInfo &NodeInfo = ISE.getSDNodeInfo(Operator);
+ return NodeInfo.hasProperty(SDNodeInfo::SDNPHasChain);
+}
+
+static bool PatternHasCtrlDep(TreePatternNode *N, DAGISelEmitter &ISE)
+{
+ if (NodeHasChain(N, ISE))
+return true;
+ else {
+for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) {
+ TreePatternNode *Child = N->getChild(i);
+ if (PatternHasCtrlDep(Child, ISE))
+return true;
+}
+ }
+
+ return false;
+}
+
/// ParseInstructions - Parse all of the instructions, inlining and resolving
/// any fragments involved. This populates the Instructions list with fully
@@ -1228,7 +1256,7 @@
DAGInstruction &TheInst = II->second;
TreePattern *I = TheInst.getPattern();
if (I == 0) continue; // No pattern.
-
+
if (I->getNumTrees() != 1) {
std::cerr << "CANNOT HANDLE: " << I->getRecord()->getName() << " yet!";
continue;
@@ -1253,6 +1281,12 @@
TreePatternNode *DstPattern = TheInst.getResultPattern();
PatternsToMatch.push_back(std::make_pair(SrcPattern, DstPattern));
+
+if (PatternHasCtrlDep(Pattern, *this)) {
+ Record *Instr = II->first;
+ CodeGenInstruction &InstInfo = Target.getInstruction(Instr->getName());
+ InstInfo.hasCtrlDep = true;
+}
}
}
@@ -1602,17 +1636,6 @@
}
};
-/// nodeHasChain - return true if TreePatternNode has the property
-/// 'hasChain', meaning it reads a ctrl-flow chain operand and writes
-/// a chain result.
-static bool nodeHasChain(TreePatternNode *N, DAGISelEmitter &ISE)
-{
- if (N->isLeaf()) return false;
-
- const SDNodeInfo &NodeInfo = ISE.getSDNodeInfo(N->getOperator());
- return NodeInfo.hasProperty(SDNodeInfo::SDNPHasChain);
-}
-
/// EmitMatchForPattern - Emit a matcher for N, going to the label for
PatternNo
/// if the match fails. At this point, we already know that the opcode for N
/// matches, and the SDNode for the result has the RootName specified name.
@@ -1650,7 +1673,7 @@
// Emit code to load the child nodes and match their contents recursively.
- unsigned OpNo = (unsigned) nodeHasChain(N, *this);
+ unsigned OpNo = (unsigned) NodeHasChain(N, *this);
for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
OS << " SDOperand " << RootName << OpNo <<" = " << RootName
<< ".getOperand(" << OpNo << ");\n";
@@ -1735,19 +1758,16 @@
std::ostream &OS,
bool &HasChain) {
if (!N->isLeaf()) {
-Record *Op = N->getOperator();
-if (Op->isSubClassOf("Instruction")) {
- bool HasCtrlDep = Op->getValueAsBit("hasCtrlDep");
- unsigned OpNo = (unsigned) HasCtrlDep;
- for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
-EmitLeadChainForPattern(N->getChild(i), RootName + utostr(OpNo),
- OS, HasChain);
-
- if (!HasChain && HasCtrlDep) {
-OS << " SDOperand Chain = Select("
- << RootName << ".getOperand(0));\n";
-HasChain = true;
- }
+bool hc = NodeHasChain(N, *this);
+unsigned OpNo = (unsigned) hc;
+for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
+ EmitLeadChainForPattern(N->getChild(i), RootName + utostr(OpNo),
+ OS, HasChain);
+
+if (!HasChain && hc) {
+ OS << " SDOperand Chain = Select("
+ << RootName << ".getOperand(0));\n";
+ HasChain = true;
}
}
}
@@ -1759,7 +1779,7 @@
std::ostream &OS,
bool &HasChain, bool &InFlag) {
const CodeGenTarget &T = getTargetInfo();
- unsigned OpNo = (unsigned) nodeHasChain(N, *this);
+ unsigned OpNo = (unsigned) NodeHasChain(N, *this);
for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
TreePatternNod
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrFormats.td AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrFormats.td updated: 1.15 -> 1.16
AlphaInstrInfo.td updated: 1.77 -> 1.78
---
Log message:
These never trigger, but whatever
---
Diffs of the changes: (+40 -9)
AlphaInstrFormats.td | 18 ++
AlphaInstrInfo.td| 31 ++-
2 files changed, 40 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.15
llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.16
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.15 Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td Mon Dec 5 17:19:44 2005
@@ -171,6 +171,24 @@
let Inst{4-0} = Rc;
}
+class OForm4A opcode, bits<7> fun, string asmstr, list pattern>
+: InstAlphaAlt {
+ let Pattern = pattern;
+
+ bits<5> Rc;
+ bits<5> Rb;
+ bits<5> Ra;
+ bits<7> Function = fun;
+
+ let isTwoAddress = 1;
+ let Inst{25-21} = Ra;
+ let Inst{20-16} = Rb;
+ let Inst{15-13} = 0;
+ let Inst{12} = 0;
+ let Inst{11-5} = Function;
+ let Inst{4-0} = Rc;
+}
+
class OFormL opcode, bits<7> fun, string asmstr, list pattern>
: InstAlpha {
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.77
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.78
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.77Mon Dec 5 14:50:53 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Mon Dec 5 17:19:44 2005
@@ -148,24 +148,37 @@
//Operation Form:
//conditional moves, int
-def CMOVEQ : OForm4< 0x11, 0x24, "cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if
RCOND = zero
def CMOVEQi : OForm4L< 0x11, 0x24, "cmoveq $RCOND,$L,$RDEST">; //CMOVE if
RCOND = zero
-def CMOVGE : OForm4< 0x11, 0x46, "cmovge $RCOND,$RSRC,$RDEST">; //CMOVE if
RCOND >= zero
def CMOVGEi : OForm4L< 0x11, 0x46, "cmovge $RCOND,$L,$RDEST">; //CMOVE if
RCOND >= zero
-def CMOVGT : OForm4< 0x11, 0x66, "cmovgt $RCOND,$RSRC,$RDEST">; //CMOVE if
RCOND > zero
def CMOVGTi : OForm4L< 0x11, 0x66, "cmovgt $RCOND,$L,$RDEST">; //CMOVE if
RCOND > zero
-def CMOVLBC : OForm4< 0x11, 0x16, "cmovlbc $RCOND,$RSRC,$RDEST">; //CMOVE if
RCOND low bit clear
def CMOVLBCi : OForm4L< 0x11, 0x16, "cmovlbc $RCOND,$L,$RDEST">; //CMOVE if
RCOND low bit clear
-def CMOVLBS : OForm4< 0x11, 0x14, "cmovlbs $RCOND,$RSRC,$RDEST">; //CMOVE if
RCOND low bit set
def CMOVLBSi : OForm4L< 0x11, 0x14, "cmovlbs $RCOND,$L,$RDEST">; //CMOVE if
RCOND low bit set
-def CMOVLE : OForm4< 0x11, 0x64, "cmovle $RCOND,$RSRC,$RDEST">; //CMOVE if
RCOND <= zero
def CMOVLEi : OForm4L< 0x11, 0x64, "cmovle $RCOND,$L,$RDEST">; //CMOVE if
RCOND <= zero
-def CMOVLT : OForm4< 0x11, 0x44, "cmovlt $RCOND,$RSRC,$RDEST">; //CMOVE if
RCOND < zero
def CMOVLTi : OForm4L< 0x11, 0x44, "cmovlt $RCOND,$L,$RDEST">; //CMOVE if
RCOND < zero
-def CMOVNE : OForm4< 0x11, 0x26, "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if
RCOND != zero
def CMOVNEi : OForm4L< 0x11, 0x26, "cmovne $RCOND,$L,$RDEST">; //CMOVE if
RCOND != zero
-//FIXME: fold setcc with select
+let OperandList = (ops GPRC:$RDEST, GPRC:$RTRUE, GPRC:$RFALSE, GPRC:$RCOND) in
{
+def CMOVLBC : OForm4A< 0x11, 0x16, "cmovlbc $RCOND,$RFALSE,$RDEST",
+[(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RTRUE,
GPRC:$RFALSE))]>;
+def CMOVLBS : OForm4A< 0x11, 0x14, "cmovlbs $RCOND,$RFALSE,$RDEST",
+[(set GPRC:$RDEST, (select (and GPRC:$RCOND, 1), GPRC:$RTRUE,
GPRC:$RFALSE))]>;
+def CMOVEQ : OForm4A< 0x11, 0x24, "cmoveq $RCOND,$RFALSE,$RDEST",
+[(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
+def CMOVGE : OForm4A< 0x11, 0x46, "cmovge $RCOND,$RFALSE,$RDEST",
+[(set GPRC:$RDEST, (select (setge GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
+def CMOVGT : OForm4A< 0x11, 0x66, "cmovgt $RCOND,$RFALSE,$RDEST",
+[(set GPRC:$RDEST, (select (setgt GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
+def CMOVLE : OForm4A< 0x11, 0x64, "cmovle $RCOND,$RFALSE,$RDEST",
+[(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
+def CMOVLT : OForm4A< 0x11, 0x44, "cmovlt $RCOND,$RFALSE,$RDEST",
+[(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
+def CMOVNE : OForm4A< 0x11, 0x26, "cmovne $RCOND,$RFALSE,$RDEST",
+[(set GPRC:$RDEST, (select (setne GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
+}
+
+//FIXME: fold setcc with select for all cases. clearly I need patterns for
inverted conditions
+// and constants (which require inverted conditions as legalize puts the
constant in the
+// wrong field for the instruction definition
def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
(CMOVEQ GPRC:$src1, GPRC:$src2, GPRC:$which)>;
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrInfo.td updated: 1.78 -> 1.79
---
Log message:
yea, it helps to have your path set right when testing
---
Diffs of the changes: (+4 -2)
AlphaInstrInfo.td |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.78
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.79
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.78Mon Dec 5 17:19:44 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Mon Dec 5 17:41:45 2005
@@ -104,10 +104,12 @@
[(set F8RC:$RA, (undef))]>;
def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf", []>;
-def ADJUSTSTACKUP : PseudoInstAlpha<(ops s64imm:$amt), "ADJUP",
+let isLoad = 1, hasCtrlDep = 1 in {
+def ADJUSTSTACKUP : PseudoInstAlpha<(ops s64imm:$amt), "; ADJUP $amt",
[(callseq_start imm:$amt)]>;
-def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops s64imm:$amt), "ADJDOWN",
+def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops s64imm:$amt), "; ADJDOWN $amt",
[(callseq_end imm:$amt)]>;
+}
def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$TARGET:\n", []>;
def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n",[]>;
def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k,
s64imm:$m),
___
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrFormats.td AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrFormats.td updated: 1.16 -> 1.17
AlphaInstrInfo.td updated: 1.79 -> 1.80
---
Log message:
added instructions with inverted immediates
---
Diffs of the changes: (+23 -32)
AlphaInstrFormats.td | 18 +-
AlphaInstrInfo.td| 37 ++---
2 files changed, 23 insertions(+), 32 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.16
llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.17
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.16 Mon Dec 5 17:19:44 2005
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td Mon Dec 5 18:33:53 2005
@@ -155,23 +155,7 @@
let Inst{4-0} = Rc;
}
-class OForm4 opcode, bits<7> fun, string asmstr>
-: InstAlpha {
- bits<5> Rc;
- bits<5> Rb;
- bits<5> Ra;
- bits<7> Function = fun;
-
- let isTwoAddress = 1;
- let Inst{25-21} = Ra;
- let Inst{20-16} = Rb;
- let Inst{15-13} = 0;
- let Inst{12} = 0;
- let Inst{11-5} = Function;
- let Inst{4-0} = Rc;
-}
-
-class OForm4A opcode, bits<7> fun, string asmstr, list pattern>
+class OForm4 opcode, bits<7> fun, string asmstr, list pattern>
: InstAlphaAlt {
let Pattern = pattern;
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.79
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.80
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.79Mon Dec 5 17:41:45 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Mon Dec 5 18:33:53 2005
@@ -35,12 +35,19 @@
//
//Paterns for matching
//
-
+def invX : SDNodeXFormgetValue());
+}]>;
def immUExt8 : PatLeaf<(imm), [{
// immUExt8 predicate - True if the immediate fits in a 8-bit zero extended
// field. Used by instructions like 'addi'.
return (unsigned long)N->getValue() == (unsigned char)N->getValue();
}]>;
+def immUExt8inv : PatLeaf<(imm), [{
+ // immUExt8inv predicate - True if the inverted immediate fits in a 8-bit
zero extended
+ // field. Used by instructions like 'ornoti'.
+ return (unsigned long)~N->getValue() == (unsigned char)~N->getValue();
+}], invX>;
def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
// field. Used by instructions like 'lda'.
@@ -160,21 +167,21 @@
def CMOVNEi : OForm4L< 0x11, 0x26, "cmovne $RCOND,$L,$RDEST">; //CMOVE if
RCOND != zero
let OperandList = (ops GPRC:$RDEST, GPRC:$RTRUE, GPRC:$RFALSE, GPRC:$RCOND) in
{
-def CMOVLBC : OForm4A< 0x11, 0x16, "cmovlbc $RCOND,$RFALSE,$RDEST",
+def CMOVLBC : OForm4< 0x11, 0x16, "cmovlbc $RCOND,$RFALSE,$RDEST",
[(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RTRUE,
GPRC:$RFALSE))]>;
-def CMOVLBS : OForm4A< 0x11, 0x14, "cmovlbs $RCOND,$RFALSE,$RDEST",
+def CMOVLBS : OForm4< 0x11, 0x14, "cmovlbs $RCOND,$RFALSE,$RDEST",
[(set GPRC:$RDEST, (select (and GPRC:$RCOND, 1), GPRC:$RTRUE,
GPRC:$RFALSE))]>;
-def CMOVEQ : OForm4A< 0x11, 0x24, "cmoveq $RCOND,$RFALSE,$RDEST",
+def CMOVEQ : OForm4< 0x11, 0x24, "cmoveq $RCOND,$RFALSE,$RDEST",
[(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
-def CMOVGE : OForm4A< 0x11, 0x46, "cmovge $RCOND,$RFALSE,$RDEST",
+def CMOVGE : OForm4< 0x11, 0x46, "cmovge $RCOND,$RFALSE,$RDEST",
[(set GPRC:$RDEST, (select (setge GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
-def CMOVGT : OForm4A< 0x11, 0x66, "cmovgt $RCOND,$RFALSE,$RDEST",
+def CMOVGT : OForm4< 0x11, 0x66, "cmovgt $RCOND,$RFALSE,$RDEST",
[(set GPRC:$RDEST, (select (setgt GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
-def CMOVLE : OForm4A< 0x11, 0x64, "cmovle $RCOND,$RFALSE,$RDEST",
+def CMOVLE : OForm4< 0x11, 0x64, "cmovle $RCOND,$RFALSE,$RDEST",
[(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
-def CMOVLT : OForm4A< 0x11, 0x44, "cmovlt $RCOND,$RFALSE,$RDEST",
+def CMOVLT : OForm4< 0x11, 0x44, "cmovlt $RCOND,$RFALSE,$RDEST",
[(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
-def CMOVNE : OForm4A< 0x11, 0x26, "cmovne $RCOND,$RFALSE,$RDEST",
+def CMOVNE : OForm4< 0x11, 0x26, "cmovne $RCOND,$RFALSE,$RDEST",
[(set GPRC:$RDEST, (select (setne GPRC:$RCOND, 0),
GPRC:$RTRUE, GPRC:$RFALSE))]>;
}
@@ -199,8 +206,8 @@
[(set GPRC:$RC, (and GPRC:$RA, immUExt8:$L))]>;
def BIC : OForm< 0x11, 0x08, "bic $RA,$RB,$RC",
[(set GPRC:$RC, (and GPRC:$RA, (not GPRC:$RB)))]>;
-def BICi : OFormL<0x11, 0x08, "bic $RA,$L,$RC", []>;
-// [(set GPRC:$RC, (and GPRC:$RA, (not immUExt8:$L)))]>;
//FIXME?
+def BICi : OFormL<0x11, 0x08, "bic $RA,$L,$RC",
+ [(set GPRC:$RC, (and GPRC:$RA, immUExt8inv:$L))]>;
def BIS
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.48 -> 1.49
PPCISelLowering.h updated: 1.10 -> 1.11
PPCInstrInfo.td updated: 1.151 -> 1.152
---
Log message:
Use new PPC-specific nodes to represent shifts which require the 6-bit
amount handling that PPC provides. These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits. This fixes a miscompilation of crafty with
the new front-end.
---
Diffs of the changes: (+40 -15)
PPCISelLowering.cpp | 24
PPCISelLowering.h |6 ++
PPCInstrInfo.td | 25 ++---
3 files changed, 40 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.48
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.49
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.48Wed Nov 30 14:40:54 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Dec 5 20:10:38 2005
@@ -279,14 +279,14 @@
SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
DAG.getConstant(32, MVT::i32), Amt);
-SDOperand Tmp2 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Amt);
-SDOperand Tmp3 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Tmp1);
+SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
+SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
DAG.getConstant(-32U, MVT::i32));
-SDOperand Tmp6 = DAG.getNode(ISD::SHL, MVT::i32, Lo, Tmp5);
+SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
-SDOperand OutLo = DAG.getNode(ISD::SHL, MVT::i32, Lo, Amt);
+SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
}
case ISD::SRL: {
@@ -305,14 +305,14 @@
SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
DAG.getConstant(32, MVT::i32), Amt);
-SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
-SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
+SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
+SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
DAG.getConstant(-32U, MVT::i32));
-SDOperand Tmp6 = DAG.getNode(ISD::SRL, MVT::i32, Hi, Tmp5);
+SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
-SDOperand OutHi = DAG.getNode(ISD::SRL, MVT::i32, Hi, Amt);
+SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
}
case ISD::SRA: {
@@ -330,13 +330,13 @@
SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
DAG.getConstant(32, MVT::i32), Amt);
-SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
-SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
+SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
+SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
DAG.getConstant(-32U, MVT::i32));
-SDOperand Tmp6 = DAG.getNode(ISD::SRA, MVT::i32, Hi, Tmp5);
-SDOperand OutHi = DAG.getNode(ISD::SRA, MVT::i32, Hi, Amt);
+SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
+SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
Tmp4, Tmp6, ISD::SETLE);
return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.10
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.11
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.10 Thu Nov 17 01:30:41 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Mon Dec 5 20:10:38 2005
@@ -49,6 +49,12 @@
/// GlobalBaseReg - On Darwin, this node represents the result of the
mflr
/// at function entry, used for PIC code.
GlobalBaseReg,
+
+
+ /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
+ /// shift amounts. These nodes are generated by the multi-precision
shift
+ /// code.
+ SRL, SRA, SHL,
};
}
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/Power
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.222 -> 1.223
SelectionDAG.cpp updated: 1.222 -> 1.223
SelectionDAGISel.cpp updated: 1.110 -> 1.111
---
Log message:
Teach the SelectionDAG ISel how to turn ConstantPacked values into
constant nodes with vector types. Also teach the asm printer how to print
ConstantPacked constant pool entries. This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.
LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
.space 4
.space 4
.space 4
.long 1065353216 ; float 1
.text
.align 4
.globl _foo
_foo:
lis r2, ha16(LCPI1_0)
la r2, lo16(LCPI1_0)(r2)
li r4, 0
lvx v0, r4, r2
lvx v1, r4, r3
vaddfp v0, v1, v0
stvx v0, r4, r3
blr
For the llvm code:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
---
Diffs of the changes: (+54 -5)
LegalizeDAG.cpp | 26 ++
SelectionDAG.cpp |3 +--
SelectionDAGISel.cpp | 30 +++---
3 files changed, 54 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.222
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.223
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.222 Fri Dec 2 00:08:08 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Dec 6 00:18:55 2005
@@ -690,6 +690,32 @@
}
break;
}
+ case ISD::ConstantVec: {
+// We assume that vector constants are not legal, and will be immediately
+// spilled to the constant pool.
+//
+// FIXME: revisit this when we have some kind of mechanism by which targets
+// can decided legality of vector constants, of which there may be very
+// many.
+//
+// Create a ConstantPacked, and put it in the constant pool.
+std::vector CV;
+MVT::ValueType VT = Node->getValueType(0);
+for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) {
+ SDOperand OpN = Node->getOperand(I);
+ const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType());
+ if (MVT::isFloatingPoint(VT))
+CV.push_back(ConstantFP::get(OpNTy,
+ cast(OpN)->getValue()));
+ else
+CV.push_back(ConstantUInt::get(OpNTy,
+ cast(OpN)->getValue()));
+}
+Constant *CP = ConstantPacked::get(CV);
+SDOperand CPIdx = DAG.getConstantPool(CP, Node->getValueType(0));
+Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
+break;
+ }
case ISD::TokenFactor:
if (Node->getNumOperands() == 2) {
bool Changed = false;
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.222
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.223
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.222Thu Dec 1
17:14:50 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Dec 6 00:18:55 2005
@@ -501,8 +501,6 @@
return SDOperand(N, 0);
}
-
-
SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV,
MVT::ValueType VT, int offset) {
SDNode *&N = GlobalValues[std::make_pair(GV, offset)];
@@ -1837,6 +1835,7 @@
case ISD::Constant: return "Constant";
case ISD::TargetConstant: return "TargetConstant";
case ISD::ConstantFP:return "ConstantFP";
+ case ISD::ConstantVec: return "ConstantVec";
case ISD::GlobalAddress: return "GlobalAddress";
case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
case ISD::FrameIndex:return "FrameIndex";
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.110
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.111
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.110Mon Dec 5
01:10:48 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Dec 6 00:18:55 2005
@@ -282,7 +282,8 @@
SDOperand &N = NodeMap[V];
if (N.Val) return N;
-MVT::ValueType VT = TLI.getValueType(V->getType());
+const Type *VTy = V->getType();
+MVT::ValueType VT = TLI.getValueType(VTy);
if (Constant *C = const_cast(dyn_cast(V)))
if (ConstantExpr *CE = dyn_cast(C)) {
visit(CE->getOpcode(), *CE);
@@ -296,6 +297,30 @@
return N = DAG.getNode(ISD::UNDEF, VT);
} else if (ConstantFP *CFP = dyn_cast(C)) {
return N = DAG.getConstantFP(CFP->getValue(), VT);
+ } else if (const PackedType *PTy = dyn_cast(VTy)) {
+unsigned NumElements = PTy->getNumElements();
+MVT::Val
[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAGNodes.h updated: 1.80 -> 1.81
---
Log message:
Teach the SelectionDAG ISel how to turn ConstantPacked values into
constant nodes with vector types. Also teach the asm printer how to print
ConstantPacked constant pool entries. This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.
LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
.space 4
.space 4
.space 4
.long 1065353216 ; float 1
.text
.align 4
.globl _foo
_foo:
lis r2, ha16(LCPI1_0)
la r2, lo16(LCPI1_0)(r2)
li r4, 0
lvx v0, r4, r2
lvx v1, r4, r3
vaddfp v0, v1, v0
stvx v0, r4, r3
blr
For the llvm code:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
---
Diffs of the changes: (+4 -0)
SelectionDAGNodes.h |4
1 files changed, 4 insertions(+)
Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.80
llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.81
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.80 Tue Nov 29 20:04:11 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Tue Dec 6 00:18:55 2005
@@ -67,6 +67,10 @@
GlobalAddress, FrameIndex, ConstantPool,
BasicBlock, ExternalSymbol, VALUETYPE, CONDCODE, Register,
+// ConstantVec works like Constant or ConstantFP, except that it is not a
+// leaf node. All operands are either Constant or ConstantFP nodes.
+ConstantVec,
+
// TargetConstant - Like Constant, but the DAG does not do any folding or
// simplification of the constant. This is used by the DAG->DAG selector.
TargetConstant,
___
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[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.29 -> 1.30
---
Log message:
Teach the SelectionDAG ISel how to turn ConstantPacked values into
constant nodes with vector types. Also teach the asm printer how to print
ConstantPacked constant pool entries. This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.
LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
.space 4
.space 4
.space 4
.long 1065353216 ; float 1
.text
.align 4
.globl _foo
_foo:
lis r2, ha16(LCPI1_0)
la r2, lo16(LCPI1_0)(r2)
li r4, 0
lvx v0, r4, r2
lvx v1, r4, r3
vaddfp v0, v1, v0
stvx v0, r4, r3
blr
For the llvm code:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
---
Diffs of the changes: (+8 -0)
AsmPrinter.cpp |8
1 files changed, 8 insertions(+)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.29
llvm/lib/CodeGen/AsmPrinter.cpp:1.30
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.29Mon Nov 21 02:25:09 2005
+++ llvm/lib/CodeGen/AsmPrinter.cpp Tue Dec 6 00:18:55 2005
@@ -11,6 +11,7 @@
//
//===--===//
+#include "llvm/DerivedTypes.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/Constants.h"
#include "llvm/Module.h"
@@ -326,6 +327,13 @@
}
return;
}
+ } else if (const ConstantPacked *CP = dyn_cast(CV)) {
+const PackedType *PTy = CP->getType();
+
+for (unsigned I = 0, E = PTy->getNumElements(); I < E; ++I)
+ EmitGlobalConstant(CP->getOperand(I));
+
+return;
}
const Type *type = CV->getType();
___
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[llvm-commits] CVS: llvm/include/llvm/ADT/PostOrderIterator.h
Changes in directory llvm/include/llvm/ADT:
PostOrderIterator.h updated: 1.18 -> 1.19
---
Log message:
Implement external storage for post-order iteration, implementing PR267:
http://llvm.cs.uiuc.edu/PR267
Patch by Saem Ghani, thanks!
---
Diffs of the changes: (+84 -10)
PostOrderIterator.h | 94 ++--
1 files changed, 84 insertions(+), 10 deletions(-)
Index: llvm/include/llvm/ADT/PostOrderIterator.h
diff -u llvm/include/llvm/ADT/PostOrderIterator.h:1.18
llvm/include/llvm/ADT/PostOrderIterator.h:1.19
--- llvm/include/llvm/ADT/PostOrderIterator.h:1.18 Thu Apr 21 22:25:01 2005
+++ llvm/include/llvm/ADT/PostOrderIterator.h Tue Dec 6 01:05:27 2005
@@ -23,8 +23,26 @@
namespace llvm {
-template >
-class po_iterator : public forward_iterator {
+template // Non-external set
+class po_iterator_storage {
+public:
+ SetType Visited;
+};
+
+template
+class po_iterator_storage {
+public:
+ po_iterator_storage(SetType &VSet) : Visited(VSet) {}
+ po_iterator_storage(const po_iterator_storage &S) : Visited(S.Visited) {}
+ SetType &Visited;
+};
+
+template::NodeType*>,
+bool ExtStorage = false,
+class GT = GraphTraits >
+class po_iterator : public forward_iterator,
+public po_iterator_storage {
typedef forward_iterator super;
typedef typename GT::NodeType NodeType;
typedef typename GT::ChildIteratorType ChildItTy;
@@ -37,27 +55,45 @@
void traverseChild() {
while (VisitStack.top().second != GT::child_end(VisitStack.top().first)) {
NodeType *BB = *VisitStack.top().second++;
- if (!Visited.count(BB)) { // If the block is not visited...
-Visited.insert(BB);
+ if (!this->Visited.count(BB)) { // If the block is not visited...
+this->Visited.insert(BB);
VisitStack.push(std::make_pair(BB, GT::child_begin(BB)));
}
}
}
inline po_iterator(NodeType *BB) {
-Visited.insert(BB);
+this->Visited.insert(BB);
VisitStack.push(std::make_pair(BB, GT::child_begin(BB)));
traverseChild();
}
- inline po_iterator() { /* End is when stack is empty */ }
+ inline po_iterator() {} // End is when stack is empty.
+
+ inline po_iterator(NodeType *BB, SetType &S) :
+po_iterator_storage(&S) {
+if(!S.count(BB)) {
+ this->Visited.insert(BB);
+ VisitStack.push(std::make_pair(BB, GT::child_begin(BB)));
+ traverseChild();
+}
+ }
+
+ inline po_iterator(SetType &S) :
+ po_iterator_storage(&S) {
+ } // End is when stack is empty.
public:
typedef typename super::pointer pointer;
- typedef po_iterator _Self;
+ typedef po_iterator _Self;
// Provide static "constructors"...
static inline _Self begin(GraphT G) { return _Self(GT::getEntryNode(G)); }
static inline _Self end (GraphT G) { return _Self(); }
+ static inline _Self begin(GraphT G, SetType &S) {
+return _Self(GT::getEntryNode(G), S);
+ }
+ static inline _Self end (GraphT G, SetType &S) { return _Self(S); }
+
inline bool operator==(const _Self& x) const {
return VisitStack == x.VisitStack;
}
@@ -92,10 +128,30 @@
template
po_iterator po_end (T G) { return po_iterator::end(G); }
+// Provide global definitions of external postorder iterators...
+template::NodeType*> >
+struct po_ext_iterator : public po_iterator {
+ po_ext_iterator(const po_iterator &V) :
+ po_iterator(V) {}
+};
+
+template
+po_ext_iterator po_ext_begin(T G, SetType &S) {
+ return po_ext_iterator::begin(G, S);
+}
+
+template
+po_ext_iterator po_ext_end(T G, SetType &S) {
+ return po_ext_iterator::end(G, S);
+}
+
// Provide global definitions of inverse post order iterators...
-template
-struct ipo_iterator : public po_iterator > {
- ipo_iterator(const po_iterator > &V) :po_iterator
>(V){}
+template ::NoddeType*>,
+ bool External = false>
+struct ipo_iterator : public po_iterator, SetType, External > {
+ ipo_iterator(const po_iterator, SetType, External> &V) :
+ po_iterator, SetType, External> (V) {}
};
template
@@ -108,6 +164,24 @@
return ipo_iterator::end(G);
}
+//Provide global definitions of external inverse postorder iterators...
+template ::NodeType*> >
+struct ipo_ext_iterator : public ipo_iterator {
+ ipo_ext_iterator(const ipo_iterator &V) :
+ipo_iterator(&V) {}
+ ipo_ext_iterator(const po_iterator, SetType, true> &V) :
+ipo_iterator(&V) {}
+};
+
+template
+ipo_ext_iterator ipo_ext_begin(T G, SetType &S) {
+ return ipo_ext_iterator::begin(G, S);
+}
+
+template
+ipo_ext_iterator ipo_ext_end(T G, SetType &S) {
+ return ipo_ext_iterator::end(G, S);
+}
//======//
// Reverse Post Order CFG iterator code
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