[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.38 -> 1.39
---
Log message:
1. Embed and not inherit vector for NodeGroup.
2. Iterate operands and not uses (performance.)
3. Some long pending comment changes.
---
Diffs of the changes: (+39 -20)
ScheduleDAG.cpp | 59 +---
1 files changed, 39 insertions(+), 20 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.38
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.39
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.38 Sun Oct 30 12:54:27 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Mon Oct 31 06:49:09 2005
@@ -2,7 +2,7 @@
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Chris Lattner and is distributed under the
+// This file was developed by James M. Laskey and is distributed under the
// University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===--===//
@@ -192,15 +192,17 @@
// Forward
class NodeInfo;
-typedef std::vector NIVector;
-typedef std::vector::iterator NIIterator;
+typedef NodeInfo *NodeInfoPtr;
+typedef std::vector NIVector;
+typedef std::vector::iterator NIIterator;
//===--===//
///
/// Node group - This struct is used to manage flagged node groups.
///
-class NodeGroup : public NIVector {
+class NodeGroup {
private:
+ NIVector Members;// Group member nodes
int Pending;// Number of visits pending before
//adding to order
@@ -209,10 +211,24 @@
NodeGroup() : Pending(0) {}
// Accessors
- inline NodeInfo *getLeader() { return empty() ? NULL : front(); }
+ inline NodeInfo *getLeader() {
+return Members.empty() ? NULL : Members.front();
+ }
inline int getPending() const { return Pending; }
inline void setPending(int P) { Pending = P; }
inline int addPending(int I) { return Pending += I; }
+
+ // Pass thru
+ inline bool group_empty() { return Members.empty(); }
+ inline NIIterator group_begin() { return Members.begin(); }
+ inline NIIterator group_end() { return Members.end(); }
+ inline void group_push_back(const NodeInfoPtr &NI) { Members.push_back(NI); }
+ inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr &NI) {
+return Members.insert(Pos, NI);
+ }
+ inline void group_insert(NIIterator Pos, NIIterator First, NIIterator Last) {
+Members.insert(Pos, First, Last);
+ }
static void Add(NodeInfo *D, NodeInfo *U);
static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U);
@@ -257,7 +273,7 @@
// Accessors
inline bool isInGroup() const {
-assert(!Group || !Group->empty() && "Group with no members");
+assert(!Group || !Group->group_empty() && "Group with no members");
return Group != NULL;
}
inline bool isGroupLeader() const {
@@ -298,8 +314,8 @@
if (N->isInGroup()) {
// get Group
NodeGroup *Group = NI->Group;
- NGI = Group->begin();
- NGE = Group->end();
+ NGI = Group->group_begin();
+ NGE = Group->group_end();
// Prevent this node from being used (will be in members list
NI = NULL;
}
@@ -491,7 +507,8 @@
}
}
// Merge the two lists
-DGroup->insert(DGroup->end(), UGroup->begin(), UGroup->end());
+DGroup->group_insert(DGroup->group_end(),
+ UGroup->group_begin(), UGroup->group_end());
} else if (DGroup) {
// Make user member of definers group
U->Group = DGroup;
@@ -503,7 +520,7 @@
// Remove internal edges
DGroup->addPending(-CountInternalUses(DNI, U));
}
-DGroup->push_back(U);
+DGroup->group_push_back(U);
} else if (UGroup) {
// Make definer member of users group
D->Group = UGroup;
@@ -515,13 +532,13 @@
// Remove internal edges
UGroup->addPending(-CountInternalUses(D, UNI));
}
-UGroup->insert(UGroup->begin(), D);
+UGroup->group_insert(UGroup->group_begin(), D);
} else {
D->Group = U->Group = DGroup = new NodeGroup();
DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
CountInternalUses(D, U));
-DGroup->push_back(D);
-DGroup->push_back(U);
+DGroup->group_push_back(D);
+DGroup->group_push_back(U);
}
}
@@ -529,10 +546,11 @@
///
unsigned NodeGroup::CountInternalUses(NodeInfo *D, NodeInfo *U) {
unsigned N = 0;
- for (SDNode:: use_iterator UI = D->Node->use_begin(),
- E = D->Node->use_end(); UI != E; UI++) {
-if (*UI == U->Node) N++;
+ for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
+SDOperand Op = U->Node->getOperand(M);
+if (Op.Val == D->N
[llvm-commits] CVS: llvm/test/Regression/Archive/ranlib_GNU.ll ranlib_SVR4.ll ranlib_xpg4.ll
Changes in directory llvm/test/Regression/Archive: ranlib_GNU.ll updated: 1.6 -> 1.7 ranlib_SVR4.ll updated: 1.6 -> 1.7 ranlib_xpg4.ll updated: 1.6 -> 1.7 --- Log message: these tests fail on alpha for some reason --- Diffs of the changes: (+6 -0) ranlib_GNU.ll |2 ++ ranlib_SVR4.ll |2 ++ ranlib_xpg4.ll |2 ++ 3 files changed, 6 insertions(+) Index: llvm/test/Regression/Archive/ranlib_GNU.ll diff -u llvm/test/Regression/Archive/ranlib_GNU.ll:1.6 llvm/test/Regression/Archive/ranlib_GNU.ll:1.7 --- llvm/test/Regression/Archive/ranlib_GNU.ll:1.6 Sat Nov 27 00:44:10 2004 +++ llvm/test/Regression/Archive/ranlib_GNU.ll Mon Oct 31 10:15:49 2005 @@ -5,3 +5,5 @@ ;RUN: llvm-ranlib %t.GNU.a ;RUN: llvm-ar t %t.GNU.a > %t1 ;RUN: diff %t1 %p/GNU.toc + +; XFAIL: alpha Index: llvm/test/Regression/Archive/ranlib_SVR4.ll diff -u llvm/test/Regression/Archive/ranlib_SVR4.ll:1.6 llvm/test/Regression/Archive/ranlib_SVR4.ll:1.7 --- llvm/test/Regression/Archive/ranlib_SVR4.ll:1.6 Sat Nov 27 00:44:10 2004 +++ llvm/test/Regression/Archive/ranlib_SVR4.ll Mon Oct 31 10:15:49 2005 @@ -5,3 +5,5 @@ ;RUN: llvm-ranlib %t.SVR4.a ;RUN: llvm-ar t %t.SVR4.a > %t1 ;RUN: diff %t1 %p/SVR4.toc + +; XFAIL: alpha Index: llvm/test/Regression/Archive/ranlib_xpg4.ll diff -u llvm/test/Regression/Archive/ranlib_xpg4.ll:1.6 llvm/test/Regression/Archive/ranlib_xpg4.ll:1.7 --- llvm/test/Regression/Archive/ranlib_xpg4.ll:1.6 Sat Nov 27 00:44:10 2004 +++ llvm/test/Regression/Archive/ranlib_xpg4.ll Mon Oct 31 10:15:49 2005 @@ -5,3 +5,5 @@ ;RUN: llvm-ranlib %t.xpg4.a ;RUN: llvm-ar t %t.xpg4.a > %t1 ;RUN: diff %t1 %p/xpg4.toc + +; XFAIL: alpha ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/SubtargetEmitter.h SubtargetEmitter.cpp
Changes in directory llvm/utils/TableGen:
SubtargetEmitter.h updated: 1.5 -> 1.6
SubtargetEmitter.cpp updated: 1.11 -> 1.12
---
Log message:
Generate cpu to itinerary map.
---
Diffs of the changes: (+63 -8)
SubtargetEmitter.cpp | 68 +--
SubtargetEmitter.h |3 +-
2 files changed, 63 insertions(+), 8 deletions(-)
Index: llvm/utils/TableGen/SubtargetEmitter.h
diff -u llvm/utils/TableGen/SubtargetEmitter.h:1.5
llvm/utils/TableGen/SubtargetEmitter.h:1.6
--- llvm/utils/TableGen/SubtargetEmitter.h:1.5 Fri Oct 28 16:47:29 2005
+++ llvm/utils/TableGen/SubtargetEmitter.h Mon Oct 31 11:16:01 2005
@@ -38,8 +38,9 @@
void EmitStageData(std::ostream &OS, unsigned NItinClasses,
std::map &ItinClassesMap,
std::vector > &ProcList);
- void EmitProcessData(std::ostream &OS,
+ void EmitProcessorData(std::ostream &OS,
std::vector > &ProcList);
+ void EmitProcessorLookup(std::ostream &OS);
void EmitData(std::ostream &OS);
void ParseFeaturesFunction(std::ostream &OS);
Index: llvm/utils/TableGen/SubtargetEmitter.cpp
diff -u llvm/utils/TableGen/SubtargetEmitter.cpp:1.11
llvm/utils/TableGen/SubtargetEmitter.cpp:1.12
--- llvm/utils/TableGen/SubtargetEmitter.cpp:1.11 Fri Oct 28 17:49:02 2005
+++ llvm/utils/TableGen/SubtargetEmitter.cppMon Oct 31 11:16:01 2005
@@ -7,7 +7,8 @@
//
//===--===//
//
-// This tablegen backend emits subtarget enumerations.
+// This tablegen backend emits subtarget enumerations. The format is in a
state
+// flux and will be tightened up when integration to scheduling is complete.
//
//===--===//
@@ -62,7 +63,7 @@
// If bit flags then emit expression (1 << i)
if (isBits) OS << " = " << " 1 << " << i;
-// Depending on if more in the list emit comma
+// Depending on 'if more in the list' emit comma
if (++i < N) OS << ",";
OS << "\n";
@@ -102,7 +103,7 @@
<< Name
<< " }";
-// Depending on if more in the list emit comma
+// Depending on 'if more in the list' emit comma
if (++i < N) OS << ",";
OS << "\n";
@@ -158,7 +159,7 @@
OS << " }";
-// Depending on if more in the list emit comma
+// Depending on 'if more in the list' emit comma
if (++i < N) OS << ",";
OS << "\n";
@@ -315,9 +316,9 @@
}
//
-// EmitProcessData - Generate data for processor itineraries.
+// EmitProcessorData - Generate data for processor itineraries.
//
-void SubtargetEmitter::EmitProcessData(std::ostream &OS,
+void SubtargetEmitter::EmitProcessorData(std::ostream &OS,
std::vector > &ProcList) {
// Get an iterator for processor itinerary stages
std::vector >::iterator
@@ -362,6 +363,54 @@
// End processor itinerary table
OS << "};\n";
}
+
+OS << "\n";
+OS << "static llvm::InstrItinerary NoItineraries[] = {};\n";
+}
+
+//
+// EmitProcessorLookup - generate cpu name to itinerary lookup table.
+//
+void SubtargetEmitter::EmitProcessorLookup(std::ostream &OS) {
+ // Gather and sort processor information
+ std::vector ProcessorList =
+ Records.getAllDerivedDefinitions("Processor");
+ sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
+
+ // Begin processor table
+ OS << "\n";
+ OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
+ << "static const llvm::SubtargetInfoKV SubTypeInfoKV[] = {\n";
+
+ // For each processor
+ for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
+// Next processor
+Record *Processor = ProcessorList[i];
+
+std::string Name = Processor->getValueAsString("Name");
+std::string ProcItin = Processor->getValueAsDef("ProcItin")->getName();
+
+// Emit as { "cpu", procinit },
+OS << " { "
+ << "\"" << Name << "\", "
+ << "(void *)&" << ProcItin;
+
+OS << " }";
+
+// Depending on ''if more in the list'' emit comma
+if (++i < N) OS << ",";
+
+OS << "\n";
+ }
+
+ // End processor table
+ OS << "};\n";
+
+ // Emit size of table
+ OS<<"\nenum {\n";
+ OS<<" SubTypeInfoKVSize = sizeof(SubTypeInfoKV)/"
+"sizeof(llvm::SubtargetInfoKV)\n";
+ OS<<"};\n";
}
//
@@ -376,7 +425,9 @@
// Emit the stage data
EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList);
// Emit the processor itinerary data
- EmitProcessData(OS, ProcList);
+ EmitProcessorData(OS, ProcList);
+ // Emit the processor lookup data
+ EmitProcessorLookup(OS);
}
//
@@ -409,6 +460,9 @@
OS << " " << Attribute << " = (Bits & " << Instance << ") != 0;\n";
}
+ OS << "\n"
+ << " InstrItinerary *Itin = (InstrItinerary *)"
+"Features.getInfo(SubTypeInfoKV,
SubTyp
[llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp InstrInfoEmitter.h
Changes in directory llvm/utils/TableGen:
InstrInfoEmitter.cpp updated: 1.29 -> 1.30
InstrInfoEmitter.h updated: 1.11 -> 1.12
---
Log message:
Emit itinerary class in instruction info.
---
Diffs of the changes: (+39 -2)
InstrInfoEmitter.cpp | 34 +-
InstrInfoEmitter.h |7 ++-
2 files changed, 39 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.29
llvm/utils/TableGen/InstrInfoEmitter.cpp:1.30
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.29 Fri Oct 28 17:59:53 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.cppMon Oct 31 11:16:46 2005
@@ -76,6 +76,8 @@
// run - Emit the main instruction description records for the target...
void InstrInfoEmitter::run(std::ostream &OS) {
+ GatherItinClasses();
+
EmitSourceFileHeader("Target Instruction Descriptors", OS);
OS << "namespace llvm {\n\n";
@@ -168,7 +170,13 @@
OS << Inst.TheDef->getName();
else
OS << Inst.Name;
- OS << "\",\t" << NumOperands << ", -1, 0, false, 0, 0, 0, 0";
+
+ unsigned ItinClass = !IsItineraries ? 0 :
+
ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
+
+ OS << "\",\t" << NumOperands << ", -1, 0, false, 0, 0, "
+ << ItinClass
+ << ", 0";
// Emit all of the target indepedent flags...
if (Inst.isReturn) OS << "|M_RET_FLAG";
@@ -222,6 +230,30 @@
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
+struct LessRecord {
+ bool operator()(const Record *Rec1, const Record *Rec2) const {
+return Rec1->getName() < Rec2->getName();
+ }
+};
+void InstrInfoEmitter::GatherItinClasses() {
+ std::vector DefList =
+ Records.getAllDerivedDefinitions("InstrItinClass");
+ IsItineraries = !DefList.empty();
+
+ if (!IsItineraries) return;
+
+ sort(DefList.begin(), DefList.end(), LessRecord());
+
+ for (unsigned i = 0, N = DefList.size(); i < N; i++) {
+Record *Def = DefList[i];
+ItinClassMap[Def->getName()] = i + 1;
+ }
+}
+
+unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
+ return ItinClassMap[ItinName];
+}
+
void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
IntInit *ShiftInt, std::ostream &OS) {
if (Val == 0 || ShiftInt == 0)
Index: llvm/utils/TableGen/InstrInfoEmitter.h
diff -u llvm/utils/TableGen/InstrInfoEmitter.h:1.11
llvm/utils/TableGen/InstrInfoEmitter.h:1.12
--- llvm/utils/TableGen/InstrInfoEmitter.h:1.11 Fri Oct 28 17:59:53 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.h Mon Oct 31 11:16:46 2005
@@ -28,8 +28,11 @@
class InstrInfoEmitter : public TableGenBackend {
RecordKeeper &Records;
+ bool IsItineraries;
+ std::map ItinClassMap;
+
public:
- InstrInfoEmitter(RecordKeeper &R) : Records(R) {}
+ InstrInfoEmitter(RecordKeeper &R) : Records(R), IsItineraries(false) {}
// run - Output the instruction set description, returning true on failure.
void run(std::ostream &OS);
@@ -44,6 +47,8 @@
std::map, unsigned> &EL,
std::map, unsigned> &OpInfo,
std::ostream &OS);
+ void GatherItinClasses();
+ unsigned ItinClassNumber(std::string ItinName);
void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift,
std::ostream &OS);
};
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.401 -> 1.402
---
Log message:
Limit the search depth of MaskedValueIsZero to 6 instructions, to avoid
bad cases. This fixes Markus's second testcase in PR639:
http://llvm.cs.uiuc.edu/PR639 , and should
seal it for good.
---
Diffs of the changes: (+14 -10)
InstructionCombining.cpp | 24 ++--
1 files changed, 14 insertions(+), 10 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.401
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.402
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.401 Fri Oct 28
23:36:15 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Oct 31 12:35:52 2005
@@ -389,7 +389,8 @@
/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
/// this predicate to simplify operations downstream. V and Mask are known to
/// be the same type.
-static bool MaskedValueIsZero(Value *V, ConstantIntegral *Mask) {
+static bool MaskedValueIsZero(Value *V, ConstantIntegral *Mask,
+ unsigned Depth = 0) {
// Note, we cannot consider 'undef' to be "IsZero" here. The problem is that
// we cannot optimize based on the assumption that it is zero without
changing
// to to an explicit zero. If we don't change it to zero, other code could
@@ -400,6 +401,8 @@
return true;
if (ConstantIntegral *CI = dyn_cast(V))
return ConstantExpr::getAnd(CI, Mask)->isNullValue();
+
+ if (Depth == 6) return false; // Limit search depth.
if (Instruction *I = dyn_cast(V)) {
switch (I->getOpcode()) {
@@ -408,21 +411,21 @@
if (ConstantIntegral *CI = dyn_cast(I->getOperand(1)))
{
ConstantIntegral *C1C2 =
cast(ConstantExpr::getAnd(CI, Mask));
-if (MaskedValueIsZero(I->getOperand(0), C1C2))
+if (MaskedValueIsZero(I->getOperand(0), C1C2, Depth+1))
return true;
}
// If either the LHS or the RHS are MaskedValueIsZero, the result is
zero.
- return MaskedValueIsZero(I->getOperand(1), Mask) ||
- MaskedValueIsZero(I->getOperand(0), Mask);
+ return MaskedValueIsZero(I->getOperand(1), Mask, Depth+1) ||
+ MaskedValueIsZero(I->getOperand(0), Mask, Depth+1);
case Instruction::Or:
case Instruction::Xor:
// If the LHS and the RHS are MaskedValueIsZero, the result is also zero.
- return MaskedValueIsZero(I->getOperand(1), Mask) &&
- MaskedValueIsZero(I->getOperand(0), Mask);
+ return MaskedValueIsZero(I->getOperand(1), Mask, Depth+1) &&
+ MaskedValueIsZero(I->getOperand(0), Mask, Depth+1);
case Instruction::Select:
// If the T and F values are MaskedValueIsZero, the result is also zero.
- return MaskedValueIsZero(I->getOperand(2), Mask) &&
- MaskedValueIsZero(I->getOperand(1), Mask);
+ return MaskedValueIsZero(I->getOperand(2), Mask, Depth+1) &&
+ MaskedValueIsZero(I->getOperand(1), Mask, Depth+1);
case Instruction::Cast: {
const Type *SrcTy = I->getOperand(0)->getType();
if (SrcTy == Type::BoolTy)
@@ -440,7 +443,7 @@
Constant *NewMask =
ConstantExpr::getCast(Mask, I->getOperand(0)->getType());
return MaskedValueIsZero(I->getOperand(0),
- cast(NewMask));
+ cast(NewMask), Depth+1);
}
}
break;
@@ -449,7 +452,8 @@
// (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
if (ConstantUInt *SA = dyn_cast(I->getOperand(1)))
return MaskedValueIsZero(I->getOperand(0),
-cast(ConstantExpr::getUShr(Mask, SA)));
+cast(ConstantExpr::getUShr(Mask, SA)),
+ Depth+1);
break;
case Instruction::Shr:
// (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
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[llvm-commits] CVS: llvm/lib/VMCore/SymbolTable.cpp
Changes in directory llvm/lib/VMCore:
SymbolTable.cpp updated: 1.59 -> 1.60
---
Log message:
Fix an iterator invalidation problem in code used by the -strip pass
---
Diffs of the changes: (+1 -1)
SymbolTable.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/VMCore/SymbolTable.cpp
diff -u llvm/lib/VMCore/SymbolTable.cpp:1.59
llvm/lib/VMCore/SymbolTable.cpp:1.60
--- llvm/lib/VMCore/SymbolTable.cpp:1.59Thu Apr 21 18:46:51 2005
+++ llvm/lib/VMCore/SymbolTable.cpp Mon Oct 31 12:42:37 2005
@@ -269,12 +269,12 @@
value_iterator B = Plane.begin(), Bend = Plane.end();
while (B != Bend) { // Found nonempty type plane!
Value *V = B->second;
+ ++B;
if (!isa(V) || cast(V)->hasInternalLinkage()) {
// Set name to "", removing from symbol table!
V->setName("");
RemovedSymbol = true;
}
- ++B;
}
}
___
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[llvm-commits] XFail on alpha
> Changes in directory llvm/test/Regression/Archive: > > ranlib_GNU.ll updated: 1.6 -> 1.7 > ranlib_SVR4.ll updated: 1.6 -> 1.7 > ranlib_xpg4.ll updated: 1.6 -> 1.7 > --- > Log message: > > these tests fail on alpha for some reason These only fail on old gcc/ld versions. They pass on both of my more up to date testers. > --- > Diffs of the changes: (+6 -0) > > ranlib_GNU.ll |2 ++ > ranlib_SVR4.ll |2 ++ > ranlib_xpg4.ll |2 ++ > 3 files changed, 6 insertions(+) > > > Index: llvm/test/Regression/Archive/ranlib_GNU.ll > diff -u llvm/test/Regression/Archive/ranlib_GNU.ll:1.6 > llvm/test/Regression/Archive/ranlib_GNU.ll:1.7 > --- llvm/test/Regression/Archive/ranlib_GNU.ll:1.6Sat Nov 27 00:44:10 2004 > +++ llvm/test/Regression/Archive/ranlib_GNU.llMon Oct 31 10:15:49 2005 > @@ -5,3 +5,5 @@ > ;RUN: llvm-ranlib %t.GNU.a > ;RUN: llvm-ar t %t.GNU.a > %t1 > ;RUN: diff %t1 %p/GNU.toc > + > +; XFAIL: alpha > > > Index: llvm/test/Regression/Archive/ranlib_SVR4.ll > diff -u llvm/test/Regression/Archive/ranlib_SVR4.ll:1.6 > llvm/test/Regression/Archive/ranlib_SVR4.ll:1.7 > --- llvm/test/Regression/Archive/ranlib_SVR4.ll:1.6 Sat Nov 27 00:44:10 2004 > +++ llvm/test/Regression/Archive/ranlib_SVR4.ll Mon Oct 31 10:15:49 2005 > @@ -5,3 +5,5 @@ > ;RUN: llvm-ranlib %t.SVR4.a > ;RUN: llvm-ar t %t.SVR4.a > %t1 > ;RUN: diff %t1 %p/SVR4.toc > + > +; XFAIL: alpha > > > Index: llvm/test/Regression/Archive/ranlib_xpg4.ll > diff -u llvm/test/Regression/Archive/ranlib_xpg4.ll:1.6 > llvm/test/Regression/Archive/ranlib_xpg4.ll:1.7 > --- llvm/test/Regression/Archive/ranlib_xpg4.ll:1.6 Sat Nov 27 00:44:10 2004 > +++ llvm/test/Regression/Archive/ranlib_xpg4.ll Mon Oct 31 10:15:49 2005 > @@ -5,3 +5,5 @@ > ;RUN: llvm-ranlib %t.xpg4.a > ;RUN: llvm-ar t %t.xpg4.a > %t1 > ;RUN: diff %t1 %p/xpg4.toc > + > +; XFAIL: alpha > signature.asc Description: This is a digitally signed message part ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] XFail on alpha
On Mon, 31 Oct 2005, Andrew Lenharth wrote: Changes in directory llvm/test/Regression/Archive: these tests fail on alpha for some reason These only fail on old gcc/ld versions. They pass on both of my more up to date testers. Ok. Will revert. -chris --- Diffs of the changes: (+6 -0) ranlib_GNU.ll |2 ++ ranlib_SVR4.ll |2 ++ ranlib_xpg4.ll |2 ++ 3 files changed, 6 insertions(+) Index: llvm/test/Regression/Archive/ranlib_GNU.ll diff -u llvm/test/Regression/Archive/ranlib_GNU.ll:1.6 llvm/test/Regression/Archive/ranlib_GNU.ll:1.7 --- llvm/test/Regression/Archive/ranlib_GNU.ll:1.6 Sat Nov 27 00:44:10 2004 +++ llvm/test/Regression/Archive/ranlib_GNU.ll Mon Oct 31 10:15:49 2005 @@ -5,3 +5,5 @@ ;RUN: llvm-ranlib %t.GNU.a ;RUN: llvm-ar t %t.GNU.a > %t1 ;RUN: diff %t1 %p/GNU.toc + +; XFAIL: alpha Index: llvm/test/Regression/Archive/ranlib_SVR4.ll diff -u llvm/test/Regression/Archive/ranlib_SVR4.ll:1.6 llvm/test/Regression/Archive/ranlib_SVR4.ll:1.7 --- llvm/test/Regression/Archive/ranlib_SVR4.ll:1.6 Sat Nov 27 00:44:10 2004 +++ llvm/test/Regression/Archive/ranlib_SVR4.ll Mon Oct 31 10:15:49 2005 @@ -5,3 +5,5 @@ ;RUN: llvm-ranlib %t.SVR4.a ;RUN: llvm-ar t %t.SVR4.a > %t1 ;RUN: diff %t1 %p/SVR4.toc + +; XFAIL: alpha Index: llvm/test/Regression/Archive/ranlib_xpg4.ll diff -u llvm/test/Regression/Archive/ranlib_xpg4.ll:1.6 llvm/test/Regression/Archive/ranlib_xpg4.ll:1.7 --- llvm/test/Regression/Archive/ranlib_xpg4.ll:1.6 Sat Nov 27 00:44:10 2004 +++ llvm/test/Regression/Archive/ranlib_xpg4.ll Mon Oct 31 10:15:49 2005 @@ -5,3 +5,5 @@ ;RUN: llvm-ranlib %t.xpg4.a ;RUN: llvm-ar t %t.xpg4.a > %t1 ;RUN: diff %t1 %p/xpg4.toc + +; XFAIL: alpha -Chris -- http://nondot.org/sabre/ http://llvm.org/ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/Archive/ranlib_GNU.ll ranlib_SVR4.ll ranlib_xpg4.ll
Changes in directory llvm/test/Regression/Archive: ranlib_GNU.ll updated: 1.7 -> 1.8 ranlib_SVR4.ll updated: 1.7 -> 1.8 ranlib_xpg4.ll updated: 1.7 -> 1.8 --- Log message: Apparently these do pass on some alphas --- Diffs of the changes: (+0 -3) ranlib_GNU.ll |1 - ranlib_SVR4.ll |1 - ranlib_xpg4.ll |1 - 3 files changed, 3 deletions(-) Index: llvm/test/Regression/Archive/ranlib_GNU.ll diff -u llvm/test/Regression/Archive/ranlib_GNU.ll:1.7 llvm/test/Regression/Archive/ranlib_GNU.ll:1.8 --- llvm/test/Regression/Archive/ranlib_GNU.ll:1.7 Mon Oct 31 10:15:49 2005 +++ llvm/test/Regression/Archive/ranlib_GNU.ll Mon Oct 31 13:06:13 2005 @@ -6,4 +6,3 @@ ;RUN: llvm-ar t %t.GNU.a > %t1 ;RUN: diff %t1 %p/GNU.toc -; XFAIL: alpha Index: llvm/test/Regression/Archive/ranlib_SVR4.ll diff -u llvm/test/Regression/Archive/ranlib_SVR4.ll:1.7 llvm/test/Regression/Archive/ranlib_SVR4.ll:1.8 --- llvm/test/Regression/Archive/ranlib_SVR4.ll:1.7 Mon Oct 31 10:15:49 2005 +++ llvm/test/Regression/Archive/ranlib_SVR4.ll Mon Oct 31 13:06:13 2005 @@ -6,4 +6,3 @@ ;RUN: llvm-ar t %t.SVR4.a > %t1 ;RUN: diff %t1 %p/SVR4.toc -; XFAIL: alpha Index: llvm/test/Regression/Archive/ranlib_xpg4.ll diff -u llvm/test/Regression/Archive/ranlib_xpg4.ll:1.7 llvm/test/Regression/Archive/ranlib_xpg4.ll:1.8 --- llvm/test/Regression/Archive/ranlib_xpg4.ll:1.7 Mon Oct 31 10:15:49 2005 +++ llvm/test/Regression/Archive/ranlib_xpg4.ll Mon Oct 31 13:06:13 2005 @@ -6,4 +6,3 @@ ;RUN: llvm-ar t %t.xpg4.a > %t1 ;RUN: diff %t1 %p/xpg4.toc -; XFAIL: alpha ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/ReleaseNotes.html
Changes in directory llvm/docs: ReleaseNotes.html updated: 1.339 -> 1.340 --- Log message: Updated alpha known problems. --- Diffs of the changes: (+1 -3) ReleaseNotes.html |4 +--- 1 files changed, 1 insertion(+), 3 deletions(-) Index: llvm/docs/ReleaseNotes.html diff -u llvm/docs/ReleaseNotes.html:1.339 llvm/docs/ReleaseNotes.html:1.340 --- llvm/docs/ReleaseNotes.html:1.339 Sat Oct 29 02:08:19 2005 +++ llvm/docs/ReleaseNotes.html Mon Oct 31 13:07:29 2005 @@ -635,8 +635,6 @@ On 21164s, some rare FP arithmetic sequences which may trap do not have the appropriate nops inserted to ensure restartability. -Due to the vararg problems, C++ exceptions do not work. Small changes are required to the CFE (which break correctness in the exception handler) to compile the exception handling library (and thus the C++ standard library). - @@ -717,7 +715,7 @@ src="http://www.w3.org/Icons/valid-html401"; alt="Valid HTML 4.01!" /> http://llvm.org/";>The LLVM Compiler Infrastructure - Last modified: $Date: 2005/10/29 07:08:19 $ + Last modified: $Date: 2005/10/31 19:07:29 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.175 -> 1.176 --- Log message: issolate LSR on alpha-beta --- Diffs of the changes: (+2 -2) Makefile.programs |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.175 llvm-test/Makefile.programs:1.176 --- llvm-test/Makefile.programs:1.175 Fri Oct 28 13:23:28 2005 +++ llvm-test/Makefile.programs Mon Oct 31 15:18:30 2005 @@ -190,8 +190,8 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),Alpha) -LLCBETAOPTION := -enable-alpha-FTOI -enable-lsr-for-alpha -#-enable-alpha-intfpdiv +LLCBETAOPTION := -enable-lsr-for-alpha +#-enable-alpha-intfpdiv -enable-alpha-FTOI endif ifeq ($(ARCH),IA64) LLCBETAOPTION := -enable-ia64-dag-isel ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.101 -> 1.102 --- Log message: Make constant pool entries use private labels. This is important when you're not compiling a whole program at a time :) --- Diffs of the changes: (+3 -3) PPCAsmPrinter.cpp |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.101 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.102 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.101 Fri Oct 28 13:44:07 2005 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Mon Oct 31 16:12:06 2005 @@ -294,7 +294,7 @@ } case MachineOperand::MO_ConstantPoolIndex: -O << ".CPI" << CurrentFnName << "_" << MO.getConstantPoolIndex(); +O << "LCPI" << CurrentFnName << "_" << MO.getConstantPoolIndex(); return; case MachineOperand::MO_ExternalSymbol: @@ -436,7 +436,7 @@ emitAlignment(3); else emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType())); -O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString +O << "LCPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString << *CP[i] << "\n"; emitGlobalConstant(CP[i]); } @@ -633,7 +633,7 @@ O << "\t.const\n"; O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) << "\n"; -O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t;" +O << "LCPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t;" << *CP[i] << "\n"; emitGlobalConstant(CP[i]); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.102 -> 1.103 --- Log message: Add a flag to enable a darwin linker optimization --- Diffs of the changes: (+7 -1) PPCAsmPrinter.cpp |8 +++- 1 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.102 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.103 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.102 Mon Oct 31 16:12:06 2005 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Mon Oct 31 18:12:36 2005 @@ -567,6 +567,13 @@ << "\t.long\t" << *i << '\n'; } + // Funny Darwin hack: This flag tells the linker that no global symbols + // contain code that falls through to other global symbols (e.g. the obvious + // implementation of multiple entry points). If this doesn't occur, the + // linker can safely perform dead code stripping. Since LLVM never generates + // code that does this, it is always safe to set. + O << "\t.subsections_via_symbols\n"; + AsmPrinter::doFinalization(M); return false; // success } @@ -711,7 +718,6 @@ O << "_section_.text:\n" << "\t.csect .data[RW],3\n" << "\t.llong _section_.text\n"; - delete Mang; return false; // success } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.20 -> 1.21
---
Log message:
add zeroextend predicate->integer
---
Diffs of the changes: (+42 -37)
IA64InstrInfo.td | 79 +--
1 files changed, 42 insertions(+), 37 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.20
llvm/lib/Target/IA64/IA64InstrInfo.td:1.21
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.20 Sun Oct 30 19:42:11 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Mon Oct 31 19:29:55 2005
@@ -93,6 +93,48 @@
return true;
}]>;
+def ADD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "add $dst = $src1, $src2;;",
+ [(set GR:$dst, (add GR:$src1, GR:$src2))]>;
+
+def ADD1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "add $dst = $src1, $src2, 1;;",
+ [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>;
+
+def ADDS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
+ "adds $dst = $imm, $src1;;",
+ [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>;
+
+def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
+ "movl $dst = $imm;;",
+ [(set GR:$dst, imm64:$imm)]>;
+
+def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1,
globaladdress:$imm),
+ "addl $dst = $imm, $src1;;",
+ []>;
+
+def SUB : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "sub $dst = $src1, $src2;;",
+ [(set GR:$dst, (sub GR:$src1, GR:$src2))]>;
+
+def SUB1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "sub $dst = $src1, $src2, 1;;",
+ [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>;
+
+let isTwoAddress = 1 in {
+def TPCADDIMM22 : AForm<0x03, 0x0b,
+ (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
+"($qp) add $dst = $imm, $dst;;">;
+def TPCMPIMM8NE : AForm<0x03, 0x0b,
+ (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
+"($qp) cmp.ne $dst , p0 = $imm, $src2;;">;
+}
+
+// zero extend a bool (predicate reg) into an integer reg
+def ZXTb : Pat<(zext PR:$src),
+ (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src)>;
+
+// normal sign/zero-extends
def SXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;",
[(set GR:$dst, (sext_inreg GR:$src, i8))]>;
def ZXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;",
@@ -137,34 +179,6 @@
[(set GR:$dst, (or (and (shl GR:$src1, 32), isMIX4Rable),
(and GR:$src2, isMIX4Rable)))]>;
-def ADD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- "add $dst = $src1, $src2;;",
- [(set GR:$dst, (add GR:$src1, GR:$src2))]>;
-
-def ADD1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- "add $dst = $src1, $src2, 1;;",
- [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>;
-
-def ADDS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
- "adds $dst = $imm, $src1;;",
- [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>;
-
-def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
- "movl $dst = $imm;;",
- [(set GR:$dst, imm64:$imm)]>;
-
-def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1,
globaladdress:$imm),
- "addl $dst = $imm, $src1;;",
- []>;
-
-def SUB : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- "sub $dst = $src1, $src2;;",
- [(set GR:$dst, (sub GR:$src1, GR:$src2))]>;
-
-def SUB1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- "sub $dst = $src1, $src2, 1;;",
- [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>;
-
def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src),
"getf.sig $dst = $src;;",
[]>;
@@ -424,15 +438,6 @@
def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
"($qp) add $dst = $imm, $src1;;">;
-let isTwoAddress = 1 in {
-def TPCADDIMM22 : AForm<0x03, 0x0b,
- (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
-"($qp) add $dst = $imm, $dst;;">;
-def TPCMPIMM8NE : AForm<0x03, 0x0b,
- (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
-"($qp) cmp.ne $dst , p0 = $imm, $src2;;">;
-}
-
def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
"sub $dst = $imm, $src2;;">;
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.7 -> 1.8 --- Log message: add support for int->FP and FP->int ops, and add ia64 patterns for these --- Diffs of the changes: (+11 -0) TargetSelectionDAG.td | 11 +++ 1 files changed, 11 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.7 llvm/lib/Target/TargetSelectionDAG.td:1.8 --- llvm/lib/Target/TargetSelectionDAG.td:1.7 Wed Oct 26 12:00:25 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Mon Oct 31 21:07:25 2005 @@ -94,6 +94,12 @@ def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> ]>; +def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp + SDTCisFP<0>, SDTCisInt<1> +]>; +def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int + SDTCisInt<0>, SDTCisFP<1> +]>; def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, SDTCisVTSmallerThanOp<2, 1> @@ -172,6 +178,11 @@ def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; def fextend: SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; +def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; +def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; +def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; +def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; + def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.21 -> 1.22
---
Log message:
add support for int->FP and FP->int ops, and add ia64 patterns for these
---
Diffs of the changes: (+12 -0)
IA64InstrInfo.td | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.21
llvm/lib/Target/IA64/IA64InstrInfo.td:1.22
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.21 Mon Oct 31 19:29:55 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Mon Oct 31 21:07:25 2005
@@ -553,6 +553,18 @@
def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
"setf.sig $dst = $src;;">;
+// these four FP<->int conversion patterns need checking/cleaning
+def SINT_TO_FP : Pat<(sint_to_fp GR:$src),
+ (FNORMD (FCVTXF (SETFSIG GR:$src)))>;
+def UINT_TO_FP : Pat<(uint_to_fp GR:$src),
+ (FNORMD (FCVTXUF (SETFSIG GR:$src)))>;
+/* FIXME: tablegen coughs on these
+def FP_TO_SINT : Pat<(fp_to_sint FP:$src),
+ (GETFSIG (FCVTFXTRUNC FP:$src))>;
+def FP_TO_UINT : Pat<(fp_to_uint FP:$src),
+ (GETFSIG (FCVTFXUTRUNC FP:$src))>;
+*/
+
let isTerminator = 1, isBranch = 1 in {
def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
"(p0) brl.cond.sptk $dst;;">;
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.22 -> 1.23
---
Log message:
so tablegen was thinking I might want to convert FPs to predicates.
clever little tablegen!
---
Diffs of the changes: (+3 -4)
IA64InstrInfo.td |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.22
llvm/lib/Target/IA64/IA64InstrInfo.td:1.23
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.22 Mon Oct 31 21:07:25 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Mon Oct 31 21:32:15 2005
@@ -558,12 +558,11 @@
(FNORMD (FCVTXF (SETFSIG GR:$src)))>;
def UINT_TO_FP : Pat<(uint_to_fp GR:$src),
(FNORMD (FCVTXUF (SETFSIG GR:$src)))>;
-/* FIXME: tablegen coughs on these
-def FP_TO_SINT : Pat<(fp_to_sint FP:$src),
+def FP_TO_SINT : Pat<(i64 (fp_to_sint FP:$src)),
(GETFSIG (FCVTFXTRUNC FP:$src))>;
-def FP_TO_UINT : Pat<(fp_to_uint FP:$src),
+def FP_TO_UINT : Pat<(i64 (fp_to_uint FP:$src)),
(GETFSIG (FCVTFXUTRUNC FP:$src))>;
-*/
+
let isTerminator = 1, isBranch = 1 in {
def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.3 -> 1.4
---
Log message:
FORTRAN!!! :( and other similarly unfortunate things mean that on ia64
one sometimes needs to pass FP args in both FP *and* integer registers.
---
Diffs of the changes: (+20 -0)
IA64ISelDAGToDAG.cpp | 20
1 files changed, 20 insertions(+)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.3
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.4
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.3 Sat Oct 29 11:08:30 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Oct 31 23:46:16 2005
@@ -208,7 +208,13 @@
CallOpcode = IA64::BRCALL_INDIRECT;
}
+ // see section 8.5.8 of "Itanium Software Conventions and
+ // Runtime Architecture Guide to see some examples of what's going
+ // on here. (in short: int args get mapped 1:1 'slot-wise' to out0->out7,
+ // while FP args get mapped to F8->F15 as needed)
+
// TODO: support in-memory arguments
+
unsigned used_FPArgs=0; // how many FP args have been used so far?
unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
@@ -236,6 +242,20 @@
Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
InFlag = Chain.getValue(1);
CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
+ // some functions (e.g. printf) want floating point arguments
+ // *also* passed as in-memory representations in integer registers
+ // this is FORTRAN legacy junk which we don't _always_ need
+ // to do, but to be on the safe side, we do.
+ if(MVT::isFloatingPoint(N->getOperand(i).getValueType())) {
+assert((i-2) < 8 && "FP args alone would fit, but no int regs left");
+ DestReg = intArgs[i-2]; // this FP arg goes in an int reg
+// GETFD takes an FP reg and writes a GP reg
+ Chain = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Val, InFlag);
+// FIXME: this next line is a bit unfortunate
+ Chain = CurDAG->getCopyToReg(Chain, DestReg, Chain, InFlag);
+InFlag = Chain.getValue(1);
+CallOperands.push_back(CurDAG->getRegister(DestReg, MVT::i64));
+ }
}
}
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/README
Changes in directory llvm/lib/Target/IA64: README updated: 1.4 -> 1.5 --- Log message: heh, scheduling was easy? need to send chris, jim and sampo a box of fish each --- Diffs of the changes: (+3 -1) README |4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/IA64/README diff -u llvm/lib/Target/IA64/README:1.4 llvm/lib/Target/IA64/README:1.5 --- llvm/lib/Target/IA64/README:1.4 Tue Apr 12 13:42:59 2005 +++ llvm/lib/Target/IA64/README Mon Oct 31 23:49:08 2005 @@ -54,6 +54,8 @@ TODO: + - stop passing FP args in both FP *and* integer regs when not required + - allocate low (nonstacked) registers more aggressively - clean up and thoroughly test the isel patterns. - fix stacked register allocation order: (for readability) we don't want the out? registers being the first ones used @@ -62,7 +64,7 @@ - bundling! (we will avoid the mess that is: http://gcc.gnu.org/ml/gcc/2003-12/msg00832.html ) - - instruction scheduling (yep) + - instruction scheduling (h! ;) - write truly inspirational documentation - if-conversion (predicate database/knowledge? etc etc) - counted loop support ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
