[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/ConstantExprLowering.llx
Changes in directory llvm/test/Regression/CodeGen/Generic: ConstantExprLowering.llx updated: 1.2 -> 1.3 --- Log message: The pass was removed, but the spirit lives on --- Diffs of the changes: (+1 -1) ConstantExprLowering.llx |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/Generic/ConstantExprLowering.llx diff -u llvm/test/Regression/CodeGen/Generic/ConstantExprLowering.llx:1.2 llvm/test/Regression/CodeGen/Generic/ConstantExprLowering.llx:1.3 --- llvm/test/Regression/CodeGen/Generic/ConstantExprLowering.llx:1.2 Fri Jan 7 15:37:13 2005 +++ llvm/test/Regression/CodeGen/Generic/ConstantExprLowering.llx Sun Oct 30 01:22:15 2005 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -lowerconstantexprs -disable-output +; RUN: llvm-as < %s | llc %.str_1 = internal constant [16 x sbyte] c"%d %d %d %d %d\0A\00" ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.18 -> 1.19 --- Log message: fix some broken comparisons, this affected the Pattern isel too. --- Diffs of the changes: (+4 -27) IA64InstrInfo.td | 31 --- 1 files changed, 4 insertions(+), 27 deletions(-) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.18 llvm/lib/Target/IA64/IA64InstrInfo.td:1.19 --- llvm/lib/Target/IA64/IA64InstrInfo.td:1.18 Sat Oct 29 11:08:30 2005 +++ llvm/lib/Target/IA64/IA64InstrInfo.td Sun Oct 30 04:14:19 2005 @@ -257,29 +257,6 @@ "shr $dst = $src1, $src2;;", [(set GR:$dst, (sra GR:$src1, GR:$src2))]>; -/* -def CMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.eq $dst, p0 = $src1, $src2;;">; -def CMPGT : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.gt $dst, p0 = $src1, $src2;;">; -def CMPGE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.ge $dst, p0 = $src1, $src2;;">; -def CMPLT : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.lt $dst, p0 = $src1, $src2;;">; -def CMPLE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.le $dst, p0 = $src1, $src2;;">; -def CMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.ne $dst, p0 = $src1, $src2;;">; -def CMPLTU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.ltu $dst, p0 = $src1, $src2;;">; -def CMPGTU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.gtu $dst, p0 = $src1, $src2;;">; -def CMPLEU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.leu $dst, p0 = $src1, $src2;;">; -def CMPGEU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.geu $dst, p0 = $src1, $src2;;">; -*/ - // the following are all a bit unfortunate: we throw away the complement // of the compare! def CMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), @@ -301,16 +278,16 @@ "cmp.ne $dst, p0 = $src1, $src2;;", [(set PR:$dst, (setne GR:$src1, GR:$src2))]>; def CMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.eq $dst, p0 = $src1, $src2;;", + "cmp.ltu $dst, p0 = $src1, $src2;;", [(set PR:$dst, (setult GR:$src1, GR:$src2))]>; def CMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.eq $dst, p0 = $src1, $src2;;", + "cmp.gtu $dst, p0 = $src1, $src2;;", [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>; def CMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.eq $dst, p0 = $src1, $src2;;", + "cmp.leu $dst, p0 = $src1, $src2;;", [(set PR:$dst, (setule GR:$src1, GR:$src2))]>; def CMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2), - "cmp.eq $dst, p0 = $src1, $src2;;", + "cmp.geu $dst, p0 = $src1, $src2;;", [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>; // TODO: support postincrement (reg, imm9) loads+stores - this needs more ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
Changes in directory llvm/lib/Target/Alpha:
AlphaTargetMachine.cpp updated: 1.14 -> 1.15
---
Log message:
If the module has no t-t and the host is an alpha, default to using the Alpha BE
---
Diffs of the changes: (+1 -1)
AlphaTargetMachine.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.14
llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.15
--- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.14 Wed Oct 19 19:28:31 2005
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.cppSun Oct 30 10:44:01 2005
@@ -51,7 +51,7 @@
M.getPointerSize() != Module::AnyPointerSize)
return 0;// Match for some other target
- return 0;
+ return getJITMatchQuality()/2;
}
unsigned AlphaTargetMachine::getJITMatchQuality() {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.37 -> 1.38
---
Log message:
Reduce the number of copies emitted as machine instructions by
generating results in vregs that will need them. In the case of something
like this: CopyToReg((add X, Y), reg1024), we no longer emit code like
this:
reg1025 = add X, Y
reg1024 = reg 1025
Instead, we emit:
reg1024 = add X, Y
Whoa! :)
---
Diffs of the changes: (+57 -16)
ScheduleDAG.cpp | 73 +++-
1 files changed, 57 insertions(+), 16 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.37
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.38
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.37 Thu Oct 13 11:44:00 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Sun Oct 30 12:54:27 2005
@@ -1006,7 +1006,28 @@
// Add result register values for things that are defined by this
// instruction.
-if (NumResults) VRBase = CreateVirtualRegisters(MI, NumResults, II);
+
+// If the node is only used by a CopyToReg and the dest reg is a vreg, use
+// the CopyToReg'd destination register instead of creating a new vreg.
+if (NumResults == 1) {
+ for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
+ UI != E; ++UI) {
+SDNode *Use = *UI;
+if (Use->getOpcode() == ISD::CopyToReg &&
+Use->getOperand(2).Val == Node) {
+ unsigned Reg = cast(Use->getOperand(1))->getReg();
+ if (MRegisterInfo::isVirtualRegister(Reg)) {
+VRBase = Reg;
+MI->addRegOperand(Reg, MachineOperand::Def);
+break;
+ }
+}
+ }
+}
+
+// Otherwise, create new virtual registers.
+if (NumResults && VRBase == 0)
+ VRBase = CreateVirtualRegisters(MI, NumResults, II);
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.
@@ -1084,10 +1105,11 @@
case ISD::TokenFactor:
break;
case ISD::CopyToReg: {
- unsigned Val = getVR(Node->getOperand(2));
- MRI.copyRegToReg(*BB, BB->end(),
- cast(Node->getOperand(1))->getReg(),
Val,
- RegMap->getRegClass(Val));
+ unsigned InReg = getVR(Node->getOperand(2));
+ unsigned DestReg = cast(Node->getOperand(1))->getReg();
+ if (InReg != DestReg) // Coallesced away the copy?
+MRI.copyRegToReg(*BB, BB->end(), DestReg, InReg,
+ RegMap->getRegClass(InReg));
break;
}
case ISD::CopyFromReg: {
@@ -1097,21 +1119,40 @@
break;
}
+ // If the node is only used by a CopyToReg and the dest reg is a vreg,
use
+ // the CopyToReg'd destination register instead of creating a new vreg.
+ for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
+ UI != E; ++UI) {
+SDNode *Use = *UI;
+if (Use->getOpcode() == ISD::CopyToReg &&
+Use->getOperand(2).Val == Node) {
+ unsigned DestReg =
cast(Use->getOperand(1))->getReg();
+ if (MRegisterInfo::isVirtualRegister(DestReg)) {
+VRBase = DestReg;
+break;
+ }
+}
+ }
+
// Figure out the register class to create for the destreg.
const TargetRegisterClass *TRC = 0;
+ if (VRBase) {
+TRC = RegMap->getRegClass(VRBase);
+ } else {
- // Pick the register class of the right type that contains this physreg.
- for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
- E = MRI.regclass_end(); I != E; ++I)
-if ((*I)->getType() == Node->getValueType(0) &&
-(*I)->contains(SrcReg)) {
- TRC = *I;
- break;
-}
- assert(TRC && "Couldn't find register class for reg copy!");
+// Pick the register class of the right type that contains this
physreg.
+for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
+ E = MRI.regclass_end(); I != E; ++I)
+ if ((*I)->getType() == Node->getValueType(0) &&
+ (*I)->contains(SrcReg)) {
+TRC = *I;
+break;
+ }
+assert(TRC && "Couldn't find register class for reg copy!");
- // Create the reg, emit the copy.
- VRBase = RegMap->createVirtualRegister(TRC);
+// Create the reg, emit the copy.
+VRBase = RegMap->createVirtualRegister(TRC);
+ }
MRI.copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
break;
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.91 -> 1.92
---
Log message:
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1; [#uses=1]
%tmp2 = cast ubyte %tmp to int ; [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
---
Diffs of the changes: (+49 -102)
SelectionDAGISel.cpp | 151 ---
1 files changed, 49 insertions(+), 102 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.91
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.92
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.91 Tue Oct 18
18:23:37 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Oct 30 13:42:35 2005
@@ -72,14 +72,6 @@
/// anywhere in the function.
std::map StaticAllocaMap;
-/// BlockLocalArguments - If any arguments are only used in a single basic
-/// block, and if the target can access the arguments without side-effects,
-/// avoid emitting CopyToReg nodes for those arguments. This map keeps
-/// track of which arguments are local to each BB.
-std::multimap > BlockLocalArguments;
-
-
unsigned MakeReg(MVT::ValueType VT) {
return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
}
@@ -125,17 +117,30 @@
return false;
}
+/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
+/// entry block, return true.
+static bool isOnlyUsedInEntryBlock(Argument *A) {
+ BasicBlock *Entry = A->getParent()->begin();
+ for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E;
++UI)
+if (cast(*UI)->getParent() != Entry)
+ return false; // Use not in entry block.
+ return true;
+}
+
FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
Function &fn, MachineFunction &mf)
: TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
- // Initialize the mapping of values to registers. This is only set up for
- // instruction values that are used outside of the block that defines
- // them.
+ // Create a vreg for each argument register that is not dead and is used
+ // outside of the entry block for the function.
for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
AI != E; ++AI)
-InitializeRegForValue(AI);
+if (!isOnlyUsedInEntryBlock(AI))
+ InitializeRegForValue(AI);
+ // Initialize the mapping of values to registers. This is only set up for
+ // instruction values that are used outside of the block that defines
+ // them.
Function::iterator BB = Fn.begin(), EB = Fn.end();
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
if (AllocaInst *AI = dyn_cast(I))
@@ -1072,104 +1077,45 @@
}
}
-/// IsOnlyUsedInOneBasicBlock - If the specified argument is only used in a
-/// single basic block, return that block. Otherwise, return a null pointer.
-static BasicBlock *IsOnlyUsedInOneBasicBlock(Argument *A) {
- if (A->use_empty()) return 0;
- BasicBlock *BB = cast(A->use_back())->getParent();
- for (Argument::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E;
- ++UI)
-if (isa(*UI) || cast(*UI)->getParent() != BB)
- return 0; // Disagreement among the users?
-
- // Okay, there is a single BB user. Only permit this optimization if this is
- // the entry block, otherwise, we might sink argument loads into loops and
- // stuff. Later, when we have global instruction selection, this won't be an
- // issue clearly.
- if (BB == BB->getParent()->begin())
-return BB;
- return 0;
-}
-
void SelectionDAGISel::
LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
std::vector &UnorderedChains) {
// If this is the entry block, emit arguments.
Function &F = *BB->getParent();
FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
+ SDOperand OldRoot = SDL.DAG.getRoot();
+ std::vector Args = TLI.LowerArguments(F, SDL.DAG);
- if (BB == &F.front()) {
-SDOperand OldRoot = SDL.DAG.getRoot();
-
-std::vector Args = TLI.LowerArguments(F, SDL.DAG);
-
-// If there were side effects accessing the argument l
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/reg-coallesce-simple.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
reg-coallesce-simple.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+12 -0)
reg-coallesce-simple.ll | 12
1 files changed, 12 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/reg-coallesce-simple.ll
diff -c /dev/null
llvm/test/Regression/CodeGen/PowerPC/reg-coallesce-simple.ll:1.1
*** /dev/null Sun Oct 30 13:42:29 2005
--- llvm/test/Regression/CodeGen/PowerPC/reg-coallesce-simple.llSun Oct
30 13:42:19 2005
***
*** 0
--- 1,12
+ ; RUN: llvm-as < %s | llc -march=ppc32 &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | not grep or
+
+ %struct.foo = type { int, int, [0 x ubyte] }
+ int %test(%struct.foo* %X) {
+ %tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
+ %tmp = load ubyte* %tmp1; [#uses=1]
+ %tmp2 = cast ubyte %tmp to int ; [#uses=1]
+ ret int %tmp2}
+
+
+
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[llvm-commits] CVS: llvm-test/External/SPEC/CINT95/132.ijpeg/Makefile
Changes in directory llvm-test/External/SPEC/CINT95/132.ijpeg: Makefile updated: 1.6 -> 1.7 --- Log message: remove this hack --- Diffs of the changes: (+0 -4) Makefile |4 1 files changed, 4 deletions(-) Index: llvm-test/External/SPEC/CINT95/132.ijpeg/Makefile diff -u llvm-test/External/SPEC/CINT95/132.ijpeg/Makefile:1.6 llvm-test/External/SPEC/CINT95/132.ijpeg/Makefile:1.7 --- llvm-test/External/SPEC/CINT95/132.ijpeg/Makefile:1.6 Mon Sep 6 23:18:02 2004 +++ llvm-test/External/SPEC/CINT95/132.ijpeg/Makefile Sun Oct 30 14:01:56 2005 @@ -8,10 +8,6 @@ STDOUT_FILENAME := $(FILENAME).out RUN_OPTIONS := -image_file $(FILENAME).ppm -compression.quality 90 -compression.optimize_coding 0 -compression.smoothing_factor 90 -difference.image 1 -difference.x_stride 10 -difference.y_stride 10 -verbose 1 -GO.findoptcomp -# This line nukes the __const's found in /usr/include/stdio.h that prevent the -# extern char * sys_errlist variable from linking properly. -CPPFLAGS += -D__const="" - # This #define is the perfectly logical way to get 132.ijpeg to #include errno.h CPPFLAGS += -D__VMS ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/GettingStartedVS.html
Changes in directory llvm/docs: GettingStartedVS.html updated: 1.4 -> 1.5 --- Log message: Update Getting Started for Visual Studio page. --- Diffs of the changes: (+12 -19) GettingStartedVS.html | 31 --- 1 files changed, 12 insertions(+), 19 deletions(-) Index: llvm/docs/GettingStartedVS.html diff -u llvm/docs/GettingStartedVS.html:1.4 llvm/docs/GettingStartedVS.html:1.5 --- llvm/docs/GettingStartedVS.html:1.4 Mon Mar 7 21:56:50 2005 +++ llvm/docs/GettingStartedVS.html Sun Oct 30 15:00:24 2005 @@ -170,15 +170,10 @@ beta, there are no guarantees and there is no support for it at this time. It has been reported that VC++ Express also works. - You will also need several open source packages: bison, flex, and sed. - These must be installed in llvm/win32/tools. These can be found at - http://gnuwin32.sourceforge.net";>http://gnuwin32.sourceforge.net - or - http://unxutils.sourceforge.net";>http://unxutils.sourceforge.net. - Bison prefers that m4 be in the path. You must add it to the Visual Studio - configuration under the menu Options -> Projects -> VC++ Directories. - Alternatively, you can set the environment variable M4 to point to - m4 executable. + If you plan to modify any .y or .l files, you will need to have bison + and/or flex installed where Visual Studio can find them. Otherwise, you do + not need them and the pre-generated files that come with the source tree + will be used. @@ -279,28 +274,26 @@ Note: while you cannot do this step on Windows, you can do it on a Unix system and transfer hello.bc to Windows. - Run the program. To make sure the program ran, execute the - following command: + Run the program using the just-in-time compiler: % lli hello.bc Use the llvm-dis utility to take a look at the LLVM assembly code: - % llvm-dis < hello.bc | less + % llvm-dis < hello.bc | more - Compile the program to native assembly using the LLC code - generator: + Compile the program to C using the LLC code generator: - % llc hello.bc -o hello.s + % llc -march=c hello.bc - Assemble the native assembly language file into a program: + Compile to binary using Microsoft C: - Not currently possible, but eventually will use NASMW. + % cl hello.cbe.c Execute the native code program: - % ./hello.native + % hello.cbe.exe @@ -354,7 +347,7 @@ mailto:[EMAIL PROTECTED]">Jeff Cohen http://llvm.cs.uiuc.edu";>The LLVM Compiler Infrastructure - Last modified: $Date: 2005/03/08 03:56:50 $ + Last modified: $Date: 2005/10/30 21:00:24 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrFormats.td IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrFormats.td updated: 1.2 -> 1.3
IA64InstrInfo.td updated: 1.19 -> 1.20
---
Log message:
add FP compares and implicit register defs to the dag isel
---
Diffs of the changes: (+45 -23)
IA64InstrFormats.td |4 +++
IA64InstrInfo.td| 64 +---
2 files changed, 45 insertions(+), 23 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrFormats.td
diff -u llvm/lib/Target/IA64/IA64InstrFormats.td:1.2
llvm/lib/Target/IA64/IA64InstrFormats.td:1.3
--- llvm/lib/Target/IA64/IA64InstrFormats.td:1.2Fri Oct 28 12:46:36 2005
+++ llvm/lib/Target/IA64/IA64InstrFormats.tdSun Oct 30 19:42:11 2005
@@ -72,4 +72,8 @@
class PseudoInstIA64 : InstIA64<0, OL, nm> {
}
+class PseudoInstIA64_DAG pattern>
+ : InstIA64<0, OL, nm> {
+ let Pattern = pattern;
+}
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.19
llvm/lib/Target/IA64/IA64InstrInfo.td:1.20
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.19 Sun Oct 30 04:14:19 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Sun Oct 30 19:42:11 2005
@@ -200,7 +200,7 @@
// load constants of various sizes // FIXME: prettyprint -ve constants
def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>;
-// TODO: def : Pat<(i1 1), (MOV p0)>;
+// TODO: def : Pat<(i1 1), ()>;
def AND : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
"and $dst = $src1, $src2;;",
@@ -290,11 +290,51 @@
"cmp.geu $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setuge GR:$src1, GR:$src2))]>;
+// and we do the whole thing again for FP compares!
+def FCMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ "fcmp.eq $dst, p0 = $src1, $src2;;",
+ [(set PR:$dst, (seteq FP:$src1, FP:$src2))]>;
+def FCMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ "fcmp.gt $dst, p0 = $src1, $src2;;",
+ [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>;
+def FCMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ "fcmp.ge $dst, p0 = $src1, $src2;;",
+ [(set PR:$dst, (setge FP:$src1, FP:$src2))]>;
+def FCMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ "fcmp.lt $dst, p0 = $src1, $src2;;",
+ [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>;
+def FCMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ "fcmp.le $dst, p0 = $src1, $src2;;",
+ [(set PR:$dst, (setle FP:$src1, FP:$src2))]>;
+def FCMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ "fcmp.neq $dst, p0 = $src1, $src2;;",
+ [(set PR:$dst, (setne FP:$src1, FP:$src2))]>;
+def FCMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ "fcmp.ltu $dst, p0 = $src1, $src2;;",
+ [(set PR:$dst, (setult FP:$src1, FP:$src2))]>;
+def FCMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ "fcmp.gtu $dst, p0 = $src1, $src2;;",
+ [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>;
+def FCMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ "fcmp.leu $dst, p0 = $src1, $src2;;",
+ [(set PR:$dst, (setule FP:$src1, FP:$src2))]>;
+def FCMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ "fcmp.geu $dst, p0 = $src1, $src2;;",
+ [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>;
+
// TODO: support postincrement (reg, imm9) loads+stores - this needs more
// tablegen support
def PHI : PseudoInstIA64<(ops variable_ops), "PHI">;
def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">;
+
+def IDEF_GR_D : PseudoInstIA64_DAG<(ops GR:$reg), "// $reg = IDEF",
+[(set GR:$reg, (undef))]>;
+def IDEF_FP_D : PseudoInstIA64_DAG<(ops FP:$reg), "// $reg = IDEF",
+[(set FP:$reg, (undef))]>;
+def IDEF_PR_D : PseudoInstIA64_DAG<(ops PR:$reg), "// $reg = IDEF",
+[(set PR:$reg, (undef))]>;
+
def IUSE : PseudoInstIA64<(ops variable_ops), "// IUSE">;
def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops variable_ops),
"// ADJUSTCALLSTACKUP">;
@@ -365,28 +405,6 @@
def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1,
u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
-// and we do the whole thing again for FP compares!
-def FCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- "fcmp.eq $dst, p0 = $src1, $src2;;">;
-def FCMPGT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- "fcmp.gt $dst, p0 = $src1, $src2;;">;
-def FCMPGE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- "fcmp.ge $dst, p0 = $src1, $src2;;">;
-def FCMPLT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- "fcmp.lt $dst, p0 = $src1, $src2;;">;
-def FCMPLE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- "fcmp.le $dst, p0 = $src1, $src2;;">;
-def FCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1,
