[llvm-commits] CVS: llvm/docs/ReleaseNotes.html
Changes in directory llvm/docs: ReleaseNotes.html updated: 1.337 -> 1.338 --- Log message: First hack-and-slash on the release notes. Comments and improvements welcome --- Diffs of the changes: (+168 -24) ReleaseNotes.html | 192 +++--- 1 files changed, 168 insertions(+), 24 deletions(-) Index: llvm/docs/ReleaseNotes.html diff -u llvm/docs/ReleaseNotes.html:1.337 llvm/docs/ReleaseNotes.html:1.338 --- llvm/docs/ReleaseNotes.html:1.337 Sat Oct 29 00:14:01 2005 +++ llvm/docs/ReleaseNotes.html Sat Oct 29 02:07:09 2005 @@ -20,7 +20,7 @@ - Written by the http://llvm.cs.uiuc.edu";>LLVM Team + Written by the http://llvm.org";>LLVM Team @@ -35,12 +35,12 @@ infrastructure, release 1.6. Here we describe the status of LLVM, including any known problems and major improvements from the previous release. The most up-to-date version of this document can be found on the http://llvm.cs.uiuc.edu/releases/1.6/";>LLVM 1.6 web site. If you are +href="http://llvm.org/releases/1.6/";>LLVM 1.6 web site. If you are not reading this on the LLVM web pages, you should probably go there because this document may be updated after the release. For more information about LLVM, including information about the latest -release, please check out the http://llvm.cs.uiuc.edu";>main LLVM +release, please check out the http://llvm.org/";>main LLVM web site. If you have questions or comments, the http://mail.cs.uiuc.edu/mailman/listinfo/llvmdev";>LLVM developer's mailing list is a good place to send them. @@ -48,7 +48,7 @@ Note that if you are reading this file from CVS or the main LLVM web page, this document applies to the next release, not the current one. To see the release notes for the current or previous releases, see the http://llvm.cs.uiuc.edu/releases/";>releases page. +href="http://llvm.org/releases/";>releases page. @@ -60,11 +60,12 @@ -This is the seventh public release of the LLVM Compiler Infrastructure. - -LLVM 1.6 is known to correctly compile a wide range of C and C++ programs, -includes bug fixes for those problems found since the 1.5 release, and includes -a large number of new features and enhancements, described below. +This is the seventh public release of the LLVM Compiler Infrastructure. This +release incorporates a large number of enhancements and additions (primarily in +the code generator), which combine to improve the quality of the code generated +by LLVM by up to 30% in some cases. This release is also the first release to +have first-class support for Mac OS/X: all of the major bugs have been shaken +out and it is now as well supported as Linux on X86. @@ -73,14 +74,106 @@ New Features in LLVM 1.6 + +Instruction Selector +Generation from Target Description + + +LLVM now includes support for auto-generating large portions of the +instruction selectors from target descriptions. This allows us to +write patterns in the target .td file, instead of writing lots of +nasty C++ code. Most of the PowerPC instruction selector is now +generated from the PowerPC target description files and other targets +are adding support that will be live for LLVM 1.7. + +For example, here are some patterns used by the PowerPC backend. A +floating-point multiply then subtract instruction (FMSUBS): + + +(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB)) + + +Exclusive-or by 16-bit immediate (XORI): + + +(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2)) + + +Exclusive-or by 16-bit immediate shifted right 16-bits (XORIS): + + +(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2)) + + +With these definitions, we teach the code generator how to combine these two +instructions to xor an abitrary 32-bit immediate with the following +definition. The first line specifies what to match (a xor with an arbitrary +immediate) the second line specifies what to produce: + + +def : Pat<(xor GPRC:$in, imm:$imm), + (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; + + + + + + +Instruction Scheduling +Support + + + +Instruction selectors using the refined instruction selection framework can now +use a simple pre-pass scheduler included with LLVM 1.6. This scheduler is +currently simple (cannot be configured much by the targets), but will be +extended in the future. + + + +Code Generator Subtarget +Support + + +It is now straight-forward to parameterize a target implementation, and +provide a mapping from CPU names to sets of target parameters. LLC now supports +a -mcpu=cpu option that lets you choose a subtarget by CPU name: use +"llvm-as < /dev/null | llc -march=XXX -mcpu=help" to get a list of +supported CPUs for target "XXX". It also provides a +-mattr=+attr1,-attr2 option that can be used to control individual +features of a target (the previous command will list available features as +well). + +This functionality is nice when you want tell LLC something like "compile to +code that is specia
[llvm-commits] CVS: llvm/docs/ReleaseNotes.html
Changes in directory llvm/docs: ReleaseNotes.html updated: 1.338 -> 1.339 --- Log message: Fix <> in html --- Diffs of the changes: (+3 -3) ReleaseNotes.html |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/docs/ReleaseNotes.html diff -u llvm/docs/ReleaseNotes.html:1.338 llvm/docs/ReleaseNotes.html:1.339 --- llvm/docs/ReleaseNotes.html:1.338 Sat Oct 29 02:07:09 2005 +++ llvm/docs/ReleaseNotes.html Sat Oct 29 02:08:19 2005 @@ -111,8 +111,8 @@ immediate) the second line specifies what to produce: -def : Pat<(xor GPRC:$in, imm:$imm), - (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; +def : Pat<(xor GPRC:$in, imm:$imm), + (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; @@ -717,7 +717,7 @@ src="http://www.w3.org/Icons/valid-html401"; alt="Valid HTML 4.01!" /> http://llvm.org/";>The LLVM Compiler Infrastructure - Last modified: $Date: 2005/10/29 07:07:09 $ + Last modified: $Date: 2005/10/29 07:08:19 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.2 -> 1.3
IA64InstrInfo.td updated: 1.17 -> 1.18
---
Log message:
add some FP stuff, some mix.* stuff, and constant pool support to the
DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream
---
Diffs of the changes: (+131 -61)
IA64ISelDAGToDAG.cpp |7 +
IA64InstrInfo.td | 185 ++-
2 files changed, 131 insertions(+), 61 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.2
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.3
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.2 Fri Oct 28 13:26:52 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Oct 29 11:08:30 2005
@@ -313,6 +313,13 @@
CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
+ case ISD::ConstantPool: {
+Constant *C = cast(N)->get();
+SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
+return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
+ CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
+ }
+
case ISD::GlobalAddress: {
GlobalValue *GV = cast(N)->getGlobal();
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.17
llvm/lib/Target/IA64/IA64InstrInfo.td:1.18
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.17 Fri Oct 28 23:13:40 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Sat Oct 29 11:08:30 2005
@@ -45,10 +45,33 @@
def is32ones : PatLeaf<(i64 imm), [{
// is32ones predicate - True if the immediate is 0x
// Used to create ZXT4s appropriately
- int64_t v = (int64_t)N->getValue();
+ uint64_t v = (uint64_t)N->getValue();
return (v == 0xLL);
}]>;
+// isMIXable predicates - True if the immediate is
+// 0xFF00FF00FF00FF00, 0x00FF00FF00FF00FF
+// etc, through 0x
+// Used to test for the suitability of mix*
+def isMIX1Lable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0xFF00FF00FF00FF00LL);
+}]>;
+def isMIX1Rable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0x00FF00FF00FF00FFLL);
+}]>;
+def isMIX2Lable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0xLL);
+}]>;
+def isMIX2Rable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0xLL);
+}]>;
+def isMIX4Lable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0xLL);
+}]>;
+def isMIX4Rable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0xLL);
+}]>;
+
def isSHLADDimm: PatLeaf<(i64 imm), [{
// isSHLADDimm predicate - True if the immediate is exactly 1, 2, 3 or 4
// - 0 is *not* okay.
@@ -83,6 +106,37 @@
def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;",
[(set GR:$dst, (and GR:$src, is32ones))]>;
+// fixme: shrs vs shru?
+def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix1.l $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
+(and (srl GR:$src2, 8), isMIX1Lable)))]>;
+
+def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix2.l $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
+(and (srl GR:$src2, 16), isMIX2Lable)))]>;
+
+def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix4.l $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
+(and (srl GR:$src2, 32), isMIX4Lable)))]>;
+
+def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix1.r $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and (shl GR:$src1, 8), isMIX1Rable),
+(and GR:$src2, isMIX1Rable)))]>;
+
+def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix2.r $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and (shl GR:$src1, 16), isMIX2Rable),
+(and GR:$src2, isMIX2Rable)))]>;
+
+def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix4.r $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and (shl GR:$src1, 32), isMIX4Rable),
+(and GR:$src2, isMIX4Rable)))]>;
+
def ADD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
"add $dst = $src1, $src2;;",
[(set GR:$dst, (add GR:$src1, GR:$src2))]>;
@@ -122,10 +176,20 @@
def XMALD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
"xma.l $dst = $src1, $src2, $src3;;",
[]>;
+def XMAHD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
+ "xma.h $dst = $src1, $s
[llvm-commits] CVS: llvm-www/testresults/index.html
Changes in directory llvm-www/testresults: index.html updated: 1.36 -> 1.37 --- Log message: Reid says his tester is out of action --- Diffs of the changes: (+0 -3) index.html |3 --- 1 files changed, 3 deletions(-) Index: llvm-www/testresults/index.html diff -u llvm-www/testresults/index.html:1.36 llvm-www/testresults/index.html:1.37 --- llvm-www/testresults/index.html:1.36Sat Oct 29 00:44:50 2005 +++ llvm-www/testresults/index.html Sat Oct 29 11:32:45 2005 @@ -56,9 +56,6 @@ Linux (Dual P4 Xeon @ 3.06GHz) -- debug build - -http://illuvium.net/testresults/Optimized/";>Linux (Dual P4 -Xeon @ 2.3GHz) -- release build http://npt.cc.rsu.ru/testresults-X86-FreeBSD/index.html";>FreeBSD 6.0BETA (Pentium 3 @ 1.0Ghz) -- debug build ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.70 -> 1.71
---
Log message:
Make negative immediates in patterns work correctly, silence some warnings
building the itanium backend.
---
Diffs of the changes: (+1 -1)
DAGISelEmitter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.70
llvm/utils/TableGen/DAGISelEmitter.cpp:1.71
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.70 Fri Oct 28 17:49:02 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Sat Oct 29 11:39:40 2005
@@ -1592,7 +1592,7 @@
} else if (IntInit *II = dynamic_cast(Child->getLeafValue())) {
OS << " if (!isa(" << RootName << i << ") ||\n"
<< " cast(" << RootName << i
- << ")->getValue() != " << II->getValue() << ")\n"
+ << ")->getSignExtended() != " << II->getValue() << ")\n"
<< "goto P" << PatternNo << "Fail;\n";
} else {
Child->dump();
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
Changes in directory llvm/lib/Target/Alpha:
AlphaISelPattern.cpp updated: 1.176 -> 1.177
---
Log message:
Make -time-passes output prettier
---
Diffs of the changes: (+4 -0)
AlphaISelPattern.cpp |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.176
llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.177
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.176Fri Oct 21 11:01:26 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Sat Oct 29 11:45:02 2005
@@ -82,6 +82,10 @@
AlphaLowering(TM)
{}
+virtual const char *getPassName() const {
+ return "Alpha Pattern Instruction Selection";
+}
+
/// InstructionSelectBasicBlock - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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[llvm-commits] CVS: llvm/win32/Transforms/Transforms.vcproj
Changes in directory llvm/win32/Transforms: Transforms.vcproj updated: 1.15 -> 1.16 --- Log message: More files deleted. --- Diffs of the changes: (+0 -3) Transforms.vcproj |3 --- 1 files changed, 3 deletions(-) Index: llvm/win32/Transforms/Transforms.vcproj diff -u llvm/win32/Transforms/Transforms.vcproj:1.15 llvm/win32/Transforms/Transforms.vcproj:1.16 --- llvm/win32/Transforms/Transforms.vcproj:1.15Wed Oct 26 00:36:51 2005 +++ llvm/win32/Transforms/Transforms.vcproj Sat Oct 29 11:51:48 2005 @@ -253,9 +253,6 @@ RelativePath="..\..\lib\Transforms\Scalar\LowerAllocations.cpp"> - - http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/win32/Analysis/Analysis.vcproj
Changes in directory llvm/win32/Analysis: Analysis.vcproj updated: 1.14 -> 1.15 --- Log message: More files deleted. --- Diffs of the changes: (+0 -6) Analysis.vcproj |6 -- 1 files changed, 6 deletions(-) Index: llvm/win32/Analysis/Analysis.vcproj diff -u llvm/win32/Analysis/Analysis.vcproj:1.14 llvm/win32/Analysis/Analysis.vcproj:1.15 --- llvm/win32/Analysis/Analysis.vcproj:1.14Thu Oct 27 20:43:09 2005 +++ llvm/win32/Analysis/Analysis.vcproj Sat Oct 29 11:51:48 2005 @@ -128,9 +128,6 @@ RelativePath="..\..\lib\Analysis\ConstantFolding.cpp"> - - - - http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/NightlyTest.pl
Changes in directory llvm/utils:
NightlyTest.pl updated: 1.98 -> 1.99
---
Log message:
Revert an accidental commit.
---
Diffs of the changes: (+1 -1)
NightlyTest.pl |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/utils/NightlyTest.pl
diff -u llvm/utils/NightlyTest.pl:1.98 llvm/utils/NightlyTest.pl:1.99
--- llvm/utils/NightlyTest.pl:1.98 Fri Oct 28 11:35:18 2005
+++ llvm/utils/NightlyTest.pl Sat Oct 29 12:01:41 2005
@@ -410,7 +410,7 @@
#
if (!$NOCHECKOUT) {
if ( $VERBOSE ) { print "CONFIGURE STAGE\n"; }
- my $EXTRAFLAGS =
"--enable-spec2000=/Volumes/ProjectsDisk/cvs/benchmarks/speccpu2000-llvm/benchspec/
--enable-povray=/Volumes/ProjectsDisk/cvs/benchmarks/povray31
--enable-namd=/Volumes/ProjectsDisk/cvs/benchmarks/namd";
+ my $EXTRAFLAGS = "--enable-spec --with-objroot=.";
system "(time -p $NICE ./configure $CONFIGUREARGS $EXTRAFLAGS) > $BuildLog
2>&1";
if ( $VERBOSE ) { print "BUILD STAGE\n"; }
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[llvm-commits] CVS: llvm/test/Regression/Transforms/LoopStrengthReduce/nested-reduce.ll
Changes in directory llvm/test/Regression/Transforms/LoopStrengthReduce:
nested-reduce.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+57 -0)
nested-reduce.ll | 57 +++
1 files changed, 57 insertions(+)
Index: llvm/test/Regression/Transforms/LoopStrengthReduce/nested-reduce.ll
diff -c /dev/null
llvm/test/Regression/Transforms/LoopStrengthReduce/nested-reduce.ll:1.1
*** /dev/null Sun Oct 30 00:14:13 2005
--- llvm/test/Regression/Transforms/LoopStrengthReduce/nested-reduce.ll Sun Oct
30 00:14:03 2005
***
*** 0
--- 1,57
+ ; RUN: llvm-as < %s | opt -loop-reduce &&
+ ; RUN: llvm-as < %s | opt -loop-reduce | llvm-dis | not grep mul
+
+ ; Make sure we don't get a multiply by 6 in this loop.
+
+ int %foo(int %A, int %B, int %C, int %D) {
+ entry:
+ %tmp.5 = setgt int %C, 0; [#uses=1]
+ %tmp.25 = and int %A, 1 ; [#uses=1]
+ br label %loopentry.1
+
+ loopentry.1: ; preds = %loopexit.1, %entry
+ %indvar20 = phi uint [ 0, %entry ], [ %indvar.next21, %loopexit.1 ]
; [#uses=2]
+ %k.1 = phi int [ 0, %entry ], [ %k.1.3, %loopexit.1 ] ;
[#uses=2]
+ br bool %tmp.5, label %no_exit.1.preheader, label %loopexit.1
+
+ no_exit.1.preheader: ; preds = %loopentry.1
+ %i.0.0 = cast uint %indvar20 to int ; [#uses=1]
+ %tmp.9 = mul int %i.0.0, 6 ; [#uses=1]
+ br label %no_exit.1.outer
+
+ no_exit.1.outer: ; preds = %cond_true, %no_exit.1.preheader
+ %k.1.2.ph = phi int [ %k.1, %no_exit.1.preheader ], [ %k.09, %cond_true
] ; [#uses=2]
+ %j.1.2.ph = phi int [ 0, %no_exit.1.preheader ], [ %inc.1, %cond_true ]
; [#uses=1]
+ br label %no_exit.1
+
+ no_exit.1:; preds = %cond_continue, %no_exit.1.outer
+ %indvar = phi uint [ 0, %no_exit.1.outer ], [ %indvar.next,
%cond_continue ]; [#uses=2]
+ %indvar = cast uint %indvar to int ; [#uses=1]
+ %j.1.2 = add int %indvar, %j.1.2.ph ; [#uses=2]
+ %tmp.11 = add int %j.1.2, %tmp.9; [#uses=1]
+ %tmp.12 = cast int %tmp.11 to ubyte ; [#uses=1]
+ %tmp.13 = shl int %D, ubyte %tmp.12 ; [#uses=2]
+ %tmp.15 = seteq int %tmp.13, %B ; [#uses=1]
+ %inc.1 = add int %j.1.2, 1 ; [#uses=3]
+ br bool %tmp.15, label %cond_true, label %cond_continue
+
+ cond_true:; preds = %no_exit.1
+ %tmp.26 = and int %tmp.25, %tmp.13 ; [#uses=1]
+ %k.09 = add int %tmp.26, %k.1.2.ph ; [#uses=2]
+ %tmp.517 = setlt int %inc.1, %C ; [#uses=1]
+ br bool %tmp.517, label %no_exit.1.outer, label %loopexit.1
+
+ cond_continue:; preds = %no_exit.1
+ %tmp.519 = setlt int %inc.1, %C ; [#uses=1]
+ %indvar.next = add uint %indvar, 1 ; [#uses=1]
+ br bool %tmp.519, label %no_exit.1, label %loopexit.1
+
+ loopexit.1: ; preds = %cond_continue, %cond_true, %loopentry.1
+ %k.1.3 = phi int [ %k.1, %loopentry.1 ], [ %k.09, %cond_true ], [
%k.1.2.ph, %cond_continue ] ; [#uses=2]
+ %indvar.next21 = add uint %indvar20, 1 ; [#uses=2]
+ %exitcond = seteq uint %indvar.next21, 4;
[#uses=1]
+ br bool %exitcond, label %loopexit.0, label %loopentry.1
+
+ loopexit.0: ; preds = %loopexit.1
+ ret int %k.1.3
+ }
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[llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolutionExpander.cpp
Changes in directory llvm/lib/Analysis:
ScalarEvolutionExpander.cpp updated: 1.1 -> 1.2
---
Log message:
Fix a problem that Nate noticed with LSR:
When inserting code for an addrec expression with a non-unit stride, be
more careful where we insert the multiply. In particular, insert the multiply
in the outermost loop we can, instead of the requested insertion point.
This allows LSR to notice the mul in the right loop, reducing it when it gets
to it. This allows it to reduce the multiply, where before it missed it.
This happens quite a bit in the test suite, for example, eliminating 2
multiplies in art, 3 in ammp, 4 in apsi, reducing from 1050 multiplies to
910 muls in galgel (!), from 877 to 859 in applu, and 36 to 30 in bzip2.
This speeds up galgel from 16.45s to 16.01s, applu from 14.21 to 13.94s and
fourinarow from 66.67s to 63.48s.
This implements Transforms/LoopStrengthReduce/nested-reduce.ll
---
Diffs of the changes: (+26 -1)
ScalarEvolutionExpander.cpp | 27 ++-
1 files changed, 26 insertions(+), 1 deletion(-)
Index: llvm/lib/Analysis/ScalarEvolutionExpander.cpp
diff -u llvm/lib/Analysis/ScalarEvolutionExpander.cpp:1.1
llvm/lib/Analysis/ScalarEvolutionExpander.cpp:1.2
--- llvm/lib/Analysis/ScalarEvolutionExpander.cpp:1.1 Fri Jul 29 19:12:19 2005
+++ llvm/lib/Analysis/ScalarEvolutionExpander.cpp Sun Oct 30 01:24:33 2005
@@ -87,9 +87,34 @@
// Get the canonical induction variable I for this loop.
Value *I = getOrInsertCanonicalInductionVariable(L, Ty);
+ // If this is a simple linear addrec, emit it now as a special case.
if (S->getNumOperands() == 2) { // {0,+,F} --> i*F
Value *F = expandInTy(S->getOperand(1), Ty);
-return BinaryOperator::createMul(I, F, "tmp.", InsertPt);
+
+// IF the step is by one, just return the inserted IV.
+if (ConstantIntegral *CI = dyn_cast(F))
+ if (CI->getRawValue() == 1)
+return I;
+
+// If the insert point is directly inside of the loop, emit the multiply at
+// the insert point. Otherwise, L is a loop that is a parent of the insert
+// point loop. If we can, move the multiply to the outer most loop that it
+// is safe to be in.
+Instruction *MulInsertPt = InsertPt;
+Loop *InsertPtLoop = LI.getLoopFor(MulInsertPt->getParent());
+if (InsertPtLoop != L && InsertPtLoop &&
+L->contains(InsertPtLoop->getHeader())) {
+ while (InsertPtLoop != L) {
+// If we cannot hoist the multiply out of this loop, don't.
+if (!InsertPtLoop->isLoopInvariant(F)) break;
+
+// Otherwise, move the insert point to the preheader of the loop.
+MulInsertPt = InsertPtLoop->getLoopPreheader()->getTerminator();
+InsertPtLoop = InsertPtLoop->getParentLoop();
+ }
+}
+
+return BinaryOperator::createMul(I, F, "tmp.", MulInsertPt);
}
// If this is a chain of recurrences, turn it into a closed form, using the
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/mul-neg-power-2.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
mul-neg-power-2.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+9 -0)
mul-neg-power-2.ll |9 +
1 files changed, 9 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/mul-neg-power-2.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/mul-neg-power-2.ll:1.1
*** /dev/null Sun Oct 30 01:37:44 2005
--- llvm/test/Regression/CodeGen/PowerPC/mul-neg-power-2.ll Sun Oct 30
01:37:34 2005
***
*** 0
--- 1,9
+ ; RUN: llvm-as < %s | llc -march=ppc32 &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | not grep mul
+
+ int %test1(int %a) {
+ %tmp.1 = mul int %a, -2 ; [#uses=1]
+ %tmp.2 = add int %tmp.1, 63 ; [#uses=1]
+ ret int %tmp.2
+ }
+
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.57 -> 1.58
---
Log message:
Codegen mul by negative power of two with a shift and negate.
This implements test/Regression/CodeGen/PowerPC/mul-neg-power-2.ll,
producing:
_foo:
slwi r2, r3, 1
subfic r3, r2, 63
blr
instead of:
_foo:
mulli r2, r3, -2
addi r3, r2, 63
blr
---
Diffs of the changes: (+13 -3)
DAGCombiner.cpp | 16 +---
1 files changed, 13 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.57
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.58
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.57 Thu Oct 27 02:10:34 2005
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Oct 30 01:41:49 2005
@@ -735,8 +735,7 @@
// fold (mul c1, c2) -> c1*c2
if (N0C && N1C)
-return DAG.getConstant(N0C->getValue() * N1C->getValue(),
- N->getValueType(0));
+return DAG.getConstant(N0C->getValue() * N1C->getValue(), VT);
// canonicalize constant to RHS
if (N0C && !N1C)
return DAG.getNode(ISD::MUL, VT, N1, N0);
@@ -748,9 +747,20 @@
return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
// fold (mul x, (1 << c)) -> x << c
if (N1C && isPowerOf2_64(N1C->getValue()))
-return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
+return DAG.getNode(ISD::SHL, VT, N0,
DAG.getConstant(Log2_64(N1C->getValue()),
TLI.getShiftAmountTy()));
+ // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
+ if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
+// FIXME: If the input is something that is easily negated (e.g. a
+// single-use add), we should put the negate there.
+return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
+ DAG.getNode(ISD::SHL, VT, N0,
+DAG.getConstant(Log2_64(-N1C->getSignExtended()),
+TLI.getShiftAmountTy(;
+ }
+
+
// fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
if (N1C && N0.getOpcode() == ISD::MUL) {
ConstantSDNode *N00C = dyn_cast(N0.getOperand(0));
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.36 -> 1.37
---
Log message:
This is implemented
---
Diffs of the changes: (+0 -19)
README.txt | 19 ---
1 files changed, 19 deletions(-)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.36
llvm/lib/Target/PowerPC/README.txt:1.37
--- llvm/lib/Target/PowerPC/README.txt:1.36 Fri Oct 28 18:26:57 2005
+++ llvm/lib/Target/PowerPC/README.txt Sun Oct 30 01:42:12 2005
@@ -217,22 +217,3 @@
stw r2, 0(r3)
blr
-===-===
-
-Compile
-int foo(int a) { return a * -2 + 63; }
-
-to
-
-_foo:
-slwi r0,r3,1
-subfic r3,r0,63
-blr
-
-instead of:
-
-_foo:
-mulli r2,r3,-2
-addi r3,r2,63
-blr
-
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