[llvm-commits] CVS: llvm/lib/Transforms/IPO/GlobalOpt.cpp
Changes in directory llvm/lib/Transforms/IPO:
GlobalOpt.cpp updated: 1.58 -> 1.59
---
Log message:
Stop using deprecated types
---
Diffs of the changes: (+2 -1)
GlobalOpt.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Transforms/IPO/GlobalOpt.cpp
diff -u llvm/lib/Transforms/IPO/GlobalOpt.cpp:1.58
llvm/lib/Transforms/IPO/GlobalOpt.cpp:1.59
--- llvm/lib/Transforms/IPO/GlobalOpt.cpp:1.58 Tue Sep 27 17:28:11 2005
+++ llvm/lib/Transforms/IPO/GlobalOpt.cpp Tue Oct 25 06:18:06 2005
@@ -1113,7 +1113,8 @@
/// FindGlobalCtors - Find the llvm.globalctors list, verifying that all
/// initializers have an init priority of 65535.
GlobalVariable *GlobalOpt::FindGlobalCtors(Module &M) {
- for (Module::giterator I = M.global_begin(), E = M.global_end(); I != E; ++I)
+ for (Module::global_iterator I = M.global_begin(), E = M.global_end();
+ I != E; ++I)
if (I->getName() == "llvm.global_ctors") {
// Found it, verify it's an array of { int, void()* }.
const ArrayType *ATy
=dyn_cast(I->getType()->getElementType());
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[llvm-commits] CVS: llvm/include/llvm/Target/SubtargetFeature.h
Changes in directory llvm/include/llvm/Target:
SubtargetFeature.h updated: 1.4 -> 1.5
---
Log message:
Preparation of supporting scheduling info. Need to find info based on selected
CPU.
---
Diffs of the changes: (+27 -9)
SubtargetFeature.h | 36 +++-
1 files changed, 27 insertions(+), 9 deletions(-)
Index: llvm/include/llvm/Target/SubtargetFeature.h
diff -u llvm/include/llvm/Target/SubtargetFeature.h:1.4
llvm/include/llvm/Target/SubtargetFeature.h:1.5
--- llvm/include/llvm/Target/SubtargetFeature.h:1.4 Sun Oct 23 00:25:19 2005
+++ llvm/include/llvm/Target/SubtargetFeature.h Tue Oct 25 10:15:28 2005
@@ -43,6 +43,21 @@
//===--===//
///
+/// SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary
+/// pointers.
+//
+struct SubtargetInfoKV {
+ const char *Key; // K-V key string
+ void *Value; // K-V pointer value
+
+ // Compare routine for std binary search
+ bool operator<(const std::string &S) const {
+return strcmp(Key, S.c_str()) < 0;
+ }
+};
+
+//===--===//
+///
/// SubtargetFeatures - Manages the enabling and disabling of subtarget
/// specific features. Features are encoded as a string of the form
/// "cpu,+attr1,+attr2,-attr3,...,+attrN"
@@ -63,20 +78,23 @@
std::string getString() const;
void setString(const std::string &Initial);
- /// Setting CPU string. Replaces previous setting. Setting to "" clears
CPU.
- ///
+ /// Set the CPU string. Replaces previous setting. Setting to "" clears
CPU.
void setCPU(const std::string &String);
+ /// Setting CPU string only if no string is set.
+ void setCPUIfNone(const std::string &String);
+
/// Adding Features.
void AddFeature(const std::string &String, bool IsEnabled = true);
- /// Parse feature string for quick usage.
- static uint32_t Parse(const std::string &String,
-const std::string &DefaultCPU,
-const SubtargetFeatureKV *CPUTable,
-size_t CPUTableSize,
-const SubtargetFeatureKV *FeatureTable,
-size_t FeatureTableSize);
+ /// Get feature bits.
+ uint32_t getBits(const SubtargetFeatureKV *CPUTable,
+ size_t CPUTableSize,
+ const SubtargetFeatureKV *FeatureTable,
+ size_t FeatureTableSize);
+
+ /// Get info pointer
+ void *getInfo(const SubtargetInfoKV *Table, size_t TableSize);
/// Print feature string.
void print(std::ostream &OS) const;
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCSubtarget.cpp updated: 1.12 -> 1.13 --- Log message: Preparation of supporting scheduling info. Need to find info based on selected CPU. --- Diffs of the changes: (+4 -3) PPCSubtarget.cpp |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp diff -u llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.12 llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.13 --- llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.12 Sun Oct 23 17:34:25 2005 +++ llvm/lib/Target/PowerPC/PPCSubtarget.cppTue Oct 25 10:15:28 2005 @@ -76,9 +76,10 @@ #if defined(__APPLE__) CPU = GetCurrentPowerPCCPU(); #endif - uint32_t Bits = - SubtargetFeatures::Parse(FS, CPU, - SubTypeKV, SubTypeKVSize, FeatureKV, FeatureKVSize); + SubtargetFeatures Features(FS); + Features.setCPUIfNone(CPU); + uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize, +FeatureKV, FeatureKVSize); IsGigaProcessor = (Bits & FeatureGPUL ) != 0; Is64Bit = (Bits & Feature64Bit) != 0; HasFSQRT= (Bits & FeatureFSqrt) != 0; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaSubtarget.cpp
Changes in directory llvm/lib/Target/Alpha:
AlphaSubtarget.cpp updated: 1.5 -> 1.6
---
Log message:
Preparation of supporting scheduling info. Need to find info based on selected
CPU.
---
Diffs of the changes: (+4 -4)
AlphaSubtarget.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaSubtarget.cpp
diff -u llvm/lib/Target/Alpha/AlphaSubtarget.cpp:1.5
llvm/lib/Target/Alpha/AlphaSubtarget.cpp:1.6
--- llvm/lib/Target/Alpha/AlphaSubtarget.cpp:1.5Sun Oct 23 17:33:22 2005
+++ llvm/lib/Target/Alpha/AlphaSubtarget.cppTue Oct 25 10:15:28 2005
@@ -19,10 +19,10 @@
AlphaSubtarget::AlphaSubtarget(const Module &M, const std::string &FS)
: HasF2I(false), HasCT(false) {
std::string CPU = "generic";
- uint32_t Bits =
-SubtargetFeatures::Parse(FS, CPU,
- SubTypeKV, SubTypeKVSize,
- FeatureKV, FeatureKVSize);
+ SubtargetFeatures Features(FS);
+ Features.setCPUIfNone(CPU);
+ uint32_t Bits =Features.getBits(SubTypeKV, SubTypeKVSize,
+ FeatureKV, FeatureKVSize);
HasF2I = (Bits & FeatureFIX) != 0;
HasCT = (Bits & FeatureCIX) != 0;
}
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[llvm-commits] CVS: llvm/lib/Target/SubtargetFeature.cpp
Changes in directory llvm/lib/Target:
SubtargetFeature.cpp updated: 1.7 -> 1.8
---
Log message:
Preparation of supporting scheduling info. Need to find info based on selected
CPU.
---
Diffs of the changes: (+46 -21)
SubtargetFeature.cpp | 67 +++
1 files changed, 46 insertions(+), 21 deletions(-)
Index: llvm/lib/Target/SubtargetFeature.cpp
diff -u llvm/lib/Target/SubtargetFeature.cpp:1.7
llvm/lib/Target/SubtargetFeature.cpp:1.8
--- llvm/lib/Target/SubtargetFeature.cpp:1.7Sun Oct 23 17:23:13 2005
+++ llvm/lib/Target/SubtargetFeature.cppTue Oct 25 10:15:28 2005
@@ -110,13 +110,12 @@
}
}
-/// Find item in array using binary search.
-static const SubtargetFeatureKV *Find(const std::string &S,
- const SubtargetFeatureKV *A, size_t L) {
+/// Find KV in array using binary search.
+template const T *Find(const std::string &S, const T *A, size_t L)
{
// Determine the end of the array
- const SubtargetFeatureKV *Hi = A + L;
+ const T *Hi = A + L;
// Binary search the array
- const SubtargetFeatureKV *F = std::lower_bound(A, Hi, S);
+ const T *F = std::lower_bound(A, Hi, S);
// If not found then return NULL
if (F == Hi || std::string(F->Key) != S) return NULL;
// Return the found array item
@@ -182,6 +181,7 @@
Split(Features, LowercaseString(Initial));
}
+
/// setCPU - Set the CPU string. Replaces previous setting. Setting to ""
/// clears CPU.
void SubtargetFeatures::setCPU(const std::string &String) {
@@ -189,15 +189,19 @@
}
+/// setCPUIfNone - Setting CPU string only if no string is set.
+///
+void SubtargetFeatures::setCPUIfNone(const std::string &String) {
+ if (Features[0].empty()) setCPU(String);
+}
-/// Parse feature string for quick usage.
+
+/// getBits - Get feature bits.
///
-uint32_t SubtargetFeatures::Parse(const std::string &String,
- const std::string &DefaultCPU,
- const SubtargetFeatureKV *CPUTable,
- size_t CPUTableSize,
- const SubtargetFeatureKV *FeatureTable,
- size_t FeatureTableSize) {
+uint32_t SubtargetFeatures::getBits(const SubtargetFeatureKV *CPUTable,
+ size_t CPUTableSize,
+const SubtargetFeatureKV *FeatureTable,
+ size_t FeatureTableSize) {
assert(CPUTable && "missing CPU table");
assert(FeatureTable && "missing features table");
#ifndef NDEBUG
@@ -210,15 +214,10 @@
"CPU features table is not sorted");
}
#endif
- std::vector Features;// Subtarget features as a vector
uint32_t Bits = 0;// Resulting bits
- // Split up features
- Split(Features, String);
- // Check if default is needed
- if (Features[0].empty())
-Features[0] = DefaultCPU;
- else if (Features[0] == "help")
+ // Check if help is needed
+ if (Features[0] == "help")
Help(CPUTable, CPUTableSize, FeatureTable, FeatureTableSize);
// Find CPU entry
@@ -260,7 +259,32 @@
return Bits;
}
-/// Print feature string.
+/// Get info pointer
+void *SubtargetFeatures::getInfo(const SubtargetInfoKV *Table,
+ size_t TableSize) {
+ assert(Table && "missing table");
+#ifndef NDEBUG
+ for (size_t i = 1; i < TableSize; i++) {
+assert(strcmp(Table[i - 1].Key, Table[i].Key) < 0 && "Table is not
sorted");
+ }
+#endif
+
+ // Find entry
+ const SubtargetInfoKV *Entry = Find(Features[0], Table, TableSize);
+
+ if (Entry) {
+return Entry->Value;
+ } else {
+std::cerr << "'" << Features[0]
+ << "' is not a recognized processor for this target"
+ << " (ignoring processor)"
+ << "\n";
+return NULL;
+ }
+}
+
+/// print - Print feature string.
+///
void SubtargetFeatures::print(std::ostream &OS) const {
for (size_t i = 0; i < Features.size(); i++) {
OS << Features[i] << " ";
@@ -268,7 +292,8 @@
OS << "\n";
}
-/// Dump feature info.
+/// dump - Dump feature info.
+///
void SubtargetFeatures::dump() const {
print(std::cerr);
}
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[llvm-commits] CVS: llvm/utils/TableGen/SubtargetEmitter.cpp SubtargetEmitter.h
Changes in directory llvm/utils/TableGen:
SubtargetEmitter.cpp updated: 1.3 -> 1.4
SubtargetEmitter.h updated: 1.1 -> 1.2
---
Log message:
Refactored to make room for more stuff (scheduling info.)
---
Diffs of the changes: (+102 -77)
SubtargetEmitter.cpp | 174 ---
SubtargetEmitter.h |5 +
2 files changed, 102 insertions(+), 77 deletions(-)
Index: llvm/utils/TableGen/SubtargetEmitter.cpp
diff -u llvm/utils/TableGen/SubtargetEmitter.cpp:1.3
llvm/utils/TableGen/SubtargetEmitter.cpp:1.4
--- llvm/utils/TableGen/SubtargetEmitter.cpp:1.3Sun Oct 23 17:33:08 2005
+++ llvm/utils/TableGen/SubtargetEmitter.cppTue Oct 25 10:16:36 2005
@@ -44,96 +44,116 @@
}
};
-
-//
-// SubtargetEmitter::run - Main subtarget enumeration emitter.
//
-void SubtargetEmitter::run(std::ostream &OS) {
- EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
-
+// FeatureEnumeration - Emit an enumeration of all the subtarget features.
+//
+void SubtargetEmitter::FeatureEnumeration(std::ostream &OS) {
RecordList Features = Records.getAllDerivedDefinitions("SubtargetFeature");
sort(Features.begin(), Features.end(), LessRecord());
-
- RecordList Processors = Records.getAllDerivedDefinitions("Processor");
- sort(Processors.begin(), Processors.end(), LessRecordFieldName());
- OS << "#include \"llvm/Target/SubtargetFeature.h\"\n\n";
+ int i = 0;
- { // Feature enumeration
-int i = 0;
-
-OS << "enum {\n";
-
-for (RecordListIter RI = Features.begin(), E = Features.end(); RI != E;){
- Record *R = *RI++;
- std::string Instance = R->getName();
- OS << " "
- << Instance
- << " = "
- << " 1 << " << i++
- << ((RI != E) ? ",\n" : "\n");
-}
-
-OS << "};\n";
- }
+ OS << "enum {\n";
- { // Feature key values
-OS << "\n"
- << "// Sorted (by key) array of values for CPU features.\n"
- << "static llvm::SubtargetFeatureKV FeatureKV[] = {\n";
-for (RecordListIter RI = Features.begin(), E = Features.end(); RI != E;) {
- Record *R = *RI++;
- std::string Instance = R->getName();
- std::string Name = R->getValueAsString("Name");
- std::string Desc = R->getValueAsString("Desc");
- OS << " { "
- << "\"" << Name << "\", "
- << "\"" << Desc << "\", "
- << Instance
- << ((RI != E) ? " },\n" : " }\n");
-}
-OS << "};\n";
+ for (RecordListIter RI = Features.begin(), E = Features.end(); RI != E;){
+Record *R = *RI++;
+std::string Instance = R->getName();
+OS << " "
+ << Instance
+ << " = "
+ << " 1 << " << i++
+ << ((RI != E) ? ",\n" : "\n");
}
- { // CPU key values
-OS << "\n"
- << "// Sorted (by key) array of values for CPU subtype.\n"
- << "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n";
-for (RecordListIter RI = Processors.begin(), E = Processors.end();
- RI != E;) {
- Record *R = *RI++;
- std::string Name = R->getValueAsString("Name");
- Record *ProcItin = R->getValueAsDef("ProcItin");
- ListInit *Features = R->getValueAsListInit("Features");
- unsigned N = Features->getSize();
- OS << " { "
- << "\"" << Name << "\", "
- << "\"Select the " << Name << " processor\", ";
-
-
- if (N == 0) {
-OS << "0";
- } else {
-for (unsigned i = 0; i < N; ) {
- if (DefInit *DI = dynamic_cast(Features->getElement(i++)))
{
-Record *Feature = DI->getDef();
-std::string Name = Feature->getName();
-OS << Name;
-if (i != N) OS << " | ";
- } else {
-throw "Feature: " + Name +
- " expected feature in processor feature list!";
- }
+ OS << "};\n";
+}
+
+//
+// FeatureKeyValues - Emit data of all the subtarget features. Used by command
+// line.
+//
+void SubtargetEmitter::FeatureKeyValues(std::ostream &OS) {
+ RecordList Features = Records.getAllDerivedDefinitions("SubtargetFeature");
+ sort(Features.begin(), Features.end(), LessRecord());
+
+ OS << "\n"
+ << "// Sorted (by key) array of values for CPU features.\n"
+ << "static llvm::SubtargetFeatureKV FeatureKV[] = {\n";
+ for (RecordListIter RI = Features.begin(), E = Features.end(); RI != E;) {
+Record *R = *RI++;
+std::string Instance = R->getName();
+std::string Name = R->getValueAsString("Name");
+std::string Desc = R->getValueAsString("Desc");
+OS << " { "
+ << "\"" << Name << "\", "
+ << "\"" << Desc << "\", "
+ << Instance
+ << ((RI != E) ? " },\n" : " }\n");
+ }
+ OS << "};\n";
+
+ OS<<"\nenum {\n";
+ OS<<" FeatureKVSize = sizeof(FeatureKV)/sizeof(llvm::SubtargetFeatureKV)\n";
+ OS<<"};\n";
+}
+
+//
+// CPUKeyValues - Emit data of all the subtarget processors. Used by command
+// line.
+//
+void SubtargetEmitter:
[llvm-commits] CVS: llvm/tools/llc/Makefile
Changes in directory llvm/tools/llc: Makefile updated: 1.74 -> 1.75 --- Log message: transforms before analyses --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/tools/llc/Makefile diff -u llvm/tools/llc/Makefile:1.74 llvm/tools/llc/Makefile:1.75 --- llvm/tools/llc/Makefile:1.74Sun Oct 23 20:13:21 2005 +++ llvm/tools/llc/Makefile Tue Oct 25 12:10:30 2005 @@ -70,8 +70,8 @@ LLVMipa.a \ LLVMTransforms.a \ LLVMScalarOpts.a \ - LLVMAnalysis.a \ LLVMTransformUtils.a \ + LLVMAnalysis.a \ LLVMBCReader \ LLVMBCWriter \ LLVMCore \ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.332 -> 1.333 --- Log message: analyses after transformations --- Diffs of the changes: (+1 -1) Makefile.rules |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.332 llvm/Makefile.rules:1.333 --- llvm/Makefile.rules:1.332 Sun Oct 23 21:21:45 2005 +++ llvm/Makefile.rules Tue Oct 25 12:54:19 2005 @@ -617,7 +617,7 @@ JIT_LIBS += LLVMAlpha LLVMSelectionDAG endif -LLVMLIBS := $(JIT_LIBS) LLVMScalarOpts.a LLVMAnalysis.a LLVMTransformUtils.a \ +LLVMLIBS := $(JIT_LIBS) LLVMScalarOpts.a LLVMTransformUtils.a LLVMAnalysis.a \ LLVMBCReader LLVMCore LLVMSupport.a LLVMTarget.a LLVMbzip2 \ LLVMSystem.a $(PLATFORMLIBDL) endif ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Module.h Function.h
Changes in directory llvm/include/llvm:
Module.h updated: 1.63 -> 1.64
Function.h updated: 1.66 -> 1.67
---
Log message:
Add a missing Module::setTargetTriple method.
Remove Function::aiterator and Module::giterator typedefs (and const versions)
as they should have been removed when abegin/gbegin were removed. Thanks to
alkis for bringing this to my attn.
---
Diffs of the changes: (+10 -12)
Function.h |2 --
Module.h | 20 ++--
2 files changed, 10 insertions(+), 12 deletions(-)
Index: llvm/include/llvm/Module.h
diff -u llvm/include/llvm/Module.h:1.63 llvm/include/llvm/Module.h:1.64
--- llvm/include/llvm/Module.h:1.63 Sat Oct 22 23:37:19 2005
+++ llvm/include/llvm/Module.h Tue Oct 25 12:58:00 2005
@@ -52,17 +52,15 @@
typedef iplist FunctionListType;
typedef SetVector LibraryListType;
- // Global Variable iterators...
- typedef GlobalListType::iterator
global_iterator;
- typedef GlobalListType::const_iterator
const_global_iterator;
- typedef global_iterator giterator; // these are legacy, deprecated
- typedef const_global_iterator const_giterator;
+ // Global Variable iterators.
+ typedef GlobalListType::iterator global_iterator;
+ typedef GlobalListType::const_iterator const_global_iterator;
- // Function iterators...
+ // Function iterators.
typedef FunctionListType::iterator iterator;
typedef FunctionListType::const_iterator const_iterator;
- // Library list iterators
+ // Library list iterators.
typedef LibraryListType::const_iterator lib_iterator;
enum Endianness { AnyEndianness, LittleEndian, BigEndian };
@@ -87,9 +85,11 @@
Module(const std::string &ModuleID);
~Module();
- const std::string& getModuleIdentifier() const { return ModuleID; }
- const std::string& getTargetTriple() const { return TargetTriple; }
- void setTargetTriple(const std::string& T) { TargetTriple = T; }
+ const std::string &getModuleIdentifier() const { return ModuleID; }
+ void setModuleIdentifier(const std::string &ID) { ModuleID = ID; }
+
+ const std::string &getTargetTriple() const { return TargetTriple; }
+ void setTargetTriple(const std::string &T) { TargetTriple = T; }
/// Target endian information...
Endianness getEndianness() const { return Endian; }
Index: llvm/include/llvm/Function.h
diff -u llvm/include/llvm/Function.h:1.66 llvm/include/llvm/Function.h:1.67
--- llvm/include/llvm/Function.h:1.66 Sun May 15 20:49:12 2005
+++ llvm/include/llvm/Function.hTue Oct 25 12:58:00 2005
@@ -57,8 +57,6 @@
typedef ArgumentListType::iterator arg_iterator;
typedef ArgumentListType::const_iterator const_arg_iterator;
- typedef arg_iterator aiterator; // legacy, deprecated
- typedef const_arg_iterator const_aiterator; // legacy, deprecated
private:
// Important things that make up a function!
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[llvm-commits] CVS: llvm/include/llvm/BasicBlock.h Constant.h GlobalValue.h Instruction.h
Changes in directory llvm/include/llvm:
BasicBlock.h updated: 1.56 -> 1.57
Constant.h updated: 1.25 -> 1.26
GlobalValue.h updated: 1.23 -> 1.24
Instruction.h updated: 1.68 -> 1.69
---
Log message:
Remove some dead argument names which irritates GCC at certain warning levels.
---
Diffs of the changes: (+4 -4)
BasicBlock.h |2 +-
Constant.h|2 +-
GlobalValue.h |2 +-
Instruction.h |2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/BasicBlock.h
diff -u llvm/include/llvm/BasicBlock.h:1.56 llvm/include/llvm/BasicBlock.h:1.57
--- llvm/include/llvm/BasicBlock.h:1.56 Fri Aug 12 17:13:27 2005
+++ llvm/include/llvm/BasicBlock.h Tue Oct 25 12:59:28 2005
@@ -139,7 +139,7 @@
void print(std::ostream &OS, AssemblyAnnotationWriter *AAW) const;
/// Methods for support type inquiry through isa, cast, and dyn_cast:
- static inline bool classof(const BasicBlock *BB) { return true; }
+ static inline bool classof(const BasicBlock *) { return true; }
static inline bool classof(const Value *V) {
return V->getValueType() == Value::BasicBlockVal;
}
Index: llvm/include/llvm/Constant.h
diff -u llvm/include/llvm/Constant.h:1.25 llvm/include/llvm/Constant.h:1.26
--- llvm/include/llvm/Constant.h:1.25 Tue Oct 4 13:12:13 2005
+++ llvm/include/llvm/Constant.hTue Oct 25 12:59:28 2005
@@ -75,7 +75,7 @@
/// use Value::replaceAllUsesWith, which automatically dispatches to this
/// method as needed.
///
- virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U) {
+ virtual void replaceUsesOfWithOnConstant(Value *, Value *, Use *) {
// Provide a default implementation for constants (like integers) that
// cannot use any other values. This cannot be called at runtime, but
needs
// to be here to avoid link errors.
Index: llvm/include/llvm/GlobalValue.h
diff -u llvm/include/llvm/GlobalValue.h:1.23
llvm/include/llvm/GlobalValue.h:1.24
--- llvm/include/llvm/GlobalValue.h:1.23Thu Apr 21 15:11:51 2005
+++ llvm/include/llvm/GlobalValue.h Tue Oct 25 12:59:28 2005
@@ -101,7 +101,7 @@
void removeDeadConstantUsers();
// Methods for support type inquiry through isa, cast, and dyn_cast:
- static inline bool classof(const GlobalValue *T) { return true; }
+ static inline bool classof(const GlobalValue *) { return true; }
static inline bool classof(const Value *V) {
return V->getValueType() == Value::FunctionVal ||
V->getValueType() == Value::GlobalVariableVal;
Index: llvm/include/llvm/Instruction.h
diff -u llvm/include/llvm/Instruction.h:1.68
llvm/include/llvm/Instruction.h:1.69
--- llvm/include/llvm/Instruction.h:1.68Mon Aug 8 00:21:33 2005
+++ llvm/include/llvm/Instruction.h Tue Oct 25 12:59:28 2005
@@ -157,7 +157,7 @@
void print(std::ostream &OS, AssemblyAnnotationWriter *AAW) const;
/// Methods for support type inquiry through isa, cast, and dyn_cast:
- static inline bool classof(const Instruction *I) { return true; }
+ static inline bool classof(const Instruction *) { return true; }
static inline bool classof(const Value *V) {
return V->getValueType() >= Value::InstructionVal;
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.54 -> 1.55 --- Log message: Clear a bit in this file that was causing a miscompilation of 178.galgel. --- Diffs of the changes: (+1 -1) DAGCombiner.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.54 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.55 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.54 Sat Oct 22 13:50:15 2005 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Oct 25 13:57:30 2005 @@ -2472,7 +2472,7 @@ if (N0.getOperand(0) == N1.getOperand(1)) return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); if (N0.getOperand(1) == N1.getOperand(0)) -return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); +return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.116 -> 1.117
---
Log message:
Fix a couple of minor bugs. The first fixes povray, the second fixes things
if the dag combiner isn't run
---
Diffs of the changes: (+9 -3)
PPCISelDAGToDAG.cpp | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.116
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.117
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.116 Fri Oct 21 16:17:10 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Oct 25 14:32:37 2005
@@ -898,8 +898,11 @@
Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32,
getGlobalBaseReg(),CPI);
else
Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
-CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
-return SDOperand(N, 0);
+if (N->hasOneUse()) {
+ CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
+ return SDOperand(N, 0);
+}
+return CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, CPI);
}
case ISD::GlobalAddress: {
GlobalValue *GV = cast(N)->getGlobal();
@@ -1035,7 +1038,10 @@
unsigned SH, MB, ME;
if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
Val = Select(N->getOperand(0).getOperand(0));
- } else {
+ } else if (Imm == 0) {
+// AND X, 0 -> 0, not "rlwinm 32".
+return Select(N->getOperand(1));
+ } else {
Val = Select(N->getOperand(0));
isRunOfOnes(Imm, MB, ME);
SH = 0;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.117 -> 1.118
---
Log message:
Be a bit more paranoid about calling SelectNodeTo
---
Diffs of the changes: (+11 -7)
PPCISelDAGToDAG.cpp | 18 +++---
1 files changed, 11 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.117
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.118
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.117 Tue Oct 25 14:32:37 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Oct 25 15:26:41 2005
@@ -886,10 +886,15 @@
return SDOperand(N, 0);
case ISD::FrameIndex: {
int FI = cast(N)->getIndex();
-CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
- CurDAG->getTargetFrameIndex(FI, MVT::i32),
- getI32Imm(0));
-return SDOperand(N, 0);
+if (N->hasOneUse()) {
+ CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
+ CurDAG->getTargetFrameIndex(FI, MVT::i32),
+ getI32Imm(0));
+ return SDOperand(N, 0);
+}
+return CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
+ CurDAG->getTargetFrameIndex(FI, MVT::i32),
+ getI32Imm(0));
}
case ISD::ConstantPool: {
Constant *C = cast(N)->get();
@@ -914,10 +919,9 @@
Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
if (GV->hasWeakLinkage() || GV->isExternal())
- CurDAG->SelectNodeTo(N, PPC::LWZ, MVT::i32, GA, Tmp);
+ return CurDAG->getTargetNode(PPC::LWZ, MVT::i32, GA, Tmp);
else
- CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, GA);
-return SDOperand(N, 0);
+ return CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, GA);
}
case PPCISD::FSEL: {
___
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.65 -> 1.66
---
Log message:
Emit some boilerplate for targets
---
Diffs of the changes: (+29 -0)
DAGISelEmitter.cpp | 29 +
1 files changed, 29 insertions(+)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.65
llvm/utils/TableGen/DAGISelEmitter.cpp:1.66
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.65 Thu Oct 20 20:19:59 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Oct 25 15:35:14 2005
@@ -1859,6 +1859,35 @@
<< "SDOperand Tmp0 = Select(N.getOperand(0));\n"
<< "if (!N.Val->hasOneUse()) CodeGenMap[N] = Tmp0;\n"
<< "return Tmp0;\n"
+ << " }\n"
+ << " case ISD::TokenFactor:\n"
+ << "if (N.getNumOperands() == 2) {\n"
+ << " SDOperand Op0 = Select(N.getOperand(0));\n"
+ << " SDOperand Op1 = Select(N.getOperand(1));\n"
+ << " return CodeGenMap[N] =\n"
+ << " CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);\n"
+ << "} else {\n"
+ << " std::vector Ops;\n"
+ << " for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)\n"
+ << "Ops.push_back(Select(N.getOperand(i)));\n"
+ << " return CodeGenMap[N] = \n"
+ << " CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);\n"
+ << "}\n"
+ << " case ISD::CopyFromReg: {\n"
+ << "SDOperand Chain = Select(N.getOperand(0));\n"
+ << "if (Chain == N.getOperand(0)) return N; // No change\n"
+ << "SDOperand New = CurDAG->getCopyFromReg(Chain,\n"
+ << "
cast(N.getOperand(1))->getReg(),\n"
+ << " N.Val->getValueType(0));\n"
+ << "return New.getValue(N.ResNo);\n"
+ << " }\n"
+ << " case ISD::CopyToReg: {\n"
+ << "SDOperand Chain = Select(N.getOperand(0));\n"
+ << "SDOperand Reg = N.getOperand(1);\n"
+ << "SDOperand Val = Select(N.getOperand(2));\n"
+ << "return CodeGenMap[N] = \n"
+ << " CurDAG->getNode(ISD::CopyToReg, MVT::Other,\n"
+ << " Chain, Reg, Val);\n"
<< " }\n";
// Group the patterns by their top-level opcodes.
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.118 -> 1.119
---
Log message:
The dag isel generator generates this now
---
Diffs of the changes: (+0 -32)
PPCISelDAGToDAG.cpp | 32
1 files changed, 32 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.118
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.119
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.118 Tue Oct 25 15:26:41 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Oct 25 15:36:10 2005
@@ -844,38 +844,6 @@
case ISD::CALL: return SelectCALL(Op);
case ISD::TAILCALL: return SelectCALL(Op);
- case ISD::TokenFactor: {
-SDOperand New;
-if (N->getNumOperands() == 2) {
- SDOperand Op0 = Select(N->getOperand(0));
- SDOperand Op1 = Select(N->getOperand(1));
- New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
-} else {
- std::vector Ops;
- for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-Ops.push_back(Select(N->getOperand(i)));
- New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
-}
-
-CodeGenMap[Op] = New;
-return New;
- }
- case ISD::CopyFromReg: {
-SDOperand Chain = Select(N->getOperand(0));
-if (Chain == N->getOperand(0)) return Op; // No change
-SDOperand New = CurDAG->getCopyFromReg(Chain,
- cast(N->getOperand(1))->getReg(), N->getValueType(0));
-return New.getValue(Op.ResNo);
- }
- case ISD::CopyToReg: {
-SDOperand Chain = Select(N->getOperand(0));
-SDOperand Reg = N->getOperand(1);
-SDOperand Val = Select(N->getOperand(2));
-SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
-Chain, Reg, Val);
-CodeGenMap[Op] = New;
-return New;
- }
case ISD::UNDEF:
if (N->getValueType(0) == MVT::i32)
CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
___
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.3 -> 1.4
---
Log message:
The dag isel generator generates this now
---
Diffs of the changes: (+0 -32)
AlphaISelDAGToDAG.cpp | 32
1 files changed, 32 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.3
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.4
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.3 Sat Oct 22 22:43:48 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Tue Oct 25 15:36:10 2005
@@ -183,38 +183,6 @@
return SDOperand(N, 0);
}
- case ISD::TokenFactor: {
-SDOperand New;
-if (N->getNumOperands() == 2) {
- SDOperand Op0 = Select(N->getOperand(0));
- SDOperand Op1 = Select(N->getOperand(1));
- New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
-} else {
- std::vector Ops;
- for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-Ops.push_back(Select(N->getOperand(i)));
- New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
-}
-
-CodeGenMap[Op] = New;
-return New;
- }
- case ISD::CopyFromReg: {
-SDOperand Chain = Select(N->getOperand(0));
-if (Chain == N->getOperand(0)) return Op; // No change
-SDOperand New = CurDAG->getCopyFromReg(Chain,
- cast(N->getOperand(1))->getReg(), N->getValueType(0));
-return New.getValue(Op.ResNo);
- }
- case ISD::CopyToReg: {
-SDOperand Chain = Select(N->getOperand(0));
-SDOperand Reg = N->getOperand(1);
-SDOperand Val = Select(N->getOperand(2));
-SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
-Chain, Reg, Val);
-CodeGenMap[Op] = New;
-return New;
- }
case ISD::UNDEF:
if (N->getValueType(0) == MVT::i64)
CurDAG->SelectNodeTo(N, Alpha::IDEF, MVT::i64);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.119 -> 1.120
PPCInstrInfo.td updated: 1.133 -> 1.134
---
Log message:
Autogen a few new ppc-specific nodes
---
Diffs of the changes: (+11 -15)
PPCISelDAGToDAG.cpp | 12
PPCInstrInfo.td | 14 +++---
2 files changed, 11 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.119
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.120
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.119 Tue Oct 25 15:36:10 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Oct 25 15:41:46 2005
@@ -903,18 +903,6 @@
Select(N->getOperand(1)), Select(N->getOperand(2)));
return SDOperand(N, 0);
}
- case PPCISD::FCFID:
-CurDAG->SelectNodeTo(N, PPC::FCFID, N->getValueType(0),
- Select(N->getOperand(0)));
-return SDOperand(N, 0);
- case PPCISD::FCTIDZ:
-CurDAG->SelectNodeTo(N, PPC::FCTIDZ, N->getValueType(0),
- Select(N->getOperand(0)));
-return SDOperand(N, 0);
- case PPCISD::FCTIWZ:
-CurDAG->SelectNodeTo(N, PPC::FCTIWZ, N->getValueType(0),
- Select(N->getOperand(0)));
-return SDOperand(N, 0);
case ISD::FADD: {
MVT::ValueType Ty = N->getValueType(0);
if (!NoExcessFPPrecision) { // Match FMA ops
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.133
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.134
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.133 Fri Oct 21 16:17:10 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Oct 25 15:41:46 2005
@@ -14,6 +14,14 @@
include "PPCInstrFormats.td"
+//===--===//
+// PowerPC specific DAG Nodes.
+//
+
+def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
+def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
+def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
+
//===--===//
// PowerPC specific transformation functions and pattern fragments.
@@ -449,13 +457,13 @@
}
def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
"fcfid $frD, $frB", FPGeneral,
- []>, isPPC64;
+ [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
"fctidz $frD, $frB", FPGeneral,
- []>, isPPC64;
+ [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
"fctiwz $frD, $frB", FPGeneral,
- []>;
+ [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
"frsp $frD, $frB", FPGeneral,
[(set F4RC:$frD, (fround F8RC:$frB))]>;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.36 -> 1.37
---
Log message:
Expose the fextend on the DAG instead of doing it in the matcher
---
Diffs of the changes: (+21 -8)
PPCISelLowering.cpp | 29 +
1 files changed, 21 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.36
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.37
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.36Thu Oct 20 19:02:42 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Oct 25 15:54:57 2005
@@ -204,34 +204,47 @@
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETUGE:
case ISD::SETGE:
+if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
+ LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETULE:
case ISD::SETLE:
+if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
+ LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
return DAG.getNode(PPCISD::FSEL, ResVT,
DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
}
+SDOperand Cmp;
switch (CC) {
default: assert(0 && "Invalid FSEL condition"); abort();
case ISD::SETULT:
case ISD::SETLT:
- return DAG.getNode(PPCISD::FSEL, ResVT,
- DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS), FV, TV);
+ Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
+ return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
case ISD::SETUGE:
case ISD::SETGE:
- return DAG.getNode(PPCISD::FSEL, ResVT,
- DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS), TV, FV);
+ Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
+ return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
- return DAG.getNode(PPCISD::FSEL, ResVT,
- DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS), FV, TV);
+ Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
+ return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
case ISD::SETULE:
case ISD::SETLE:
- return DAG.getNode(PPCISD::FSEL, ResVT,
- DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS), TV, FV);
+ Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
+ return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
}
break;
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.120 -> 1.121
PPCInstrInfo.td updated: 1.134 -> 1.135
---
Log message:
Autogen fsel
---
Diffs of the changes: (+6 -14)
PPCISelDAGToDAG.cpp | 12
PPCInstrInfo.td |8 ++--
2 files changed, 6 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.120
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.121
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.120 Tue Oct 25 15:41:46 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Oct 25 15:55:47 2005
@@ -891,18 +891,6 @@
else
return CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, GA);
}
-
- case PPCISD::FSEL: {
-SDOperand Comparison = Select(N->getOperand(0));
-// Extend the comparison to 64-bits.
-if (Comparison.getValueType() == MVT::f32)
- Comparison = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Comparison);
-
-unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FSELS : PPC::FSELD;
-CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Comparison,
- Select(N->getOperand(1)), Select(N->getOperand(2)));
-return SDOperand(N, 0);
- }
case ISD::FADD: {
MVT::ValueType Ty = N->getValueType(0);
if (!NoExcessFPPrecision) { // Match FMA ops
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.134
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.135
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.134 Tue Oct 25 15:41:46 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Oct 25 15:55:47 2005
@@ -22,6 +22,10 @@
def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
+def PPCfsel : SDNode<"PPCISD::FSEL",
+ // Type constraint for fsel.
+ SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
+SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
//===--===//
// PowerPC specific transformation functions and pattern fragments.
@@ -654,11 +658,11 @@
def FSELD : AForm_1<63, 23,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
-[]>;
+[(set F8RC:$FRT, (PPCfsel
F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
def FSELS : AForm_1<63, 23,
(ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
- []>;
+[(set F4RC:$FRT, (PPCfsel
F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
def FADD : AForm_2<63, 21,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
"fadd $FRT, $FRA, $FRB", FPGeneral,
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.54 -> 1.55
PPCInstrInfo.td updated: 1.135 -> 1.136
---
Log message:
Allow pseudos to have patterns, no functionality change
---
Diffs of the changes: (+13 -13)
PPCInstrFormats.td |4 ++--
PPCInstrInfo.td| 22 +++---
2 files changed, 13 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.54
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.55
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.54 Wed Oct 19 14:51:16 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Oct 25 15:58:43 2005
@@ -550,10 +550,10 @@
//===--===//
def NoItin : InstrItinClass;
-class Pseudo
+class Pseudo pattern>
: I<0, OL, asmstr, NoItin> {
let PPC64 = 0;
let VMX = 0;
-
+ let Pattern = pattern;
let Inst{31-0} = 0;
}
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.135
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.136
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.135 Tue Oct 25 15:55:47 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Oct 25 15:58:43 2005
@@ -147,25 +147,25 @@
// PowerPC Instruction Definitions.
// Pseudo-instructions:
-def PHI : Pseudo<(ops variable_ops), "; PHI">;
+def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
let isLoad = 1 in {
-def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
-def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
+def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
+def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
}
-def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
-def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
-def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
+def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", []>;
+def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8", []>;
+def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4", []>;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by
the
// scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+ i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+ i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+ i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
}
@@ -176,12 +176,12 @@
}
let Defs = [LR] in
- def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
+ def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
let isBranch = 1, isTerminator = 1 in {
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
target:$true, target:$false),
- "; COND_BRANCH">;
+ "; COND_BRANCH", []>;
def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>;
def BL : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>;
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.64 -> 1.65
---
Log message:
Add a method
---
Diffs of the changes: (+4 -1)
SelectionDAG.h |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.64
llvm/include/llvm/CodeGen/SelectionDAG.h:1.65
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.64 Sat Oct 22 22:40:17 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.hTue Oct 25 16:02:21 2005
@@ -280,7 +280,10 @@
void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
SDOperand Op3);
-
+
+ SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT) {
+return getNode(ISD::BUILTIN_OP_END+Opcode, VT);
+ }
SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
SDOperand Op1) {
return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1);
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.5 -> 1.6 --- Log message: Add undef --- Diffs of the changes: (+3 -1) TargetSelectionDAG.td |4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.5 llvm/lib/Target/TargetSelectionDAG.td:1.6 --- llvm/lib/Target/TargetSelectionDAG.td:1.5 Thu Oct 20 18:30:37 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Tue Oct 25 16:03:14 2005 @@ -68,7 +68,8 @@ // Builtin profiles. def SDTImm: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. -def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt' +def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. +def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> ]>; @@ -123,6 +124,7 @@ def imm: SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">; def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">; +def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; def sub: SDNode<"ISD::SUB" , SDTIntBinOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.121 -> 1.122
PPCInstrInfo.td updated: 1.136 -> 1.137
---
Log message:
autogen undef
---
Diffs of the changes: (+6 -11)
PPCISelDAGToDAG.cpp |8
PPCInstrInfo.td |9 ++---
2 files changed, 6 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.121
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.122
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.121 Tue Oct 25 15:55:47 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Oct 25 16:03:41 2005
@@ -844,14 +844,6 @@
case ISD::CALL: return SelectCALL(Op);
case ISD::TAILCALL: return SelectCALL(Op);
- case ISD::UNDEF:
-if (N->getValueType(0) == MVT::i32)
- CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
-else if (N->getValueType(0) == MVT::f32)
- CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F4, MVT::f32);
-else
- CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F8, MVT::f64);
-return SDOperand(N, 0);
case ISD::FrameIndex: {
int FI = cast(N)->getIndex();
if (N->hasOneUse()) {
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.136
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.137
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.136 Tue Oct 25 15:58:43 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Oct 25 16:03:41 2005
@@ -153,9 +153,12 @@
def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
}
-def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", []>;
-def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8", []>;
-def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4", []>;
+def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
+ [(set GPRC:$rD, (undef))]>;
+def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
+ [(set F8RC:$rD, (undef))]>;
+def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
+ [(set F4RC:$rD, (undef))]>;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by
the
// scheduler into a branch sequence.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.202 -> 1.203
---
Log message:
Allow custom lowered FP_TO_SINT ops in the check for whether a larger
FP_TO_SINT is preferred to a larger FP_TO_UINT. This seems to be begging
for a TLI.isOperationCustom() helper function.
---
Diffs of the changes: (+2 -1)
LegalizeDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.202
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.203
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.202 Tue Oct 18 19:06:56 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Oct 25 18:47:25 2005
@@ -2266,7 +2266,8 @@
// legal, such as PowerPC.
if (Node->getOpcode() == ISD::FP_TO_UINT &&
!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
-TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) {
+(TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
+ TLI.getOperationAction(ISD::FP_TO_SINT,
NVT)==TargetLowering::Custom)){
Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
} else {
Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.37 -> 1.38
---
Log message:
Correctly Expand or Promote FP_TO_UINT based on the capabilities of the
machine. This allows us to generate great code for i32 FP_TO_UINT now on
targets with 64 bit extensions.
---
Diffs of the changes: (+5 -3)
PPCISelLowering.cpp |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.37
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.38
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.37Tue Oct 25 15:54:57 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Oct 25 18:48:36 2005
@@ -81,9 +81,6 @@
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
- // PowerPC does not have FP_TO_UINT
- setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
-
// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
@@ -98,6 +95,11 @@
// They also have instructions for converting between i64 and fp.
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
+// To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
+setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
+ } else {
+// PowerPC does not have FP_TO_UINT on 32 bit implementations.
+setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
}
if (TM.getSubtarget().has64BitRegs()) {
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.33 -> 1.34
---
Log message:
Add a note about some bitfield stuff we could be doing better.
---
Diffs of the changes: (+64 -0)
README.txt | 64 +
1 files changed, 64 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.33
llvm/lib/Target/PowerPC/README.txt:1.34
--- llvm/lib/Target/PowerPC/README.txt:1.33 Tue Oct 18 01:30:51 2005
+++ llvm/lib/Target/PowerPC/README.txt Tue Oct 25 18:50:02 2005
@@ -121,3 +121,67 @@
If we exposed the srl & mask ops after the MFCR that we are doing to select
the correct CR bit, then we could fold the slwi into the rlwinm before it.
+
+===-===
+
+#define ARRAY_LENGTH 16
+
+union bitfield {
+ struct {
+#ifndef__ppc__
+ unsigned int field0 : 6;
+ unsigned int field1 : 6;
+ unsigned int field2 : 6;
+ unsigned int field3 : 6;
+ unsigned int field4 : 3;
+ unsigned int field5 : 4;
+ unsigned int field6 : 1;
+#else
+ unsigned int field6 : 1;
+ unsigned int field5 : 4;
+ unsigned int field4 : 3;
+ unsigned int field3 : 6;
+ unsigned int field2 : 6;
+ unsigned int field1 : 6;
+ unsigned int field0 : 6;
+#endif
+ } bitfields, bits;
+ unsigned intu32All;
+ signed int i32All;
+ float f32All;
+};
+
+
+typedef struct program_t {
+ union bitfieldarray[ARRAY_LENGTH];
+int size;
+int loaded;
+} program;
+
+
+void AdjustBitfields(program* prog, unsigned int fmt1)
+{
+ unsigned int shift = 0;
+ unsigned int texCount = 0;
+ unsigned int i;
+
+ for (i = 0; i < 8; i++)
+ {
+ prog->array[i].bitfields.field0 = texCount;
+ prog->array[i].bitfields.field1 = texCount + 1;
+ prog->array[i].bitfields.field2 = texCount + 2;
+ prog->array[i].bitfields.field3 = texCount + 3;
+
+ texCount += (fmt1 >> shift) & 0x7;
+ shift+= 3;
+ }
+}
+
+In the loop above, the bitfield adds get generated as
+(add (shl bitfield, C1), (shl C2, C1)) where C2 is 1, 2 or 3.
+
+Since the input to the (or and, and) is an (add) rather than a (shl), the shift
+doesn't get folded into the rlwimi instruction. We should ideally see through
+things like this, rather than forcing llvm to generate the equivalent
+
+(shl (add bitfield, C2), C1) with some kind of mask.
___
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/fp_to_uint.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
fp_to_uint.ll added (r1.1)
---
Log message:
Add a regression test for the recent fix for FP_TO_UINT lowering in the ppc
backend.
---
Diffs of the changes: (+9 -0)
fp_to_uint.ll |9 +
1 files changed, 9 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/fp_to_uint.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/fp_to_uint.ll:1.1
*** /dev/null Tue Oct 25 18:53:32 2005
--- llvm/test/Regression/CodeGen/PowerPC/fp_to_uint.ll Tue Oct 25 18:53:22 2005
***
*** 0
--- 1,9
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep fctiwz | wc -l | grep 1
+
+ implementation
+
+ ushort %foo(float %a) {
+ entry:
+ %tmp.1 = cast float %a to ushort
+ ret ushort %tmp.1
+ }
___
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[llvm-commits] CVS: llvm/win32/Transforms/Transforms.vcproj
Changes in directory llvm/win32/Transforms: Transforms.vcproj updated: 1.14 -> 1.15 --- Log message: Update Visual Studio projects to reflect moved file. --- Diffs of the changes: (+3 -3) Transforms.vcproj |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/win32/Transforms/Transforms.vcproj diff -u llvm/win32/Transforms/Transforms.vcproj:1.14 llvm/win32/Transforms/Transforms.vcproj:1.15 --- llvm/win32/Transforms/Transforms.vcproj:1.14Sun Oct 23 21:57:24 2005 +++ llvm/win32/Transforms/Transforms.vcproj Wed Oct 26 00:36:51 2005 @@ -241,9 +241,6 @@ RelativePath="..\..\lib\Transforms\Scalar\LICM.cpp"> - - + + http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/win32/AsmParser/.cvsignore AsmParser.vcproj
Changes in directory llvm/win32/AsmParser: .cvsignore added (r1.1) AsmParser.vcproj updated: 1.5 -> 1.6 --- Log message: Eliminate need for bison/flex in Visual Studio builds. --- Diffs of the changes: (+17 -15) .cvsignore |4 AsmParser.vcproj | 28 +--- 2 files changed, 17 insertions(+), 15 deletions(-) Index: llvm/win32/AsmParser/.cvsignore diff -c /dev/null llvm/win32/AsmParser/.cvsignore:1.1 *** /dev/null Wed Oct 26 00:37:45 2005 --- llvm/win32/AsmParser/.cvsignore Wed Oct 26 00:37:35 2005 *** *** 0 --- 1,4 + Lexer.cpp + llvmAsmParser.cpp + llvmAsmParser.h + llvmAsmParser.output Index: llvm/win32/AsmParser/AsmParser.vcproj diff -u llvm/win32/AsmParser/AsmParser.vcproj:1.5 llvm/win32/AsmParser/AsmParser.vcproj:1.6 --- llvm/win32/AsmParser/AsmParser.vcproj:1.5 Wed Feb 2 00:33:11 2005 +++ llvm/win32/AsmParser/AsmParser.vcproj Wed Oct 26 00:37:35 2005 @@ -20,7 +20,7 @@ + CommandLine="..\doflex.cmd debug $(InputName) $(InputPath)" + Outputs="$(InputName).cpp"/> + CommandLine="..\doflex.cmd release $(InputName) $(InputPath)" + Outputs="$(InputName).cpp"/> + Outputs="$(InputName).cpp;$(InputName).h"/> + Outputs="$(InputName).cpp;$(InputName).h"/> + RelativePath="Lexer.cpp"> + RelativePath="llvmAsmParser.cpp"> + RelativePath="llvmAsmParser.h"> ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/win32/dobison.cmd doflex.cmd
Changes in directory llvm/win32: dobison.cmd added (r1.1) doflex.cmd added (r1.1) --- Log message: Eliminate need for bison/flex in Visual Studio builds. --- Diffs of the changes: (+41 -0) dobison.cmd | 22 ++ doflex.cmd | 19 +++ 2 files changed, 41 insertions(+) Index: llvm/win32/dobison.cmd diff -c /dev/null llvm/win32/dobison.cmd:1.1 *** /dev/null Wed Oct 26 00:37:45 2005 --- llvm/win32/dobison.cmd Wed Oct 26 00:37:35 2005 *** *** 0 --- 1,22 + @echo off + rem dobison.cmd prefix mode target source + rem prefix - passed to bison as -p + rem mode - either debug or release + rem target - generated parser file name without extension + rem source - input to bison + + if "%2"=="debug" (set flags=-tvdo) else (set flags=-vdo) + + rem Try and run bison. If it is present, great. + bison -p%1 %flags%%3.cpp %4 + if errorlevel 1 goto error + move %3.hpp %3.h + goto done + + :error + echo Bison could not run. Using pre-generated files. + copy %~pn4.cpp %3.cpp + copy %~pn4.h %3.h + + :done + exit 0 Index: llvm/win32/doflex.cmd diff -c /dev/null llvm/win32/doflex.cmd:1.1 *** /dev/null Wed Oct 26 00:37:47 2005 --- llvm/win32/doflex.cmd Wed Oct 26 00:37:35 2005 *** *** 0 --- 1,19 + @echo off + rem doflex.cmd prefix mode target source + rem mode - either debug or release + rem target - generated parser file name without extension + rem source - input to bison + + if "%1"=="debug" (set flags=-t) else (set flags=-t) + + rem Try and run flex. If it is present, great. + flex %flags% >%2.cpp %3 + if errorlevel 1 goto error + goto done + + :error + echo Flex could not run. Using pre-generated files. + copy %~pn3.cpp %2.cpp + + :done + exit 0 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/win32/TableGen/.cvsignore TableGen.vcproj
Changes in directory llvm/win32/TableGen: .cvsignore added (r1.1) TableGen.vcproj updated: 1.16 -> 1.17 --- Log message: Eliminate need for bison/flex in Visual Studio builds. --- Diffs of the changes: (+17 -17) .cvsignore |4 TableGen.vcproj | 30 +- 2 files changed, 17 insertions(+), 17 deletions(-) Index: llvm/win32/TableGen/.cvsignore diff -c /dev/null llvm/win32/TableGen/.cvsignore:1.1 *** /dev/null Wed Oct 26 00:37:45 2005 --- llvm/win32/TableGen/.cvsignore Wed Oct 26 00:37:35 2005 *** *** 0 --- 1,4 + FileLexer.cpp + FileParser.cpp + FileParser.h + FileParser.output Index: llvm/win32/TableGen/TableGen.vcproj diff -u llvm/win32/TableGen/TableGen.vcproj:1.16 llvm/win32/TableGen/TableGen.vcproj:1.17 --- llvm/win32/TableGen/TableGen.vcproj:1.16Sun Oct 23 10:21:52 2005 +++ llvm/win32/TableGen/TableGen.vcproj Wed Oct 26 00:37:35 2005 @@ -19,7 +19,7 @@ + CommandLine="..\doflex.cmd debug $(InputName) $(InputPath)" + Outputs="$(InputName).cpp"/> + CommandLine="..\doflex.cmd release $(InputName) $(InputPath)" + Outputs="$(InputName).cpp"/> + Outputs="$(InputName).cpp;$(InputName).h"/> + Outputs="$(InputName).cpp;$(InputName).h"/> + RelativePath="FileLexer.cpp"> + RelativePath="fileparser.cpp"> + RelativePath="fileparser.h"> ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
