[llvm-branch-commits] [llvm] f3f3c9c - [RISCV] Fix name of Zba extension (NFC)

2021-02-21 Thread Simon Cook via llvm-branch-commits

Author: Simon Cook
Date: 2021-01-24T21:02:34Z
New Revision: f3f3c9c2549a268e602be8730990b552e30cc932

URL: 
https://github.com/llvm/llvm-project/commit/f3f3c9c2549a268e602be8730990b552e30cc932
DIFF: 
https://github.com/llvm/llvm-project/commit/f3f3c9c2549a268e602be8730990b552e30cc932.diff

LOG: [RISCV] Fix name of Zba extension (NFC)

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCV.td

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index a17abd0f96da..83811dadc9ab 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -58,7 +58,7 @@ def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
 
 def FeatureExtZba
 : SubtargetFeature<"experimental-zba", "HasStdExtZba", "true",
-   "'Zba' (Base 'B' Instructions)">;
+   "'Zba' (Address calculation 'B' Instructions)">;
 def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
  AssemblerPredicate<(all_of FeatureExtZba),
  "'Zba' (Address calculation 'B' Instructions)">;



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[llvm-branch-commits] [clang] afd483e - [RISCV] Add support for Zvamo/Zvlsseg to driver

2021-02-21 Thread Simon Cook via llvm-branch-commits

Author: Simon Cook
Date: 2021-01-24T22:07:56Z
New Revision: afd483e57d166418e94a65bd9716e7dc4c114eed

URL: 
https://github.com/llvm/llvm-project/commit/afd483e57d166418e94a65bd9716e7dc4c114eed
DIFF: 
https://github.com/llvm/llvm-project/commit/afd483e57d166418e94a65bd9716e7dc4c114eed.diff

LOG: [RISCV] Add support for Zvamo/Zvlsseg to driver

Differential Revision: https://reviews.llvm.org/D94930

Added: 


Modified: 
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Driver/riscv-arch.c

Removed: 




diff  --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index ae7cc21ec235..2a303dd22062 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,7 +62,7 @@ isExperimentalExtension(StringRef Ext) {
   Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
   Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "93"};
-  if (Ext == "v")
+  if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
 return RISCVExtensionVersion{"0", "9"};
   if (Ext == "zfh")
 return RISCVExtensionVersion{"0", "1"};

diff  --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ebd9b8e79b8d..04dce2ab8215 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -396,3 +396,41 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
 // RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo -### %s -c 2>&1 | 
\
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izvamo'
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-NOVERS: error: invalid arch name 'rv32izvamo'
+// RV32-EXPERIMENTAL-ZVAMO-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p1 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-BADVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-BADVERS: error: invalid arch name 'rv32izvamo0p1'
+// RV32-EXPERIMENTAL-ZVAMO-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-GOODVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32izvlsseg'
+// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires 
'-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32izvlsseg'
+// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p1 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 
'rv32izvlsseg0p1'
+// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" 
"+experimental-zvlsseg"



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[llvm-branch-commits] [llvm] a7c1239 - [RISCV] Add attribute support for all supported extensions

2021-02-21 Thread Simon Cook via llvm-branch-commits

Author: Simon Cook
Date: 2021-01-25T08:58:53Z
New Revision: a7c1239f374907107dcc65a3e6a4b20c53d973c9

URL: 
https://github.com/llvm/llvm-project/commit/a7c1239f374907107dcc65a3e6a4b20c53d973c9
DIFF: 
https://github.com/llvm/llvm-project/commit/a7c1239f374907107dcc65a3e6a4b20c53d973c9.diff

LOG: [RISCV] Add attribute support for all supported extensions

This adds support for ".attribute arch" for all extensions that are
currently supported by the compiler.

Differential Revision: https://reviews.llvm.org/D94931

Added: 


Modified: 
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s

Removed: 




diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b4af0e81dfa7..11e7cf1113d2 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1997,7 +1997,33 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
 else
   return Error(ValueExprLoc, "bad arch string " + Arch);
 
+// .attribute arch overrides the current architecture, so unset all
+// currently enabled extensions
+clearFeatureBits(RISCV::FeatureRV32E, "e");
+clearFeatureBits(RISCV::FeatureStdExtM, "m");
+clearFeatureBits(RISCV::FeatureStdExtA, "a");
+clearFeatureBits(RISCV::FeatureStdExtF, "f");
+clearFeatureBits(RISCV::FeatureStdExtD, "d");
+clearFeatureBits(RISCV::FeatureStdExtC, "c");
+clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
+clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
+clearFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+clearFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
+clearFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
+clearFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
+clearFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
+clearFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
+clearFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
+clearFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
+clearFeatureBits(RISCV::FeatureExtZbproposedc, "experimental-zbproposedc");
+clearFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
+clearFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
+clearFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
+clearFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
+clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
+
 while (!Arch.empty()) {
+  bool DropFirst = true;
   if (Arch[0] == 'i')
 clearFeatureBits(RISCV::FeatureRV32E, "e");
   else if (Arch[0] == 'e')
@@ -2019,19 +2045,57 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
 setFeatureBits(RISCV::FeatureStdExtD, "d");
   } else if (Arch[0] == 'c') {
 setFeatureBits(RISCV::FeatureStdExtC, "c");
+  } else if (Arch[0] == 'b') {
+setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
+  } else if (Arch[0] == 'v') {
+setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
+  } else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') {
+StringRef Ext =
+Arch.take_until([](char c) { return ::isdigit(c) || c == '_'; });
+if (Ext == "zba")
+  setFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
+else if (Ext == "zbb")
+  setFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
+else if (Ext == "zbc")
+  setFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
+else if (Ext == "zbe")
+  setFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
+else if (Ext == "zbf")
+  setFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
+else if (Ext == "zbm")
+  setFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
+else if (Ext == "zbp")
+  setFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
+else if (Ext == "zbproposedc")
+  setFeatureBits(RISCV::FeatureExtZbproposedc,
+ "experimental-zbproposedc");
+else if (Ext == "zbr")
+  setFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
+else if (Ext == "zbs")
+  setFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
+else if (Ext == "zbt")
+  setFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
+else if (Ext == "zfh")
+  setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+else if (Ext == "zvamo")
+  setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
+else if (Ext == "zvlsseg")
+  setFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
+ 

[llvm-branch-commits] [clang] 666815d - [RISCV] Implement new architecture extension macros

2021-02-21 Thread Simon Cook via llvm-branch-commits

Author: Simon Cook
Date: 2021-01-25T08:58:46Z
New Revision: 666815d61bc2475aa7b3ecf8e3a91022d6ccce4b

URL: 
https://github.com/llvm/llvm-project/commit/666815d61bc2475aa7b3ecf8e3a91022d6ccce4b
DIFF: 
https://github.com/llvm/llvm-project/commit/666815d61bc2475aa7b3ecf8e3a91022d6ccce4b.diff

LOG: [RISCV] Implement new architecture extension macros

This adds support for the new architecture extension test macros as
defined in the C-API Document:
https://github.com/riscv/riscv-c-api-doc/blob/master/riscv-c-api.md

Extension versions have been taken from what are used in
RISCVTargetStreamer for ratified extensions, and the -march parser
for experimental extensions.

Differential Revision: https://reviews.llvm.org/D94403

Added: 


Modified: 
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Preprocessor/riscv-target-features.c

Removed: 




diff  --git a/clang/lib/Basic/Targets/RISCV.cpp 
b/clang/lib/Basic/Targets/RISCV.cpp
index 4436db904d59..7e6118af38e0 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -109,13 +109,18 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions 
&Opts,
   if (ABIName == "ilp32e")
 Builder.defineMacro("__riscv_abi_rve");
 
+  Builder.defineMacro("__riscv_arch_test");
+  Builder.defineMacro("__riscv_i", "200");
+
   if (HasM) {
+Builder.defineMacro("__riscv_m", "200");
 Builder.defineMacro("__riscv_mul");
 Builder.defineMacro("__riscv_div");
 Builder.defineMacro("__riscv_muldiv");
   }
 
   if (HasA) {
+Builder.defineMacro("__riscv_a", "200");
 Builder.defineMacro("__riscv_atomic");
 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
@@ -125,22 +130,71 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions 
&Opts,
   }
 
   if (HasF || HasD) {
+Builder.defineMacro("__riscv_f", "200");
 Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");
 Builder.defineMacro("__riscv_fdiv");
 Builder.defineMacro("__riscv_fsqrt");
   }
 
-  if (HasC)
+  if (HasD)
+Builder.defineMacro("__riscv_d", "200");
+
+  if (HasC) {
+Builder.defineMacro("__riscv_c", "200");
 Builder.defineMacro("__riscv_compressed");
+  }
 
-  if (HasB)
+  if (HasB) {
+Builder.defineMacro("__riscv_b", "93000");
 Builder.defineMacro("__riscv_bitmanip");
+  }
 
-  if (HasV)
+  if (HasV) {
+Builder.defineMacro("__riscv_v", "9000");
 Builder.defineMacro("__riscv_vector");
+  }
+
+  if (HasZba)
+Builder.defineMacro("__riscv_zba", "93000");
+
+  if (HasZbb)
+Builder.defineMacro("__riscv_zbb", "93000");
+
+  if (HasZbc)
+Builder.defineMacro("__riscv_zbc", "93000");
+
+  if (HasZbe)
+Builder.defineMacro("__riscv_zbe", "93000");
+
+  if (HasZbf)
+Builder.defineMacro("__riscv_zbf", "93000");
+
+  if (HasZbm)
+Builder.defineMacro("__riscv_zbm", "93000");
+
+  if (HasZbp)
+Builder.defineMacro("__riscv_zbp", "93000");
+
+  if (HasZbproposedc)
+Builder.defineMacro("__riscv_zbproposedc", "93000");
+
+  if (HasZbr)
+Builder.defineMacro("__riscv_zbr", "93000");
+
+  if (HasZbs)
+Builder.defineMacro("__riscv_zbs", "93000");
+
+  if (HasZbt)
+Builder.defineMacro("__riscv_zbt", "93000");
 
   if (HasZfh)
-Builder.defineMacro("__riscv_zfh");
+Builder.defineMacro("__riscv_zfh", "1000");
+
+  if (HasZvamo)
+Builder.defineMacro("__riscv_zvamo", "9000");
+
+  if (HasZvlsseg)
+Builder.defineMacro("__riscv_zvlsseg", "9000");
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -157,7 +211,20 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
   .Case("c", HasC)
   .Case("experimental-b", HasB)
   .Case("experimental-v", HasV)
+  .Case("experimental-zba", HasZba)
+  .Case("experimental-zbb", HasZbb)
+  .Case("experimental-zbc", HasZbc)
+  .Case("experimental-zbe", HasZbe)
+  .Case("experimental-zbf", HasZbf)
+  .Case("experimental-zbm", HasZbm)
+  .Case("experimental-zbp", HasZbp)
+  .Case("experimental-zbproposedc", HasZbproposedc)
+  .Case("experimental-zbr", HasZbr)
+  .Case("experimental-zbs", HasZbs)
+  .Case("experimental-zbt", HasZbt)
   .Case("experimental-zfh", HasZfh)
+  .Case("experimental-zvamo", HasZvamo)
+  .Case("experimental-zvlsseg", HasZvlsseg)
   .Default(false);
 }
 
@@ -179,8 +246,34 @@ bool 
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
   HasB = true;
 else if (Feature == "+experimental-v")
   HasV = true;
+else if (Feature == "+experimental-zba")
+  HasZba = true;
+else if (Feature == "+experimental-zbb")
+  HasZbb = true;
+else if (Feature == "+experimental-zbc")
+  HasZbc = true;
+else if (Feature == "+exper

[llvm-branch-commits] [llvm] 698ae90 - [RegisterScavenging] Fix assert in scavengeRegisterBackwards

2021-01-03 Thread Simon Cook via llvm-branch-commits

Author: Craig Blackmore
Date: 2020-12-18T16:57:05Z
New Revision: 698ae90f306248aafbfb5c85cdd9bb81c387bb59

URL: 
https://github.com/llvm/llvm-project/commit/698ae90f306248aafbfb5c85cdd9bb81c387bb59
DIFF: 
https://github.com/llvm/llvm-project/commit/698ae90f306248aafbfb5c85cdd9bb81c387bb59.diff

LOG: [RegisterScavenging] Fix assert in scavengeRegisterBackwards

According to the documentation, if a spill is required to make a
register available and AllowSpill is false, then NoRegister should be
returned, however, this scenario was actually triggering an assertion
failure.

This patch moves the assertion after the handling of AllowSpill.

Authored by: Lewis Revill

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D92104

Added: 


Modified: 
llvm/lib/CodeGen/RegisterScavenging.cpp

Removed: 




diff  --git a/llvm/lib/CodeGen/RegisterScavenging.cpp 
b/llvm/lib/CodeGen/RegisterScavenging.cpp
index ab9a1d66b835..ab8f4fd9778b 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -573,9 +573,8 @@ Register RegScavenger::scavengeRegisterBackwards(const 
TargetRegisterClass &RC,
 RestoreAfter);
   MCPhysReg Reg = P.first;
   MachineBasicBlock::iterator SpillBefore = P.second;
-  assert(Reg != 0 && "No register left to scavenge!");
   // Found an available register?
-  if (SpillBefore == MBB.end()) {
+  if (Reg != 0 && SpillBefore == MBB.end()) {
 LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
<< '\n');
 return Reg;
@@ -584,6 +583,8 @@ Register RegScavenger::scavengeRegisterBackwards(const 
TargetRegisterClass &RC,
   if (!AllowSpill)
 return 0;
 
+  assert(Reg != 0 && "No register left to scavenge!");
+
   MachineBasicBlock::iterator ReloadAfter =
 RestoreAfter ? std::next(MBBI) : MBBI;
   MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);



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