[llvm-branch-commits] [llvm] 192d968 - [RISCV] add the MC layer support of Zfinx extension
Author: Shao-Ce SUN
Date: 2022-02-18T00:12:38+08:00
New Revision: 192d9680c1b11877e84b7431626ac8321c52d9c1
URL:
https://github.com/llvm/llvm-project/commit/192d9680c1b11877e84b7431626ac8321c52d9c1
DIFF:
https://github.com/llvm/llvm-project/commit/192d9680c1b11877e84b7431626ac8321c52d9c1.diff
LOG: [RISCV] add the MC layer support of Zfinx extension
This patch added the MC layer support of Zfinx extension.
Authored-by: StephenFan
Co-Authored-by: Shao-Ce Sun
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D93298
(cherry picked from commit 7798ecca9c3db42241169d31fea4fb820ed01830)
Added:
llvm/test/MC/RISCV/rv32zdinx-invalid.s
llvm/test/MC/RISCV/rv32zdinx-valid.s
llvm/test/MC/RISCV/rv32zfinx-invalid.s
llvm/test/MC/RISCV/rv32zfinx-valid.s
llvm/test/MC/RISCV/rv32zhinx-invalid.s
llvm/test/MC/RISCV/rv32zhinx-valid.s
llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
llvm/test/MC/RISCV/rv32zhinxmin-valid.s
llvm/test/MC/RISCV/rv64zdinx-invalid.s
llvm/test/MC/RISCV/rv64zdinx-valid.s
llvm/test/MC/RISCV/rv64zfinx-invalid.s
llvm/test/MC/RISCV/rv64zfinx-valid.s
llvm/test/MC/RISCV/rv64zhinx-invalid.s
llvm/test/MC/RISCV/rv64zhinx-valid.s
llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
llvm/test/MC/RISCV/rv64zhinxmin-valid.s
llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
Modified:
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv32i-invalid.s
Removed:
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 2b3395b669b86..18de7dcd08f31 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -51,6 +51,11 @@ static const RISCVSupportedExtension SupportedExtensions[] =
{
{"zfhmin", RISCVExtensionVersion{1, 0}},
{"zfh", RISCVExtensionVersion{1, 0}},
+{"zfinx", RISCVExtensionVersion{1, 0}},
+{"zdinx", RISCVExtensionVersion{1, 0}},
+{"zhinxmin", RISCVExtensionVersion{1, 0}},
+{"zhinx", RISCVExtensionVersion{1, 0}},
+
{"zba", RISCVExtensionVersion{1, 0}},
{"zbb", RISCVExtensionVersion{1, 0}},
{"zbc", RISCVExtensionVersion{1, 0}},
@@ -686,6 +691,8 @@ Error RISCVISAInfo::checkDependency() {
bool HasE = Exts.count("e") != 0;
bool HasD = Exts.count("d") != 0;
bool HasF = Exts.count("f") != 0;
+ bool HasZfinx = Exts.count("zfinx") != 0;
+ bool HasZdinx = Exts.count("zdinx") != 0;
bool HasZve32x = Exts.count("zve32x") != 0;
bool HasZve32f = Exts.count("zve32f") != 0;
bool HasZve64d = Exts.count("zve64d") != 0;
@@ -706,17 +713,15 @@ Error RISCVISAInfo::checkDependency() {
return createStringError(errc::invalid_argument,
"d requires f extension to also be specified");
- // FIXME: Consider Zfinx in the future
- if (HasZve32f && !HasF)
+ if (HasZve32f && !HasF && !HasZfinx)
return createStringError(
errc::invalid_argument,
-"zve32f requires f extension to also be specified");
+"zve32f requires f or zfinx extension to also be specified");
- // FIXME: Consider Zdinx in the future
- if (HasZve64d && !HasD)
+ if (HasZve64d && !HasD && !HasZdinx)
return createStringError(
errc::invalid_argument,
-"zve64d requires d extension to also be specified");
+"zve64d requires d or zdinx extension to also be specified");
if (HasZvl && !HasVector)
return createStringError(
@@ -733,6 +738,9 @@ Error RISCVISAInfo::checkDependency() {
static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"};
static const char *ImpliedExtsZfhmin[] = {"f"};
static const char *ImpliedExtsZfh[] = {"f"};
+static const char *ImpliedExtsZdinx[] = {"zfinx"};
+static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
+static const char *ImpliedExtsZhinx[] = {"zfinx"};
static const char *ImpliedExtsZve64d[] = {"zve64f"};
static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
@@ -767,8 +775,11 @@ struct ImpliedExtsEntry {
// Note: The table needs to be sorted by name.
static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"v"}, {ImpliedExtsV}},
+{{"zdinx"}, {ImpliedExtsZdinx}},
{{"zfh"}, {ImpliedExtsZfh}},
{{"zfhmin"}, {ImpliedExtsZfhmin}},
+{{"zhinx"}, {ImpliedExtsZhinx}},
+{{"zhinxmin"}, {ImpliedExtsZhinxmin}},
{{"zk"}, {ImpliedExtsZk}},
{{"zkn"}, {Imp
[llvm-branch-commits] [llvm] 967296b - [RISCV] Fix inline asm errors in zfinx
Author: Shao-Ce SUN
Date: 2022-03-02T14:31:23+08:00
New Revision: 967296bfefee9740b1dfb4644970d776e1b37b5b
URL:
https://github.com/llvm/llvm-project/commit/967296bfefee9740b1dfb4644970d776e1b37b5b
DIFF:
https://github.com/llvm/llvm-project/commit/967296bfefee9740b1dfb4644970d776e1b37b5b.diff
LOG: [RISCV] Fix inline asm errors in zfinx
Patch is from craig.topper's comments in https://reviews.llvm.org/D93298
Added:
llvm/test/CodeGen/RISCV/zfinx-types.ll
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7fb9b7a85..19935caa34dfb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10466,7 +10466,29 @@
RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
}
}
- return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+ std::pair Res =
+ TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+
+ if (Res.second == &RISCV::GPRF32RegClass) {
+if (!Subtarget.is64Bit() || VT == MVT::Other)
+ return std::make_pair(Res.first, &RISCV::GPRRegClass);
+return std::make_pair(0, nullptr);
+ }
+
+ if (Res.second == &RISCV::GPRF64RegClass ||
+ Res.second == &RISCV::GPRPF64RegClass) {
+if (Subtarget.is64Bit() || VT == MVT::Other)
+ return std::make_pair(Res.first, &RISCV::GPRRegClass);
+return std::make_pair(0, nullptr);
+ }
+
+ if (Res.second == &RISCV::GPRF16RegClass) {
+if (VT == MVT::Other)
+ return std::make_pair(Res.first, &RISCV::GPRRegClass);
+return std::make_pair(0, nullptr);
+ }
+
+ return Res;
}
unsigned
diff --git a/llvm/test/CodeGen/RISCV/zfinx-types.ll
b/llvm/test/CodeGen/RISCV/zfinx-types.ll
new file mode 100644
index 0..9cbc7d9ce219b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zfinx-types.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RVZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN: -target-abi=lp64f | FileCheck -check-prefix=RVZFINX %s
+
+define float @test_float(float %x) {
+; RVZFINX-LABEL: test_float:
+; RVZFINX: # %bb.0:
+; RVZFINX-NEXT:.cfi_def_cfa_offset 0
+; RVZFINX-NEXT:li a0, 0
+; RVZFINX-NEXT:#APP
+; RVZFINX-NEXT:mv a0, a0
+; RVZFINX-NEXT:#NO_APP
+; RVZFINX-NEXT:li a0, 0
+; RVZFINX-NEXT:ret
+ %1 = tail call float asm sideeffect alignstack "mv a0, a0",
"={x10},{x10}"(float 0.00e+00)
+ ret float 0.00e+00
+}
___
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[llvm-branch-commits] [llvm] 65d5327 - [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
Author: Shao-Ce SUN
Date: 2022-03-03T14:52:36+08:00
New Revision: 65d53279b1fddeae4bd455d588ea7527aed50bb9
URL:
https://github.com/llvm/llvm-project/commit/65d53279b1fddeae4bd455d588ea7527aed50bb9
DIFF:
https://github.com/llvm/llvm-project/commit/65d53279b1fddeae4bd455d588ea7527aed50bb9.diff
LOG: [RISCV] More correctly ignore Zfinx register classes in
getRegForInlineAsmConstraint.
Until Zfinx is supported in CodeGen we need to convert all Zfinx
register classes to GPR.
Remove the zfinx-types.ll test which didn't test anything meaningful
since -mattr=zfinx isn't implemented completely in llc.
Follow up to D93298.
(cherry picked from commit 6cb42cd6669785f3b611106e1b6b38bbe65733a9)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll
Removed:
llvm/test/CodeGen/RISCV/zfinx-types.ll
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 19935caa34dfb..e7672a7652cdd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10469,24 +10469,13 @@
RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
std::pair Res =
TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
- if (Res.second == &RISCV::GPRF32RegClass) {
-if (!Subtarget.is64Bit() || VT == MVT::Other)
- return std::make_pair(Res.first, &RISCV::GPRRegClass);
-return std::make_pair(0, nullptr);
- }
-
- if (Res.second == &RISCV::GPRF64RegClass ||
- Res.second == &RISCV::GPRPF64RegClass) {
-if (Subtarget.is64Bit() || VT == MVT::Other)
- return std::make_pair(Res.first, &RISCV::GPRRegClass);
-return std::make_pair(0, nullptr);
- }
-
- if (Res.second == &RISCV::GPRF16RegClass) {
-if (VT == MVT::Other)
- return std::make_pair(Res.first, &RISCV::GPRRegClass);
-return std::make_pair(0, nullptr);
- }
+ // If we picked one of the Zfinx register classes, remap it to the GPR class.
+ // FIXME: When Zfinx is supported in CodeGen this will need to take the
+ // Subtarget into account.
+ if (Res.second == &RISCV::GPRF16RegClass ||
+ Res.second == &RISCV::GPRF32RegClass ||
+ Res.second == &RISCV::GPRF64RegClass)
+return std::make_pair(Res.first, &RISCV::GPRRegClass);
return Res;
}
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
b/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
index 37ce0f89e7ec5..2e7ae0847f20f 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
@@ -71,3 +71,37 @@ define double @constraint_f_double_abi_name(double %a)
nounwind {
%2 = tail call double asm "fadd.d $0, $1, $2", "={ft0},{fa1},{fs0}"(double
%a, double %1)
ret double %2
}
+
+define double @constraint_gpr(double %x) {
+; RV32F-LABEL: constraint_gpr:
+; RV32F: # %bb.0:
+; RV32F-NEXT:addi sp, sp, -32
+; RV32F-NEXT:.cfi_def_cfa_offset 32
+; RV32F-NEXT:sw a0, 8(sp)
+; RV32F-NEXT:sw a1, 12(sp)
+; RV32F-NEXT:fld ft0, 8(sp)
+; RV32F-NEXT:fsd ft0, 24(sp)
+; RV32F-NEXT:lw a0, 24(sp)
+; RV32F-NEXT:lw a1, 28(sp)
+; RV32F-NEXT:#APP
+; RV32F-NEXT:mv a0, a0
+; RV32F-NEXT:#NO_APP
+; RV32F-NEXT:sw a1, 20(sp)
+; RV32F-NEXT:sw a0, 16(sp)
+; RV32F-NEXT:fld ft0, 16(sp)
+; RV32F-NEXT:fsd ft0, 8(sp)
+; RV32F-NEXT:lw a0, 8(sp)
+; RV32F-NEXT:lw a1, 12(sp)
+; RV32F-NEXT:addi sp, sp, 32
+; RV32F-NEXT:ret
+;
+; RV64F-LABEL: constraint_gpr:
+; RV64F: # %bb.0:
+; RV64F-NEXT:.cfi_def_cfa_offset 0
+; RV64F-NEXT:#APP
+; RV64F-NEXT:mv a0, a0
+; RV64F-NEXT:#NO_APP
+; RV64F-NEXT:ret
+ %1 = tail call double asm sideeffect alignstack "mv $0, $1",
"={x10},{x10}"(double %x)
+ ret double %1
+}
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
index 07d6d1a365cd8..d6df31e878313 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
@@ -63,3 +63,23 @@ define float @constraint_f_float_abi_name(float %a) nounwind
{
%2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a,
float %1)
ret float %2
}
+
+define float @constraint_gpr(float %x) {
+; RV32F-LABEL: constraint_gpr:
+; RV32F: # %bb.0:
+; RV32F-NEXT:.cfi_def_cfa_offset 0
+; RV32F-NEXT:#APP
+; RV32F-NEXT:mv a0, a0
+; RV32F-NEXT:#NO_APP
+; RV32F-NEXT:ret
+;
+; RV64F-LABEL: constraint_gpr:
+; RV64F: # %bb.0:
+; RV64F-NEXT:.cfi_def_cfa_offset 0
+; RV64F-NEXT:#APP
+; RV64F-NEXT:mv a0, a0
+; RV64F-NEXT:#NO_APP
+; RV64F-NEXT:ret
+ %1 = t
