from:"Lu Weining via llvm\-branch\-commits"

[llvm-branch-commits] [lld][ELF][LoongArch] Add support for R_LARCH_LE_{HI20, ADD, LO12}_R relocations (PR #99486)

2024-07-19 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/99486
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld][ELF][LoongArch] Support R_LARCH_TLS_{LD, GD, DESC}_PCREL_S2 (PR #100105)

2024-07-23 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM. Hope this can be merged into 19.x.

https://github.com/llvm/llvm-project/pull/100105
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld][ELF][LoongArch] Support R_LARCH_TLS_{LD, GD, DESC}_PCREL_S2 (PR #100105)

2024-07-23 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining milestoned 
https://github.com/llvm/llvm-project/pull/100105
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [LoongArch] Fix codegen for ISD::ROTR (#100292) (PR #100297)

2024-07-23 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/100297
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] PR for llvm/llvm-project#80789 (PR #80790)

2024-02-05 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

> @SixWeining What do you think about merging this PR to the release branch?

Looks good to me. As LoongArch gcc/binutils have began generating relax 
relocations for about 1 year, lld needs this PR so that it can link fundamental 
system objects (such as Scrt1.o). People have reached a consensus about this 
cherry-picking (See https://github.com/llvm/llvm-project/pull/78692).

https://github.com/llvm/llvm-project/pull/80790
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [llvm][LoongArch] Improve loongarch_lasx_xvpermi_q instrinsic (#82984) (PR #83540)

2024-03-07 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

> I have some doubt about this change.
> 
> To me if the user requests `xvpermi.q` via the `loongarch_lasx_xvpermi_q` 
> intrinsic, we should give her/him the `xvpermi.q` instruction. If (s)he is 
> passing an invalid operand then (s)he is invoking the undefined behavior 
> herself/himself and we don't need to guarantee a thing.
> 
> So to me we should not merge this and we should revert this change for main. 
> Or am I missing something? @xen0n @heiher @SixWeining @MaskRay

Yes, it can be argued. But I know gcc has similar change.

https://github.com/llvm/llvm-project/pull/83540
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [llvm][LoongArch] Improve loongarch_lasx_xvpermi_q instrinsic (#82984) (PR #83540)

2024-03-10 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining closed 
https://github.com/llvm/llvm-project/pull/83540
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [llvm][LoongArch] Improve loongarch_lasx_xvpermi_q instrinsic (#82984) (PR #83540)

2024-03-10 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

> For the record, based on the principle of "explicit is better than implicit" 
> that generally holds, I'd favor an approach where such 
> compile-time-verifiable out-of-range operands are given compile-time errors, 
> or we should just pass through the value unmodified. Otherwise the intrinsic 
> would have to carry the workaround effectively forever, and we could find 
> ourselves trapped if later micro-architectures actually start to make use of 
> the currently cleared bits.

Makes sense. After discussion with gcc-loongarch team, we both decide to revert 
this change. Thanks.

https://github.com/llvm/llvm-project/pull/83540
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/18.x: [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100) (PR #84715)

2024-03-11 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/84715
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [llvm] release/18.x: [LoongArch] Use R_LARCH_ALIGN with section symbol (#84741) (PR #88891)

2024-04-16 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

Binutils has made same change and to keep compatibility we have to cherry-pick 
it to 18.x.

https://github.com/llvm/llvm-project/pull/88891
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [LoongArch][Codegen] Add support for TLSDESC (PR #90159)

2024-04-29 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining edited 
https://github.com/llvm/llvm-project/pull/90159
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [LoongArch][Codegen] Add support for TLSDESC (PR #90159)

2024-04-29 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM except a nit.

https://github.com/llvm/llvm-project/pull/90159
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [LoongArch][Codegen] Add support for TLSDESC (PR #90159)

2024-04-29 Thread Lu Weining via llvm-branch-commits



@@ -737,7 +737,7 @@ bool tools::isTLSDESCEnabled(const ToolChain &TC,
   StringRef V = A->getValue();
   bool SupportedArgument = false, EnableTLSDESC = false;
   bool Unsupported = !Triple.isOSBinFormatELF();
-  if (Triple.isRISCV()) {
+  if (Triple.isRISCV() || Triple.isLoongArch()) {

SixWeining wrote:

Is it better to sort alphabetically?

https://github.com/llvm/llvm-project/pull/90159
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)

2024-05-15 Thread Lu Weining via llvm-branch-commits



@@ -49,63 +50,127 @@ static ABI checkABIStandardized(ABI Abi) {
   return Abi;
 }
 
-ABI computeTargetABI(const Triple &TT, StringRef ABIName) {
-  ABI ArgProvidedABI = getTargetABI(ABIName);
+static ABI getTripleABI(const Triple &TT) {
   bool Is64Bit = TT.isArch64Bit();
   ABI TripleABI;
-
-  // Figure out the ABI explicitly requested via the triple's environment type.
   switch (TT.getEnvironment()) {
   case llvm::Triple::EnvironmentType::GNUSF:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64S : LoongArchABI::ABI_ILP32S;
+TripleABI = Is64Bit ? ABI_LP64S : ABI_ILP32S;
 break;
   case llvm::Triple::EnvironmentType::GNUF32:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64F : LoongArchABI::ABI_ILP32F;
+TripleABI = Is64Bit ? ABI_LP64F : ABI_ILP32F;
 break;
-
   // Let the fallback case behave like {ILP32,LP64}D.
   case llvm::Triple::EnvironmentType::GNUF64:
   default:
-TripleABI = Is64Bit ? LoongArchABI::ABI_LP64D : LoongArchABI::ABI_ILP32D;
+TripleABI = Is64Bit ? ABI_LP64D : ABI_ILP32D;
 break;
   }
+  return TripleABI;
+}
 
-  switch (ArgProvidedABI) {
-  case LoongArchABI::ABI_Unknown:
-// Fallback to the triple-implied ABI if ABI name is not specified or
-// invalid.
-if (!ABIName.empty())
-  errs() << "'" << ABIName
- << "' is not a recognized ABI for this target, ignoring and using 
"
-"triple-implied ABI\n";
-return checkABIStandardized(TripleABI);
+ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
+ StringRef ABIName) {
+  bool Is64Bit = TT.isArch64Bit();
+  ABI ArgProvidedABI = getTargetABI(ABIName);
+  ABI TripleABI = getTripleABI(TT);
+
+  auto GetFeatureABI = [=]() {

SixWeining wrote:

Maybe move it to where it is called (i.e. line 173) for better readability?

https://github.com/llvm/llvm-project/pull/92223
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [LoongArch] Refactor LoongArchABI::computeTargetABI (PR #92223)

2024-05-16 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/92223
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [LoongArch] Use sign extend for i32 arguments in makeLibCall on LA64 (PR #92375)

2024-05-16 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM. I think this fix should be check-picked to 18.x.

https://github.com/llvm/llvm-project/pull/92375
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [LoongArch] Suppress the unnecessary extensions for arguments in makeLibCall (PR #92376)

2024-05-16 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/92376
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [llvm] release/18.x: [LoongArch] Use R_LARCH_ALIGN with section symbol (#84741) (PR #88891)

2024-05-17 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining closed 
https://github.com/llvm/llvm-project/pull/88891
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [llvm] release/18.x: [LoongArch] Use R_LARCH_ALIGN with section symbol (#84741) (PR #88891)

2024-05-17 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

This will be reverted in main branch 
(https://github.com/llvm/llvm-project/pull/92584). So close it.

https://github.com/llvm/llvm-project/pull/88891
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Optimize for immediate value materialization using BSTRINS_D instruction (PR #106332)

2024-08-29 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining closed 
https://github.com/llvm/llvm-project/pull/106332
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [LoongArch] Codegen for concat_vectors with LASX (PR #107948)

2024-09-09 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/107948
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [LoongArch][ISel] Check the number of sign bits in `PatGprGpr_32` (#107432) (PR #107945)

2024-09-10 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

> @heiher @SixWeining Do you guys have a plan to backport #107971?

Yes, I think #107971 should also be backported to 19.x.

https://github.com/llvm/llvm-project/pull/107945
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-05 Thread Lu Weining via llvm-branch-commits



@@ -0,0 +1,672 @@
+//===-- 
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include 
+#include 
+#include 
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)   
\
+  {
\
+  DEFINE_REG_NAME(dwarf_num),  
\
+  DEFINE_REG_NAME_STR(nullptr),
\
+  0,   
\
+  0,   
\
+  eEncodingInvalid,
\
+  eFormatDefault,  
\
+  {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num}, 
\
+  nullptr, 
\
+  nullptr, 
\
+  nullptr, 
\
+  }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+  DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+  r0,
+  ra,
+  r1 = ra,
+  r2,
+  sp,
+  r3 = sp,
+  r4,
+  r5,
+  r6,
+  r7,
+  r8,
+  r9,
+  r10,
+  r11,
+  r12,
+  r13,
+  r14,
+  r15,
+  r16,
+  r17,
+  r18,
+  r19,
+  r20,
+  r21,
+  fp,
+  r22 = fp,
+  r23,
+  r24,
+  r25,
+  r26,
+  r27,
+  r28,
+  r29,
+  r30,
+  r31,
+  pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+  count = dwarf::g_register_infos.size();
+  return dwarf::g_register_infos.data();
+}
+
+//--
+// Static Functions
+//--
+
+ABISP
+ABISysV_loongarch::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {
+  llvm::Triple::ArchType machine = arch.GetTriple().getAr

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-05 Thread Lu Weining via llvm-branch-commits



@@ -0,0 +1,672 @@
+//===-- 
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include 
+#include 
+#include 
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)   
\
+  {
\
+  DEFINE_REG_NAME(dwarf_num),  
\
+  DEFINE_REG_NAME_STR(nullptr),
\
+  0,   
\
+  0,   
\
+  eEncodingInvalid,
\
+  eFormatDefault,  
\
+  {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num}, 
\
+  nullptr, 
\
+  nullptr, 
\
+  nullptr, 
\
+  }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+  DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+  r0,
+  ra,
+  r1 = ra,
+  r2,
+  sp,
+  r3 = sp,
+  r4,
+  r5,
+  r6,
+  r7,
+  r8,
+  r9,
+  r10,
+  r11,
+  r12,
+  r13,
+  r14,
+  r15,
+  r16,
+  r17,
+  r18,
+  r19,
+  r20,
+  r21,
+  fp,
+  r22 = fp,
+  r23,
+  r24,
+  r25,
+  r26,
+  r27,
+  r28,
+  r29,
+  r30,
+  r31,
+  pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+  count = dwarf::g_register_infos.size();
+  return dwarf::g_register_infos.data();
+}
+
+//--
+// Static Functions
+//--
+
+ABISP
+ABISysV_loongarch::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {
+  llvm::Triple::ArchType machine = arch.GetTriple().getAr

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-05 Thread Lu Weining via llvm-branch-commits



@@ -0,0 +1,672 @@
+//===-- 
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include 
+#include 
+#include 
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)   
\
+  {
\
+  DEFINE_REG_NAME(dwarf_num),  
\
+  DEFINE_REG_NAME_STR(nullptr),
\
+  0,   
\
+  0,   
\
+  eEncodingInvalid,
\
+  eFormatDefault,  
\
+  {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num}, 
\
+  nullptr, 
\
+  nullptr, 
\
+  nullptr, 
\
+  }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+  DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+  r0,
+  ra,
+  r1 = ra,
+  r2,
+  sp,
+  r3 = sp,
+  r4,
+  r5,
+  r6,
+  r7,
+  r8,
+  r9,
+  r10,
+  r11,
+  r12,
+  r13,
+  r14,
+  r15,
+  r16,
+  r17,
+  r18,
+  r19,
+  r20,
+  r21,
+  fp,
+  r22 = fp,
+  r23,
+  r24,
+  r25,
+  r26,
+  r27,
+  r28,
+  r29,
+  r30,
+  r31,
+  pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+  count = dwarf::g_register_infos.size();
+  return dwarf::g_register_infos.data();
+}
+
+//--
+// Static Functions
+//--
+
+ABISP
+ABISysV_loongarch::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {
+  llvm::Triple::ArchType machine = arch.GetTriple().getAr

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-05 Thread Lu Weining via llvm-branch-commits



@@ -0,0 +1,672 @@
+//===-- 
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include 
+#include 
+#include 
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)   
\
+  {
\
+  DEFINE_REG_NAME(dwarf_num),  
\
+  DEFINE_REG_NAME_STR(nullptr),
\
+  0,   
\
+  0,   
\
+  eEncodingInvalid,
\
+  eFormatDefault,  
\
+  {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num}, 
\
+  nullptr, 
\
+  nullptr, 
\
+  nullptr, 
\
+  }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+  DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+  r0,
+  ra,
+  r1 = ra,
+  r2,
+  sp,
+  r3 = sp,
+  r4,
+  r5,
+  r6,
+  r7,
+  r8,
+  r9,
+  r10,
+  r11,
+  r12,
+  r13,
+  r14,
+  r15,
+  r16,
+  r17,
+  r18,
+  r19,
+  r20,
+  r21,
+  fp,
+  r22 = fp,
+  r23,
+  r24,
+  r25,
+  r26,
+  r27,
+  r28,
+  r29,
+  r30,
+  r31,
+  pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+  count = dwarf::g_register_infos.size();
+  return dwarf::g_register_infos.data();
+}
+
+//--
+// Static Functions
+//--
+
+ABISP
+ABISysV_loongarch::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {
+  llvm::Triple::ArchType machine = arch.GetTriple().getAr

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-05 Thread Lu Weining via llvm-branch-commits



@@ -0,0 +1,672 @@
+//===-- 
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include 
+#include 
+#include 
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)   
\
+  {
\
+  DEFINE_REG_NAME(dwarf_num),  
\
+  DEFINE_REG_NAME_STR(nullptr),
\
+  0,   
\
+  0,   
\
+  eEncodingInvalid,
\
+  eFormatDefault,  
\
+  {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num}, 
\
+  nullptr, 
\
+  nullptr, 
\
+  nullptr, 
\
+  }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+  DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+  r0,
+  ra,
+  r1 = ra,
+  r2,
+  sp,
+  r3 = sp,
+  r4,
+  r5,
+  r6,
+  r7,
+  r8,
+  r9,
+  r10,
+  r11,
+  r12,
+  r13,
+  r14,
+  r15,
+  r16,
+  r17,
+  r18,
+  r19,
+  r20,
+  r21,
+  fp,
+  r22 = fp,
+  r23,
+  r24,
+  r25,
+  r26,
+  r27,
+  r28,
+  r29,
+  r30,
+  r31,
+  pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;

SixWeining wrote:

Should we take floating point registers into account? Or we should mention 
somewhere that only GPRs are supported currently.

https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-05 Thread Lu Weining via llvm-branch-commits



@@ -0,0 +1,104 @@
+//===-- ABISysV_loongarch.h -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+#define LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+
+// Other libraries and framework includes
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_loongarch : public lldb_private::RegInfoBasedABI {
+public:
+  ~ABISysV_loongarch() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+  lldb::addr_t functionAddress,
+  lldb::addr_t returnAddress,
+  llvm::ArrayRef args) const override;
+
+  bool GetArgumentValues(lldb_private::Thread &thread,
+ lldb_private::ValueList &values) const override;
+
+  lldb_private::Status
+  SetReturnValueObject(lldb::StackFrameSP &frame_sp,
+   lldb::ValueObjectSP &new_value) override;
+
+  lldb::ValueObjectSP
+  GetReturnValueObjectImpl(lldb_private::Thread &thread,
+   lldb_private::CompilerType &type) const override;
+
+  bool
+  CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan) 
override;
+
+  bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override;
+
+  bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+  bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 16 byte aligned.
+return (cfa & 0xfull) == 0;
+  }
+
+  void SetIsLA64(bool is_la64) { m_is_la64 = is_la64; }
+
+  bool CodeAddressIsValid(lldb::addr_t pc) override {
+// Code address must be 4 byte aligned.
+if (pc & (4ull - 1ull))
+  return false;
+
+return true;
+  }
+
+  const lldb_private::RegisterInfo *
+  GetRegisterInfoArray(uint32_t &count) override;
+
+  //--
+  // Static Functions
+  //--
+
+  static void Initialize();
+
+  static void Terminate();
+
+  static lldb::ABISP CreateInstance(lldb::ProcessSP process_sp,
+const lldb_private::ArchSpec &arch);
+
+  static llvm::StringRef GetPluginNameStatic() { return "sysv-loongarch"; }
+
+  //--
+  // PluginInterface protocol
+  //--
+
+  llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
+
+protected:
+  void AugmentRegisterInfo(
+  std::vector ®s) override;
+
+  bool RegisterIsCalleeSaved(const lldb_private::RegisterInfo *reg_info);
+
+private:
+  lldb::ValueObjectSP
+  GetReturnValueObjectSimple(lldb_private::Thread &thread,
+ lldb_private::CompilerType &ast_type) const;
+
+  using lldb_private::RegInfoBasedABI::RegInfoBasedABI; // Call CreateInstance
+// instead.
+  bool m_is_la64; // true if target is loongarch64; false if target is

SixWeining wrote:

Seems the comments are redundant.

https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-05 Thread Lu Weining via llvm-branch-commits



@@ -0,0 +1,672 @@
+//===-- 
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include 
+#include 
+#include 
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)   
\
+  {
\
+  DEFINE_REG_NAME(dwarf_num),  
\
+  DEFINE_REG_NAME_STR(nullptr),
\
+  0,   
\
+  0,   
\
+  eEncodingInvalid,
\
+  eFormatDefault,  
\
+  {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num}, 
\
+  nullptr, 
\
+  nullptr, 
\
+  nullptr, 
\
+  }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+  DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+  r0,
+  ra,
+  r1 = ra,

SixWeining wrote:

```suggestion
  r1,
  ra = r1,
```

https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-05 Thread Lu Weining via llvm-branch-commits



@@ -0,0 +1,672 @@
+//===-- 
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include 
+#include 
+#include 
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)   
\
+  {
\
+  DEFINE_REG_NAME(dwarf_num),  
\
+  DEFINE_REG_NAME_STR(nullptr),
\
+  0,   
\
+  0,   
\
+  eEncodingInvalid,
\
+  eFormatDefault,  
\
+  {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num}, 
\
+  nullptr, 
\
+  nullptr, 
\
+  nullptr, 
\
+  }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+  DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+  r0,
+  ra,
+  r1 = ra,
+  r2,
+  sp,
+  r3 = sp,
+  r4,
+  r5,
+  r6,
+  r7,
+  r8,
+  r9,
+  r10,
+  r11,
+  r12,
+  r13,
+  r14,
+  r15,
+  r16,
+  r17,
+  r18,
+  r19,
+  r20,
+  r21,
+  fp,
+  r22 = fp,
+  r23,
+  r24,
+  r25,
+  r26,
+  r27,
+  r28,
+  r29,
+  r30,
+  r31,
+  pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+  count = dwarf::g_register_infos.size();
+  return dwarf::g_register_infos.data();
+}
+
+//--
+// Static Functions
+//--
+
+ABISP
+ABISysV_loongarch::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {

SixWeining wrote:

Seems this is not a st

[llvm-branch-commits] [LoongArch] Avoid indirect branch jumps using the ra register (PR #115424)

2024-11-10 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/115424
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [LoongArch] Eliminate the redundant sign extension of division (#107971) (PR #109125)

2024-09-23 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

lgtm

https://github.com/llvm/llvm-project/pull/109125
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [LoongArch] Fix the assertion for atomic store with 'ptr' type (PR #109915)

2024-09-24 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/109915
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-06 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining deleted 
https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-06 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM. But should land after #114741.

https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)

2024-11-06 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining deleted 
https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Optimize vector bitreverse using scalar bitrev and vshuf4i (PR #118054)

2024-12-01 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/118054
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb][Process] Introduce LoongArch64 hw break/watchpoint support (PR #118770)

2024-12-11 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/118770
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Fix GOT usage for `non-dso_local` function calls in large code model (PR #117134)

2024-11-21 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/117134
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Relax call36/tail36: R_LARCH_CALL36 (PR #123576)

2025-02-12 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/123576
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Relax TLS LE/GD/LD (PR #123600)

2025-02-14 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/123600
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-20 Thread Lu Weining via llvm-branch-commits



@@ -1002,6 +1008,89 @@ static bool relax(Ctx &ctx, InputSection &sec) {
   return changed;
 }
 
+// Convert TLS IE to LE in the normal or medium code model.
+// Original code sequence:
+//  * pcalau12i $a0, %ie_pc_hi20(sym)
+//  * ld.d  $a0, $a0, %ie_pc_lo12(sym)
+//
+// The code sequence converted is as follows:
+//  * lu12i.w   $a0, %le_hi20(sym)  # le_hi20 != 0, otherwise NOP
+//  * ori   $a0, src, %le_lo12(sym) # le_hi20 != 0, src = $a0,
+//  # otherwise,src = $zero
+//
+// When relaxation enables, redundant NOPs can be removed.
+void LoongArch::tlsIeToLe(uint8_t *loc, const Relocation &rel,

SixWeining wrote:

This can be defined as a static function.

https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-20 Thread Lu Weining via llvm-branch-commits



@@ -1375,14 +1375,20 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr 
expr, RelType type,
 return 1;
   }
 
+  // LoongArch support IE to LE optimization in non-extreme code model.

SixWeining wrote:

```suggestion
  // LoongArch supports IE to LE optimization in non-extreme code model.
```

https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-20 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining commented:

Seem that the commit message has some typo.

```
The code sequence converted is as follows:

lu12i.w $a0, %ie_pc_hi20(sym) # le_hi20 != 0, otherwise NOP
ori $a0 $a0, %ie_pc_lo12(sym)
```

`%ie_pc_hi20` should be `%le_hi20`, right?

And the source register of `ori` is `$zero` if `%le_hi20 == 0`.

https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-20 Thread Lu Weining via llvm-branch-commits



@@ -1002,6 +1008,87 @@ static bool relax(Ctx &ctx, InputSection &sec) {
   return changed;
 }
 
+// Convert TLS IE to LE in the normal or medium code model.
+// Original code sequence:
+//  * pcalau12i $a0, %ie_pc_hi20(sym)
+//  * ld.d  $a0, $a0, %ie_pc_lo12(sym)
+//
+// The code sequence converted is as follows:
+//  * lu12i.w   $a0, %le_hi20(sym)  # le_hi20 != 0, otherwise NOP
+//  * ori $a0   $a0, %le_lo12(sym)
+//
+// When relaxation enables, redundant NOPs can be removed.
+void LoongArch::tlsIeToLe(uint8_t *loc, const Relocation &rel,
+  uint64_t val) const {
+  assert(isInt<32>(val) &&
+ "val exceeds the range of medium code model in tlsIeToLe");
+
+  bool isUInt12 = isUInt<12>(val);
+  const uint32_t currInsn = read32le(loc);
+  switch (rel.type) {
+  case R_LARCH_TLS_IE_PC_HI20:
+if (isUInt12)
+  write32le(loc, insn(ANDI, R_ZERO, R_ZERO, 0)); // nop
+else
+  write32le(loc, insn(LU12I_W, getD5(currInsn), extractBits(val, 31, 12),
+  0)); // lu12i.w $a0, %le_hi20
+break;
+  case R_LARCH_TLS_IE_PC_LO12:
+if (isUInt12)
+  write32le(loc, insn(ORI, getD5(currInsn), R_ZERO,
+  val)); // ori $a0, $r0, %le_lo12
+else
+  write32le(loc, insn(ORI, getD5(currInsn), getJ5(currInsn),
+  lo12(val))); // ori $a0, $a0, %le_lo12
+break;
+  }
+}
+
+void LoongArch::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
+  const unsigned bits = ctx.arg.is64 ? 64 : 32;
+  uint64_t secAddr = sec.getOutputSection()->addr;
+  if (auto *s = dyn_cast(&sec))
+secAddr += s->outSecOff;
+  else if (auto *ehIn = dyn_cast(&sec))
+secAddr += ehIn->getParent()->outSecOff;
+  bool isExtreme = false;
+  const MutableArrayRef relocs = sec.relocs();
+  for (size_t i = 0, size = relocs.size(); i != size; ++i) {
+Relocation &rel = relocs[i];
+uint8_t *loc = buf + rel.offset;
+uint64_t val = SignExtend64(
+sec.getRelocTargetVA(ctx, rel, secAddr + rel.offset), bits);
+
+switch (rel.expr) {
+case R_RELAX_HINT:
+  continue;
+case R_RELAX_TLS_IE_TO_LE:
+  if (rel.type == R_LARCH_TLS_IE_PC_HI20) {
+// LoongArch does not support IE to LE optimize in the extreme code

SixWeining wrote:

```suggestion
// LoongArch does not support IE to LE optimization in the extreme code
```

https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-20 Thread Lu Weining via llvm-branch-commits



@@ -1375,14 +1375,20 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr 
expr, RelType type,
 return 1;
   }
 
+  // LoongArch support IE to LE optimization in non-extreme code model.
+  bool execOptimizeInLoongArch =
+  ctx.arg.emachine == EM_LOONGARCH &&
+  (type == R_LARCH_TLS_IE_PC_HI20 || type == R_LARCH_TLS_IE_PC_LO12);

SixWeining wrote:

R_LARCH_TLS_IE_PC_HI20 and R_LARCH_TLS_IE_PC_LO12 are also used by the extreme 
code model. Is this condition reliable?

https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-20 Thread Lu Weining via llvm-branch-commits



@@ -0,0 +1,70 @@
+# REQUIRES: loongarch
+## Test LA64 IE -> LE in various cases.
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch64 -mattr=+relax %s -o %t.o
+
+## FIXME: IE relaxation has not yet been implemented.
+## --relax/--no-relax has the same result. Also check --emit-relocs.
+# RUN: ld.lld --emit-relocs %t.o -o %t
+# RUN: llvm-readelf -x .got %t 2>&1 | FileCheck --check-prefix=LE-GOT %s
+# RUN: llvm-objdump -dr --no-show-raw-insn %t | FileCheck --check-prefixes=LE 
%s
+
+# RUN: ld.lld --emit-relocs --no-relax %t.o -o %t.norelax
+# RUN: llvm-readelf -x .got %t.norelax 2>&1 | FileCheck --check-prefix=LE-GOT 
%s
+# RUN: llvm-objdump -dr --no-show-raw-insn %t.norelax | FileCheck 
--check-prefixes=LE %s
+
+# LE-GOT: could not find section '.got'
+
+# a@tprel = st_value(a) = 0xfff
+# b@tprel = st_value(a) = 0x1000
+# LE:  20158: nop
+# LE-NEXT:  R_LARCH_TLS_IE_PC_HI20 a
+# LE-NEXT:  R_LARCH_RELAX   *ABS*
+# LE-NEXT:ori $a0, $zero, 4095
+# LE-NEXT:  R_LARCH_TLS_IE_PC_LO12 a
+# LE-NEXT:  R_LARCH_RELAX   *ABS*
+# LE-NEXT:add.d   $a0, $a0, $tp
+# LE-NEXT: 20164: lu12i.w $a1, 1
+# LE-NEXT:  R_LARCH_TLS_IE_PC_HI20 b
+# LE-NEXT:ori $a1, $a1, 0
+# LE-NEXT:  R_LARCH_TLS_IE_PC_LO12 b
+# LE-NEXT:add.d   $a1, $a1, $tp
+# LE-NEXT: 20170: nop
+# LE-NEXT:  R_LARCH_TLS_IE_PC_HI20 a
+# LE-NEXT:  R_LARCH_RELAX   *ABS*
+# LE-NEXT:lu12i.w $a3, 1
+# LE-NEXT:  R_LARCH_TLS_IE_PC_HI20 b
+# LE-NEXT:  R_LARCH_RELAX   *ABS*
+# LE-NEXT:ori $a2, $zero, 4095
+# LE-NEXT:  R_LARCH_TLS_IE_PC_LO12 a
+# LE-NEXT:ori $a3, $a3, 0
+# LE-NEXT:  R_LARCH_TLS_IE_PC_LO12 b
+# LE-NEXT:add.d   $a2, $a2, $tp
+# LE-NEXT:add.d   $a3, $a3, $tp
+
+la.tls.ie $a0, a# relax
+add.d $a0, $a0, $tp
+
+# PCALAU12I does not have R_LARCH_RELAX. No relaxation.
+pcalau12i $a1, %ie_pc_hi20(b)
+ld.d $a1, $a1, %ie_pc_lo12(b)
+add.d $a1, $a1, $tp
+
+# Test instructions are interleaved.
+# PCALAU12I has an R_LARCH_RELAX. We preform relaxation.

SixWeining wrote:

```suggestion
# PCALAU12I has an R_LARCH_RELAX. We perform relaxation.
```

https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-20 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining edited 
https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-20 Thread Lu Weining via llvm-branch-commits



@@ -1002,6 +1008,87 @@ static bool relax(Ctx &ctx, InputSection &sec) {
   return changed;
 }
 
+// Convert TLS IE to LE in the normal or medium code model.
+// Original code sequence:
+//  * pcalau12i $a0, %ie_pc_hi20(sym)
+//  * ld.d  $a0, $a0, %ie_pc_lo12(sym)
+//
+// The code sequence converted is as follows:
+//  * lu12i.w   $a0, %le_hi20(sym)  # le_hi20 != 0, otherwise NOP
+//  * ori $a0   $a0, %le_lo12(sym)
+//
+// When relaxation enables, redundant NOPs can be removed.
+void LoongArch::tlsIeToLe(uint8_t *loc, const Relocation &rel,
+  uint64_t val) const {
+  assert(isInt<32>(val) &&
+ "val exceeds the range of medium code model in tlsIeToLe");
+
+  bool isUInt12 = isUInt<12>(val);
+  const uint32_t currInsn = read32le(loc);
+  switch (rel.type) {
+  case R_LARCH_TLS_IE_PC_HI20:
+if (isUInt12)
+  write32le(loc, insn(ANDI, R_ZERO, R_ZERO, 0)); // nop
+else
+  write32le(loc, insn(LU12I_W, getD5(currInsn), extractBits(val, 31, 12),
+  0)); // lu12i.w $a0, %le_hi20
+break;
+  case R_LARCH_TLS_IE_PC_LO12:
+if (isUInt12)
+  write32le(loc, insn(ORI, getD5(currInsn), R_ZERO,
+  val)); // ori $a0, $r0, %le_lo12
+else
+  write32le(loc, insn(ORI, getD5(currInsn), getJ5(currInsn),
+  lo12(val))); // ori $a0, $a0, %le_lo12
+break;
+  }
+}
+
+void LoongArch::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
+  const unsigned bits = ctx.arg.is64 ? 64 : 32;
+  uint64_t secAddr = sec.getOutputSection()->addr;
+  if (auto *s = dyn_cast(&sec))
+secAddr += s->outSecOff;
+  else if (auto *ehIn = dyn_cast(&sec))
+secAddr += ehIn->getParent()->outSecOff;
+  bool isExtreme = false;
+  const MutableArrayRef relocs = sec.relocs();
+  for (size_t i = 0, size = relocs.size(); i != size; ++i) {
+Relocation &rel = relocs[i];
+uint8_t *loc = buf + rel.offset;
+uint64_t val = SignExtend64(
+sec.getRelocTargetVA(ctx, rel, secAddr + rel.offset), bits);
+
+switch (rel.expr) {
+case R_RELAX_HINT:
+  continue;
+case R_RELAX_TLS_IE_TO_LE:
+  if (rel.type == R_LARCH_TLS_IE_PC_HI20) {
+// LoongArch does not support IE to LE optimize in the extreme code
+// model. In this case, the relocs are as follows:
+//
+//  * i   -- R_LARCH_TLS_IE_PC_HI20
+//  * i+1 -- R_LARCH_TLS_IE_PC_LO12
+//  * i+2 -- R_LARCH_TLS_IE64_PC_LO20
+//  * i+3 -- R_LARCH_TLS_IE64_PC_HI12
+isExtreme =
+(i + 2 < size && relocs[i + 2].type == R_LARCH_TLS_IE64_PC_LO20);
+  }
+  if (isExtreme) {
+rel.expr = getRelExpr(rel.type, *rel.sym, loc);
+val = SignExtend64(sec.getRelocTargetVA(ctx, rel, secAddr + 
rel.offset),
+   bits);
+relocateNoSym(loc, rel.type, val);
+  } else
+tlsIeToLe(loc, rel, val);

SixWeining wrote:

Use braces for the `else if` and `else` block to keep it uniform with the `if` 
block. See: 
https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements

```suggestion
  } else {
tlsIeToLe(loc, rel, val);
  }
```

https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-20 Thread Lu Weining via llvm-branch-commits



@@ -1002,6 +1008,87 @@ static bool relax(Ctx &ctx, InputSection &sec) {
   return changed;
 }
 
+// Convert TLS IE to LE in the normal or medium code model.
+// Original code sequence:
+//  * pcalau12i $a0, %ie_pc_hi20(sym)
+//  * ld.d  $a0, $a0, %ie_pc_lo12(sym)
+//
+// The code sequence converted is as follows:
+//  * lu12i.w   $a0, %le_hi20(sym)  # le_hi20 != 0, otherwise NOP
+//  * ori $a0   $a0, %le_lo12(sym)
+//
+// When relaxation enables, redundant NOPs can be removed.
+void LoongArch::tlsIeToLe(uint8_t *loc, const Relocation &rel,
+  uint64_t val) const {
+  assert(isInt<32>(val) &&
+ "val exceeds the range of medium code model in tlsIeToLe");
+
+  bool isUInt12 = isUInt<12>(val);
+  const uint32_t currInsn = read32le(loc);
+  switch (rel.type) {
+  case R_LARCH_TLS_IE_PC_HI20:
+if (isUInt12)
+  write32le(loc, insn(ANDI, R_ZERO, R_ZERO, 0)); // nop
+else
+  write32le(loc, insn(LU12I_W, getD5(currInsn), extractBits(val, 31, 12),
+  0)); // lu12i.w $a0, %le_hi20
+break;
+  case R_LARCH_TLS_IE_PC_LO12:
+if (isUInt12)
+  write32le(loc, insn(ORI, getD5(currInsn), R_ZERO,
+  val)); // ori $a0, $r0, %le_lo12

SixWeining wrote:

```suggestion
  val)); // ori $a0, $zero, %le_lo12
```

https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-20 Thread Lu Weining via llvm-branch-commits



@@ -1002,6 +1008,87 @@ static bool relax(Ctx &ctx, InputSection &sec) {
   return changed;
 }
 
+// Convert TLS IE to LE in the normal or medium code model.
+// Original code sequence:
+//  * pcalau12i $a0, %ie_pc_hi20(sym)
+//  * ld.d  $a0, $a0, %ie_pc_lo12(sym)
+//
+// The code sequence converted is as follows:
+//  * lu12i.w   $a0, %le_hi20(sym)  # le_hi20 != 0, otherwise NOP
+//  * ori $a0   $a0, %le_lo12(sym)

SixWeining wrote:

If `le_hi20` == 0, the source register of `ori` should be `$zero`, right?

https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Pre-commit test for fixing tls-le symbol type (PR #132361)

2025-04-05 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/132361
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb] release/20.x: [LLDB][LoongArch] Fix build errors about NT_LOONGARCH_HW_{BREAK, WATCH} (#126020) (PR #134479)

2025-04-06 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/134479
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Backport/20.x: [LoongArch] Fix the type of tls-le symbols (PR #133027)

2025-03-25 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/133027
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Move fix-tle-le-sym-type test to test/MC. NFC (#133839) (PR #134014)

2025-04-14 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

Sorry I missed it. LGTM.

https://github.com/llvm/llvm-project/pull/134014
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Relax TLSDESC code sequence (PR #123677)

2025-02-19 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

cc @xen0n for review

https://github.com/llvm/llvm-project/pull/123677
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Relax TLSDESC code sequence (PR #123677)

2025-02-19 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining commented:

Actually the `FIXME` in commit message is `TODO`, right?

https://github.com/llvm/llvm-project/pull/123677
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Support TLSDESC GD/LD to IE/LE (PR #123715)

2025-02-19 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

cc @xen0n 

https://github.com/llvm/llvm-project/pull/123715
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Support relaxation during TLSDESC GD/LD to IE/LE conversion (PR #123730)

2025-02-19 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

cc @xen0n 

https://github.com/llvm/llvm-project/pull/123730
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-02-19 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

cc @xen0n 

https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Support relaxation during IE to LE conversion (PR #123702)

2025-02-19 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

cc @xen0n 

https://github.com/llvm/llvm-project/pull/123702
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] GOT indirection to PC relative optimization (PR #123743)

2025-02-19 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

cc @xen0n 

https://github.com/llvm/llvm-project/pull/123743
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)

2025-03-24 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining edited 
https://github.com/llvm/llvm-project/pull/123680
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [LoongArch][MC] Add relocation support for fld fst [x]vld [x]vst (PR #133225)

2025-03-27 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/133225
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/21.x: LoongArch: Improve detection of valid TripleABI (#147952) (PR #149961)

2025-07-22 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/149961
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Optimize general fp build_vector lowering (PR #149486)

2025-07-21 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

AArch64 has similar logic.
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L15259-L15286

https://github.com/llvm/llvm-project/pull/149486
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/21.x: [LoongArch] Strengthen stack size estimation for LSX/LASX extension (#146455) (PR #149777)

2025-07-21 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining updated 
https://github.com/llvm/llvm-project/pull/149777

>From 4e9b5d1d8acfe3c12ab25d393cf92731016f8fa9 Mon Sep 17 00:00:00 2001
From: tangaac 
Date: Fri, 18 Jul 2025 16:12:11 +0800
Subject: [PATCH] [LoongArch] Strengthen stack size estimation for LSX/LASX
 extension (#146455)

This patch adds an emergency spill slot when ran out of registers.
PR #139201 introduces `vstelm` instructions with only 8-bit imm offset,
it causes no spill slot to store the spill registers.

(cherry picked from commit 64a0478e08829ec6bcae2b05e154aa58c2c46ac0)
---
 .../LoongArch/LoongArchFrameLowering.cpp  |   7 +-
 .../CodeGen/LoongArch/calling-conv-common.ll  |  48 +--
 .../CodeGen/LoongArch/calling-conv-half.ll|  16 +-
 .../LoongArch/can-not-realign-stack.ll|  44 +--
 .../CodeGen/LoongArch/emergency-spill-slot.ll |   4 +-
 llvm/test/CodeGen/LoongArch/frame.ll  | 107 ++-
 .../CodeGen/LoongArch/intrinsic-memcpy.ll |   8 +-
 llvm/test/CodeGen/LoongArch/lasx/fpowi.ll |  88 +++---
 .../lasx/ir-instruction/extractelement.ll | 120 
 .../lasx/ir-instruction/insertelement.ll  | 132 
 llvm/test/CodeGen/LoongArch/llvm.sincos.ll| 150 -
 llvm/test/CodeGen/LoongArch/lsx/pr146455.ll   | 287 ++
 ...realignment-with-variable-sized-objects.ll |  24 +-
 .../CodeGen/LoongArch/stack-realignment.ll|  80 ++---
 .../LoongArch/unaligned-memcpy-inline.ll  |  14 +-
 llvm/test/CodeGen/LoongArch/vararg.ll |  70 ++---
 16 files changed, 783 insertions(+), 416 deletions(-)
 create mode 100644 llvm/test/CodeGen/LoongArch/lsx/pr146455.ll

diff --git a/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp 
b/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp
index ac5e7f3891c72..1493bf4cba695 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp
@@ -158,7 +158,12 @@ void 
LoongArchFrameLowering::processFunctionBeforeFrameFinalized(
   // estimateStackSize has been observed to under-estimate the final stack
   // size, so give ourselves wiggle-room by checking for stack size
   // representable an 11-bit signed field rather than 12-bits.
-  if (!isInt<11>(MFI.estimateStackSize(MF)))
+  // For [x]vstelm.{b/h/w/d} memory instructions with 8 imm offset, 7-bit
+  // signed field is fine.
+  unsigned EstimateStackSize = MFI.estimateStackSize(MF);
+  if (!isInt<11>(EstimateStackSize) ||
+  (MF.getSubtarget().hasExtLSX() &&
+   !isInt<7>(EstimateStackSize)))
 ScavSlotsNum = std::max(ScavSlotsNum, 1u);
 
   // For CFR spill.
diff --git a/llvm/test/CodeGen/LoongArch/calling-conv-common.ll 
b/llvm/test/CodeGen/LoongArch/calling-conv-common.ll
index d07e2914c753a..f7653af1fa9ba 100644
--- a/llvm/test/CodeGen/LoongArch/calling-conv-common.ll
+++ b/llvm/test/CodeGen/LoongArch/calling-conv-common.ll
@@ -122,23 +122,23 @@ define i64 @callee_large_scalars(i256 %a, i256 %b) 
nounwind {
 define i64 @caller_large_scalars() nounwind {
 ; CHECK-LABEL: caller_large_scalars:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:addi.d $sp, $sp, -80
-; CHECK-NEXT:st.d $ra, $sp, 72 # 8-byte Folded Spill
-; CHECK-NEXT:st.d $zero, $sp, 24
+; CHECK-NEXT:addi.d $sp, $sp, -96
+; CHECK-NEXT:st.d $ra, $sp, 88 # 8-byte Folded Spill
+; CHECK-NEXT:st.d $zero, $sp, 40
 ; CHECK-NEXT:vrepli.b $vr0, 0
-; CHECK-NEXT:vst $vr0, $sp, 8
+; CHECK-NEXT:vst $vr0, $sp, 24
 ; CHECK-NEXT:ori $a0, $zero, 2
-; CHECK-NEXT:st.d $a0, $sp, 0
-; CHECK-NEXT:st.d $zero, $sp, 56
-; CHECK-NEXT:vst $vr0, $sp, 40
+; CHECK-NEXT:st.d $a0, $sp, 16
+; CHECK-NEXT:st.d $zero, $sp, 72
+; CHECK-NEXT:vst $vr0, $sp, 56
 ; CHECK-NEXT:ori $a2, $zero, 1
-; CHECK-NEXT:addi.d $a0, $sp, 32
-; CHECK-NEXT:addi.d $a1, $sp, 0
-; CHECK-NEXT:st.d $a2, $sp, 32
+; CHECK-NEXT:addi.d $a0, $sp, 48
+; CHECK-NEXT:addi.d $a1, $sp, 16
+; CHECK-NEXT:st.d $a2, $sp, 48
 ; CHECK-NEXT:pcaddu18i $ra, %call36(callee_large_scalars)
 ; CHECK-NEXT:jirl $ra, $ra, 0
-; CHECK-NEXT:ld.d $ra, $sp, 72 # 8-byte Folded Reload
-; CHECK-NEXT:addi.d $sp, $sp, 80
+; CHECK-NEXT:ld.d $ra, $sp, 88 # 8-byte Folded Reload
+; CHECK-NEXT:addi.d $sp, $sp, 96
 ; CHECK-NEXT:ret
   %1 = call i64 @callee_large_scalars(i256 1, i256 2)
   ret i64 %1
@@ -177,20 +177,20 @@ define i64 @callee_large_scalars_exhausted_regs(i64 %a, 
i64 %b, i64 %c, i64 %d,
 define i64 @caller_large_scalars_exhausted_regs() nounwind {
 ; CHECK-LABEL: caller_large_scalars_exhausted_regs:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:addi.d $sp, $sp, -96
-; CHECK-NEXT:st.d $ra, $sp, 88 # 8-byte Folded Spill
-; CHECK-NEXT:addi.d $a0, $sp, 16
+; CHECK-NEXT:addi.d $sp, $sp, -112
+; CHECK-NEXT:st.d $ra, $sp, 104 # 8-byte Folded Spill
+; CHECK-NEXT:addi.d $a0, $sp, 32
 ; CHECK-NEXT:st.d $a0, $sp, 8
 ; CHECK-NEXT:ori $a0, $zero, 9
 ; CHECK-NEXT:st.d $a0, $sp, 0
-; CHECK-NE

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Pass OptLevel to LoongArchDAGToDAGISel correctly (PR #144459)

2025-06-16 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/144459
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Custom legalizing build_vector with same constant elements (PR #150584)

2025-07-25 Thread Lu Weining via llvm-branch-commits



@@ -613,9 +595,10 @@ define void @buildvector_v2f64_with_constant(ptr %dst, 
double %a0) nounwind {
 ; CHECK-LABEL: buildvector_v2f64_with_constant:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:# kill: def $f0_64 killed $f0_64 def $vr0
-; CHECK-NEXT:vldi $vr1, -1024
-; CHECK-NEXT:vpackev.d $vr0, $vr1, $vr0
-; CHECK-NEXT:vst $vr0, $a0, 0
+; CHECK-NEXT:lu52i.d $a1, $zero, 1024
+; CHECK-NEXT:vreplgr2vr.d $vr1, $a1
+; CHECK-NEXT:vextrins.d $vr1, $vr0, 0
+; CHECK-NEXT:vst $vr1, $a0, 0

SixWeining wrote:

Seems it's worse then before.

https://github.com/llvm/llvm-project/pull/150584
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Custom legalizing build_vector with same constant elements (PR #150584)

2025-07-25 Thread Lu Weining via llvm-branch-commits



@@ -2495,26 +2492,47 @@ SDValue 
LoongArchTargetLowering::lowerBUILD_VECTOR(SDValue Op,
   if (DAG.isSplatValue(Op, /*AllowUndefs=*/false))
 return Op;
 
-  if (!isConstantBUILD_VECTOR(Node)) {
+  for (unsigned i = 0; i < NumElts; ++i) {
+SDValue Opi = Node->getOperand(i);
+if (isIntOrFPConstant(Opi)) {
+  IsConstant = true;
+  if (!ConstantValue.getNode())
+ConstantValue = Opi;
+  else if (ConstantValue != Opi)
+UseSameConstant = false;
+}
+  }
+
+  if (IsConstant && UseSameConstant) {
+SDValue Result = DAG.getSplatBuildVector(ResTy, DL, ConstantValue);
+for (unsigned i = 0; i < NumElts; ++i) {
+  SDValue Opi = Node->getOperand(i);
+  if (!isIntOrFPConstant(Opi))
+Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Result, Opi,
+ DAG.getConstant(i, DL, Subtarget.getGRLenVT()));
+}
+return Result;
+  }
+
+  if (!IsConstant) {
 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
 // The resulting code is the same length as the expansion, but it doesn't
 // use memory operations.
 assert(ResTy.isVector());
 
-unsigned NumElts = ResTy.getVectorNumElements();
 SDValue Op0 = Node->getOperand(0);
-SDValue Vector = DAG.getUNDEF(ResTy);
+SDValue Result = DAG.getUNDEF(ResTy);

SixWeining wrote:

The naming change is unnecessary.

https://github.com/llvm/llvm-project/pull/150584
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] release/21.x: [lld][LoongArch] Support relaxation during TLSDESC GD/LD to IE/LE conversion (#123730) (PR #150895)

2025-07-28 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/150895
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] release/21.x: [lld][LoongArch] GOT indirection to PC relative optimization (#123743) (PR #151794)

2025-08-03 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM. Thank you for the backport.

https://github.com/llvm/llvm-project/pull/151794
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] release/21.x: [lld][LoongArch] Check that the relocation addend is zero before applying relaxation to R_LARCH_GOT_PC_{HI20, LO12} (#151264) (PR #151470)

2025-07-31 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/151470
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Fix fp_to_uint/fp_to_sint conversion errors for lasx (#137129) (PR #139851)

2025-05-14 Thread Lu Weining via llvm-branch-commits


SixWeining wrote:

This PR fixes https://github.com/llvm/llvm-project/issues/136971.

https://github.com/llvm/llvm-project/pull/139851
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/20.x: [LoongArch] Fix '-mno-lsx' option not disabling LASX feature (#143821) (PR #143882)

2025-06-12 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/143882
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Use section-relaxable check instead of relax feature from STI (PR #153792)

2025-08-18 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/153792
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/21.x: [clang][LoongArch] Ensure `target("lasx")` implies LSX support (#153542) (PR #153739)

2025-08-15 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/153739
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Reduce number of reserved relocations when relax enabled (PR #153769)

2025-08-17 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/153769
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

78 matches

Mail list logo