[llvm-branch-commits] [clang] 402aaf7 - [RISCV] Add non-standard Xin feature for N3 core
Author: Jun Ma
Date: 2021-12-17T10:30:02+08:00
New Revision: 402aaf7d3f6d48e023b0aa6005c439a18cd4d029
URL:
https://github.com/llvm/llvm-project/commit/402aaf7d3f6d48e023b0aa6005c439a18cd4d029
DIFF:
https://github.com/llvm/llvm-project/commit/402aaf7d3f6d48e023b0aa6005c439a18cd4d029.diff
LOG: [RISCV] Add non-standard Xin feature for N3 core
Added:
Modified:
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/select-bare.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 5b99643309a57..8866d9301b545 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -472,3 +472,12 @@
// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p10
-menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature"
"+experimental-zvlsseg"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ixin -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-XIN-NOFLAG %s
+// RV32-EXPERIMENTAL-XIN-NOFLAG: error: invalid arch name 'rv32ixin'
+// RV32-EXPERIMENTAL-XIN-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ixin0p1
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-XIN %s
+// RV32-EXPERIMENTAL-XIN: "-target-feature" "+experimental-xin"
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index a0a1ac59cc4cc..14a605a7ef43c 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -33,6 +33,7 @@
// CHECK-NOT: __riscv_vector
// CHECK-NOT: __riscv_zvamo
// CHECK-NOT: __riscv_zvlsseg
+// CHECK-NOT: __riscv_xin
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -223,3 +224,11 @@
// RUN: -march=rv64izfh0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
// CHECK-ZFH-EXT: __riscv_zfh 1000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv32i_xin0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XIN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv64i_xin0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XIN-EXT %s
+// CHECK-XIN-EXT: __riscv_xin 1000
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 94929e7e052f1..b4a310254db59 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -66,6 +66,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfhmin", RISCVExtensionVersion{0, 1}},
{"zfh", RISCVExtensionVersion{0, 1}},
+
+{"xin", RISCVExtensionVersion{0, 1}},
};
static bool stripExperimentalPrefix(StringRef &Ext) {
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 772a4f8ecd535..4a94581107b19 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -176,6 +176,19 @@ def HasStdExtZvamo :
Predicate<"Subtarget->hasStdExtZvamo()">,
AssemblerPredicate<(all_of FeatureStdExtZvamo),
"'Zvamo' (Vector AMO Operations)">;
+def FeatureStdExtXin
+: SubtargetFeature<"experimental-xin", "HasStdExtXin", "true",
+ "'Xin' ('N3' Instructions)">;
+def HasStdExtXin : Predicate<"Subtarget->hasStdExtXin()">,
+ AssemblerPredicate<(all_of FeatureStdExtXin),
+ "'Xin' ('N3' Instructions)">;
+
+def HasStdExtZbtOrXin
+: Predicate<"Subtarget->hasStdExtZbt() || Subtarget->hasStdExtXin()">,
+AssemblerPredicate<(any_of FeatureStdExtZbt, FeatureStdExtXin),
+ "'Zbt' (Ternary 'B' Instructions) or "
+ "'Xin' ('N3' Instructions)">;
+
def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f33965b504591..9c485e834b21d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.c
[llvm-branch-commits] [llvm] eb64afd - [RISCV] Add N3 Load/Store under Xin
Author: Jun Ma
Date: 2021-12-17T10:30:02+08:00
New Revision: eb64afdb5c50932d271952538a4778849029a68d
URL:
https://github.com/llvm/llvm-project/commit/eb64afdb5c50932d271952538a4778849029a68d
DIFF:
https://github.com/llvm/llvm-project/commit/eb64afdb5c50932d271952538a4778849029a68d.diff
LOG: [RISCV] Add N3 Load/Store under Xin
Added:
llvm/lib/Target/RISCV/RISCVInstrInfoXin.td
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
Removed:
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 75592dd4c6f54..d54faba4315a6 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -669,6 +669,14 @@ struct RISCVOperand : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
}
+ bool isSImm10Lsb000() const {
+int64_t Imm;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && isShiftedInt<7, 3>(Imm) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
bool isUImm20LUI() const {
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
int64_t Imm;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 6a16b6354f954..bcb6413a17ad0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -145,6 +145,7 @@ def OPC_BRANCH: RISCVOpcode<"BRANCH",0b1100011>;
def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>;
def OPC_JAL : RISCVOpcode<"JAL", 0b110>;
def OPC_SYSTEM: RISCVOpcode<"SYSTEM",0b1110011>;
+def OPC_CUSTOM1 : RISCVOpcode<"CUSTOM1", 0b0001011>;
class RVInst pattern, InstFormat format>
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 71eb6f01a4f42..1db89b71af294 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1478,3 +1478,4 @@ include "RISCVInstrInfoC.td"
include "RISCVInstrInfoZb.td"
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZfh.td"
+include "RISCVInstrInfoXin.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXin.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoXin.td
new file mode 100644
index 0..eed9e8fab6a3f
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXin.td
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoXin.td - Target Description for Xin ---*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the Xin instructions in TableGen format.
+//
+//===--===//
+
+
+//===--===//
+// Operand and SDNode transformation definitions.
+//===--===//
+
+// A 10-bit signed immediate where the least significant three bits are zero.
+def simm10_lsb000: Operand,
+ImmLeaf(Imm);}]> {
+ let ParserMatchClass = SImmAsmOperand<10, "Lsb000">;
+ let EncoderMethod = "getImmOpValue";
+ let DecoderMethod = "decodeSImmOperand<10>";
+ let MCOperandPredicate = [{
+int64_t Imm;
+if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+return isShiftedInt<7, 3>(Imm);
+ }];
+}
+
+//===--===//
+// Instruction class templates
+//===--===//
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class RVXinLoadPair funct3, string opcodestr>
+ : RVInstR<0, funct3, OPC_CUSTOM1,
+ (outs GPR:$rd, GPR:$rs2), (ins GPR:$rs1, simm10_lsb000:$imm),
+ opcodestr, "$rd, $rs2, ${imm}(${rs1})"> {
+ bits<10> imm;
+ let Inst{31-25} = imm{9-3};
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class RVXinStorePair funct3, string opcodestr>
+ : RVInstR<0, funct3, OPC_CUSTOM1,
+ (outs), (ins GPR:$rd, GPR:$rs2, GPR:$rs1, simm10_lsb000:$imm),
+ opcodestr, "$rd, $rs2, ${imm}(${rs1})"> {
+ bits<10> imm;
+ let Inst{31-25} = imm{9-3};
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class RVXinLoadReg funct7, bits<3> funct3, string opcodestr>
+ : RVInstR;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class RVXinStoreReg funct7, bits<3> funct3, string opcodestr>
+ : RVInstR;
+
+let Predicates = [HasStdE
[llvm-branch-commits] [llvm] dd399a6 - [RISCV] Use ldp/sdp for EPI
Author: Jun Ma
Date: 2021-12-17T12:08:28+08:00
New Revision: dd399a6194e8506d2af87794d78cb920c66f19b0
URL:
https://github.com/llvm/llvm-project/commit/dd399a6194e8506d2af87794d78cb920c66f19b0
DIFF:
https://github.com/llvm/llvm-project/commit/dd399a6194e8506d2af87794d78cb920c66f19b0.diff
LOG: [RISCV] Use ldp/sdp for EPI
Added:
llvm/test/CodeGen/RISCV/callee-saved-n3.ll
llvm/test/CodeGen/RISCV/large-stack-n3.ll
Modified:
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index f5d491938050..9e1381ec5c6e 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1010,7 +1010,11 @@ RISCVFrameLowering::getFirstSPAdjustAmount(const
MachineFunction &MF) const {
// Return the FirstSPAdjustAmount if the StackSize can not fit in signed
// 12-bit and there exists a callee saved register need to be pushed.
- if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
+ if (!hasFP(MF) && !isInt<10>(StackSize) &&
+ STI.hasFeature(RISCV::Feature64Bit) &&
+ STI.hasFeature(RISCV::FeatureStdExtXin) && (CSI.size() > 1)) {
+return 512 - getStackAlign().value();
+ } else if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
// FirstSPAdjustAmount is choosed as (2048 - StackAlign)
// because 2048 will cause sp = sp + 2048 in epilogue split into
// multi-instructions. The offset smaller than 2048 can fit in signle
@@ -1048,12 +1052,43 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
// Manually spill values not spilled by libcall.
const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI);
- for (auto &CS : NonLibcallCSI) {
+ unsigned Count = NonLibcallCSI.size();
+ for (unsigned i = 0; i < Count; i += 1) {
// Insert the spill to the stack frame.
-Register Reg = CS.getReg();
+Register Reg = NonLibcallCSI[i].getReg();
+int FI = NonLibcallCSI[i].getFrameIdx();
+bool IsN3 = STI.hasFeature(RISCV::Feature64Bit) &&
+STI.hasFeature(RISCV::FeatureStdExtXin);
+if (IsN3 && unsigned(i + 1) < Count) {
+ unsigned NextReg = NonLibcallCSI[i + 1].getReg();
+ int NextFI = NonLibcallCSI[i + 1].getFrameIdx();
+ if (!hasFP(*MF) && RISCV::GPRRegClass.contains(Reg) &&
+ RISCV::GPRRegClass.contains(NextReg) && FI + 1 == NextFI) {
+
+MachineFrameInfo &MFI = MF->getFrameInfo();
+MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(RISCV::SDP));
+
+MIB.addReg(Reg, getKillRegState(!MBB.isLiveIn(Reg)));
+MIB.addMemOperand(MF->getMachineMemOperand(
+MachinePointerInfo::getFixedStack(*MF, FI),
+MachineMemOperand::MOStore, MFI.getObjectSize(FI),
+MFI.getObjectAlign(FI)));
+
+MIB.addReg(NextReg, getKillRegState(!MBB.isLiveIn(NextReg)));
+MIB.addMemOperand(MF->getMachineMemOperand(
+MachinePointerInfo::getFixedStack(*MF, NextFI),
+MachineMemOperand::MOStore, MFI.getObjectSize(NextFI),
+MFI.getObjectAlign(NextFI)));
+
+MIB.addFrameIndex(FI).addImm(0);
+
+i += 1;
+continue;
+ }
+}
+
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
-TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(),
-RC, TRI);
+TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), FI, RC, TRI);
}
return true;
@@ -1078,10 +1113,43 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters(
// load-to-use data hazard between loading RA and return by RA.
// loadRegFromStackSlot can insert multiple instructions.
const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI);
- for (auto &CS : NonLibcallCSI) {
-Register Reg = CS.getReg();
+ unsigned Count = NonLibcallCSI.size();
+ for (unsigned i = 0; i < Count; i += 1) {
+// Insert the spill to the stack frame.
+Register Reg = NonLibcallCSI[i].getReg();
+int FI = NonLibcallCSI[i].getFrameIdx();
+bool IsN3 = STI.hasFeature(RISCV::Feature64Bit) &&
+STI.hasFeature(RISCV::FeatureStdExtXin);
+if (IsN3 && unsigned(i + 1) < Count) {
+ unsigned NextReg = NonLibcallCSI[i + 1].getReg();
+ int NextFI = NonLibcallCSI[i + 1].getFrameIdx();
+ if (!hasFP(*MF) && RISCV::GPRRegClass.contains(Reg) &&
+ RISCV::GPRRegClass.contains(NextReg) && FI + 1 == NextFI) {
+
+MachineFrameInfo &MFI = MF->getFrameInfo();
+MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(RISCV::LDP));
+
+MIB.addReg(Reg, RegState::Define);
+MIB.addMemOperand(MF->getMachineMemOperand(
+MachinePointerInfo::getFixedStack(*MF, FI),
+MachineMemOperand::MOLoad, MFI.getObjectSize(FI),
+MFI.getObjectAlign(FI)));
+
+MIB.addReg(NextReg, RegState::Defi
[llvm-branch-commits] [llvm] e12f584 - [InstCombine] Remove scalable vector restriction in InstCombineCompares
Author: Jun Ma
Date: 2020-12-15T20:36:57+08:00
New Revision: e12f584578006e877cc947cde17c8da86177e9cc
URL:
https://github.com/llvm/llvm-project/commit/e12f584578006e877cc947cde17c8da86177e9cc
DIFF:
https://github.com/llvm/llvm-project/commit/e12f584578006e877cc947cde17c8da86177e9cc.diff
LOG: [InstCombine] Remove scalable vector restriction in InstCombineCompares
Differential Revision: https://reviews.llvm.org/D93269
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/test/Transforms/InstCombine/vscale_cmp.ll
Removed:
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index d6285dcd387d..139b04bb6a81 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -899,8 +899,8 @@ Instruction *InstCombinerImpl::foldGEPICmp(GEPOperator
*GEPLHS, Value *RHS,
// For vectors, we apply the same reasoning on a per-lane basis.
auto *Base = GEPLHS->getPointerOperand();
if (GEPLHS->getType()->isVectorTy() && Base->getType()->isPointerTy()) {
- int NumElts = cast(GEPLHS->getType())->getNumElements();
- Base = Builder.CreateVectorSplat(NumElts, Base);
+ auto EC = cast(GEPLHS->getType())->getElementCount();
+ Base = Builder.CreateVectorSplat(EC, Base);
}
return new ICmpInst(Cond, Base,
ConstantExpr::getPointerBitCastOrAddrSpaceCast(
@@ -1885,8 +1885,7 @@ Instruction
*InstCombinerImpl::foldICmpAndConstant(ICmpInst &Cmp,
if (ExactLogBase2 != -1 && DL.isLegalInteger(ExactLogBase2 + 1)) {
Type *NTy = IntegerType::get(Cmp.getContext(), ExactLogBase2 + 1);
if (auto *AndVTy = dyn_cast(And->getType()))
-NTy = FixedVectorType::get(
-NTy, cast(AndVTy)->getNumElements());
+NTy = VectorType::get(NTy, AndVTy->getElementCount());
Value *Trunc = Builder.CreateTrunc(X, NTy);
auto NewPred = Cmp.getPredicate() == CmpInst::ICMP_EQ ? CmpInst::ICMP_SGE
:
CmpInst::ICMP_SLT;
@@ -2192,8 +2191,7 @@ Instruction
*InstCombinerImpl::foldICmpShlConstant(ICmpInst &Cmp,
DL.isLegalInteger(TypeBits - Amt)) {
Type *TruncTy = IntegerType::get(Cmp.getContext(), TypeBits - Amt);
if (auto *ShVTy = dyn_cast(ShType))
- TruncTy = FixedVectorType::get(
- TruncTy, cast(ShVTy)->getNumElements());
+ TruncTy = VectorType::get(TruncTy, ShVTy->getElementCount());
Constant *NewC =
ConstantInt::get(TruncTy, C.ashr(*ShiftAmt).trunc(TypeBits - Amt));
return new ICmpInst(Pred, Builder.CreateTrunc(X, TruncTy), NewC);
@@ -2827,8 +2825,7 @@ static Instruction *foldICmpBitCast(ICmpInst &Cmp,
Type *NewType = Builder.getIntNTy(XType->getScalarSizeInBits());
if (auto *XVTy = dyn_cast(XType))
-NewType = FixedVectorType::get(
-NewType, cast(XVTy)->getNumElements());
+NewType = VectorType::get(NewType, XVTy->getElementCount());
Value *NewBitcast = Builder.CreateBitCast(X, NewType);
if (TrueIfSigned)
return new ICmpInst(ICmpInst::ICMP_SLT, NewBitcast,
@@ -3411,8 +3408,8 @@ static Value *foldICmpWithLowBitMaskedVal(ICmpInst &I,
// those elements by copying an existing, defined, and safe scalar constant.
Type *OpTy = M->getType();
auto *VecC = dyn_cast(M);
- if (OpTy->isVectorTy() && VecC && VecC->containsUndefElement()) {
-auto *OpVTy = cast(OpTy);
+ auto *OpVTy = dyn_cast(OpTy);
+ if (OpVTy && VecC && VecC->containsUndefElement()) {
Constant *SafeReplacementConstant = nullptr;
for (unsigned i = 0, e = OpVTy->getNumElements(); i != e; ++i) {
if (!isa(VecC->getAggregateElement(i))) {
diff --git a/llvm/test/Transforms/InstCombine/vscale_cmp.ll
b/llvm/test/Transforms/InstCombine/vscale_cmp.ll
index bbceab06e3fc..e7b8a2e3e3f2 100644
--- a/llvm/test/Transforms/InstCombine/vscale_cmp.ll
+++ b/llvm/test/Transforms/InstCombine/vscale_cmp.ll
@@ -9,3 +9,27 @@ define @sge( %x) {
%cmp = icmp sge %x, zeroinitializer
ret %cmp
}
+
+define @gep_scalevector1(i32* %X) nounwind {
+; CHECK-LABEL: @gep_scalevector1(
+; CHECK-NEXT:[[S:%.*]] = insertelement undef, i32*
[[X:%.*]], i32 0
+; CHECK-NEXT:[[C:%.*]] = icmp eq [[S]], zeroinitializer
+; CHECK-NEXT:[[C1:%.*]] = shufflevector [[C]], undef, zeroinitializer
+; CHECK-NEXT:ret [[C1]]
+;
+ %A = getelementptr inbounds i32, i32* %X, zeroinitializer
+ %C = icmp eq %A, zeroinitializer
+ ret %C
+}
+
+define @signbit_bitcast_fpext_scalevec(
%x) {
+; CHECK-LABEL: @signbit_bitcast_fpext_scalevec(
+; CHECK-NEXT:[[TMP1:%.*]] = bitcast [[X:%.*]] to
+; CHECK-NEXT:[[R:%.*]] = icmp slt [[TMP1]],
zeroinitializer
+; CHECK-NEXT:ret [[R]]
+;
+ %f = fpext
[llvm-branch-commits] [llvm] 2ac58e2 - [InstCombine] Remove scalable vector restriction when fold SelectInst
Author: Jun Ma
Date: 2020-12-15T20:36:57+08:00
New Revision: 2ac58e21a115d16a91578defc4636c43e3608a2e
URL:
https://github.com/llvm/llvm-project/commit/2ac58e21a115d16a91578defc4636c43e3608a2e
DIFF:
https://github.com/llvm/llvm-project/commit/2ac58e21a115d16a91578defc4636c43e3608a2e.diff
LOG: [InstCombine] Remove scalable vector restriction when fold SelectInst
Differential Revision: https://reviews.llvm.org/D93083
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
llvm/test/Transforms/InstCombine/select.ll
Removed:
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
index 6e94e5823433..e9ec8021e466 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -2322,13 +2322,11 @@ static Instruction *foldBitCastSelect(BitCastInst
&BitCast,
// A vector select must maintain the same number of elements in its operands.
Type *CondTy = Cond->getType();
Type *DestTy = BitCast.getType();
- if (auto *CondVTy = dyn_cast(CondTy)) {
-if (!DestTy->isVectorTy())
+ if (auto *CondVTy = dyn_cast(CondTy))
+if (!DestTy->isVectorTy() ||
+CondVTy->getElementCount() !=
+cast(DestTy)->getElementCount())
return nullptr;
-if (cast(DestTy)->getNumElements() !=
-cast(CondVTy)->getNumElements())
- return nullptr;
- }
// FIXME: This transform is restricted from changing the select between
// scalars and vectors to avoid backend problems caused by creating
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 397cb0b0e187..c32f6ace42db 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -283,10 +283,9 @@ Instruction *InstCombinerImpl::foldSelectOpOp(SelectInst
&SI, Instruction *TI,
// The select condition may be a vector. We may only change the operand
// type if the vector width remains the same (and matches the condition).
if (auto *CondVTy = dyn_cast(CondTy)) {
- if (!FIOpndTy->isVectorTy())
-return nullptr;
- if (cast(CondVTy)->getNumElements() !=
- cast(FIOpndTy)->getNumElements())
+ if (!FIOpndTy->isVectorTy() ||
+ CondVTy->getElementCount() !=
+ cast(FIOpndTy)->getElementCount())
return nullptr;
// TODO: If the backend knew how to deal with casts better, we could
diff --git a/llvm/test/Transforms/InstCombine/select.ll
b/llvm/test/Transforms/InstCombine/select.ll
index 987f34e52ad2..819ac6dd3a82 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -68,6 +68,15 @@ define <2 x i1> @test8vec(<2 x i1> %C, <2 x i1> %X) {
ret <2 x i1> %R
}
+define @test8vvec( %C,
%X) {
+; CHECK-LABEL: @test8vvec(
+; CHECK-NEXT:[[R:%.*]] = and [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT:ret [[R]]
+;
+ %R = select %C, %X,
zeroinitializer
+ ret %R
+}
+
define i1 @test9(i1 %C, i1 %X) {
; CHECK-LABEL: @test9(
; CHECK-NEXT:[[NOT_C:%.*]] = xor i1 [[C:%.*]], true
@@ -88,6 +97,16 @@ define <2 x i1> @test9vec(<2 x i1> %C, <2 x i1> %X) {
ret <2 x i1> %R
}
+define @test9vvec( %C,
%X) {
+; CHECK-LABEL: @test9vvec(
+; CHECK-NEXT:[[NOT_C:%.*]] = xor [[C:%.*]],
shufflevector ( insertelement ( undef, i1
true, i32 0), undef, zeroinitializer)
+; CHECK-NEXT:[[R:%.*]] = and [[NOT_C]], [[X:%.*]]
+; CHECK-NEXT:ret [[R]]
+;
+ %R = select %C, zeroinitializer, %X
+ ret %R
+}
+
define i1 @test10(i1 %C, i1 %X) {
; CHECK-LABEL: @test10(
; CHECK-NEXT:[[NOT_C:%.*]] = xor i1 [[C:%.*]], true
@@ -699,6 +718,34 @@ define i48 @test51(<3 x i1> %icmp, <3 x i16> %tmp) {
ret i48 %tmp2
}
+define @bitcast_select_bitcast( %icmp,
%a, %b) {
+; CHECK-LABEL: @bitcast_select_bitcast(
+; CHECK-NEXT:[[BC1:%.*]] = bitcast [[A:%.*]] to
+; CHECK-NEXT:[[SELECT:%.*]] = select [[ICMP:%.*]],
[[B:%.*]], [[BC1]]
+; CHECK-NEXT:ret [[SELECT]]
+;
+ %bc1 = bitcast %b to
+ %select = select %icmp, %bc1, %a
+ %bc2 = bitcast %select to
+ ret %bc2
+}
+
+define void @select_oneuse_bitcast( %a, %b, %c, %d, *
%ptr1) {
+; CHECK-LABEL: @select_oneuse_bitcast(
+; CHECK-NEXT:[[CMP:%.*]] = icmp ult [[C:%.*]], [[D:%.*]]
+; CHECK-NEXT:[[SEL1_V:%.*]] = select [[CMP]], [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:[[TMP1:%.*]] = bitcast * [[PTR1:%.*]] to
*
+; CHECK-NEXT:store [[SEL1_V]], *
[[TMP1]], align 16
+; CHECK-NEXT:ret void
+;
+ %cmp = icmp ult %c, %d
+ %bc1 = bitcast %a to
+ %bc2 = bitcast %b to
+ %sel1 = select %cmp, %bc1, %bc2
+ store %sel1, * %ptr1
+ ret void
+}
+
; Allow select promotion ev
[llvm-branch-commits] [llvm] ffe84d9 - [InstCombine][NFC] Change cast of FixedVectorType to dyn_cast.
Author: Jun Ma
Date: 2020-12-15T20:36:57+08:00
New Revision: ffe84d90e9a7279fafbdcaf70da03174a522ab62
URL:
https://github.com/llvm/llvm-project/commit/ffe84d90e9a7279fafbdcaf70da03174a522ab62
DIFF:
https://github.com/llvm/llvm-project/commit/ffe84d90e9a7279fafbdcaf70da03174a522ab62.diff
LOG: [InstCombine][NFC] Change cast of FixedVectorType to dyn_cast.
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Removed:
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index c32f6ace42db..d6f8d2dcc7ce 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -1985,11 +1985,11 @@ Instruction
*InstCombinerImpl::foldSelectExtConst(SelectInst &Sel) {
static Instruction *canonicalizeSelectToShuffle(SelectInst &SI) {
Value *CondVal = SI.getCondition();
Constant *CondC;
- if (!CondVal->getType()->isVectorTy() || !match(CondVal, m_Constant(CondC)))
+ auto *CondValTy = dyn_cast(CondVal->getType());
+ if (!CondValTy || !match(CondVal, m_Constant(CondC)))
return nullptr;
- unsigned NumElts =
- cast(CondVal->getType())->getNumElements();
+ unsigned NumElts = CondValTy->getNumElements();
SmallVector Mask;
Mask.reserve(NumElts);
for (unsigned i = 0; i != NumElts; ++i) {
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[llvm-branch-commits] [llvm] 52a3267 - [InstCombine] Remove scalable vector restriction in foldVectorBinop
Author: Jun Ma
Date: 2020-12-15T21:14:59+08:00
New Revision: 52a3267ffafc27d2dbe3d419256f18a4a9d8c681
URL:
https://github.com/llvm/llvm-project/commit/52a3267ffafc27d2dbe3d419256f18a4a9d8c681
DIFF:
https://github.com/llvm/llvm-project/commit/52a3267ffafc27d2dbe3d419256f18a4a9d8c681.diff
LOG: [InstCombine] Remove scalable vector restriction in foldVectorBinop
Differential Revision: https://reviews.llvm.org/D93289
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
llvm/test/Transforms/InstCombine/fold-bin-operand.ll
llvm/test/Transforms/InstCombine/vec-binop-select.ll
llvm/test/Transforms/InstCombine/vec_shuffle.ll
Removed:
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index bbc76325a67b..9306e99f5d52 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -959,8 +959,7 @@ Instruction *InstCombinerImpl::FoldOpIntoSelect(Instruction
&Op,
return nullptr;
// If vectors, verify that they have the same number of elements.
-if (SrcTy && cast(SrcTy)->getNumElements() !=
- cast(DestTy)->getNumElements())
+if (SrcTy && SrcTy->getElementCount() != DestTy->getElementCount())
return nullptr;
}
@@ -1515,8 +1514,7 @@ Value *InstCombinerImpl::Descale(Value *Val, APInt Scale,
bool &NoSignedWrap) {
}
Instruction *InstCombinerImpl::foldVectorBinop(BinaryOperator &Inst) {
- // FIXME: some of this is likely fine for scalable vectors
- if (!isa(Inst.getType()))
+ if (!isa(Inst.getType()))
return nullptr;
BinaryOperator::BinaryOps Opcode = Inst.getOpcode();
@@ -1605,13 +1603,16 @@ Instruction
*InstCombinerImpl::foldVectorBinop(BinaryOperator &Inst) {
// intends to move shuffles closer to other shuffles and binops closer to
// other binops, so they can be folded. It may also enable demanded elements
// transforms.
- unsigned NumElts = cast(Inst.getType())->getNumElements();
Constant *C;
- if (match(&Inst,
+ auto *InstVTy = dyn_cast(Inst.getType());
+ if (InstVTy &&
+ match(&Inst,
m_c_BinOp(m_OneUse(m_Shuffle(m_Value(V1), m_Undef(),
m_Mask(Mask))),
- m_Constant(C))) && !isa(C) &&
- cast(V1->getType())->getNumElements() <= NumElts) {
-assert(Inst.getType()->getScalarType() == V1->getType()->getScalarType() &&
+ m_Constant(C))) &&
+ !isa(C) &&
+ cast(V1->getType())->getNumElements() <=
+ InstVTy->getNumElements()) {
+assert(InstVTy->getScalarType() == V1->getType()->getScalarType() &&
"Shuffle should not change scalar type");
// Find constant NewC that has property:
@@ -1626,6 +1627,7 @@ Instruction
*InstCombinerImpl::foldVectorBinop(BinaryOperator &Inst) {
UndefValue *UndefScalar = UndefValue::get(C->getType()->getScalarType());
SmallVector NewVecC(SrcVecNumElts, UndefScalar);
bool MayChange = true;
+unsigned NumElts = InstVTy->getNumElements();
for (unsigned I = 0; I < NumElts; ++I) {
Constant *CElt = C->getAggregateElement(I);
if (ShMask[I] >= 0) {
@@ -2379,9 +2381,9 @@ Instruction
*InstCombinerImpl::visitGetElementPtrInst(GetElementPtrInst &GEP) {
DL.getTypeAllocSize(ArrTy) == DL.getTypeAllocSize(VecTy);
};
if (GEP.getNumOperands() == 3 &&
-((GEPEltType->isArrayTy() && SrcEltType->isVectorTy() &&
+((GEPEltType->isArrayTy() && isa(SrcEltType) &&
areMatchingArrayAndVecTypes(GEPEltType, SrcEltType, DL)) ||
- (GEPEltType->isVectorTy() && SrcEltType->isArrayTy() &&
+ (isa(GEPEltType) && SrcEltType->isArrayTy() &&
areMatchingArrayAndVecTypes(SrcEltType, GEPEltType, DL {
// Create a new GEP here, as using `setOperand()` followed by
diff --git a/llvm/test/Transforms/InstCombine/fold-bin-operand.ll
b/llvm/test/Transforms/InstCombine/fold-bin-operand.ll
index d3303262be3f..fc0c13a5f1a7 100644
--- a/llvm/test/Transforms/InstCombine/fold-bin-operand.ll
+++ b/llvm/test/Transforms/InstCombine/fold-bin-operand.ll
@@ -1,17 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
target datalayout =
"E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
define i1 @f(i1 %x) {
; CHECK-LABEL: @f(
-; CHECK: ret i1 false
- %b = and i1 %x, icmp eq (i8* inttoptr (i32 1 to i8*), i8* inttoptr (i32
2 to i8*))
- ret i1 %b
+; CHECK-NEXT:ret i1 false
+;
+ %b = and i1 %x, icmp eq (i8* inttoptr (i32 1 to i8*), i8* inttoptr (i32 2 to
i8*))
+ ret i1 %b
}
define i32 @g(i32 %x) {
; CHECK-LABEL: @g(
-; CHECK: ret i32 %x
- %b = add i32 %x, zext (i1 icmp eq (i8* inttoptr (
[llvm-branch-commits] [llvm] 0138399 - [InstCombine] Remove scalable vector restriction in InstCombineCasts
Author: Jun Ma
Date: 2020-12-17T22:02:33+08:00
New Revision: 01383999037760288f617e24084991eaf6bd9272
URL:
https://github.com/llvm/llvm-project/commit/01383999037760288f617e24084991eaf6bd9272
DIFF:
https://github.com/llvm/llvm-project/commit/01383999037760288f617e24084991eaf6bd9272.diff
LOG: [InstCombine] Remove scalable vector restriction in InstCombineCasts
Differential Revision: https://reviews.llvm.org/D93389
Added:
Modified:
llvm/lib/IR/Verifier.cpp
llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
llvm/test/Transforms/InstCombine/addrspacecast.ll
llvm/test/Transforms/InstCombine/ptr-int-cast.ll
llvm/test/Transforms/InstCombine/trunc-extractelement.ll
llvm/test/Transforms/InstCombine/vec_shuffle.ll
Removed:
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 71bb94e77593..cac5df81661c 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -2961,8 +2961,8 @@ void Verifier::visitAddrSpaceCastInst(AddrSpaceCastInst
&I) {
Assert(SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace(),
"AddrSpaceCast must be between
diff erent address spaces", &I);
if (auto *SrcVTy = dyn_cast(SrcTy))
-Assert(cast(SrcVTy)->getNumElements() ==
- cast(DestTy)->getNumElements(),
+Assert(SrcVTy->getElementCount() ==
+ cast(DestTy)->getElementCount(),
"AddrSpaceCast vector pointer number of elements mismatch", &I);
visitInstruction(I);
}
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
index e9ec8021e466..8750e83623e6 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -907,20 +907,21 @@ Instruction *InstCombinerImpl::visitTrunc(TruncInst
&Trunc) {
Value *VecOp;
ConstantInt *Cst;
if (match(Src, m_OneUse(m_ExtractElt(m_Value(VecOp), m_ConstantInt(Cst) {
-auto *VecOpTy = cast(VecOp->getType());
-unsigned VecNumElts = VecOpTy->getNumElements();
+auto *VecOpTy = cast(VecOp->getType());
+auto VecElts = VecOpTy->getElementCount();
// A badly fit destination size would result in an invalid cast.
if (SrcWidth % DestWidth == 0) {
uint64_t TruncRatio = SrcWidth / DestWidth;
- uint64_t BitCastNumElts = VecNumElts * TruncRatio;
+ uint64_t BitCastNumElts = VecElts.getKnownMinValue() * TruncRatio;
uint64_t VecOpIdx = Cst->getZExtValue();
uint64_t NewIdx = DL.isBigEndian() ? (VecOpIdx + 1) * TruncRatio - 1
: VecOpIdx * TruncRatio;
assert(BitCastNumElts <= std::numeric_limits::max() &&
"overflow 32-bits");
- auto *BitCastTo = FixedVectorType::get(DestTy, BitCastNumElts);
+ auto *BitCastTo =
+ VectorType::get(DestTy, BitCastNumElts, VecElts.isScalable());
Value *BitCast = Builder.CreateBitCast(VecOp, BitCastTo);
return ExtractElementInst::Create(BitCast, Builder.getInt32(NewIdx));
}
@@ -1974,12 +1975,9 @@ Instruction
*InstCombinerImpl::visitPtrToInt(PtrToIntInst &CI) {
unsigned PtrSize = DL.getPointerSizeInBits(AS);
if (TySize != PtrSize) {
Type *IntPtrTy = DL.getIntPtrType(CI.getContext(), AS);
-if (auto *VecTy = dyn_cast(Ty)) {
- // Handle vectors of pointers.
- // FIXME: what should happen for scalable vectors?
- IntPtrTy = FixedVectorType::get(
- IntPtrTy, cast(VecTy)->getNumElements());
-}
+// Handle vectors of pointers.
+if (auto *VecTy = dyn_cast(Ty))
+ IntPtrTy = VectorType::get(IntPtrTy, VecTy->getElementCount());
Value *P = Builder.CreatePtrToInt(SrcOp, IntPtrTy);
return CastInst::CreateIntegerCast(P, Ty, /*isSigned=*/false);
@@ -2660,13 +2658,11 @@ Instruction *InstCombinerImpl::visitBitCast(BitCastInst
&CI) {
// a bitcast to a vector with the same # elts.
Value *ShufOp0 = Shuf->getOperand(0);
Value *ShufOp1 = Shuf->getOperand(1);
-unsigned NumShufElts =
-cast(Shuf->getType())->getNumElements();
-unsigned NumSrcVecElts =
-cast(ShufOp0->getType())->getNumElements();
+auto ShufElts = cast(Shuf->getType())->getElementCount();
+auto SrcVecElts = cast(ShufOp0->getType())->getElementCount();
if (Shuf->hasOneUse() && DestTy->isVectorTy() &&
-cast(DestTy)->getNumElements() == NumShufElts &&
-NumShufElts == NumSrcVecElts) {
+cast(DestTy)->getElementCount() == ShufElts &&
+ShufElts == SrcVecElts) {
BitCastInst *Tmp;
// If either of the operands is a cast from CI.getType(), then
// evaluating the shuffle in the casted destination's type will allow
@@ -2689,8 +2685,9 @@ Instruction *InstCombinerImpl::visitBitCast(BitCastInst
&CI) {
// TODO: We should match the related pattern for bitreverse.
if (D
[llvm-branch-commits] [llvm] 216689a - [Coroutines] Add DW_OP_deref for transformed dbg.value intrinsic.
Author: Jun Ma
Date: 2020-12-07T10:24:44+08:00
New Revision: 216689ace71dee579c0e42f67978beb25f5f7df0
URL:
https://github.com/llvm/llvm-project/commit/216689ace71dee579c0e42f67978beb25f5f7df0
DIFF:
https://github.com/llvm/llvm-project/commit/216689ace71dee579c0e42f67978beb25f5f7df0.diff
LOG: [Coroutines] Add DW_OP_deref for transformed dbg.value intrinsic.
Differential Revision: https://reviews.llvm.org/D92462
Added:
Modified:
llvm/lib/Transforms/Coroutines/CoroFrame.cpp
llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll
Removed:
diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
index 1a000c1913c6..48d52ff1d8df 100644
--- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
@@ -1289,7 +1289,9 @@ static Instruction *insertSpills(const FrameDataInfo
&FrameData,
// that control flow can be later changed by other passes.
auto *DI = cast(FirstDbgDecl);
BasicBlock *CurrentBlock = I->getParent();
- DIB.insertDbgValueIntrinsic(G, DI->getVariable(), DI->getExpression(),
+ auto *DerefExpr =
+ DIExpression::append(DI->getExpression(), dwarf::DW_OP_deref);
+ DIB.insertDbgValueIntrinsic(G, DI->getVariable(), DerefExpr,
DI->getDebugLoc(),
&*CurrentBlock->getFirstInsertionPt());
SeenDbgBBs.insert(CurrentBlock);
diff --git a/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll
b/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll
index 00a77cb790dc..68d496c880ff 100644
--- a/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll
+++ b/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll
@@ -37,8 +37,8 @@
; CHECK: call void @llvm.dbg.declare(metadata i32* [[IGEP]], metadata
![[IVAR:[0-9]+]], metadata !DIExpression()), !dbg ![[IDBGLOC:[0-9]+]]
; CHECK: call void @llvm.dbg.declare(metadata [10 x i32]* [[XGEP]],
metadata ![[XVAR:[0-9]+]], metadata !DIExpression()), !dbg ![[IDBGLOC]]
; CHECK: await.ready:
-; CHECK: call void @llvm.dbg.value(metadata [10 x i32]* [[XGEP]],
metadata ![[XVAR]], metadata !DIExpression()), !dbg ![[IDBGLOC]]
-; CHECK: call void @llvm.dbg.value(metadata i32* [[IGEP]], metadata
![[IVAR]], metadata !DIExpression()), !dbg ![[IDBGLOC]]
+; CHECK: call void @llvm.dbg.value(metadata [10 x i32]* [[XGEP]],
metadata ![[XVAR]], metadata !DIExpression(DW_OP_deref)), !dbg ![[IDBGLOC]]
+; CHECK: call void @llvm.dbg.value(metadata i32* [[IGEP]], metadata
![[IVAR]], metadata !DIExpression(DW_OP_deref)), !dbg ![[IDBGLOC]]
; CHECK: call void @llvm.dbg.declare(metadata i32* %j, metadata
![[JVAR:[0-9]+]], metadata !DIExpression()), !dbg ![[JDBGLOC:[0-9]+]]
;
; CHECK-LABEL: define internal fastcc void @f.resume({{.*}}) {
@@ -50,8 +50,8 @@
; CHECK: call void @llvm.dbg.declare(metadata i32* [[IGEP_RESUME]],
metadata ![[IVAR_RESUME:[0-9]+]], metadata !DIExpression()), !dbg
![[IDBGLOC_RESUME:[0-9]+]]
; CHECK: call void @llvm.dbg.declare(metadata [10 x i32]*
[[XGEP_RESUME]], metadata ![[XVAR_RESUME:[0-9]+]], metadata !DIExpression()),
!dbg ![[IDBGLOC_RESUME]]
; CHECK: await.ready:
-; CHECK: call void @llvm.dbg.value(metadata [10 x i32]*
[[XGEP_RESUME]], metadata ![[XVAR_RESUME]], metadata !DIExpression()), !dbg
![[IDBGLOC_RESUME]]
-; CHECK: call void @llvm.dbg.value(metadata i32* [[IGEP_RESUME]],
metadata ![[IVAR_RESUME]], metadata !DIExpression()), !dbg ![[IDBGLOC_RESUME]]
+; CHECK: call void @llvm.dbg.value(metadata [10 x i32]*
[[XGEP_RESUME]], metadata ![[XVAR_RESUME]], metadata
!DIExpression(DW_OP_deref)), !dbg ![[IDBGLOC_RESUME]]
+; CHECK: call void @llvm.dbg.value(metadata i32* [[IGEP_RESUME]],
metadata ![[IVAR_RESUME]], metadata !DIExpression(DW_OP_deref)), !dbg
![[IDBGLOC_RESUME]]
; CHECK: call void @llvm.dbg.declare(metadata i32* %j, metadata
![[JVAR_RESUME:[0-9]+]], metadata !DIExpression()), !dbg
![[JDBGLOC_RESUME:[0-9]+]]
;
; CHECK: ![[IVAR]] = !DILocalVariable(name: "i"
@@ -247,4 +247,4 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly,
i8, i64, i1 immarg)
!19 = !DILocation(line: 42, column: 8, scope: !7)
!20 = !DILocation(line: 43, column: 3, scope: !7)
!21 = !DILocation(line: 43, column: 8, scope: !7)
-!22 = distinct !DILexicalBlock(scope: !8, file: !1, line: 23, column: 12)
\ No newline at end of file
+!22 = distinct !DILexicalBlock(scope: !8, file: !1, line: 23, column: 12)
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[llvm-branch-commits] [llvm] 137674f - [TruncInstCombine] Remove scalable vector restriction
Author: Jun Ma
Date: 2020-12-10T18:00:19+08:00
New Revision: 137674f882fc7d08fc9bff8acecc240699eac096
URL:
https://github.com/llvm/llvm-project/commit/137674f882fc7d08fc9bff8acecc240699eac096
DIFF:
https://github.com/llvm/llvm-project/commit/137674f882fc7d08fc9bff8acecc240699eac096.diff
LOG: [TruncInstCombine] Remove scalable vector restriction
Differential Revision: https://reviews.llvm.org/D92819
Added:
Modified:
llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
llvm/test/Transforms/AggressiveInstCombine/trunc_const_expr.ll
Removed:
diff --git a/llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
b/llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
index e9418175c842..0bcebc17af8d 100644
--- a/llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
+++ b/llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
@@ -289,11 +289,8 @@ Type *TruncInstCombine::getBestTruncatedType() {
/// version of \p Ty, otherwise return \p Ty.
static Type *getReducedType(Value *V, Type *Ty) {
assert(Ty && !Ty->isVectorTy() && "Expect Scalar Type");
- if (auto *VTy = dyn_cast(V->getType())) {
-// FIXME: should this handle scalable vectors?
-return FixedVectorType::get(Ty,
-cast(VTy)->getNumElements());
- }
+ if (auto *VTy = dyn_cast(V->getType()))
+return VectorType::get(Ty, VTy->getElementCount());
return Ty;
}
diff --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_const_expr.ll
b/llvm/test/Transforms/AggressiveInstCombine/trunc_const_expr.ll
index b83fcb470cc3..32f323602498 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/trunc_const_expr.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/trunc_const_expr.ll
@@ -8,6 +8,7 @@ target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
declare i32 @use32(i32)
declare <2 x i32> @use32_vec(<2 x i32>)
+declare @use32_scale_vec()
;; These tests check cases where expression dag post-dominated by TruncInst
@@ -108,3 +109,35 @@ define void @const_expression_trunc_vec() {
call <2 x i32> @use32_vec(<2 x i32> %T)
ret void
}
+
+define void @const_expression_mul_scale_vec() {
+; CHECK-LABEL: @const_expression_mul_scale_vec(
+; CHECK-NEXT:[[TMP1:%.*]] = call
@use32_scale_vec( zeroinitializer)
+; CHECK-NEXT:ret void
+;
+ %A = mul zeroinitializer, zeroinitializer
+ %T = trunc %A to
+ call @use32_scale_vec( %T)
+ ret void
+}
+
+define void @const_expression_zext_scale_vec() {
+; CHECK-LABEL: @const_expression_zext_scale_vec(
+; CHECK-NEXT:[[TMP1:%.*]] = call
@use32_scale_vec( zeroinitializer)
+; CHECK-NEXT:ret void
+;
+ %A = zext zeroinitializer to
+ %T = trunc %A to
+ call @use32_scale_vec( %T)
+ ret void
+}
+
+define void @const_expression_trunc_scale_vec() {
+; CHECK-LABEL: @const_expression_trunc_scale_vec(
+; CHECK-NEXT:[[TMP1:%.*]] = call
@use32_scale_vec( zeroinitializer)
+; CHECK-NEXT:ret void
+;
+ %T = trunc zeroinitializer to
+ call @use32_scale_vec( %T)
+ ret void
+}
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