[llvm-branch-commits] [llvm] e8ade45 - [LegalizeType] When LegalizeType procedure widens a masked_gather, set MemoryType's EltNum equal to Result's EltNum

2020-12-21 Thread Bing1 Yu via llvm-branch-commits

Author: Bing1 Yu
Date: 2020-12-22T13:27:38+08:00
New Revision: e8ade4569b7b5343ae8d4d7c9d83706eca0e8e90

URL: 
https://github.com/llvm/llvm-project/commit/e8ade4569b7b5343ae8d4d7c9d83706eca0e8e90
DIFF: 
https://github.com/llvm/llvm-project/commit/e8ade4569b7b5343ae8d4d7c9d83706eca0e8e90.diff

LOG: [LegalizeType] When LegalizeType procedure widens a masked_gather, set 
MemoryType's EltNum equal to Result's EltNum

When LegalizeType procedure widens a masked_gather, set MemoryType's EltNum 
equal to Result's EltNum.

As I mentioned in https://reviews.llvm.org/D91092, in previous code, If we have 
a v17i32's masked_gather in avx512, we widen it to a v32i32's masked_gather 
with a v17i32's MemoryType. When the SplitVecRes_MGATHER process this v32i32's 
masked_gather, GetSplitDestVTs will assert fail since what you are going to 
split is v17i32.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93610

Added: 


Modified: 
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll

Removed: 




diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index f21ec1dbdfe5..57cb364f1939 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -4044,10 +4044,13 @@ SDValue 
DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
   Index = ModifyToType(Index, WideIndexVT);
   SDValue Ops[] = { N->getChain(), PassThru, Mask, N->getBasePtr(), Index,
 Scale };
+
+  // Widen the MemoryType
+  EVT WideMemVT = EVT::getVectorVT(*DAG.getContext(),
+   N->getMemoryVT().getScalarType(), NumElts);
   SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
-N->getMemoryVT(), dl, Ops,
-N->getMemOperand(), N->getIndexType(),
-N->getExtensionType());
+WideMemVT, dl, Ops, N->getMemOperand(),
+N->getIndexType(), N->getExtensionType());
 
   // Legalize the chain result - switch anything that used the old chain to
   // use the new one.
@@ -4881,6 +4884,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, 
unsigned OpNo) {
   SDValue Mask = MSC->getMask();
   SDValue Index = MSC->getIndex();
   SDValue Scale = MSC->getScale();
+  EVT WideMemVT = MSC->getMemoryVT();
 
   if (OpNo == 1) {
 DataOp = GetWidenedVector(DataOp);
@@ -4897,6 +4901,10 @@ SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, 
unsigned OpNo) {
 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
   MaskVT.getVectorElementType(), NumElts);
 Mask = ModifyToType(Mask, WideMaskVT, true);
+
+// Widen the MemoryType
+WideMemVT = EVT::getVectorVT(*DAG.getContext(),
+ MSC->getMemoryVT().getScalarType(), NumElts);
   } else if (OpNo == 4) {
 // Just widen the index. It's allowed to have extra elements.
 Index = GetWidenedVector(Index);
@@ -4905,9 +4913,8 @@ SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, 
unsigned OpNo) {
 
   SDValue Ops[] = {MSC->getChain(), DataOp, Mask, MSC->getBasePtr(), Index,
Scale};
-  return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
-  MSC->getMemoryVT(), SDLoc(N), Ops,
-  MSC->getMemOperand(), MSC->getIndexType(),
+  return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), WideMemVT, SDLoc(N),
+  Ops, MSC->getMemOperand(), MSC->getIndexType(),
   MSC->isTruncatingStore());
 }
 

diff  --git a/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll 
b/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
index ab62c3b92692..517553d455ae 100644
--- a/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
+++ b/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
@@ -247,6 +247,303 @@ define void @test_scatter_v2i32_data_index(<2 x i32> %a1, 
i32* %base, <2 x i32>
   ret void
 }
 
+define void @test_mscatter_v17f32(float* %base, <17 x i32> %index, <17 x 
float> %val)
+; WIDEN_SKX-LABEL: test_mscatter_v17f32:
+; WIDEN_SKX:   # %bb.0:
+; WIDEN_SKX-NEXT:vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]
+; WIDEN_SKX-NEXT:vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]
+; WIDEN_SKX-NEXT:vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
+; WIDEN_SKX-NEXT:vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; WIDEN_SKX-NEXT:vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
+; WIDEN_SKX-NEXT:vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
+; WIDEN_SKX-NEXT:vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; WIDEN_SKX-NEXT:vmovss {{.*#

[llvm-branch-commits] [llvm] eee30a6 - [CodeGen] Modify the refineIndexType(...)'s code to fix a bug in D90942.

2020-12-06 Thread Bing1 Yu via llvm-branch-commits

Author: Bing1 Yu
Date: 2020-12-07T08:49:07+08:00
New Revision: eee30a6dceb6da8467fa3e0a7cd35b5a221bed0f

URL: 
https://github.com/llvm/llvm-project/commit/eee30a6dceb6da8467fa3e0a7cd35b5a221bed0f
DIFF: 
https://github.com/llvm/llvm-project/commit/eee30a6dceb6da8467fa3e0a7cd35b5a221bed0f.diff

LOG: [CodeGen] Modify the refineIndexType(...)'s code to fix a bug in D90942.

In previous code, when refineIndexType(...) is called and Index is undef, 
Index.getOperand(0) will raise a assertion fail.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D92548

Added: 
llvm/test/CodeGen/X86/combine-undef-index-mscatter.ll

Modified: 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 




diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c40c2502f536..5481c52a5b12 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9413,9 +9413,9 @@ bool refineUniformBase(SDValue &BasePtr, SDValue &Index, 
SelectionDAG &DAG) {
 bool refineIndexType(MaskedScatterSDNode *MSC, SDValue &Index, bool Scaled,
  SelectionDAG &DAG) {
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-  SDValue Op = Index.getOperand(0);
 
   if (Index.getOpcode() == ISD::ZERO_EXTEND) {
+SDValue Op = Index.getOperand(0);
 MSC->setIndexType(Scaled ? ISD::UNSIGNED_SCALED : ISD::UNSIGNED_UNSCALED);
 if (TLI.shouldRemoveExtendFromGSIndex(Op.getValueType())) {
   Index = Op;
@@ -9424,6 +9424,7 @@ bool refineIndexType(MaskedScatterSDNode *MSC, SDValue 
&Index, bool Scaled,
   }
 
   if (Index.getOpcode() == ISD::SIGN_EXTEND) {
+SDValue Op = Index.getOperand(0);
 MSC->setIndexType(Scaled ? ISD::SIGNED_SCALED : ISD::SIGNED_UNSCALED);
 if (TLI.shouldRemoveExtendFromGSIndex(Op.getValueType())) {
   Index = Op;

diff  --git a/llvm/test/CodeGen/X86/combine-undef-index-mscatter.ll 
b/llvm/test/CodeGen/X86/combine-undef-index-mscatter.ll
new file mode 100644
index ..0b8ec5a0200c
--- /dev/null
+++ b/llvm/test/CodeGen/X86/combine-undef-index-mscatter.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s
+
+define void @main(<24 x float*> %x)
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmovq %rcx, %xmm0
+; CHECK-NEXT:vmovq %rdx, %xmm1
+; CHECK-NEXT:vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; CHECK-NEXT:vmovq %rsi, %xmm1
+; CHECK-NEXT:vmovq %rdi, %xmm2
+; CHECK-NEXT:vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; CHECK-NEXT:vinserti128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:vmovq %r9, %xmm1
+; CHECK-NEXT:vmovq %r8, %xmm2
+; CHECK-NEXT:vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; CHECK-NEXT:vinserti128 $1, {{[0-9]+}}(%rsp), %ymm1, %ymm1
+; CHECK-NEXT:vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; CHECK-NEXT:vmovups {{[0-9]+}}(%rsp), %zmm1
+; CHECK-NEXT:vmovups {{[0-9]+}}(%rsp), %zmm2
+; CHECK-NEXT:kxnorw %k0, %k0, %k1
+; CHECK-NEXT:vbroadcastf128 {{.*#+}} ymm3 = 
[8.33005607E-1,8.435871E-1,1.69435993E-1,8.33005607E-1,8.33005607E-1,8.435871E-1,1.69435993E-1,8.33005607E-1]
+; CHECK-NEXT:# ymm3 = mem[0,1,0,1]
+; CHECK-NEXT:kxnorw %k0, %k0, %k2
+; CHECK-NEXT:vscatterqps %ymm3, (,%zmm0) {%k2}
+; CHECK-NEXT:kxnorw %k0, %k0, %k2
+; CHECK-NEXT:vscatterqps %ymm3, (,%zmm2) {%k2}
+; CHECK-NEXT:vscatterqps %ymm3, (,%zmm1) {%k1}
+; CHECK-NEXT:vzeroupper
+; CHECK-NEXT:retq
+{
+entry:
+  call void @llvm.masked.scatter.v24f32.v24p0f32(<24 x float> , <24 x 
float*> %x, i32 4, <24 x i1> )
+  ret void
+}
+
+declare void @llvm.masked.scatter.v24f32.v24p0f32(<24 x float>, <24 x float*>, 
i32 immarg, <24 x i1>)



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