[llvm-branch-commits] [flang] [flang][OpenMP] Parsing context selectors for METADIRECTIVE (PR #121815)
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121815
>From 215c7e6133bf07d005ac7483b8faf797e319a1fa Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH] [flang][OpenMP] Parsing context selectors for METADIRECTIVE
This is just adding parsers for context selectors. There are no tests
because there is no way to execute these parsers yet.
---
flang/include/flang/Parser/characters.h | 2 +
flang/include/flang/Parser/dump-parse-tree.h | 14 ++
flang/include/flang/Parser/parse-tree.h | 136 +++
flang/lib/Parser/openmp-parsers.cpp | 78 +++
flang/lib/Parser/token-parsers.h | 4 +
flang/lib/Parser/unparse.cpp | 38 ++
flang/lib/Semantics/check-omp-structure.cpp | 8 ++
flang/lib/Semantics/check-omp-structure.h| 3 +
flang/lib/Semantics/resolve-directives.cpp | 6 +
9 files changed, 289 insertions(+)
diff --git a/flang/include/flang/Parser/characters.h
b/flang/include/flang/Parser/characters.h
index df188d674b9eeb..dbdc058c44995a 100644
--- a/flang/include/flang/Parser/characters.h
+++ b/flang/include/flang/Parser/characters.h
@@ -180,6 +180,8 @@ inline constexpr bool IsValidFortranTokenCharacter(char ch)
{
case '>':
case '[':
case ']':
+ case '{': // Used in OpenMP context selector specification
+ case '}': //
return true;
default:
return IsLegalIdentifierStart(ch) || IsDecimalDigit(ch);
diff --git a/flang/include/flang/Parser/dump-parse-tree.h
b/flang/include/flang/Parser/dump-parse-tree.h
index 3331520922bc63..a61d7973dd5c36 100644
--- a/flang/include/flang/Parser/dump-parse-tree.h
+++ b/flang/include/flang/Parser/dump-parse-tree.h
@@ -476,6 +476,20 @@ class ParseTreeDumper {
NODE(parser, NullInit)
NODE(parser, ObjectDecl)
NODE(parser, OldParameterStmt)
+ NODE(parser, OmpDirectiveSpecification)
+ NODE(parser, OmpTraitPropertyName)
+ NODE(parser, OmpTraitScore)
+ NODE(parser, OmpTraitPropertyExtension)
+ NODE(OmpTraitPropertyExtension, ExtensionValue)
+ NODE(parser, OmpTraitProperty)
+ NODE(parser, OmpTraitSelectorName)
+ NODE_ENUM(OmpTraitSelectorName, Value)
+ NODE(parser, OmpTraitSelector)
+ NODE(OmpTraitSelector, Properties)
+ NODE(parser, OmpTraitSetSelectorName)
+ NODE_ENUM(OmpTraitSetSelectorName, Value)
+ NODE(parser, OmpTraitSetSelector)
+ NODE(parser, OmpContextSelectorSpecification)
NODE(parser, OmpMapper)
NODE(parser, OmpMapType)
NODE_ENUM(OmpMapType, Value)
diff --git a/flang/include/flang/Parser/parse-tree.h
b/flang/include/flang/Parser/parse-tree.h
index 941d70d3876291..697bddfaf16150 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -3453,6 +3453,17 @@ WRAPPER_CLASS(PauseStmt, std::optional);
// --- Common definitions
+struct OmpClause;
+struct OmpClauseList;
+
+struct OmpDirectiveSpecification {
+ TUPLE_CLASS_BOILERPLATE(OmpDirectiveSpecification);
+ std::tuple>>
+ t;
+ CharBlock source;
+};
+
// 2.1 Directives or clauses may accept a list or extended-list.
// A list item is a variable, array section or common block name (enclosed
// in slashes). An extended list item is a list item or a procedure Name.
@@ -3474,6 +3485,128 @@ WRAPPER_CLASS(OmpObjectList, std::list);
#define MODIFIERS() std::optional>
+inline namespace traits {
+// trait-property-name ->
+//identifier | string-literal
+struct OmpTraitPropertyName {
+ WRAPPER_CLASS_BOILERPLATE(OmpTraitPropertyName, std::string);
+};
+
+// trait-score ->
+//SCORE(non-negative-const-integer-expression)
+struct OmpTraitScore {
+ WRAPPER_CLASS_BOILERPLATE(OmpTraitScore, ScalarIntExpr);
+};
+
+// trait-property-extension ->
+//trait-property-name (trait-property-value, ...)
+// trait-property-value ->
+//trait-property-name |
+//scalar-integer-expression |
+//trait-property-extension
+//
+// The grammar in OpenMP 5.2+ spec is ambiguous, the above is a different
+// version (but equivalent) that doesn't have ambiguities.
+// The ambiguity is in
+// trait-property:
+// trait-property-name <- (a)
+// trait-property-clause
+// trait-property-expression<- (b)
+// trait-property-extension <- this conflicts with (a) and (b)
+// trait-property-extension:
+// trait-property-name <- conflict with (a)
+// identifier(trait-property-extension[, trait-property-extension[, ...]])
+// constant integer expression <- conflict with (b)
+//
+struct OmpTraitPropertyExtension {
+ TUPLE_CLASS_BOILERPLATE(OmpTraitPropertyExtension);
+ struct ExtensionValue {
+UNION_CLASS_BOILERPLATE(ExtensionValue);
+std::variant>
+u;
+ };
+ using ExtensionList = std::list;
+ std::tuple t;
+};
+
+// trait-property ->
+//trait-property-name | OmpClause |
+//trait-property-expression | trait-property-extension
+// trait-property-expression ->
+//scala
[llvm-branch-commits] [flang] [llvm] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus METADIRECTIVE (PR #121817)
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121817
>From 5f534c559ca1bb7911b484264582d1a5078bdcb8 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH 1/4] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus
METADIRECTIVE
Parse METADIRECTIVE as a standalone executable directive at the moment.
This will allow testing the parser code.
There is no lowering, not even clause conversion yet. There is also no
verification of the allowed values for trait sets, trait properties.
---
flang/include/flang/Parser/dump-parse-tree.h | 5 +
flang/include/flang/Parser/parse-tree.h | 41 -
flang/lib/Lower/OpenMP/Clauses.cpp | 21 ++-
flang/lib/Lower/OpenMP/Clauses.h | 1 +
flang/lib/Lower/OpenMP/OpenMP.cpp| 6 +
flang/lib/Parser/openmp-parsers.cpp | 26 ++-
flang/lib/Parser/unparse.cpp | 12 ++
flang/lib/Semantics/check-omp-structure.cpp | 9 +
flang/lib/Semantics/check-omp-structure.h| 3 +
flang/lib/Semantics/resolve-directives.cpp | 5 +
flang/test/Parser/OpenMP/metadirective.f90 | 165 +++
llvm/include/llvm/Frontend/OpenMP/OMP.td | 9 +-
12 files changed, 296 insertions(+), 7 deletions(-)
create mode 100644 flang/test/Parser/OpenMP/metadirective.f90
diff --git a/flang/include/flang/Parser/dump-parse-tree.h
b/flang/include/flang/Parser/dump-parse-tree.h
index a61d7973dd5c36..94ca7c67cbd52e 100644
--- a/flang/include/flang/Parser/dump-parse-tree.h
+++ b/flang/include/flang/Parser/dump-parse-tree.h
@@ -476,6 +476,11 @@ class ParseTreeDumper {
NODE(parser, NullInit)
NODE(parser, ObjectDecl)
NODE(parser, OldParameterStmt)
+ NODE(parser, OmpMetadirectiveDirective)
+ NODE(parser, OmpMatchClause)
+ NODE(parser, OmpOtherwiseClause)
+ NODE(parser, OmpWhenClause)
+ NODE(OmpWhenClause, Modifier)
NODE(parser, OmpDirectiveSpecification)
NODE(parser, OmpTraitPropertyName)
NODE(parser, OmpTraitScore)
diff --git a/flang/include/flang/Parser/parse-tree.h
b/flang/include/flang/Parser/parse-tree.h
index 697bddfaf16150..113ff3380ba22c 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -3964,6 +3964,7 @@ struct OmpBindClause {
// data-sharing-attribute ->
//SHARED | NONE | // since 4.5
//PRIVATE | FIRSTPRIVATE// since 5.0
+// See also otherwise-clause.
struct OmpDefaultClause {
ENUM_CLASS(DataSharingAttribute, Private, Firstprivate, Shared, None)
WRAPPER_CLASS_BOILERPLATE(OmpDefaultClause, DataSharingAttribute);
@@ -4184,6 +4185,16 @@ struct OmpMapClause {
std::tuple t;
};
+// Ref: [5.0:58-60], [5.1:63-68], [5.2:194-195]
+//
+// match-clause ->
+//MATCH (context-selector-specification)// since 5.0
+struct OmpMatchClause {
+ // The context-selector is an argument.
+ WRAPPER_CLASS_BOILERPLATE(
+ OmpMatchClause, traits::OmpContextSelectorSpecification);
+};
+
// Ref: [5.2:217-218]
// message-clause ->
//MESSAGE("message-text")
@@ -4214,6 +4225,17 @@ struct OmpOrderClause {
std::tuple t;
};
+// Ref: [5.0:56-57], [5.1:60-62], [5.2:191]
+//
+// otherwise-clause ->
+//DEFAULT ([directive-specification]) // since 5.0, until 5.1
+// otherwise-clause ->
+//OTHERWISE ([directive-specification])]// since 5.2
+struct OmpOtherwiseClause {
+ WRAPPER_CLASS_BOILERPLATE(
+ OmpOtherwiseClause, std::optional);
+};
+
// Ref: [4.5:46-50], [5.0:74-78], [5.1:92-96], [5.2:229-230]
//
// proc-bind-clause ->
@@ -4299,6 +4321,17 @@ struct OmpUpdateClause {
std::variant u;
};
+// Ref: [5.0:56-57], [5.1:60-62], [5.2:190-191]
+//
+// when-clause ->
+//WHEN (context-selector :
+//[directive-specification])// since 5.0
+struct OmpWhenClause {
+ TUPLE_CLASS_BOILERPLATE(OmpWhenClause);
+ MODIFIER_BOILERPLATE(OmpContextSelector);
+ std::tuple> t;
+};
+
// OpenMP Clauses
struct OmpClause {
UNION_CLASS_BOILERPLATE(OmpClause);
@@ -4323,6 +4356,12 @@ struct OmpClauseList {
// --- Directives and constructs
+struct OmpMetadirectiveDirective {
+ TUPLE_CLASS_BOILERPLATE(OmpMetadirectiveDirective);
+ std::tuple t;
+ CharBlock source;
+};
+
// Ref: [5.1:89-90], [5.2:216]
//
// nothing-directive ->
@@ -4696,7 +4735,7 @@ struct OpenMPStandaloneConstruct {
CharBlock source;
std::variant
+ OpenMPDepobjConstruct, OmpMetadirectiveDirective>
u;
};
diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp
b/flang/lib/Lower/OpenMP/Clauses.cpp
index b424e209d56da9..d60171552087fa 100644
--- a/flang/lib/Lower/OpenMP/Clauses.cpp
+++ b/flang/lib/Lower/OpenMP/Clauses.cpp
@@ -230,9 +230,9 @@ MAKE_EMPTY_CLASS(Threadprivate, Threadprivate);
MAKE_INCOMPLETE_CLASS(AdjustArgs, AdjustArgs);
MAKE_INCOMPLETE_CLASS(AppendArgs, AppendArgs);
-MAKE_INCOMPLETE_CLASS(Match, Match);
+// MAKE_INCOMPLETE_CLASS(Match, Mat
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to NPM (PR #118462)
@@ -20,76 +20,138 @@
using namespace llvm;
-static cl::opt Mode(
+static cl::opt Mode(
"regalloc-enable-priority-advisor", cl::Hidden,
-cl::init(RegAllocPriorityAdvisorAnalysis::AdvisorMode::Default),
+cl::init(RegAllocPriorityAdvisorProvider::AdvisorMode::Default),
cl::desc("Enable regalloc advisor mode"),
cl::values(
-clEnumValN(RegAllocPriorityAdvisorAnalysis::AdvisorMode::Default,
+clEnumValN(RegAllocPriorityAdvisorProvider::AdvisorMode::Default,
"default", "Default"),
-clEnumValN(RegAllocPriorityAdvisorAnalysis::AdvisorMode::Release,
+clEnumValN(RegAllocPriorityAdvisorProvider::AdvisorMode::Release,
"release", "precompiled"),
-clEnumValN(RegAllocPriorityAdvisorAnalysis::AdvisorMode::Development,
+clEnumValN(RegAllocPriorityAdvisorProvider::AdvisorMode::Development,
"development", "for training")));
-char RegAllocPriorityAdvisorAnalysis::ID = 0;
-INITIALIZE_PASS(RegAllocPriorityAdvisorAnalysis, "regalloc-priority",
+char RegAllocPriorityAdvisorAnalysisLegacy::ID = 0;
+INITIALIZE_PASS(RegAllocPriorityAdvisorAnalysisLegacy, "regalloc-priority",
"Regalloc priority policy", false, true)
namespace {
-class DefaultPriorityAdvisorAnalysis final
-: public RegAllocPriorityAdvisorAnalysis {
+
+class DefaultPriorityAdvisorProvider final
+: public RegAllocPriorityAdvisorProvider {
public:
- DefaultPriorityAdvisorAnalysis(bool NotAsRequested)
- : RegAllocPriorityAdvisorAnalysis(AdvisorMode::Default),
+ DefaultPriorityAdvisorProvider(bool NotAsRequested, LLVMContext &Ctx)
+ : RegAllocPriorityAdvisorProvider(AdvisorMode::Default) {
+if (NotAsRequested)
+ Ctx.emitError("Requested regalloc priority advisor analysis "
+"could be created. Using default");
+ }
+
+ // support for isa<> and dyn_cast.
+ static bool classof(const RegAllocPriorityAdvisorProvider *R) {
+return R->getAdvisorMode() == AdvisorMode::Default;
+ }
+
+ std::unique_ptr
+ getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override {
+assert(SI && "SlotIndexes result must be set");
+return std::make_unique(MF, RA, SI);
+ }
+};
+
+class DefaultPriorityAdvisorAnalysisLegacy final
+: public RegAllocPriorityAdvisorAnalysisLegacy {
+public:
+ DefaultPriorityAdvisorAnalysisLegacy(bool NotAsRequested)
+ : RegAllocPriorityAdvisorAnalysisLegacy(AdvisorMode::Default),
NotAsRequested(NotAsRequested) {}
// support for isa<> and dyn_cast.
- static bool classof(const RegAllocPriorityAdvisorAnalysis *R) {
+ static bool classof(const RegAllocPriorityAdvisorAnalysisLegacy *R) {
return R->getAdvisorMode() == AdvisorMode::Default;
}
private:
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired();
-RegAllocPriorityAdvisorAnalysis::getAnalysisUsage(AU);
+RegAllocPriorityAdvisorAnalysisLegacy::getAnalysisUsage(AU);
}
- std::unique_ptr
- getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override {
-return std::make_unique(
-MF, RA, &getAnalysis().getSI());
+
+ std::unique_ptr &getProvider() override {
+Provider->setAnalyses(&getAnalysis().getSI());
+return Provider;
}
+
bool doInitialization(Module &M) override {
-if (NotAsRequested)
- M.getContext().emitError("Requested regalloc priority advisor analysis "
- "could be created. Using default");
-return RegAllocPriorityAdvisorAnalysis::doInitialization(M);
+Provider.reset(
+new DefaultPriorityAdvisorProvider(NotAsRequested, M.getContext()));
+return false;
}
+
const bool NotAsRequested;
+ // std::unique_ptr Provider;
};
} // namespace
-template <> Pass *llvm::callDefaultCtor() {
+void RegAllocPriorityAdvisorAnalysis::initializeProvider(LLVMContext &Ctx) {
+ if (Provider)
+return;
+
+ switch (Mode) {
+ case RegAllocPriorityAdvisorProvider::AdvisorMode::Default:
+Provider.reset(
+new DefaultPriorityAdvisorProvider(/*NotAsRequested*/ false, Ctx));
+break;
+ case RegAllocPriorityAdvisorProvider::AdvisorMode::Development:
+#if defined(LLVM_HAVE_TFLITE)
+Provider.reset(createDevelopmentModePriorityAdvisorProvider(Ctx));
+#endif
+break;
+ case RegAllocPriorityAdvisorProvider::AdvisorMode::Release:
+Provider.reset(createReleaseModePriorityAdvisorProvider());
+break;
+ }
+ if (!Provider)
+Provider.reset(
+new DefaultPriorityAdvisorProvider(/*NotAsRequested*/ true, Ctx));
arsenm wrote:
I see it's pre-existing. In a follow up, should fix this and the inconsistent
error message formatting
https://github.com/llvm/llvm-project/pull/118462
___
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[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to NPM (PR #118462)
@@ -357,3 +391,21 @@ DevelopmentModePriorityAdvisor::getPriority(const
LiveInterval &LI) const {
}
#endif // #ifdef LLVM_HAVE_TFLITE
+
+void RegAllocPriorityAdvisorAnalysis::initializeMLProvider(
+RegAllocPriorityAdvisorProvider::AdvisorMode Mode, LLVMContext &Ctx) {
+ if (Provider)
+return;
+ switch (Mode) {
+ case RegAllocPriorityAdvisorProvider::AdvisorMode::Development:
+#if defined(LLVM_HAVE_TFLITE)
+Provider.reset(new DevelopmentModePriorityAdvisorProvider(Ctx));
+#endif
+break;
+ case RegAllocPriorityAdvisorProvider::AdvisorMode::Release:
+Provider.reset(new ReleaseModePriorityAdvisorProvider());
+break;
+ default:
+break;
+ }
+}
arsenm wrote:
End of file whitespace error
https://github.com/llvm/llvm-project/pull/118462
___
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https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [RISCV] Change linker job in Baremetal toolchain object accomodate GCCInstallation.(2/3) (PR #121830)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121830
>From 3a0559c3db5e9fa366d17d461028223e418f2e66 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 09:21:11 -0800
Subject: [PATCH] [RISCV] Change linker job in Baremetal toolchain object to
accomodate valid GCCInstallation.(2/3)
This patch adds the defaults for CXXSstdlib type and other runtime libs.
Additionally, this patch also modifes the linker job and extend it to support
valid GCCInstallation.
This PR preserves the behavior of both toolchain objects in the linker job with
the only new change being that the presence of `--gcc-toolchain` or
`--gcc-install-dir` will imply that GNU linker is the default linker unless
otherwise a differnt linker is passed through `-fuse-ld` flag.
This is the second PR in the series of 3 PRs for merging and extending Baremetal
toolchain object. The division of the PRs is as follows:
- Teach Baremetal toolchain about GCC installation and make sysroot and
assembler
related changes.
- Changes related to linker job and defaults for CXXStdlib and other runtime
libs.
- Finally removing the call to RISCVToolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: I8fdb3490a3888001b1bb999e7ee8df90a187d18d
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 110 +++-
clang/lib/Driver/ToolChains/BareMetal.h | 21 ++--
clang/test/Driver/aarch64-toolchain-extra.c | 6 ++
clang/test/Driver/aarch64-toolchain.c | 73 +
clang/test/Driver/arm-toolchain-extra.c | 7 +-
clang/test/Driver/arm-toolchain.c | 77 +-
clang/test/Driver/baremetal-multilib.yaml | 2 +-
clang/test/Driver/baremetal-sysroot.cpp | 2 +-
clang/test/Driver/baremetal.cpp | 77 +++---
clang/test/Driver/sanitizer-ld.c| 2 +-
10 files changed, 301 insertions(+), 76 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 7b0f2bc2fd3895..38de25e20ea8df 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -172,6 +172,8 @@ BareMetal::BareMetal(const Driver &D, const llvm::Triple
&Triple,
: Generic_ELF(D, Triple, Args) {
GCCInstallation.init(Triple, Args);
SysRoot = computeSysRoot();
+ UseLD =
+ Args.getLastArgValue(options::OPT_fuse_ld_EQ).equals_insensitive("ld");
if (GCCInstallation.isValid()) {
Multilibs = GCCInstallation.getMultilibs();
SelectedMultilibs.assign({GCCInstallation.getMultilib()});
@@ -342,6 +344,32 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::CST_Libstdcxx;
+ return ToolChain::CST_Libcxx;
+}
+
+ToolChain::RuntimeLibType BareMetal::GetDefaultRuntimeLibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::RLT_Libgcc;
+ return ToolChain::RLT_CompilerRT;
+}
+
+ToolChain::UnwindLibType
+BareMetal::GetUnwindLibType(const llvm::opt::ArgList &Args) const {
+ if (getTriple().isRISCV())
+return ToolChain::UNW_None;
+
+ return ToolChain::GetUnwindLibType(Args);
+}
+
+const char *BareMetal::getDefaultLinker() const {
+ if (isUsingLD())
+return "ld";
+ return "ld.lld";
+}
+
void BareMetal::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
ArgStringList &CC1Args) const {
if (DriverArgs.hasArg(options::OPT_nostdinc))
@@ -535,12 +563,21 @@ void baremetal::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
const llvm::Triple::ArchType Arch = TC.getArch();
const llvm::Triple &Triple = getToolChain().getEffectiveTriple();
- AddLinkerInputs(TC, Inputs, Args, CmdArgs, JA);
+ if (!D.SysRoot.empty())
+CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot));
CmdArgs.push_back("-Bstatic");
- if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+ if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+ CmdArgs.push_back("--no-relax");
+if (TC.isUsingLD()) {
+ CmdArgs.push_back("-m");
+ CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+ : "elf32lriscv");
+}
+CmdArgs.push_back("-X");
+ }
if (Triple.isARM() || Triple.isThumb()) {
bool IsBigEndian = arm::isARMBigEndian(Triple, Args);
@@ -551,19 +588,54 @@ void baremetal::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
CmdArgs.push_back(Arch == llvm::Triple::aarch64_be ? "-EB" : "-EL");
}
- if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles,
- options::OPT_r)) {
-CmdArgs.pu
[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object.(3/3) (PR #121831)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From 824839c706f91d2d23c43fdd3ab1d930434112a3 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
and deprecate RISCVToolchain object.(3/3)
This PR is last in the series of merging RISCVToolchain object into BareMetal
toolchain object. This PR make change to call BareMetal toolchain object for
riscv targets as well and remove RISCVToolChain object.
The division of the PRs is as follows:
- Teach Baremetal toolchain about GCC installation and make sysroot and
assembler
related changes.
- Changes related to linker job and defaults for CXXStdlib and other runtime
libs.
- Finally removing the call to RISCVToolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: I2877ac328f55a7638cc185d6034866cbd2ac4203
---
clang/lib/Driver/CMakeLists.txt | 1 -
clang/lib/Driver/Driver.cpp | 7 +-
clang/test/Driver/riscv-args.c | 2 +-
clang/test/Driver/riscv32-toolchain-extra.c | 7 +++---
clang/test/Driver/riscv32-toolchain.c | 26 ++---
clang/test/Driver/riscv64-toolchain-extra.c | 7 +++---
clang/test/Driver/riscv64-toolchain.c | 20
7 files changed, 31 insertions(+), 39 deletions(-)
diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt
index 5bdb6614389cff..eee29af5d181a1 100644
--- a/clang/lib/Driver/CMakeLists.txt
+++ b/clang/lib/Driver/CMakeLists.txt
@@ -74,7 +74,6 @@ add_clang_library(clangDriver
ToolChains/OHOS.cpp
ToolChains/OpenBSD.cpp
ToolChains/PS4CPU.cpp
- ToolChains/RISCVToolchain.cpp
ToolChains/Solaris.cpp
ToolChains/SPIRV.cpp
ToolChains/SPIRVOpenMP.cpp
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 36d6c93c43321f..4dda9a34b08d99 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -41,7 +41,6 @@
#include "ToolChains/PPCFreeBSD.h"
#include "ToolChains/PPCLinux.h"
#include "ToolChains/PS4CPU.h"
-#include "ToolChains/RISCVToolchain.h"
#include "ToolChains/SPIRV.h"
#include "ToolChains/SPIRVOpenMP.h"
#include "ToolChains/SYCL.h"
@@ -6665,11 +6664,7 @@ const ToolChain &Driver::getToolChain(const ArgList
&Args,
break;
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
-if (toolchains::RISCVToolChain::hasGCCToolchain(*this, Args))
- TC =
- std::make_unique(*this, Target,
Args);
-else
- TC = std::make_unique(*this, Target, Args);
+TC = std::make_unique(*this, Target, Args);
break;
case llvm::Triple::ve:
TC = std::make_unique(*this, Target, Args);
diff --git a/clang/test/Driver/riscv-args.c b/clang/test/Driver/riscv-args.c
index cab08e5b0f811e..fc35407baf2cc6 100644
--- a/clang/test/Driver/riscv-args.c
+++ b/clang/test/Driver/riscv-args.c
@@ -3,4 +3,4 @@
// Make sure -T is the last with gcc-toolchain option
// RUN: %clang -### --target=riscv32 --gcc-toolchain= -Xlinker --defsym=FOO=10
-T a.lds -u foo %s 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LD %s
-// CHECK-LD: {{.*}} "--defsym=FOO=10" {{.*}} "-u" "foo" {{.*}} "-T" "a.lds"
+// CHECK-LD: {{.*}} "-T" "a.lds" "-u" "foo" {{.*}} "--defsym=FOO=10"
diff --git a/clang/test/Driver/riscv32-toolchain-extra.c
b/clang/test/Driver/riscv32-toolchain-extra.c
index cbb3c23ebb3421..420f7b52036090 100644
--- a/clang/test/Driver/riscv32-toolchain-extra.c
+++ b/clang/test/Driver/riscv32-toolchain-extra.c
@@ -18,12 +18,12 @@
// RUN: ln -s %S/Inputs/basic_riscv32_nogcc_tree/riscv32-unknown-elf
%t/riscv32-nogcc/riscv32-unknown-elf
// RUN: %t/riscv32-nogcc/bin/clang %s -### -no-canonical-prefixes \
// RUN:--gcc-toolchain=%t/riscv32-nogcc/invalid \
-// RUN:--target=riscv32-unknown-elf --rtlib=platform -fuse-ld= 2>&1 \
+// RUN:--target=riscv32-unknown-elf --rtlib=platform -fuse-ld=ld 2>&1 \
// RUN:| FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32-NOGCC %s
// RUN: %t/riscv32-nogcc/bin/clang %s -### -no-canonical-prefixes \
// RUN:--sysroot=%t/riscv32-nogcc/bin/../riscv32-unknown-elf \
-// RUN:--target=riscv32-unknown-elf --rtlib=platform -fuse-ld= 2>&1 \
+// RUN:--target=riscv32-unknown-elf --rtlib=platform -fuse-ld=ld 2>&1 \
// RUN:| FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32-NOGCC %s
// C-RV32-BAREMETAL-ILP32-NOGCC: "-internal-isystem"
"{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/include"
@@ -31,6 +31,5 @@
// C-RV32-BAREMETAL-ILP32-NOGCC:
"{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/lib/crt0.o"
// C-RV32-BAREMETAL-ILP32-NOGCC:
"{{.*}}/riscv32-nogcc/{{.*}}/riscv32-unknown-unknown-elf/clang_rt.crtbegin.o"
// C-RV32-BAREMETAL-ILP32-NOGCC:
"{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/lib"
-// C-RV32-BAREMETAL-ILP32-NOGCC: "--start-group" "-lc" "
[llvm-branch-commits] [clang] [RISCV] Change linker job in Baremetal toolchain object accomodate GCCInstallation.(2/3) (PR #121830)
https://github.com/quic-garvgupt edited https://github.com/llvm/llvm-project/pull/121830 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object.(3/3) (PR #121831)
https://github.com/quic-garvgupt edited https://github.com/llvm/llvm-project/pull/121831 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)
@@ -146,11 +149,137 @@ static cl::opt SplitThresholdForRegWithHint(
static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
createGreedyRegisterAllocator);
-char RAGreedy::ID = 0;
-char &llvm::RAGreedyID = RAGreedy::ID;
+namespace {
+class RAGreedyLegacy : public MachineFunctionPass {
+ RegAllocFilterFunc F;
-INITIALIZE_PASS_BEGIN(RAGreedy, "greedy",
-"Greedy Register Allocator", false, false)
+public:
+ RAGreedyLegacy(const RegAllocFilterFunc F = nullptr);
+
+ static char ID;
+ /// Return the pass name.
+ StringRef getPassName() const override { return "Greedy Register Allocator";
}
+
+ /// RAGreedy analysis usage.
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ /// Perform register allocation.
+ bool runOnMachineFunction(MachineFunction &mf) override;
+
+ MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoPHIs);
+ }
+
+ MachineFunctionProperties getClearedProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::IsSSA);
+ }
+};
+
+} // end anonymous namespace
+
+RAGreedyLegacy::RAGreedyLegacy(const RegAllocFilterFunc F)
+: MachineFunctionPass(ID), F(F) {
+ initializeRAGreedyLegacyPass(*PassRegistry::getPassRegistry());
+}
+
+RAGreedy::RAGreedy(const RegAllocFilterFunc F) : RegAllocBase(F) {}
+
+void RAGreedy::setAnalyses(RequiredAnalyses &Analyses) {
+ VRM = Analyses.VRM;
+ LIS = Analyses.LIS;
+ Matrix = Analyses.LRM;
+ Indexes = Analyses.Indexes;
+ MBFI = Analyses.MBFI;
+ DomTree = Analyses.DomTree;
+ Loops = Analyses.Loops;
+ ORE = Analyses.ORE;
+ Bundles = Analyses.Bundles;
+ SpillPlacer = Analyses.SpillPlacer;
+ DebugVars = Analyses.DebugVars;
+ LSS = Analyses.LSS;
+ EvictProvider = Analyses.EvictProvider;
+ PriorityProvider = Analyses.PriorityProvider;
+}
+
+void RAGreedyPass::printPipeline(raw_ostream &OS,
function_ref MapClassName2PassName) const {
+ StringRef FilterName = Opts.FilterName.empty() ? "all" : Opts.FilterName;
+ OS << "regallocgreedy<" << FilterName << ">";
+}
+
+PreservedAnalyses RAGreedyPass::run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM) {
+ MFPropsModifier _(*this, MF);
+
+ RAGreedy Impl(Opts.Filter);
+ RAGreedy::RequiredAnalyses Analyses;
+
+ Analyses.LIS = &MFAM.getResult(MF);
+ Analyses.LRM = &MFAM.getResult(MF);
+ Analyses.LSS = &MFAM.getResult(MF);
+ Analyses.Indexes = &MFAM.getResult(MF);
+ Analyses.MBFI = &MFAM.getResult(MF);
+ Analyses.DomTree = &MFAM.getResult(MF);
+ Analyses.ORE = &MFAM.getResult(MF);
+ Analyses.Loops = &MFAM.getResult(MF);
+ Analyses.Bundles = &MFAM.getResult(MF);
+ Analyses.SpillPlacer = &MFAM.getResult(MF);
+ Analyses.DebugVars = &MFAM.getResult(MF);
+ Analyses.EvictProvider =
+ MFAM.getResult(MF).Provider;
+ Analyses.PriorityProvider =
+ MFAM.getResult(MF).Provider;
+ Analyses.VRM = &MFAM.getResult(MF);
+
+ Impl.setAnalyses(Analyses);
arsenm wrote:
Can this just be done on construction of Impl?
https://github.com/llvm/llvm-project/pull/119540
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[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)
@@ -0,0 +1,43 @@
+//==- RegAllocGreedyPass.h --- greedy register allocator pass
--*-C++-*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/RegAllocCommon.h"
+#include "llvm/CodeGen/RegAllocFast.h"
+#include "llvm/IR/PassManager.h"
+
+using namespace llvm;
+
+class RAGreedyPass : public PassInfoMixin {
+
arsenm wrote:
```suggestion
```
https://github.com/llvm/llvm-project/pull/119540
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[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)
@@ -146,11 +149,137 @@ static cl::opt SplitThresholdForRegWithHint(
static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
createGreedyRegisterAllocator);
-char RAGreedy::ID = 0;
-char &llvm::RAGreedyID = RAGreedy::ID;
+namespace {
+class RAGreedyLegacy : public MachineFunctionPass {
+ RegAllocFilterFunc F;
-INITIALIZE_PASS_BEGIN(RAGreedy, "greedy",
-"Greedy Register Allocator", false, false)
+public:
+ RAGreedyLegacy(const RegAllocFilterFunc F = nullptr);
+
+ static char ID;
+ /// Return the pass name.
+ StringRef getPassName() const override { return "Greedy Register Allocator";
}
+
+ /// RAGreedy analysis usage.
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ /// Perform register allocation.
+ bool runOnMachineFunction(MachineFunction &mf) override;
+
+ MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoPHIs);
+ }
+
+ MachineFunctionProperties getClearedProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::IsSSA);
+ }
+};
+
+} // end anonymous namespace
+
+RAGreedyLegacy::RAGreedyLegacy(const RegAllocFilterFunc F)
+: MachineFunctionPass(ID), F(F) {
+ initializeRAGreedyLegacyPass(*PassRegistry::getPassRegistry());
+}
+
+RAGreedy::RAGreedy(const RegAllocFilterFunc F) : RegAllocBase(F) {}
+
+void RAGreedy::setAnalyses(RequiredAnalyses &Analyses) {
+ VRM = Analyses.VRM;
+ LIS = Analyses.LIS;
+ Matrix = Analyses.LRM;
+ Indexes = Analyses.Indexes;
+ MBFI = Analyses.MBFI;
+ DomTree = Analyses.DomTree;
+ Loops = Analyses.Loops;
+ ORE = Analyses.ORE;
+ Bundles = Analyses.Bundles;
+ SpillPlacer = Analyses.SpillPlacer;
+ DebugVars = Analyses.DebugVars;
+ LSS = Analyses.LSS;
+ EvictProvider = Analyses.EvictProvider;
+ PriorityProvider = Analyses.PriorityProvider;
+}
+
+void RAGreedyPass::printPipeline(raw_ostream &OS,
function_ref MapClassName2PassName) const {
+ StringRef FilterName = Opts.FilterName.empty() ? "all" : Opts.FilterName;
+ OS << "regallocgreedy<" << FilterName << ">";
arsenm wrote:
```suggestion
OS << "regallocgreedy<" << FilterName << '>';
```
https://github.com/llvm/llvm-project/pull/119540
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[llvm-branch-commits] [clang] [llvm] [mlir] [OMPIRBuilder] Introduce struct to hold default kernel teams/threads (PR #116050)
@@ -2726,15 +2740,11 @@ class OpenMPIRBuilder {
///
/// \param Loc The insert and source location description.
/// \param IsSPMD Flag to indicate if the kernel is an SPMD kernel or not.
- /// \param MinThreads Minimal number of threads, or 0.
- /// \param MaxThreads Maximal number of threads, or 0.
- /// \param MinTeams Minimal number of teams, or 0.
- /// \param MaxTeams Maximal number of teams, or 0.
- InsertPointTy createTargetInit(const LocationDescription &Loc, bool IsSPMD,
- int32_t MinThreadsVal = 0,
- int32_t MaxThreadsVal = 0,
- int32_t MinTeamsVal = 0,
- int32_t MaxTeamsVal = 0);
+ /// \param Attrs Structure containing the default numbers of threads and
teams
+ ///to launch the kernel with.
+ InsertPointTy createTargetInit(
+ const LocationDescription &Loc, bool IsSPMD,
+ const llvm::OpenMPIRBuilder::TargetKernelDefaultAttrs &Attrs);
jsjodin wrote:
Should IsSPMD also be part of Attrs also?
https://github.com/llvm/llvm-project/pull/116050
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[llvm-branch-commits] [flang] [llvm] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus METADIRECTIVE (PR #121817)
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121817
>From 5f534c559ca1bb7911b484264582d1a5078bdcb8 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH 1/4] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus
METADIRECTIVE
Parse METADIRECTIVE as a standalone executable directive at the moment.
This will allow testing the parser code.
There is no lowering, not even clause conversion yet. There is also no
verification of the allowed values for trait sets, trait properties.
---
flang/include/flang/Parser/dump-parse-tree.h | 5 +
flang/include/flang/Parser/parse-tree.h | 41 -
flang/lib/Lower/OpenMP/Clauses.cpp | 21 ++-
flang/lib/Lower/OpenMP/Clauses.h | 1 +
flang/lib/Lower/OpenMP/OpenMP.cpp| 6 +
flang/lib/Parser/openmp-parsers.cpp | 26 ++-
flang/lib/Parser/unparse.cpp | 12 ++
flang/lib/Semantics/check-omp-structure.cpp | 9 +
flang/lib/Semantics/check-omp-structure.h| 3 +
flang/lib/Semantics/resolve-directives.cpp | 5 +
flang/test/Parser/OpenMP/metadirective.f90 | 165 +++
llvm/include/llvm/Frontend/OpenMP/OMP.td | 9 +-
12 files changed, 296 insertions(+), 7 deletions(-)
create mode 100644 flang/test/Parser/OpenMP/metadirective.f90
diff --git a/flang/include/flang/Parser/dump-parse-tree.h
b/flang/include/flang/Parser/dump-parse-tree.h
index a61d7973dd5c36..94ca7c67cbd52e 100644
--- a/flang/include/flang/Parser/dump-parse-tree.h
+++ b/flang/include/flang/Parser/dump-parse-tree.h
@@ -476,6 +476,11 @@ class ParseTreeDumper {
NODE(parser, NullInit)
NODE(parser, ObjectDecl)
NODE(parser, OldParameterStmt)
+ NODE(parser, OmpMetadirectiveDirective)
+ NODE(parser, OmpMatchClause)
+ NODE(parser, OmpOtherwiseClause)
+ NODE(parser, OmpWhenClause)
+ NODE(OmpWhenClause, Modifier)
NODE(parser, OmpDirectiveSpecification)
NODE(parser, OmpTraitPropertyName)
NODE(parser, OmpTraitScore)
diff --git a/flang/include/flang/Parser/parse-tree.h
b/flang/include/flang/Parser/parse-tree.h
index 697bddfaf16150..113ff3380ba22c 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -3964,6 +3964,7 @@ struct OmpBindClause {
// data-sharing-attribute ->
//SHARED | NONE | // since 4.5
//PRIVATE | FIRSTPRIVATE// since 5.0
+// See also otherwise-clause.
struct OmpDefaultClause {
ENUM_CLASS(DataSharingAttribute, Private, Firstprivate, Shared, None)
WRAPPER_CLASS_BOILERPLATE(OmpDefaultClause, DataSharingAttribute);
@@ -4184,6 +4185,16 @@ struct OmpMapClause {
std::tuple t;
};
+// Ref: [5.0:58-60], [5.1:63-68], [5.2:194-195]
+//
+// match-clause ->
+//MATCH (context-selector-specification)// since 5.0
+struct OmpMatchClause {
+ // The context-selector is an argument.
+ WRAPPER_CLASS_BOILERPLATE(
+ OmpMatchClause, traits::OmpContextSelectorSpecification);
+};
+
// Ref: [5.2:217-218]
// message-clause ->
//MESSAGE("message-text")
@@ -4214,6 +4225,17 @@ struct OmpOrderClause {
std::tuple t;
};
+// Ref: [5.0:56-57], [5.1:60-62], [5.2:191]
+//
+// otherwise-clause ->
+//DEFAULT ([directive-specification]) // since 5.0, until 5.1
+// otherwise-clause ->
+//OTHERWISE ([directive-specification])]// since 5.2
+struct OmpOtherwiseClause {
+ WRAPPER_CLASS_BOILERPLATE(
+ OmpOtherwiseClause, std::optional);
+};
+
// Ref: [4.5:46-50], [5.0:74-78], [5.1:92-96], [5.2:229-230]
//
// proc-bind-clause ->
@@ -4299,6 +4321,17 @@ struct OmpUpdateClause {
std::variant u;
};
+// Ref: [5.0:56-57], [5.1:60-62], [5.2:190-191]
+//
+// when-clause ->
+//WHEN (context-selector :
+//[directive-specification])// since 5.0
+struct OmpWhenClause {
+ TUPLE_CLASS_BOILERPLATE(OmpWhenClause);
+ MODIFIER_BOILERPLATE(OmpContextSelector);
+ std::tuple> t;
+};
+
// OpenMP Clauses
struct OmpClause {
UNION_CLASS_BOILERPLATE(OmpClause);
@@ -4323,6 +4356,12 @@ struct OmpClauseList {
// --- Directives and constructs
+struct OmpMetadirectiveDirective {
+ TUPLE_CLASS_BOILERPLATE(OmpMetadirectiveDirective);
+ std::tuple t;
+ CharBlock source;
+};
+
// Ref: [5.1:89-90], [5.2:216]
//
// nothing-directive ->
@@ -4696,7 +4735,7 @@ struct OpenMPStandaloneConstruct {
CharBlock source;
std::variant
+ OpenMPDepobjConstruct, OmpMetadirectiveDirective>
u;
};
diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp
b/flang/lib/Lower/OpenMP/Clauses.cpp
index b424e209d56da9..d60171552087fa 100644
--- a/flang/lib/Lower/OpenMP/Clauses.cpp
+++ b/flang/lib/Lower/OpenMP/Clauses.cpp
@@ -230,9 +230,9 @@ MAKE_EMPTY_CLASS(Threadprivate, Threadprivate);
MAKE_INCOMPLETE_CLASS(AdjustArgs, AdjustArgs);
MAKE_INCOMPLETE_CLASS(AppendArgs, AppendArgs);
-MAKE_INCOMPLETE_CLASS(Match, Match);
+// MAKE_INCOMPLETE_CLASS(Match, Mat
[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)
@@ -2060,9 +2060,28 @@ bool AtomicExpandImpl::expandAtomicOpToLibcall(
I->replaceAllUsesWith(V);
} else if (HasResult) {
Value *V;
-if (UseSizedLibcall)
- V = Builder.CreateBitOrPointerCast(Result, I->getType());
-else {
+if (UseSizedLibcall) {
+ // Add bitcasts from Result's T scalar type to I's <2 x T/2> vector type
+ if (I->getType()->getScalarType()->isIntOrPtrTy() &&
+ I->getType()->isVectorTy() && !Result->getType()->isVectorTy()) {
+TypeSize Size = Result->getType()->getPrimitiveSizeInBits();
+assert((unsigned)Size % 2 == 0);
arsenm wrote:
Why does this only need to half the size?
https://github.com/llvm/llvm-project/pull/120716
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[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)
@@ -151,3 +151,17 @@ define void @pointer_cmpxchg_expand6(ptr addrspace(1) %ptr,
ret void
}
+define <2 x ptr> @atomic_vec2_ptr_align(ptr %x) nounwind {
+; CHECK-LABEL: @atomic_vec2_ptr_align(
+; CHECK-NEXT:[[TMP1:%.*]] = call i128 @__atomic_load_16(ptr [[X:%.*]], i32
2)
+; CHECK-NEXT:[[TMP2:%.*]] = trunc i128 [[TMP1]] to i64
+; CHECK-NEXT:[[TMP3:%.*]] = lshr i128 [[TMP1]], 64
+; CHECK-NEXT:[[TMP4:%.*]] = trunc i128 [[TMP3]] to i64
+; CHECK-NEXT:[[TMP5:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]],
i32 0
+; CHECK-NEXT:[[TMP6:%.*]] = insertelement <2 x i64> [[TMP5]], i64
[[TMP4]], i32 1
+; CHECK-NEXT:[[TMP7:%.*]] = inttoptr <2 x i64> [[TMP6]] to <2 x ptr>
+; CHECK-NEXT:ret <2 x ptr> [[TMP7]]
+;
+ %ret = load atomic <2 x ptr>, ptr %x acquire, align 16
+ ret <2 x ptr> %ret
+}
arsenm wrote:
Check addrspace(270) vector. Also FP and int cases?
https://github.com/llvm/llvm-project/pull/120716
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[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #120716)
@@ -151,3 +151,17 @@ define void @pointer_cmpxchg_expand6(ptr addrspace(1) %ptr,
ret void
}
+define <2 x ptr> @atomic_vec2_ptr_align(ptr %x) nounwind {
+; CHECK-LABEL: @atomic_vec2_ptr_align(
+; CHECK-NEXT:[[TMP1:%.*]] = call i128 @__atomic_load_16(ptr [[X:%.*]], i32
2)
+; CHECK-NEXT:[[TMP2:%.*]] = trunc i128 [[TMP1]] to i64
+; CHECK-NEXT:[[TMP3:%.*]] = lshr i128 [[TMP1]], 64
+; CHECK-NEXT:[[TMP4:%.*]] = trunc i128 [[TMP3]] to i64
+; CHECK-NEXT:[[TMP5:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]],
i32 0
+; CHECK-NEXT:[[TMP6:%.*]] = insertelement <2 x i64> [[TMP5]], i64
[[TMP4]], i32 1
+; CHECK-NEXT:[[TMP7:%.*]] = inttoptr <2 x i64> [[TMP6]] to <2 x ptr>
arsenm wrote:
I don't understand why you need to do all this work to decompose the integer
into pieces. You can just do bitcast i128 to `<2 x ptr>` and then `inttoptr <2
x i64> to <2 x ptr>`?
https://github.com/llvm/llvm-project/pull/120716
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[llvm-branch-commits] [clang] [RISCV] Change linker job in Baremetal toolchain object accomodate GCCInstallation.(2/3) (PR #121830)
@@ -59,4 +97,39 @@
// RUN: | FileCheck -check-prefix=CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX %s
// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX: "-internal-isystem"
"{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/../../../../armv6m-none-eabi/include/c++/v1"
-// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX: "-internal-isystem"
"{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/../../../../armv6m-none-eabi/include
\ No newline at end of file
+// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX: "-internal-isystem"
"{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/../../../../armv6m-none-eabi/include"
+// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX: "{{.*}}/ld" "-Bstatic" "-EL"
+// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX:
"{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/../../../../armv6m-none-eabi/lib/crt0.o"
+// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX:
"{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o"
+// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX:
"-L{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1"
+// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX:
"-L{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/../../../../armv6m-none-eabi/lib"
+// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX: "-lc++" "-lm" "--start-group" "-lgcc_s"
"-lgcc" "-lc" "-lgloss" "--end-group"
+// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX:
"{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o"
+
+// RUN: %clang -### %s -fuse-ld= \
+// RUN: --target=armv6m-none-eabi --rtlib=compiler-rt \
+// RUN: --gcc-toolchain=%S/Inputs/basic_arm_gcc_tree \
+// RUN: --sysroot=%S/Inputs/basic_arm_gcc_tree/armv6m-none-eabi 2>&1 \
+// RUN: | FileCheck -check-prefix=ARM-BAREMETAL-COMPILER-RT %s
+
+// ARM-BAREMETAL-COMPILER-RT: "{{.*}}crt0.o"
+// ARM-BAREMETAL-COMPILER-RT: "{{.*}}clang_rt.crtbegin.o"
+// ARM-BAREMETAL-COMPILER-RT: "--start-group" "{{.*}}libclang_rt.builtins.a"
"-lc" "-lgloss" "--end-group"
+// ARM-BAREMETAL-COMPILER-RT: "{{.*}}clang_rt.crtend.o"
+
+// RUN: %clang -### %s -fuse-ld= \
+// RUN: --target=armv6m-none-eabi --unwindlib=libunwind \
+// RUN: --gcc-toolchain=%S/Inputs/basic_arm_gcc_tree \
+// RUN: --sysroot=%S/Inputs/basic_arm_gcc_tree/armv6m-none-eabi 2>&1 \
+// RUN: | FileCheck -check-prefix=ARM-BAREMETAL-UNWINDLIB %s
+
+// RUN: %clang -### %s -fuse-ld= \
+// RUN: --target=armv6m-none-eabi --rtlib=compiler-rt --unwindlib=libunwind \
+// RUN: --gcc-toolchain=%S/Inputs/basic_arm_gcc_tree \
+// RUN: --sysroot=%S/Inputs/basic_arm_gcc_tree/armv6m-none-eabi 2>&1 \
+// RUN: | FileCheck -check-prefix=ARM-BAREMETAL-UNWINDLIB %s
+
+// ARM-BAREMETAL-UNWINDLIB: "{{.*}}crt0.o"
+// ARM-BAREMETAL-UNWINDLIB: "{{.*}}clang_rt.crtbegin.o"
+// ARM-BAREMETAL-UNWINDLIB: "--start-group" "{{.*}}libclang_rt.builtins.a"
"--as-needed" "-lunwind" "--no-as-needed" "-lc" "-lgloss" "--end-group"
+// ARM-BAREMETAL-UNWINDLIB: "{{.*}}clang_rt.crtend.o"
quic-garvgupt wrote:
Resolved
https://github.com/llvm/llvm-project/pull/121830
___
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[llvm-branch-commits] [flang] [llvm] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus METADIRECTIVE (PR #121817)
kparzysz wrote: The build failures are unrelated to the code. There is some flaky testcase that causes the breakage. https://github.com/llvm/llvm-project/pull/121817 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [DataLayout][LangRef] Split non-integral and unstable pointer properties (PR #105735)
@@ -650,48 +650,127 @@ literal types are uniqued in recent versions of LLVM. .. _nointptrtype: -Non-Integral Pointer Type -- +Non-Integral and Unstable Pointer Types +--- -Note: non-integral pointer types are a work in progress, and they should be -considered experimental at this time. +Note: non-integral/unstable pointer types are a work in progress, and they +should be considered experimental at this time. LLVM IR optionally allows the frontend to denote pointers in certain address -spaces as "non-integral" via the :ref:`datalayout string`. -Non-integral pointer types represent pointers that have an *unspecified* bitwise -representation; that is, the integral representation may be target dependent or -unstable (not backed by a fixed integer). +spaces as "non-integral" or "unstable" (or both "non-integral" and "unstable") +via the :ref:`datalayout string`. + +The exact implications of these properties are target-specific, but the +following IR semantics and restrictions to optimization passes apply: + +Unstable pointer representation +^^^ + +Pointers in this address space have an *unspecified* bitwise representation +(i.e. not backed by a fixed integer). The bitwise pattern of such pointers is +allowed to change in a target-specific way. For example, this could be a pointer +type used with copying garbage collection where the garbage collector could +update the pointer at any time in the collection sweep. ``inttoptr`` and ``ptrtoint`` instructions have the same semantics as for integral (i.e. normal) pointers in that they convert integers to and from -corresponding pointer types, but there are additional implications to be -aware of. Because the bit-representation of a non-integral pointer may -not be stable, two identical casts of the same operand may or may not +corresponding pointer types, but there are additional implications to be aware +of. + +For "unstable" pointer representations, the bit-representation of the pointer +may not be stable, so two identical casts of the same operand may or may not return the same value. Said differently, the conversion to or from the -non-integral type depends on environmental state in an implementation +"unstable" pointer type depends on environmental state in an implementation defined manner. - If the frontend wishes to observe a *particular* value following a cast, the generated IR must fence with the underlying environment in an implementation defined manner. (In practice, this tends to require ``noinline`` routines for such operations.) From the perspective of the optimizer, ``inttoptr`` and ``ptrtoint`` for -non-integral types are analogous to ones on integral types with one +"unstable" pointer types are analogous to ones on integral types with one key exception: the optimizer may not, in general, insert new dynamic occurrences of such casts. If a new cast is inserted, the optimizer would need to either ensure that a) all possible values are valid, or b) appropriate fencing is inserted. Since the appropriate fencing is implementation defined, the optimizer can't do the latter. The former is challenging as many commonly expected properties, such as -``ptrtoint(v)-ptrtoint(v) == 0``, don't hold for non-integral types. +``ptrtoint(v)-ptrtoint(v) == 0``, don't hold for "unstable" pointer types. Similar restrictions apply to intrinsics that might examine the pointer bits, such as :ref:`llvm.ptrmask`. -The alignment information provided by the frontend for a non-integral pointer +The alignment information provided by the frontend for an "unstable" pointer (typically using attributes or metadata) must be valid for every possible representation of the pointer. +Non-integral pointer representation +^^^ + +Pointers are not represented as just an address, but may instead include +additional metadata such as bounds information or a temporal identifier. +Examples include AMDGPU buffer descriptors with a 128-bit fat pointer and a +32-bit offset, or CHERI capabilities that contain bounds, permissions and a +type field (as well as an out-of-band validity bit, see next section). +In general, valid non-integral pointers cannot becreated from just an integer +value: while ``inttoptr`` yields a deterministic bitwise pattern, the resulting +value is not guaranteed to be a valid dereferenceable pointer. + +In most cases pointers with a non-integral representation behave exactly the +same as an integral pointer, the only difference is that it is not possible to +create a pointer just from an address. + +"Non-integral" pointers also impose restrictions on transformation passes, but +in general these are less restrictive than for "unstable" pointers. The main +difference compared to integral pointers is that ``inttoptr`` instructions +should not be inserted by passes as they may not be able to create a vali
[llvm-branch-commits] Reapply "[Fuchsia][cmake] Allow using FatLTO when building runtimes" (#119252) (PR #121820)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/121820 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Reapply "[Fuchsia][cmake] Allow using FatLTO when building runtimes" (#119252) (PR #121820)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/121820 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [llvm] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus METADIRECTIVE (PR #121817)
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121817
>From 5f534c559ca1bb7911b484264582d1a5078bdcb8 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH 1/5] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus
METADIRECTIVE
Parse METADIRECTIVE as a standalone executable directive at the moment.
This will allow testing the parser code.
There is no lowering, not even clause conversion yet. There is also no
verification of the allowed values for trait sets, trait properties.
---
flang/include/flang/Parser/dump-parse-tree.h | 5 +
flang/include/flang/Parser/parse-tree.h | 41 -
flang/lib/Lower/OpenMP/Clauses.cpp | 21 ++-
flang/lib/Lower/OpenMP/Clauses.h | 1 +
flang/lib/Lower/OpenMP/OpenMP.cpp| 6 +
flang/lib/Parser/openmp-parsers.cpp | 26 ++-
flang/lib/Parser/unparse.cpp | 12 ++
flang/lib/Semantics/check-omp-structure.cpp | 9 +
flang/lib/Semantics/check-omp-structure.h| 3 +
flang/lib/Semantics/resolve-directives.cpp | 5 +
flang/test/Parser/OpenMP/metadirective.f90 | 165 +++
llvm/include/llvm/Frontend/OpenMP/OMP.td | 9 +-
12 files changed, 296 insertions(+), 7 deletions(-)
create mode 100644 flang/test/Parser/OpenMP/metadirective.f90
diff --git a/flang/include/flang/Parser/dump-parse-tree.h
b/flang/include/flang/Parser/dump-parse-tree.h
index a61d7973dd5c36..94ca7c67cbd52e 100644
--- a/flang/include/flang/Parser/dump-parse-tree.h
+++ b/flang/include/flang/Parser/dump-parse-tree.h
@@ -476,6 +476,11 @@ class ParseTreeDumper {
NODE(parser, NullInit)
NODE(parser, ObjectDecl)
NODE(parser, OldParameterStmt)
+ NODE(parser, OmpMetadirectiveDirective)
+ NODE(parser, OmpMatchClause)
+ NODE(parser, OmpOtherwiseClause)
+ NODE(parser, OmpWhenClause)
+ NODE(OmpWhenClause, Modifier)
NODE(parser, OmpDirectiveSpecification)
NODE(parser, OmpTraitPropertyName)
NODE(parser, OmpTraitScore)
diff --git a/flang/include/flang/Parser/parse-tree.h
b/flang/include/flang/Parser/parse-tree.h
index 697bddfaf16150..113ff3380ba22c 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -3964,6 +3964,7 @@ struct OmpBindClause {
// data-sharing-attribute ->
//SHARED | NONE | // since 4.5
//PRIVATE | FIRSTPRIVATE// since 5.0
+// See also otherwise-clause.
struct OmpDefaultClause {
ENUM_CLASS(DataSharingAttribute, Private, Firstprivate, Shared, None)
WRAPPER_CLASS_BOILERPLATE(OmpDefaultClause, DataSharingAttribute);
@@ -4184,6 +4185,16 @@ struct OmpMapClause {
std::tuple t;
};
+// Ref: [5.0:58-60], [5.1:63-68], [5.2:194-195]
+//
+// match-clause ->
+//MATCH (context-selector-specification)// since 5.0
+struct OmpMatchClause {
+ // The context-selector is an argument.
+ WRAPPER_CLASS_BOILERPLATE(
+ OmpMatchClause, traits::OmpContextSelectorSpecification);
+};
+
// Ref: [5.2:217-218]
// message-clause ->
//MESSAGE("message-text")
@@ -4214,6 +4225,17 @@ struct OmpOrderClause {
std::tuple t;
};
+// Ref: [5.0:56-57], [5.1:60-62], [5.2:191]
+//
+// otherwise-clause ->
+//DEFAULT ([directive-specification]) // since 5.0, until 5.1
+// otherwise-clause ->
+//OTHERWISE ([directive-specification])]// since 5.2
+struct OmpOtherwiseClause {
+ WRAPPER_CLASS_BOILERPLATE(
+ OmpOtherwiseClause, std::optional);
+};
+
// Ref: [4.5:46-50], [5.0:74-78], [5.1:92-96], [5.2:229-230]
//
// proc-bind-clause ->
@@ -4299,6 +4321,17 @@ struct OmpUpdateClause {
std::variant u;
};
+// Ref: [5.0:56-57], [5.1:60-62], [5.2:190-191]
+//
+// when-clause ->
+//WHEN (context-selector :
+//[directive-specification])// since 5.0
+struct OmpWhenClause {
+ TUPLE_CLASS_BOILERPLATE(OmpWhenClause);
+ MODIFIER_BOILERPLATE(OmpContextSelector);
+ std::tuple> t;
+};
+
// OpenMP Clauses
struct OmpClause {
UNION_CLASS_BOILERPLATE(OmpClause);
@@ -4323,6 +4356,12 @@ struct OmpClauseList {
// --- Directives and constructs
+struct OmpMetadirectiveDirective {
+ TUPLE_CLASS_BOILERPLATE(OmpMetadirectiveDirective);
+ std::tuple t;
+ CharBlock source;
+};
+
// Ref: [5.1:89-90], [5.2:216]
//
// nothing-directive ->
@@ -4696,7 +4735,7 @@ struct OpenMPStandaloneConstruct {
CharBlock source;
std::variant
+ OpenMPDepobjConstruct, OmpMetadirectiveDirective>
u;
};
diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp
b/flang/lib/Lower/OpenMP/Clauses.cpp
index b424e209d56da9..d60171552087fa 100644
--- a/flang/lib/Lower/OpenMP/Clauses.cpp
+++ b/flang/lib/Lower/OpenMP/Clauses.cpp
@@ -230,9 +230,9 @@ MAKE_EMPTY_CLASS(Threadprivate, Threadprivate);
MAKE_INCOMPLETE_CLASS(AdjustArgs, AdjustArgs);
MAKE_INCOMPLETE_CLASS(AppendArgs, AppendArgs);
-MAKE_INCOMPLETE_CLASS(Match, Match);
+// MAKE_INCOMPLETE_CLASS(Match, Mat
[llvm-branch-commits] [flang] [llvm] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus METADIRECTIVE (PR #121817)
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121817
>From 5f534c559ca1bb7911b484264582d1a5078bdcb8 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH 1/7] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus
METADIRECTIVE
Parse METADIRECTIVE as a standalone executable directive at the moment.
This will allow testing the parser code.
There is no lowering, not even clause conversion yet. There is also no
verification of the allowed values for trait sets, trait properties.
---
flang/include/flang/Parser/dump-parse-tree.h | 5 +
flang/include/flang/Parser/parse-tree.h | 41 -
flang/lib/Lower/OpenMP/Clauses.cpp | 21 ++-
flang/lib/Lower/OpenMP/Clauses.h | 1 +
flang/lib/Lower/OpenMP/OpenMP.cpp| 6 +
flang/lib/Parser/openmp-parsers.cpp | 26 ++-
flang/lib/Parser/unparse.cpp | 12 ++
flang/lib/Semantics/check-omp-structure.cpp | 9 +
flang/lib/Semantics/check-omp-structure.h| 3 +
flang/lib/Semantics/resolve-directives.cpp | 5 +
flang/test/Parser/OpenMP/metadirective.f90 | 165 +++
llvm/include/llvm/Frontend/OpenMP/OMP.td | 9 +-
12 files changed, 296 insertions(+), 7 deletions(-)
create mode 100644 flang/test/Parser/OpenMP/metadirective.f90
diff --git a/flang/include/flang/Parser/dump-parse-tree.h
b/flang/include/flang/Parser/dump-parse-tree.h
index a61d7973dd5c36..94ca7c67cbd52e 100644
--- a/flang/include/flang/Parser/dump-parse-tree.h
+++ b/flang/include/flang/Parser/dump-parse-tree.h
@@ -476,6 +476,11 @@ class ParseTreeDumper {
NODE(parser, NullInit)
NODE(parser, ObjectDecl)
NODE(parser, OldParameterStmt)
+ NODE(parser, OmpMetadirectiveDirective)
+ NODE(parser, OmpMatchClause)
+ NODE(parser, OmpOtherwiseClause)
+ NODE(parser, OmpWhenClause)
+ NODE(OmpWhenClause, Modifier)
NODE(parser, OmpDirectiveSpecification)
NODE(parser, OmpTraitPropertyName)
NODE(parser, OmpTraitScore)
diff --git a/flang/include/flang/Parser/parse-tree.h
b/flang/include/flang/Parser/parse-tree.h
index 697bddfaf16150..113ff3380ba22c 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -3964,6 +3964,7 @@ struct OmpBindClause {
// data-sharing-attribute ->
//SHARED | NONE | // since 4.5
//PRIVATE | FIRSTPRIVATE// since 5.0
+// See also otherwise-clause.
struct OmpDefaultClause {
ENUM_CLASS(DataSharingAttribute, Private, Firstprivate, Shared, None)
WRAPPER_CLASS_BOILERPLATE(OmpDefaultClause, DataSharingAttribute);
@@ -4184,6 +4185,16 @@ struct OmpMapClause {
std::tuple t;
};
+// Ref: [5.0:58-60], [5.1:63-68], [5.2:194-195]
+//
+// match-clause ->
+//MATCH (context-selector-specification)// since 5.0
+struct OmpMatchClause {
+ // The context-selector is an argument.
+ WRAPPER_CLASS_BOILERPLATE(
+ OmpMatchClause, traits::OmpContextSelectorSpecification);
+};
+
// Ref: [5.2:217-218]
// message-clause ->
//MESSAGE("message-text")
@@ -4214,6 +4225,17 @@ struct OmpOrderClause {
std::tuple t;
};
+// Ref: [5.0:56-57], [5.1:60-62], [5.2:191]
+//
+// otherwise-clause ->
+//DEFAULT ([directive-specification]) // since 5.0, until 5.1
+// otherwise-clause ->
+//OTHERWISE ([directive-specification])]// since 5.2
+struct OmpOtherwiseClause {
+ WRAPPER_CLASS_BOILERPLATE(
+ OmpOtherwiseClause, std::optional);
+};
+
// Ref: [4.5:46-50], [5.0:74-78], [5.1:92-96], [5.2:229-230]
//
// proc-bind-clause ->
@@ -4299,6 +4321,17 @@ struct OmpUpdateClause {
std::variant u;
};
+// Ref: [5.0:56-57], [5.1:60-62], [5.2:190-191]
+//
+// when-clause ->
+//WHEN (context-selector :
+//[directive-specification])// since 5.0
+struct OmpWhenClause {
+ TUPLE_CLASS_BOILERPLATE(OmpWhenClause);
+ MODIFIER_BOILERPLATE(OmpContextSelector);
+ std::tuple> t;
+};
+
// OpenMP Clauses
struct OmpClause {
UNION_CLASS_BOILERPLATE(OmpClause);
@@ -4323,6 +4356,12 @@ struct OmpClauseList {
// --- Directives and constructs
+struct OmpMetadirectiveDirective {
+ TUPLE_CLASS_BOILERPLATE(OmpMetadirectiveDirective);
+ std::tuple t;
+ CharBlock source;
+};
+
// Ref: [5.1:89-90], [5.2:216]
//
// nothing-directive ->
@@ -4696,7 +4735,7 @@ struct OpenMPStandaloneConstruct {
CharBlock source;
std::variant
+ OpenMPDepobjConstruct, OmpMetadirectiveDirective>
u;
};
diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp
b/flang/lib/Lower/OpenMP/Clauses.cpp
index b424e209d56da9..d60171552087fa 100644
--- a/flang/lib/Lower/OpenMP/Clauses.cpp
+++ b/flang/lib/Lower/OpenMP/Clauses.cpp
@@ -230,9 +230,9 @@ MAKE_EMPTY_CLASS(Threadprivate, Threadprivate);
MAKE_INCOMPLETE_CLASS(AdjustArgs, AdjustArgs);
MAKE_INCOMPLETE_CLASS(AppendArgs, AppendArgs);
-MAKE_INCOMPLETE_CLASS(Match, Match);
+// MAKE_INCOMPLETE_CLASS(Match, Mat
[llvm-branch-commits] [flang] [llvm] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus METADIRECTIVE (PR #121817)
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121817
>From 5f534c559ca1bb7911b484264582d1a5078bdcb8 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH 1/6] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses plus
METADIRECTIVE
Parse METADIRECTIVE as a standalone executable directive at the moment.
This will allow testing the parser code.
There is no lowering, not even clause conversion yet. There is also no
verification of the allowed values for trait sets, trait properties.
---
flang/include/flang/Parser/dump-parse-tree.h | 5 +
flang/include/flang/Parser/parse-tree.h | 41 -
flang/lib/Lower/OpenMP/Clauses.cpp | 21 ++-
flang/lib/Lower/OpenMP/Clauses.h | 1 +
flang/lib/Lower/OpenMP/OpenMP.cpp| 6 +
flang/lib/Parser/openmp-parsers.cpp | 26 ++-
flang/lib/Parser/unparse.cpp | 12 ++
flang/lib/Semantics/check-omp-structure.cpp | 9 +
flang/lib/Semantics/check-omp-structure.h| 3 +
flang/lib/Semantics/resolve-directives.cpp | 5 +
flang/test/Parser/OpenMP/metadirective.f90 | 165 +++
llvm/include/llvm/Frontend/OpenMP/OMP.td | 9 +-
12 files changed, 296 insertions(+), 7 deletions(-)
create mode 100644 flang/test/Parser/OpenMP/metadirective.f90
diff --git a/flang/include/flang/Parser/dump-parse-tree.h
b/flang/include/flang/Parser/dump-parse-tree.h
index a61d7973dd5c36..94ca7c67cbd52e 100644
--- a/flang/include/flang/Parser/dump-parse-tree.h
+++ b/flang/include/flang/Parser/dump-parse-tree.h
@@ -476,6 +476,11 @@ class ParseTreeDumper {
NODE(parser, NullInit)
NODE(parser, ObjectDecl)
NODE(parser, OldParameterStmt)
+ NODE(parser, OmpMetadirectiveDirective)
+ NODE(parser, OmpMatchClause)
+ NODE(parser, OmpOtherwiseClause)
+ NODE(parser, OmpWhenClause)
+ NODE(OmpWhenClause, Modifier)
NODE(parser, OmpDirectiveSpecification)
NODE(parser, OmpTraitPropertyName)
NODE(parser, OmpTraitScore)
diff --git a/flang/include/flang/Parser/parse-tree.h
b/flang/include/flang/Parser/parse-tree.h
index 697bddfaf16150..113ff3380ba22c 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -3964,6 +3964,7 @@ struct OmpBindClause {
// data-sharing-attribute ->
//SHARED | NONE | // since 4.5
//PRIVATE | FIRSTPRIVATE// since 5.0
+// See also otherwise-clause.
struct OmpDefaultClause {
ENUM_CLASS(DataSharingAttribute, Private, Firstprivate, Shared, None)
WRAPPER_CLASS_BOILERPLATE(OmpDefaultClause, DataSharingAttribute);
@@ -4184,6 +4185,16 @@ struct OmpMapClause {
std::tuple t;
};
+// Ref: [5.0:58-60], [5.1:63-68], [5.2:194-195]
+//
+// match-clause ->
+//MATCH (context-selector-specification)// since 5.0
+struct OmpMatchClause {
+ // The context-selector is an argument.
+ WRAPPER_CLASS_BOILERPLATE(
+ OmpMatchClause, traits::OmpContextSelectorSpecification);
+};
+
// Ref: [5.2:217-218]
// message-clause ->
//MESSAGE("message-text")
@@ -4214,6 +4225,17 @@ struct OmpOrderClause {
std::tuple t;
};
+// Ref: [5.0:56-57], [5.1:60-62], [5.2:191]
+//
+// otherwise-clause ->
+//DEFAULT ([directive-specification]) // since 5.0, until 5.1
+// otherwise-clause ->
+//OTHERWISE ([directive-specification])]// since 5.2
+struct OmpOtherwiseClause {
+ WRAPPER_CLASS_BOILERPLATE(
+ OmpOtherwiseClause, std::optional);
+};
+
// Ref: [4.5:46-50], [5.0:74-78], [5.1:92-96], [5.2:229-230]
//
// proc-bind-clause ->
@@ -4299,6 +4321,17 @@ struct OmpUpdateClause {
std::variant u;
};
+// Ref: [5.0:56-57], [5.1:60-62], [5.2:190-191]
+//
+// when-clause ->
+//WHEN (context-selector :
+//[directive-specification])// since 5.0
+struct OmpWhenClause {
+ TUPLE_CLASS_BOILERPLATE(OmpWhenClause);
+ MODIFIER_BOILERPLATE(OmpContextSelector);
+ std::tuple> t;
+};
+
// OpenMP Clauses
struct OmpClause {
UNION_CLASS_BOILERPLATE(OmpClause);
@@ -4323,6 +4356,12 @@ struct OmpClauseList {
// --- Directives and constructs
+struct OmpMetadirectiveDirective {
+ TUPLE_CLASS_BOILERPLATE(OmpMetadirectiveDirective);
+ std::tuple t;
+ CharBlock source;
+};
+
// Ref: [5.1:89-90], [5.2:216]
//
// nothing-directive ->
@@ -4696,7 +4735,7 @@ struct OpenMPStandaloneConstruct {
CharBlock source;
std::variant
+ OpenMPDepobjConstruct, OmpMetadirectiveDirective>
u;
};
diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp
b/flang/lib/Lower/OpenMP/Clauses.cpp
index b424e209d56da9..d60171552087fa 100644
--- a/flang/lib/Lower/OpenMP/Clauses.cpp
+++ b/flang/lib/Lower/OpenMP/Clauses.cpp
@@ -230,9 +230,9 @@ MAKE_EMPTY_CLASS(Threadprivate, Threadprivate);
MAKE_INCOMPLETE_CLASS(AdjustArgs, AdjustArgs);
MAKE_INCOMPLETE_CLASS(AppendArgs, AppendArgs);
-MAKE_INCOMPLETE_CLASS(Match, Match);
+// MAKE_INCOMPLETE_CLASS(Match, Mat
[llvm-branch-commits] [libcxx] 5d47208 - Revert "Reapply "[libc++] Explicitly convert to masks in SIMD code (#107983)"…"
Author: Vitaly Buka
Date: 2025-01-07T15:59:59-08:00
New Revision: 5d47208ffaf367a2bd40ebe8a197315e5b03b66d
URL:
https://github.com/llvm/llvm-project/commit/5d47208ffaf367a2bd40ebe8a197315e5b03b66d
DIFF:
https://github.com/llvm/llvm-project/commit/5d47208ffaf367a2bd40ebe8a197315e5b03b66d.diff
LOG: Revert "Reapply "[libc++] Explicitly convert to masks in SIMD code
(#107983)"…"
This reverts commit ed572f2003275da8e06a634b4d6658b7921e8334.
Added:
Modified:
libcxx/include/__algorithm/mismatch.h
libcxx/include/__algorithm/simd_utils.h
Removed:
diff --git a/libcxx/include/__algorithm/mismatch.h
b/libcxx/include/__algorithm/mismatch.h
index f5855379f68784..a6836792c05816 100644
--- a/libcxx/include/__algorithm/mismatch.h
+++ b/libcxx/include/__algorithm/mismatch.h
@@ -78,7 +78,7 @@ __mismatch_vectorized(_Iter __first1, _Iter __last1, _Iter
__first2) {
}
for (size_t __i = 0; __i != __unroll_count; ++__i) {
-if (auto __cmp_res = std::__as_mask(__lhs[__i] == __rhs[__i]);
!std::__all_of(__cmp_res)) {
+if (auto __cmp_res = __lhs[__i] == __rhs[__i];
!std::__all_of(__cmp_res)) {
auto __offset = __i * __vec_size +
std::__find_first_not_set(__cmp_res);
return {__first1 + __offset, __first2 + __offset};
}
@@ -90,7 +90,7 @@ __mismatch_vectorized(_Iter __first1, _Iter __last1, _Iter
__first2) {
// check the remaining 0-3 vectors
while (static_cast(__last1 - __first1) >= __vec_size) {
- if (auto __cmp_res = std::__as_mask(std::__load_vector<__vec>(__first1)
== std::__load_vector<__vec>(__first2));
+ if (auto __cmp_res = std::__load_vector<__vec>(__first1) ==
std::__load_vector<__vec>(__first2);
!std::__all_of(__cmp_res)) {
auto __offset = std::__find_first_not_set(__cmp_res);
return {__first1 + __offset, __first2 + __offset};
@@ -107,8 +107,8 @@ __mismatch_vectorized(_Iter __first1, _Iter __last1, _Iter
__first2) {
if (static_cast(__first1 - __orig_first1) >= __vec_size) {
__first1 = __last1 - __vec_size;
__first2 = __last2 - __vec_size;
- auto __offset = std::__find_first_not_set(
- std::__as_mask(std::__load_vector<__vec>(__first1) ==
std::__load_vector<__vec>(__first2)));
+ auto __offset =
+ std::__find_first_not_set(std::__load_vector<__vec>(__first1) ==
std::__load_vector<__vec>(__first2));
return {__first1 + __offset, __first2 + __offset};
} // else loop over the elements individually
}
diff --git a/libcxx/include/__algorithm/simd_utils.h
b/libcxx/include/__algorithm/simd_utils.h
index 3ca79247bbd03c..4e3e4f2b9404e3 100644
--- a/libcxx/include/__algorithm/simd_utils.h
+++ b/libcxx/include/__algorithm/simd_utils.h
@@ -116,65 +116,42 @@ template
}(make_index_sequence<__simd_vector_size_v<_VecT>>{});
}
-template
-[[__nodiscard__]] _LIBCPP_HIDE_FROM_ABI bool __all_of(__simd_vector
__vec) noexcept {
- return __builtin_reduce_and(__vec);
-}
-
template
-[[__nodiscard__]] _LIBCPP_HIDE_FROM_ABI auto __as_mask(__simd_vector<_Tp, _Np>
__vec) noexcept {
- static_assert(!is_same<_Tp, bool>::value, "vector type should not be a
bool!");
- return __builtin_convertvector(__vec, __simd_vector);
-}
-
-// This uses __builtin_convertvector around the __builtin_shufflevector to
work around #107981.
-template
-[[__nodiscard__]] _LIBCPP_HIDE_FROM_ABI __simd_vector
-__extend_vector(__simd_vector __vec) noexcept {
- using _VecT = __simd_vector;
- if constexpr (_Np == 4) {
-return __builtin_convertvector(
-__builtin_shufflevector(__vec, _VecT{}, 0, 1, 2, 3, 4, 5, 6, 7),
__simd_vector);
- } else if constexpr (_Np == 2) {
-return std::__extend_vector(
-__builtin_convertvector(__builtin_shufflevector(__vec, _VecT{}, 0, 1,
2, 3), __simd_vector));
- } else if constexpr (_Np == 1) {
-return std::__extend_vector(
-__builtin_convertvector(__builtin_shufflevector(__vec, _VecT{}, 0, 1),
__simd_vector));
- } else {
-static_assert(sizeof(_VecT) == 0, "Unexpected vector size");
- }
+[[__nodiscard__]] _LIBCPP_HIDE_FROM_ABI bool __all_of(__simd_vector<_Tp, _Np>
__vec) noexcept {
+ return __builtin_reduce_and(__builtin_convertvector(__vec,
__simd_vector));
}
-template
-[[__nodiscard__]] _LIBCPP_HIDE_FROM_ABI auto __to_int_mask(__simd_vector __vec) {
- if constexpr (_Np < 8) {
-return std::__bit_cast(std::__extend_vector(__vec));
- } else if constexpr (_Np == 8) {
-return std::__bit_cast(__vec);
- } else if constexpr (_Np == 16) {
-return std::__bit_cast(__vec);
- } else if constexpr (_Np == 32) {
-return std::__bit_cast(__vec);
- } else if constexpr (_Np == 64) {
-return std::__bit_cast(__vec);
- } else {
-static_assert(sizeof(__simd_vector) == 0, "Unexpected vector
size");
-return 0;
- }
-}
+template
+[[__nodiscard__]] _LIBCPP_HIDE_FROM_ABI size_t
__fin
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to NPM (PR #118462)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/118462
>From 71f80fc3a116a28319153127cdbcb0086e64b064 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 3 Dec 2024 10:12:36 +
Subject: [PATCH 1/5] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to
NPM
---
.../llvm}/CodeGen/RegAllocPriorityAdvisor.h | 78 +++-
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 1 +
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 6 +-
.../lib/CodeGen/MLRegAllocPriorityAdvisor.cpp | 184 +++---
llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 9 +-
llvm/lib/CodeGen/RegAllocGreedy.h | 2 +-
llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp | 155 +++
llvm/lib/Passes/PassBuilder.cpp | 1 +
10 files changed, 320 insertions(+), 120 deletions(-)
rename llvm/{lib => include/llvm}/CodeGen/RegAllocPriorityAdvisor.h (57%)
diff --git a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
b/llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
similarity index 57%
rename from llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
rename to llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
index 0758743c2b1403..a53739fdc3fc40 100644
--- a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
+++ b/llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
@@ -9,8 +9,10 @@
#ifndef LLVM_CODEGEN_REGALLOCPRIORITYADVISOR_H
#define LLVM_CODEGEN_REGALLOCPRIORITYADVISOR_H
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/IR/PassManager.h"
#include "llvm/Pass.h"
namespace llvm {
@@ -68,12 +70,72 @@ class DummyPriorityAdvisor : public RegAllocPriorityAdvisor
{
unsigned getPriority(const LiveInterval &LI) const override;
};
-class RegAllocPriorityAdvisorAnalysis : public ImmutablePass {
+/// Common provider for getting the priority advisor and logging rewards.
+/// Legacy analysis forwards all calls to this provider.
+/// New analysis serves the provider as the analysis result.
+/// Expensive setup is done in the constructor, so that the advisor can be
+/// created quickly for every machine function.
+/// TODO: Remove once legacy PM support is dropped.
+class RegAllocPriorityAdvisorProvider {
public:
enum class AdvisorMode : int { Default, Release, Development, Dummy };
- RegAllocPriorityAdvisorAnalysis(AdvisorMode Mode)
- : ImmutablePass(ID), Mode(Mode){};
+ RegAllocPriorityAdvisorProvider(AdvisorMode Mode) : Mode(Mode) {}
+
+ virtual ~RegAllocPriorityAdvisorProvider() = default;
+
+ virtual void logRewardIfNeeded(const MachineFunction &MF,
+ llvm::function_ref GetReward) {};
+
+ virtual std::unique_ptr
+ getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
+
+ void setAnalyses(SlotIndexes *SI) { this->SI = SI; }
+
+ AdvisorMode getAdvisorMode() const { return Mode; }
+
+protected:
+ SlotIndexes *SI;
+
+private:
+ const AdvisorMode Mode;
+};
+
+RegAllocPriorityAdvisorProvider *createReleaseModePriorityAdvisorProvider();
+
+RegAllocPriorityAdvisorProvider *
+createDevelopmentModePriorityAdvisorProvider(LLVMContext &Ctx);
+
+class RegAllocPriorityAdvisorAnalysis
+: public AnalysisInfoMixin {
+ static AnalysisKey Key;
+ friend AnalysisInfoMixin;
+
+public:
+ struct Result {
+// Owned by this analysis.
+RegAllocPriorityAdvisorProvider *Provider;
+
+bool invalidate(MachineFunction &MF, const PreservedAnalyses &PA,
+MachineFunctionAnalysisManager::Invalidator &Inv) {
+ auto PAC = PA.getChecker();
+ return !PAC.preservedWhenStateless() ||
+ Inv.invalidate(MF, PA);
+}
+ };
+
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+
+private:
+ void initializeProvider(LLVMContext &Ctx);
+ std::unique_ptr Provider;
+};
+
+class RegAllocPriorityAdvisorAnalysisLegacy : public ImmutablePass {
+public:
+ using AdvisorMode = RegAllocPriorityAdvisorProvider::AdvisorMode;
+ RegAllocPriorityAdvisorAnalysisLegacy(AdvisorMode Mode)
+ : ImmutablePass(ID), Mode(Mode) {};
static char ID;
/// Get an advisor for the given context (i.e. machine function, etc)
@@ -81,7 +143,7 @@ class RegAllocPriorityAdvisorAnalysis : public ImmutablePass
{
getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
AdvisorMode getAdvisorMode() const { return Mode; }
virtual void logRewardIfNeeded(const MachineFunction &MF,
- llvm::function_ref GetReward){};
+ llvm::function_ref GetReward) {};
protected:
// This analysis preserves everything, and subclasses may have additional
@@ -97,11 +159,13 @@ class RegAllocPriorityAdvisorAnalysis : public
ImmutablePass {
/// Specialization for the API used by the analysis infrastructure to create
/// an instan
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to NPM (PR #118462)
https://github.com/optimisan ready_for_review https://github.com/llvm/llvm-project/pull/118462 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Spiller: Detach legacy pass and supply analyses instead (PR #119181)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119181
>From c35bc75339bd5494ff223c2fc3f0c5631d7ebab4 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 9 Dec 2024 07:58:48 +
Subject: [PATCH] Spiller: Deatach legacy pass and supply analyses instead
---
llvm/include/llvm/CodeGen/Spiller.h | 16 +++--
llvm/lib/CodeGen/InlineSpiller.cpp | 36 +++--
llvm/lib/CodeGen/RegAllocBasic.cpp | 16 +
llvm/lib/CodeGen/RegAllocGreedy.cpp | 4 +++-
llvm/lib/CodeGen/RegAllocPBQP.cpp | 5 +++-
5 files changed, 46 insertions(+), 31 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/Spiller.h
b/llvm/include/llvm/CodeGen/Spiller.h
index 51ad36bc6b1f8b..3132cefeb6c68a 100644
--- a/llvm/include/llvm/CodeGen/Spiller.h
+++ b/llvm/include/llvm/CodeGen/Spiller.h
@@ -19,6 +19,10 @@ class MachineFunction;
class MachineFunctionPass;
class VirtRegMap;
class VirtRegAuxInfo;
+class LiveIntervals;
+class LiveStacks;
+class MachineDominatorTree;
+class MachineBlockFrequencyInfo;
/// Spiller interface.
///
@@ -41,12 +45,20 @@ class Spiller {
virtual ArrayRef getReplacedRegs() = 0;
virtual void postOptimization() {}
+
+ struct RequiredAnalyses {
+LiveIntervals &LIS;
+LiveStacks &LSS;
+MachineDominatorTree &MDT;
+const MachineBlockFrequencyInfo &MBFI;
+ };
};
/// Create and return a spiller that will insert spill code directly instead
/// of deferring though VirtRegMap.
-Spiller *createInlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF,
- VirtRegMap &VRM, VirtRegAuxInfo &VRAI);
+Spiller *createInlineSpiller(const Spiller::RequiredAnalyses &Analyses,
+ MachineFunction &MF, VirtRegMap &VRM,
+ VirtRegAuxInfo &VRAI);
} // end namespace llvm
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp
b/llvm/lib/CodeGen/InlineSpiller.cpp
index 64f290f5930a1b..b9768d5c63a5d1 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -75,7 +75,6 @@ RestrictStatepointRemat("restrict-statepoint-remat",
cl::desc("Restrict remat for statepoint operands"));
namespace {
-
class HoistSpillHelper : private LiveRangeEdit::Delegate {
MachineFunction &MF;
LiveIntervals &LIS;
@@ -128,15 +127,11 @@ class HoistSpillHelper : private LiveRangeEdit::Delegate {
DenseMap &SpillsToIns);
public:
- HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
- VirtRegMap &vrm)
- : MF(mf), LIS(pass.getAnalysis().getLIS()),
-LSS(pass.getAnalysis().getLS()),
-MDT(pass.getAnalysis().getDomTree()),
+ HoistSpillHelper(const Spiller::RequiredAnalyses &Analyses,
+ MachineFunction &mf, VirtRegMap &vrm)
+ : MF(mf), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
-TRI(*mf.getSubtarget().getRegisterInfo()),
-MBFI(
-
pass.getAnalysis().getMBFI()),
+TRI(*mf.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
IPA(LIS, mf.getNumBlockIDs()) {}
void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
@@ -190,16 +185,12 @@ class InlineSpiller : public Spiller {
~InlineSpiller() override = default;
public:
- InlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF, VirtRegMap
&VRM,
-VirtRegAuxInfo &VRAI)
- : MF(MF), LIS(Pass.getAnalysis().getLIS()),
-LSS(Pass.getAnalysis().getLS()),
-MDT(Pass.getAnalysis().getDomTree()),
+ InlineSpiller(const Spiller::RequiredAnalyses &Analyses, MachineFunction &MF,
+VirtRegMap &VRM, VirtRegAuxInfo &VRAI)
+ : MF(MF), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
VRM(VRM), MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()),
-TRI(*MF.getSubtarget().getRegisterInfo()),
-MBFI(
-
Pass.getAnalysis().getMBFI()),
-HSpiller(Pass, MF, VRM), VRAI(VRAI) {}
+TRI(*MF.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
+HSpiller(Analyses, MF, VRM), VRAI(VRAI) {}
void spill(LiveRangeEdit &) override;
ArrayRef getSpilledRegs() override { return RegsToSpill; }
@@ -237,10 +228,11 @@ Spiller::~Spiller() = default;
void Spiller::anchor() {}
-Spiller *llvm::createInlineSpiller(MachineFunctionPass &Pass,
- MachineFunction &MF, VirtRegMap &VRM,
- VirtRegAuxInfo &VRAI) {
- return new InlineSpiller(Pass, MF, VRM, VRAI);
+Spiller *
+llvm::createInlineSpiller(const InlineSpiller::RequiredAnalyses &Analyses,
+ MachineFunction &MF, VirtRegMap &VRM,
+ VirtRegAuxInfo &VRAI) {
+ return new InlineSpiller(Analyses, MF, VRM, VRAI);
}
//===-
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From 4fcfde3d0081ac64e76a443d02723c32b87c1bc9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 08:51:55 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
llvm/include/llvm/CodeGen/MachineFunction.h | 1 +
llvm/include/llvm/CodeGen/Passes.h| 2 +-
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 9 +
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 185 ++
llvm/lib/CodeGen/RegAllocGreedy.h | 57 +++---
llvm/lib/Passes/PassBuilder.cpp | 1 +
8 files changed, 196 insertions(+), 63 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h
b/llvm/include/llvm/CodeGen/MachineFunction.h
index d696add8a1af53..662272e5e09618 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -901,6 +901,7 @@ class LLVM_ABI MachineFunction {
/// Run the current MachineFunction through the machine code verifier, useful
/// for debugger use.
+ /// TODO: Add the param LiveStks
/// \returns true if no problems were found.
bool verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
const char *Banner = nullptr, raw_ostream *OS = nullptr,
diff --git a/llvm/include/llvm/CodeGen/Passes.h
b/llvm/include/llvm/CodeGen/Passes.h
index d1fac4a304cffe..1096c34b307f9b 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -167,7 +167,7 @@ namespace llvm {
extern char &LiveRangeShrinkID;
/// Greedy register allocator.
- extern char &RAGreedyID;
+ extern char &RAGreedyLegacyID;
/// Basic register allocator.
extern char &RABasicID;
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index e74b85c0de886f..afe0aa6113dd21 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -250,7 +250,7 @@ void
initializeProfileSummaryInfoWrapperPassPass(PassRegistry &);
void initializePromoteLegacyPassPass(PassRegistry &);
void initializeRABasicPass(PassRegistry &);
void initializePseudoProbeInserterPass(PassRegistry &);
-void initializeRAGreedyPass(PassRegistry &);
+void initializeRAGreedyLegacyPass(PassRegistry &);
void initializeReachingDefAnalysisPass(PassRegistry &);
void initializeReassociateLegacyPassPass(PassRegistry &);
void initializeRegAllocEvictionAdvisorAnalysisLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 2d36c569cf2827..0e526e2d3781d9 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -187,6 +187,15 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocFastPassOptions(*PB, Params);
},
"filter=reg-filter;no-clear-vregs")
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+"regallocgreedy", "RAGreedy",
+[](RegAllocFilterFunc F) { return RAGreedyPass(F); },
+[PB = this](StringRef Params) {
+ // TODO: parseRegAllocFilter(*PB, Params);
+ return Expected(nullptr);
+}, ""
+)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved
from
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 8efe540770913a..6acff9cd21134b 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -111,7 +111,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
initializeProcessImplicitDefsPass(Registry);
initializeRABasicPass(Registry);
- initializeRAGreedyPass(Registry);
+ initializeRAGreedyLegacyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollectorLegacyPass(Registry);
initializeRegUsageInfoPropagationLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 57358c36879b3f..1552c3a1ef47a2 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -43,8 +43,10 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
+#include "llvm/CodeGen/RegAllocGreedyPass.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -55,6 +57,7 @@
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/IR/Analysis.h"
#include "l
[llvm-branch-commits] [llvm] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (PR #120557)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/120557
>From 634c858c8b4008010ffecdcd9b0d55c579bae3f3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 10:57:21 +
Subject: [PATCH 1/4] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline
---
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 18 +++-
.../llvm/Passes/MachinePassRegistry.def | 4 ++--
.../include/llvm/Target/CGPassBuilderOption.h | 2 +-
llvm/lib/Passes/PassBuilder.cpp | 13
...plicit-def-remat-requires-impdef-check.mir | 1 +
...implicit-def-with-impdef-greedy-assert.mir | 1 +
llvm/test/CodeGen/AArch64/pr51516.mir | 1 +
llvm/test/CodeGen/AArch64/spill-fold.mir | 2 ++
.../extend-phi-subrange-not-in-parent.mir | 1 +
llvm/test/CodeGen/MIR/Generic/runPass.mir | 1 +
.../SystemZ/clear-liverange-spillreg.mir | 1 +
llvm/test/CodeGen/Thumb/high-reg-clobber.mir | 1 +
llvm/test/CodeGen/X86/limit-split-cost.mir| 1 +
.../test/tools/llc/new-pm/regalloc-amdgpu.mir | 17 +--
llvm/tools/llc/NewPMDriver.cpp| 21 +++
15 files changed, 71 insertions(+), 14 deletions(-)
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index aca9b3b888acc3..971217923f7ef1 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -1056,7 +1056,7 @@ void CodeGenPassBuilder::addMachineSSAOptimization(
///
/// A target that uses the standard regalloc pass order for fast or optimized
/// allocation may still override this for per-target regalloc
-/// selection. But -regalloc=... always takes precedence.
+/// selection. But -regalloc-npm=... always takes precedence.
template
void CodeGenPassBuilder::addTargetRegisterAllocator(
AddMachinePass &addPass, bool Optimized) const {
@@ -1073,6 +1073,22 @@ template
void CodeGenPassBuilder::addRegAllocPass(
AddMachinePass &addPass, bool Optimized) const {
// TODO: Parse Opt.RegAlloc to add register allocator.
+ // Use the specified -regalloc-npm={basic|greedy|fast|pbqp}
+ if (Opt.RegAlloc > RegAllocType::Default) {
+switch (Opt.RegAlloc) {
+ case RegAllocType::Fast:
+addPass(RegAllocFastPass());
+break;
+ case RegAllocType::Greedy:
+addPass(RAGreedyPass());
+break;
+ default:
+llvm_unreachable("Register allocator not supported yet.");
+}
+return;
+ }
+ // -regalloc=default or unspecified, so pick based on the optimization level.
+ derived().addTargetRegisterAllocator(addPass, Optimized);
}
template
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index fa7f769f31fdde..1c89fb0eb8dbb1 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -188,12 +188,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
},
"filter=reg-filter;no-clear-vregs")
+// 'all' is the default filter
MACHINE_FUNCTION_PASS_WITH_PARAMS(
"greedy", "RAGreedyPass",
[](RAGreedyPass::Options Opts) { return RAGreedyPass(Opts); },
[PB = this](StringRef Params) {
- // TODO: parseRegAllocGreedyFilterFunc(*PB, Params);
- return Expected(RAGreedyPass::Options{});
+ return parseRegAllocGreedyFilterFunc(*PB, Params);
}, "reg-filter"
)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h
b/llvm/include/llvm/Target/CGPassBuilderOption.h
index d3d19c8a7dc9f2..c7c1572bcde603 100644
--- a/llvm/include/llvm/Target/CGPassBuilderOption.h
+++ b/llvm/include/llvm/Target/CGPassBuilderOption.h
@@ -52,7 +52,7 @@ struct CGPassBuilderOption {
bool RequiresCodeGenSCCOrder = false;
RunOutliner EnableMachineOutliner = RunOutliner::TargetDefault;
- StringRef RegAlloc = "default";
+ RegAllocType RegAlloc = RegAllocType::Default;
std::optional EnableGlobalISelAbort;
std::string FSProfileFile;
std::string FSRemappingFile;
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 3a9db2dbd59226..769d3b0a20f964 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1316,6 +1316,19 @@ parseBoundsCheckingOptions(StringRef Params) {
return Options;
}
+Expected parseRegAllocGreedyFilterFunc(PassBuilder &PB,
StringRef Params) {
+ if (Params.empty() || Params == "all") {
+return RAGreedyPass::Options();
+ }
+ std::optional Filter = PB.parseRegAllocFilter(Params);
+ if (!Filter) {
+return make_error(
+formatv("invalid regallocgreedy register filter '{0}' ", Params).str(),
+inconvertibleErrorCode());
+ }
+ return RAGreedyPass::Options{*Filter, Params};
+}
+
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git
a/llvm/test/CodeGen/AArch64/imp
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocEvictionAdvisor analysis to NPM (PR #117309)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/117309
>From 04586196b610c1348bfe5fbdd67b9faa43431b43 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 22 Nov 2024 09:31:50 +
Subject: [PATCH 1/8] [CodeGen][NewPM] Port RegAllocEvictionAdvisor analysis to
NPM
---
.../llvm}/CodeGen/RegAllocEvictionAdvisor.h | 69 +++-
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 6 +-
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 167 +-
llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp | 107 ---
llvm/lib/CodeGen/RegAllocGreedy.cpp | 9 +-
llvm/lib/CodeGen/RegAllocGreedy.h | 1 -
llvm/lib/CodeGen/RegAllocPriorityAdvisor.h| 2 +-
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/lib/Passes/PassRegistry.def | 1 +
10 files changed, 284 insertions(+), 81 deletions(-)
rename llvm/{lib => include/llvm}/CodeGen/RegAllocEvictionAdvisor.h (75%)
diff --git a/llvm/lib/CodeGen/RegAllocEvictionAdvisor.h
b/llvm/include/llvm/CodeGen/RegAllocEvictionAdvisor.h
similarity index 75%
rename from llvm/lib/CodeGen/RegAllocEvictionAdvisor.h
rename to llvm/include/llvm/CodeGen/RegAllocEvictionAdvisor.h
index 52dd946a685400..847bf032235c1d 100644
--- a/llvm/lib/CodeGen/RegAllocEvictionAdvisor.h
+++ b/llvm/include/llvm/CodeGen/RegAllocEvictionAdvisor.h
@@ -9,11 +9,13 @@
#ifndef LLVM_CODEGEN_REGALLOCEVICTIONADVISOR_H
#define LLVM_CODEGEN_REGALLOCEVICTIONADVISOR_H
+#include "llvm/ADT/Any.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/Config/llvm-config.h"
+#include "llvm/IR/PassManager.h"
#include "llvm/MC/MCRegister.h"
#include "llvm/Pass.h"
@@ -164,12 +166,12 @@ class RegAllocEvictionAdvisor {
///
/// Because we need to offer additional services in 'development' mode, the
/// implementations of this analysis need to implement RTTI support.
-class RegAllocEvictionAdvisorAnalysis : public ImmutablePass {
+class RegAllocEvictionAdvisorAnalysisLegacy : public ImmutablePass {
public:
enum class AdvisorMode : int { Default, Release, Development };
- RegAllocEvictionAdvisorAnalysis(AdvisorMode Mode)
- : ImmutablePass(ID), Mode(Mode){};
+ RegAllocEvictionAdvisorAnalysisLegacy(AdvisorMode Mode)
+ : ImmutablePass(ID), Mode(Mode) {};
static char ID;
/// Get an advisor for the given context (i.e. machine function, etc)
@@ -177,7 +179,7 @@ class RegAllocEvictionAdvisorAnalysis : public
ImmutablePass {
getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
AdvisorMode getAdvisorMode() const { return Mode; }
virtual void logRewardIfNeeded(const MachineFunction &MF,
- llvm::function_ref GetReward){};
+ llvm::function_ref GetReward) {};
protected:
// This analysis preserves everything, and subclasses may have additional
@@ -191,13 +193,66 @@ class RegAllocEvictionAdvisorAnalysis : public
ImmutablePass {
const AdvisorMode Mode;
};
+/// Common provider for legacy and new pass managers.
+/// This keeps the state for logging, and sets up and holds the provider.
+/// The legacy pass itself used to keep the logging state and provider,
+/// so this extraction helps the NPM analysis to reuse the logic.
+class RegAllocEvictionAdvisorProvider {
+public:
+ enum class AdvisorMode : int { Default, Release, Development };
+ RegAllocEvictionAdvisorProvider(AdvisorMode Mode) : Mode(Mode) {}
+
+ virtual ~RegAllocEvictionAdvisorProvider() = default;
+
+ virtual bool doInitialization(Module &M) { return false; }
+
+ virtual void logRewardIfNeeded(const MachineFunction &MF,
+ llvm::function_ref GetReward) {}
+
+ virtual std::unique_ptr
+ getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
+
+ /// Set the analyses that the advisor needs to use as they might not be
+ /// available before the advisor is created.
+ virtual void setAnalyses(std::initializer_list AnalysisP) {}
+
+ AdvisorMode getAdvisorMode() const { return Mode; }
+
+private:
+ const AdvisorMode Mode;
+};
+
+RegAllocEvictionAdvisorProvider *createReleaseModeAdvisorProvider();
+RegAllocEvictionAdvisorProvider *createDevelopmentModeAdvisorProvider();
+
+/// A Module analysis for fetching the Eviction Advisor. This is not a
+/// MachineFunction analysis for two reasons:
+/// - in the ML implementation case, the evaluator is stateless but (especially
+/// in the development mode) expensive to set up. With a Module Analysis, we
+/// `require` it and set it up once.
+/// - in the 'development' mode ML case, we want to capture the training log
+/// during allocation (this is a log of features encountered and decisions
+/// made), and then measure a score, potentially a few steps after allocation
+/// completes. So we need a Module analysis to keep the l
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to NPM (PR #118462)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/118462
>From c5bc17bd90f05e3adb9867c65c93f4a9f510b02e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 3 Dec 2024 10:12:36 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to
NPM
---
.../llvm}/CodeGen/RegAllocPriorityAdvisor.h | 78 +++-
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 1 +
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 6 +-
.../lib/CodeGen/MLRegAllocPriorityAdvisor.cpp | 184 +++---
llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 9 +-
llvm/lib/CodeGen/RegAllocGreedy.h | 2 +-
llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp | 155 +++
llvm/lib/Passes/PassBuilder.cpp | 1 +
10 files changed, 320 insertions(+), 120 deletions(-)
rename llvm/{lib => include/llvm}/CodeGen/RegAllocPriorityAdvisor.h (57%)
diff --git a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
b/llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
similarity index 57%
rename from llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
rename to llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
index 0758743c2b1403..a53739fdc3fc40 100644
--- a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
+++ b/llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
@@ -9,8 +9,10 @@
#ifndef LLVM_CODEGEN_REGALLOCPRIORITYADVISOR_H
#define LLVM_CODEGEN_REGALLOCPRIORITYADVISOR_H
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/IR/PassManager.h"
#include "llvm/Pass.h"
namespace llvm {
@@ -68,12 +70,72 @@ class DummyPriorityAdvisor : public RegAllocPriorityAdvisor
{
unsigned getPriority(const LiveInterval &LI) const override;
};
-class RegAllocPriorityAdvisorAnalysis : public ImmutablePass {
+/// Common provider for getting the priority advisor and logging rewards.
+/// Legacy analysis forwards all calls to this provider.
+/// New analysis serves the provider as the analysis result.
+/// Expensive setup is done in the constructor, so that the advisor can be
+/// created quickly for every machine function.
+/// TODO: Remove once legacy PM support is dropped.
+class RegAllocPriorityAdvisorProvider {
public:
enum class AdvisorMode : int { Default, Release, Development, Dummy };
- RegAllocPriorityAdvisorAnalysis(AdvisorMode Mode)
- : ImmutablePass(ID), Mode(Mode){};
+ RegAllocPriorityAdvisorProvider(AdvisorMode Mode) : Mode(Mode) {}
+
+ virtual ~RegAllocPriorityAdvisorProvider() = default;
+
+ virtual void logRewardIfNeeded(const MachineFunction &MF,
+ llvm::function_ref GetReward) {};
+
+ virtual std::unique_ptr
+ getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
+
+ void setAnalyses(SlotIndexes *SI) { this->SI = SI; }
+
+ AdvisorMode getAdvisorMode() const { return Mode; }
+
+protected:
+ SlotIndexes *SI;
+
+private:
+ const AdvisorMode Mode;
+};
+
+RegAllocPriorityAdvisorProvider *createReleaseModePriorityAdvisorProvider();
+
+RegAllocPriorityAdvisorProvider *
+createDevelopmentModePriorityAdvisorProvider(LLVMContext &Ctx);
+
+class RegAllocPriorityAdvisorAnalysis
+: public AnalysisInfoMixin {
+ static AnalysisKey Key;
+ friend AnalysisInfoMixin;
+
+public:
+ struct Result {
+// Owned by this analysis.
+RegAllocPriorityAdvisorProvider *Provider;
+
+bool invalidate(MachineFunction &MF, const PreservedAnalyses &PA,
+MachineFunctionAnalysisManager::Invalidator &Inv) {
+ auto PAC = PA.getChecker();
+ return !PAC.preservedWhenStateless() ||
+ Inv.invalidate(MF, PA);
+}
+ };
+
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+
+private:
+ void initializeProvider(LLVMContext &Ctx);
+ std::unique_ptr Provider;
+};
+
+class RegAllocPriorityAdvisorAnalysisLegacy : public ImmutablePass {
+public:
+ using AdvisorMode = RegAllocPriorityAdvisorProvider::AdvisorMode;
+ RegAllocPriorityAdvisorAnalysisLegacy(AdvisorMode Mode)
+ : ImmutablePass(ID), Mode(Mode) {};
static char ID;
/// Get an advisor for the given context (i.e. machine function, etc)
@@ -81,7 +143,7 @@ class RegAllocPriorityAdvisorAnalysis : public ImmutablePass
{
getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
AdvisorMode getAdvisorMode() const { return Mode; }
virtual void logRewardIfNeeded(const MachineFunction &MF,
- llvm::function_ref GetReward){};
+ llvm::function_ref GetReward) {};
protected:
// This analysis preserves everything, and subclasses may have additional
@@ -97,11 +159,13 @@ class RegAllocPriorityAdvisorAnalysis : public
ImmutablePass {
/// Specialization for the API used by the analysis infrastructure to create
/// an instan
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From d165ddda7caba11c2f268313706fbec6fa883ee3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 08:51:55 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
llvm/include/llvm/CodeGen/MachineFunction.h | 1 +
llvm/include/llvm/CodeGen/Passes.h| 2 +-
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 9 +
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 185 ++
llvm/lib/CodeGen/RegAllocGreedy.h | 57 +++---
llvm/lib/Passes/PassBuilder.cpp | 1 +
8 files changed, 196 insertions(+), 63 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h
b/llvm/include/llvm/CodeGen/MachineFunction.h
index d696add8a1af53..662272e5e09618 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -901,6 +901,7 @@ class LLVM_ABI MachineFunction {
/// Run the current MachineFunction through the machine code verifier, useful
/// for debugger use.
+ /// TODO: Add the param LiveStks
/// \returns true if no problems were found.
bool verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
const char *Banner = nullptr, raw_ostream *OS = nullptr,
diff --git a/llvm/include/llvm/CodeGen/Passes.h
b/llvm/include/llvm/CodeGen/Passes.h
index d1fac4a304cffe..1096c34b307f9b 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -167,7 +167,7 @@ namespace llvm {
extern char &LiveRangeShrinkID;
/// Greedy register allocator.
- extern char &RAGreedyID;
+ extern char &RAGreedyLegacyID;
/// Basic register allocator.
extern char &RABasicID;
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index e74b85c0de886f..afe0aa6113dd21 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -250,7 +250,7 @@ void
initializeProfileSummaryInfoWrapperPassPass(PassRegistry &);
void initializePromoteLegacyPassPass(PassRegistry &);
void initializeRABasicPass(PassRegistry &);
void initializePseudoProbeInserterPass(PassRegistry &);
-void initializeRAGreedyPass(PassRegistry &);
+void initializeRAGreedyLegacyPass(PassRegistry &);
void initializeReachingDefAnalysisPass(PassRegistry &);
void initializeReassociateLegacyPassPass(PassRegistry &);
void initializeRegAllocEvictionAdvisorAnalysisLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 2d36c569cf2827..0e526e2d3781d9 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -187,6 +187,15 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocFastPassOptions(*PB, Params);
},
"filter=reg-filter;no-clear-vregs")
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+"regallocgreedy", "RAGreedy",
+[](RegAllocFilterFunc F) { return RAGreedyPass(F); },
+[PB = this](StringRef Params) {
+ // TODO: parseRegAllocFilter(*PB, Params);
+ return Expected(nullptr);
+}, ""
+)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved
from
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 8efe540770913a..6acff9cd21134b 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -111,7 +111,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
initializeProcessImplicitDefsPass(Registry);
initializeRABasicPass(Registry);
- initializeRAGreedyPass(Registry);
+ initializeRAGreedyLegacyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollectorLegacyPass(Registry);
initializeRegUsageInfoPropagationLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 57358c36879b3f..1552c3a1ef47a2 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -43,8 +43,10 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
+#include "llvm/CodeGen/RegAllocGreedyPass.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -55,6 +57,7 @@
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/IR/Analysis.h"
#include "l
[llvm-branch-commits] [llvm] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (PR #120557)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/120557
>From 50b6c21960a7cba5a757eb3301ca568bc075ec83 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 10:57:21 +
Subject: [PATCH 1/4] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline
---
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 18 +++-
.../llvm/Passes/MachinePassRegistry.def | 4 ++--
.../include/llvm/Target/CGPassBuilderOption.h | 2 +-
llvm/lib/Passes/PassBuilder.cpp | 13
...plicit-def-remat-requires-impdef-check.mir | 1 +
...implicit-def-with-impdef-greedy-assert.mir | 1 +
llvm/test/CodeGen/AArch64/pr51516.mir | 1 +
llvm/test/CodeGen/AArch64/spill-fold.mir | 2 ++
.../extend-phi-subrange-not-in-parent.mir | 1 +
llvm/test/CodeGen/MIR/Generic/runPass.mir | 1 +
.../SystemZ/clear-liverange-spillreg.mir | 1 +
llvm/test/CodeGen/Thumb/high-reg-clobber.mir | 1 +
llvm/test/CodeGen/X86/limit-split-cost.mir| 1 +
.../test/tools/llc/new-pm/regalloc-amdgpu.mir | 17 +--
llvm/tools/llc/NewPMDriver.cpp| 21 +++
15 files changed, 71 insertions(+), 14 deletions(-)
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index aca9b3b888acc3..971217923f7ef1 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -1056,7 +1056,7 @@ void CodeGenPassBuilder::addMachineSSAOptimization(
///
/// A target that uses the standard regalloc pass order for fast or optimized
/// allocation may still override this for per-target regalloc
-/// selection. But -regalloc=... always takes precedence.
+/// selection. But -regalloc-npm=... always takes precedence.
template
void CodeGenPassBuilder::addTargetRegisterAllocator(
AddMachinePass &addPass, bool Optimized) const {
@@ -1073,6 +1073,22 @@ template
void CodeGenPassBuilder::addRegAllocPass(
AddMachinePass &addPass, bool Optimized) const {
// TODO: Parse Opt.RegAlloc to add register allocator.
+ // Use the specified -regalloc-npm={basic|greedy|fast|pbqp}
+ if (Opt.RegAlloc > RegAllocType::Default) {
+switch (Opt.RegAlloc) {
+ case RegAllocType::Fast:
+addPass(RegAllocFastPass());
+break;
+ case RegAllocType::Greedy:
+addPass(RAGreedyPass());
+break;
+ default:
+llvm_unreachable("Register allocator not supported yet.");
+}
+return;
+ }
+ // -regalloc=default or unspecified, so pick based on the optimization level.
+ derived().addTargetRegisterAllocator(addPass, Optimized);
}
template
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index fa7f769f31fdde..1c89fb0eb8dbb1 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -188,12 +188,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
},
"filter=reg-filter;no-clear-vregs")
+// 'all' is the default filter
MACHINE_FUNCTION_PASS_WITH_PARAMS(
"greedy", "RAGreedyPass",
[](RAGreedyPass::Options Opts) { return RAGreedyPass(Opts); },
[PB = this](StringRef Params) {
- // TODO: parseRegAllocGreedyFilterFunc(*PB, Params);
- return Expected(RAGreedyPass::Options{});
+ return parseRegAllocGreedyFilterFunc(*PB, Params);
}, "reg-filter"
)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h
b/llvm/include/llvm/Target/CGPassBuilderOption.h
index d3d19c8a7dc9f2..c7c1572bcde603 100644
--- a/llvm/include/llvm/Target/CGPassBuilderOption.h
+++ b/llvm/include/llvm/Target/CGPassBuilderOption.h
@@ -52,7 +52,7 @@ struct CGPassBuilderOption {
bool RequiresCodeGenSCCOrder = false;
RunOutliner EnableMachineOutliner = RunOutliner::TargetDefault;
- StringRef RegAlloc = "default";
+ RegAllocType RegAlloc = RegAllocType::Default;
std::optional EnableGlobalISelAbort;
std::string FSProfileFile;
std::string FSRemappingFile;
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 3a9db2dbd59226..769d3b0a20f964 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1316,6 +1316,19 @@ parseBoundsCheckingOptions(StringRef Params) {
return Options;
}
+Expected parseRegAllocGreedyFilterFunc(PassBuilder &PB,
StringRef Params) {
+ if (Params.empty() || Params == "all") {
+return RAGreedyPass::Options();
+ }
+ std::optional Filter = PB.parseRegAllocFilter(Params);
+ if (!Filter) {
+return make_error(
+formatv("invalid regallocgreedy register filter '{0}' ", Params).str(),
+inconvertibleErrorCode());
+ }
+ return RAGreedyPass::Options{*Filter, Params};
+}
+
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git
a/llvm/test/CodeGen/AArch64/imp
[llvm-branch-commits] [llvm] Spiller: Detach legacy pass and supply analyses instead (PR #119181)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119181
>From 0cff04bc8e3745ac627796faaf61e77c9dfd9ff6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 9 Dec 2024 07:58:48 +
Subject: [PATCH] Spiller: Deatach legacy pass and supply analyses instead
---
llvm/include/llvm/CodeGen/Spiller.h | 16 +++--
llvm/lib/CodeGen/InlineSpiller.cpp | 36 +++--
llvm/lib/CodeGen/RegAllocBasic.cpp | 16 +
llvm/lib/CodeGen/RegAllocGreedy.cpp | 4 +++-
llvm/lib/CodeGen/RegAllocPBQP.cpp | 5 +++-
5 files changed, 46 insertions(+), 31 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/Spiller.h
b/llvm/include/llvm/CodeGen/Spiller.h
index 51ad36bc6b1f8b..3132cefeb6c68a 100644
--- a/llvm/include/llvm/CodeGen/Spiller.h
+++ b/llvm/include/llvm/CodeGen/Spiller.h
@@ -19,6 +19,10 @@ class MachineFunction;
class MachineFunctionPass;
class VirtRegMap;
class VirtRegAuxInfo;
+class LiveIntervals;
+class LiveStacks;
+class MachineDominatorTree;
+class MachineBlockFrequencyInfo;
/// Spiller interface.
///
@@ -41,12 +45,20 @@ class Spiller {
virtual ArrayRef getReplacedRegs() = 0;
virtual void postOptimization() {}
+
+ struct RequiredAnalyses {
+LiveIntervals &LIS;
+LiveStacks &LSS;
+MachineDominatorTree &MDT;
+const MachineBlockFrequencyInfo &MBFI;
+ };
};
/// Create and return a spiller that will insert spill code directly instead
/// of deferring though VirtRegMap.
-Spiller *createInlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF,
- VirtRegMap &VRM, VirtRegAuxInfo &VRAI);
+Spiller *createInlineSpiller(const Spiller::RequiredAnalyses &Analyses,
+ MachineFunction &MF, VirtRegMap &VRM,
+ VirtRegAuxInfo &VRAI);
} // end namespace llvm
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp
b/llvm/lib/CodeGen/InlineSpiller.cpp
index 64f290f5930a1b..b9768d5c63a5d1 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -75,7 +75,6 @@ RestrictStatepointRemat("restrict-statepoint-remat",
cl::desc("Restrict remat for statepoint operands"));
namespace {
-
class HoistSpillHelper : private LiveRangeEdit::Delegate {
MachineFunction &MF;
LiveIntervals &LIS;
@@ -128,15 +127,11 @@ class HoistSpillHelper : private LiveRangeEdit::Delegate {
DenseMap &SpillsToIns);
public:
- HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
- VirtRegMap &vrm)
- : MF(mf), LIS(pass.getAnalysis().getLIS()),
-LSS(pass.getAnalysis().getLS()),
-MDT(pass.getAnalysis().getDomTree()),
+ HoistSpillHelper(const Spiller::RequiredAnalyses &Analyses,
+ MachineFunction &mf, VirtRegMap &vrm)
+ : MF(mf), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
-TRI(*mf.getSubtarget().getRegisterInfo()),
-MBFI(
-
pass.getAnalysis().getMBFI()),
+TRI(*mf.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
IPA(LIS, mf.getNumBlockIDs()) {}
void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
@@ -190,16 +185,12 @@ class InlineSpiller : public Spiller {
~InlineSpiller() override = default;
public:
- InlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF, VirtRegMap
&VRM,
-VirtRegAuxInfo &VRAI)
- : MF(MF), LIS(Pass.getAnalysis().getLIS()),
-LSS(Pass.getAnalysis().getLS()),
-MDT(Pass.getAnalysis().getDomTree()),
+ InlineSpiller(const Spiller::RequiredAnalyses &Analyses, MachineFunction &MF,
+VirtRegMap &VRM, VirtRegAuxInfo &VRAI)
+ : MF(MF), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
VRM(VRM), MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()),
-TRI(*MF.getSubtarget().getRegisterInfo()),
-MBFI(
-
Pass.getAnalysis().getMBFI()),
-HSpiller(Pass, MF, VRM), VRAI(VRAI) {}
+TRI(*MF.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
+HSpiller(Analyses, MF, VRM), VRAI(VRAI) {}
void spill(LiveRangeEdit &) override;
ArrayRef getSpilledRegs() override { return RegsToSpill; }
@@ -237,10 +228,11 @@ Spiller::~Spiller() = default;
void Spiller::anchor() {}
-Spiller *llvm::createInlineSpiller(MachineFunctionPass &Pass,
- MachineFunction &MF, VirtRegMap &VRM,
- VirtRegAuxInfo &VRAI) {
- return new InlineSpiller(Pass, MF, VRM, VRAI);
+Spiller *
+llvm::createInlineSpiller(const InlineSpiller::RequiredAnalyses &Analyses,
+ MachineFunction &MF, VirtRegMap &VRM,
+ VirtRegAuxInfo &VRAI) {
+ return new InlineSpiller(Analyses, MF, VRM, VRAI);
}
//===-
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to NPM (PR #118462)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/118462
>From c5bc17bd90f05e3adb9867c65c93f4a9f510b02e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 3 Dec 2024 10:12:36 +
Subject: [PATCH 1/5] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to
NPM
---
.../llvm}/CodeGen/RegAllocPriorityAdvisor.h | 78 +++-
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 1 +
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 6 +-
.../lib/CodeGen/MLRegAllocPriorityAdvisor.cpp | 184 +++---
llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 9 +-
llvm/lib/CodeGen/RegAllocGreedy.h | 2 +-
llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp | 155 +++
llvm/lib/Passes/PassBuilder.cpp | 1 +
10 files changed, 320 insertions(+), 120 deletions(-)
rename llvm/{lib => include/llvm}/CodeGen/RegAllocPriorityAdvisor.h (57%)
diff --git a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
b/llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
similarity index 57%
rename from llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
rename to llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
index 0758743c2b1403..a53739fdc3fc40 100644
--- a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
+++ b/llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
@@ -9,8 +9,10 @@
#ifndef LLVM_CODEGEN_REGALLOCPRIORITYADVISOR_H
#define LLVM_CODEGEN_REGALLOCPRIORITYADVISOR_H
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/IR/PassManager.h"
#include "llvm/Pass.h"
namespace llvm {
@@ -68,12 +70,72 @@ class DummyPriorityAdvisor : public RegAllocPriorityAdvisor
{
unsigned getPriority(const LiveInterval &LI) const override;
};
-class RegAllocPriorityAdvisorAnalysis : public ImmutablePass {
+/// Common provider for getting the priority advisor and logging rewards.
+/// Legacy analysis forwards all calls to this provider.
+/// New analysis serves the provider as the analysis result.
+/// Expensive setup is done in the constructor, so that the advisor can be
+/// created quickly for every machine function.
+/// TODO: Remove once legacy PM support is dropped.
+class RegAllocPriorityAdvisorProvider {
public:
enum class AdvisorMode : int { Default, Release, Development, Dummy };
- RegAllocPriorityAdvisorAnalysis(AdvisorMode Mode)
- : ImmutablePass(ID), Mode(Mode){};
+ RegAllocPriorityAdvisorProvider(AdvisorMode Mode) : Mode(Mode) {}
+
+ virtual ~RegAllocPriorityAdvisorProvider() = default;
+
+ virtual void logRewardIfNeeded(const MachineFunction &MF,
+ llvm::function_ref GetReward) {};
+
+ virtual std::unique_ptr
+ getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
+
+ void setAnalyses(SlotIndexes *SI) { this->SI = SI; }
+
+ AdvisorMode getAdvisorMode() const { return Mode; }
+
+protected:
+ SlotIndexes *SI;
+
+private:
+ const AdvisorMode Mode;
+};
+
+RegAllocPriorityAdvisorProvider *createReleaseModePriorityAdvisorProvider();
+
+RegAllocPriorityAdvisorProvider *
+createDevelopmentModePriorityAdvisorProvider(LLVMContext &Ctx);
+
+class RegAllocPriorityAdvisorAnalysis
+: public AnalysisInfoMixin {
+ static AnalysisKey Key;
+ friend AnalysisInfoMixin;
+
+public:
+ struct Result {
+// Owned by this analysis.
+RegAllocPriorityAdvisorProvider *Provider;
+
+bool invalidate(MachineFunction &MF, const PreservedAnalyses &PA,
+MachineFunctionAnalysisManager::Invalidator &Inv) {
+ auto PAC = PA.getChecker();
+ return !PAC.preservedWhenStateless() ||
+ Inv.invalidate(MF, PA);
+}
+ };
+
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+
+private:
+ void initializeProvider(LLVMContext &Ctx);
+ std::unique_ptr Provider;
+};
+
+class RegAllocPriorityAdvisorAnalysisLegacy : public ImmutablePass {
+public:
+ using AdvisorMode = RegAllocPriorityAdvisorProvider::AdvisorMode;
+ RegAllocPriorityAdvisorAnalysisLegacy(AdvisorMode Mode)
+ : ImmutablePass(ID), Mode(Mode) {};
static char ID;
/// Get an advisor for the given context (i.e. machine function, etc)
@@ -81,7 +143,7 @@ class RegAllocPriorityAdvisorAnalysis : public ImmutablePass
{
getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
AdvisorMode getAdvisorMode() const { return Mode; }
virtual void logRewardIfNeeded(const MachineFunction &MF,
- llvm::function_ref GetReward){};
+ llvm::function_ref GetReward) {};
protected:
// This analysis preserves everything, and subclasses may have additional
@@ -97,11 +159,13 @@ class RegAllocPriorityAdvisorAnalysis : public
ImmutablePass {
/// Specialization for the API used by the analysis infrastructure to create
/// an instan
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From 4b62a383d0f187c72e64ccf952a3c78150c743a5 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 08:51:55 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
llvm/include/llvm/CodeGen/MachineFunction.h | 1 +
llvm/include/llvm/CodeGen/Passes.h| 2 +-
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 9 +
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 185 ++
llvm/lib/CodeGen/RegAllocGreedy.h | 57 +++---
llvm/lib/Passes/PassBuilder.cpp | 1 +
8 files changed, 196 insertions(+), 63 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h
b/llvm/include/llvm/CodeGen/MachineFunction.h
index d696add8a1af53..662272e5e09618 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -901,6 +901,7 @@ class LLVM_ABI MachineFunction {
/// Run the current MachineFunction through the machine code verifier, useful
/// for debugger use.
+ /// TODO: Add the param LiveStks
/// \returns true if no problems were found.
bool verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
const char *Banner = nullptr, raw_ostream *OS = nullptr,
diff --git a/llvm/include/llvm/CodeGen/Passes.h
b/llvm/include/llvm/CodeGen/Passes.h
index d1fac4a304cffe..1096c34b307f9b 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -167,7 +167,7 @@ namespace llvm {
extern char &LiveRangeShrinkID;
/// Greedy register allocator.
- extern char &RAGreedyID;
+ extern char &RAGreedyLegacyID;
/// Basic register allocator.
extern char &RABasicID;
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index e74b85c0de886f..afe0aa6113dd21 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -250,7 +250,7 @@ void
initializeProfileSummaryInfoWrapperPassPass(PassRegistry &);
void initializePromoteLegacyPassPass(PassRegistry &);
void initializeRABasicPass(PassRegistry &);
void initializePseudoProbeInserterPass(PassRegistry &);
-void initializeRAGreedyPass(PassRegistry &);
+void initializeRAGreedyLegacyPass(PassRegistry &);
void initializeReachingDefAnalysisPass(PassRegistry &);
void initializeReassociateLegacyPassPass(PassRegistry &);
void initializeRegAllocEvictionAdvisorAnalysisLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 2d36c569cf2827..0e526e2d3781d9 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -187,6 +187,15 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocFastPassOptions(*PB, Params);
},
"filter=reg-filter;no-clear-vregs")
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+"regallocgreedy", "RAGreedy",
+[](RegAllocFilterFunc F) { return RAGreedyPass(F); },
+[PB = this](StringRef Params) {
+ // TODO: parseRegAllocFilter(*PB, Params);
+ return Expected(nullptr);
+}, ""
+)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved
from
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 8efe540770913a..6acff9cd21134b 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -111,7 +111,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
initializeProcessImplicitDefsPass(Registry);
initializeRABasicPass(Registry);
- initializeRAGreedyPass(Registry);
+ initializeRAGreedyLegacyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollectorLegacyPass(Registry);
initializeRegUsageInfoPropagationLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 57358c36879b3f..1552c3a1ef47a2 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -43,8 +43,10 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
+#include "llvm/CodeGen/RegAllocGreedyPass.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -55,6 +57,7 @@
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/IR/Analysis.h"
#include "l
[llvm-branch-commits] [llvm] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (PR #120557)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/120557
>From b7da349a13bff1055ae0bca795c922cf41cbd290 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 10:57:21 +
Subject: [PATCH 1/4] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline
---
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 18 +++-
.../llvm/Passes/MachinePassRegistry.def | 4 ++--
.../include/llvm/Target/CGPassBuilderOption.h | 2 +-
llvm/lib/Passes/PassBuilder.cpp | 13
...plicit-def-remat-requires-impdef-check.mir | 1 +
...implicit-def-with-impdef-greedy-assert.mir | 1 +
llvm/test/CodeGen/AArch64/pr51516.mir | 1 +
llvm/test/CodeGen/AArch64/spill-fold.mir | 2 ++
.../extend-phi-subrange-not-in-parent.mir | 1 +
llvm/test/CodeGen/MIR/Generic/runPass.mir | 1 +
.../SystemZ/clear-liverange-spillreg.mir | 1 +
llvm/test/CodeGen/Thumb/high-reg-clobber.mir | 1 +
llvm/test/CodeGen/X86/limit-split-cost.mir| 1 +
.../test/tools/llc/new-pm/regalloc-amdgpu.mir | 17 +--
llvm/tools/llc/NewPMDriver.cpp| 21 +++
15 files changed, 71 insertions(+), 14 deletions(-)
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index aca9b3b888acc3..971217923f7ef1 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -1056,7 +1056,7 @@ void CodeGenPassBuilder::addMachineSSAOptimization(
///
/// A target that uses the standard regalloc pass order for fast or optimized
/// allocation may still override this for per-target regalloc
-/// selection. But -regalloc=... always takes precedence.
+/// selection. But -regalloc-npm=... always takes precedence.
template
void CodeGenPassBuilder::addTargetRegisterAllocator(
AddMachinePass &addPass, bool Optimized) const {
@@ -1073,6 +1073,22 @@ template
void CodeGenPassBuilder::addRegAllocPass(
AddMachinePass &addPass, bool Optimized) const {
// TODO: Parse Opt.RegAlloc to add register allocator.
+ // Use the specified -regalloc-npm={basic|greedy|fast|pbqp}
+ if (Opt.RegAlloc > RegAllocType::Default) {
+switch (Opt.RegAlloc) {
+ case RegAllocType::Fast:
+addPass(RegAllocFastPass());
+break;
+ case RegAllocType::Greedy:
+addPass(RAGreedyPass());
+break;
+ default:
+llvm_unreachable("Register allocator not supported yet.");
+}
+return;
+ }
+ // -regalloc=default or unspecified, so pick based on the optimization level.
+ derived().addTargetRegisterAllocator(addPass, Optimized);
}
template
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index fa7f769f31fdde..1c89fb0eb8dbb1 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -188,12 +188,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
},
"filter=reg-filter;no-clear-vregs")
+// 'all' is the default filter
MACHINE_FUNCTION_PASS_WITH_PARAMS(
"greedy", "RAGreedyPass",
[](RAGreedyPass::Options Opts) { return RAGreedyPass(Opts); },
[PB = this](StringRef Params) {
- // TODO: parseRegAllocGreedyFilterFunc(*PB, Params);
- return Expected(RAGreedyPass::Options{});
+ return parseRegAllocGreedyFilterFunc(*PB, Params);
}, "reg-filter"
)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h
b/llvm/include/llvm/Target/CGPassBuilderOption.h
index d3d19c8a7dc9f2..c7c1572bcde603 100644
--- a/llvm/include/llvm/Target/CGPassBuilderOption.h
+++ b/llvm/include/llvm/Target/CGPassBuilderOption.h
@@ -52,7 +52,7 @@ struct CGPassBuilderOption {
bool RequiresCodeGenSCCOrder = false;
RunOutliner EnableMachineOutliner = RunOutliner::TargetDefault;
- StringRef RegAlloc = "default";
+ RegAllocType RegAlloc = RegAllocType::Default;
std::optional EnableGlobalISelAbort;
std::string FSProfileFile;
std::string FSRemappingFile;
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 3a9db2dbd59226..769d3b0a20f964 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1316,6 +1316,19 @@ parseBoundsCheckingOptions(StringRef Params) {
return Options;
}
+Expected parseRegAllocGreedyFilterFunc(PassBuilder &PB,
StringRef Params) {
+ if (Params.empty() || Params == "all") {
+return RAGreedyPass::Options();
+ }
+ std::optional Filter = PB.parseRegAllocFilter(Params);
+ if (!Filter) {
+return make_error(
+formatv("invalid regallocgreedy register filter '{0}' ", Params).str(),
+inconvertibleErrorCode());
+ }
+ return RAGreedyPass::Options{*Filter, Params};
+}
+
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git
a/llvm/test/CodeGen/AArch64/imp
[llvm-branch-commits] [llvm] Spiller: Detach legacy pass and supply analyses instead (PR #119181)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119181
>From 231749a31aaa89a92a810c6356a006b68bb0f3a0 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 9 Dec 2024 07:58:48 +
Subject: [PATCH] Spiller: Deatach legacy pass and supply analyses instead
---
llvm/include/llvm/CodeGen/Spiller.h | 16 +++--
llvm/lib/CodeGen/InlineSpiller.cpp | 36 +++--
llvm/lib/CodeGen/RegAllocBasic.cpp | 16 +
llvm/lib/CodeGen/RegAllocGreedy.cpp | 4 +++-
llvm/lib/CodeGen/RegAllocPBQP.cpp | 5 +++-
5 files changed, 46 insertions(+), 31 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/Spiller.h
b/llvm/include/llvm/CodeGen/Spiller.h
index 51ad36bc6b1f8b..3132cefeb6c68a 100644
--- a/llvm/include/llvm/CodeGen/Spiller.h
+++ b/llvm/include/llvm/CodeGen/Spiller.h
@@ -19,6 +19,10 @@ class MachineFunction;
class MachineFunctionPass;
class VirtRegMap;
class VirtRegAuxInfo;
+class LiveIntervals;
+class LiveStacks;
+class MachineDominatorTree;
+class MachineBlockFrequencyInfo;
/// Spiller interface.
///
@@ -41,12 +45,20 @@ class Spiller {
virtual ArrayRef getReplacedRegs() = 0;
virtual void postOptimization() {}
+
+ struct RequiredAnalyses {
+LiveIntervals &LIS;
+LiveStacks &LSS;
+MachineDominatorTree &MDT;
+const MachineBlockFrequencyInfo &MBFI;
+ };
};
/// Create and return a spiller that will insert spill code directly instead
/// of deferring though VirtRegMap.
-Spiller *createInlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF,
- VirtRegMap &VRM, VirtRegAuxInfo &VRAI);
+Spiller *createInlineSpiller(const Spiller::RequiredAnalyses &Analyses,
+ MachineFunction &MF, VirtRegMap &VRM,
+ VirtRegAuxInfo &VRAI);
} // end namespace llvm
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp
b/llvm/lib/CodeGen/InlineSpiller.cpp
index 64f290f5930a1b..b9768d5c63a5d1 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -75,7 +75,6 @@ RestrictStatepointRemat("restrict-statepoint-remat",
cl::desc("Restrict remat for statepoint operands"));
namespace {
-
class HoistSpillHelper : private LiveRangeEdit::Delegate {
MachineFunction &MF;
LiveIntervals &LIS;
@@ -128,15 +127,11 @@ class HoistSpillHelper : private LiveRangeEdit::Delegate {
DenseMap &SpillsToIns);
public:
- HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
- VirtRegMap &vrm)
- : MF(mf), LIS(pass.getAnalysis().getLIS()),
-LSS(pass.getAnalysis().getLS()),
-MDT(pass.getAnalysis().getDomTree()),
+ HoistSpillHelper(const Spiller::RequiredAnalyses &Analyses,
+ MachineFunction &mf, VirtRegMap &vrm)
+ : MF(mf), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
-TRI(*mf.getSubtarget().getRegisterInfo()),
-MBFI(
-
pass.getAnalysis().getMBFI()),
+TRI(*mf.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
IPA(LIS, mf.getNumBlockIDs()) {}
void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
@@ -190,16 +185,12 @@ class InlineSpiller : public Spiller {
~InlineSpiller() override = default;
public:
- InlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF, VirtRegMap
&VRM,
-VirtRegAuxInfo &VRAI)
- : MF(MF), LIS(Pass.getAnalysis().getLIS()),
-LSS(Pass.getAnalysis().getLS()),
-MDT(Pass.getAnalysis().getDomTree()),
+ InlineSpiller(const Spiller::RequiredAnalyses &Analyses, MachineFunction &MF,
+VirtRegMap &VRM, VirtRegAuxInfo &VRAI)
+ : MF(MF), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
VRM(VRM), MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()),
-TRI(*MF.getSubtarget().getRegisterInfo()),
-MBFI(
-
Pass.getAnalysis().getMBFI()),
-HSpiller(Pass, MF, VRM), VRAI(VRAI) {}
+TRI(*MF.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
+HSpiller(Analyses, MF, VRM), VRAI(VRAI) {}
void spill(LiveRangeEdit &) override;
ArrayRef getSpilledRegs() override { return RegsToSpill; }
@@ -237,10 +228,11 @@ Spiller::~Spiller() = default;
void Spiller::anchor() {}
-Spiller *llvm::createInlineSpiller(MachineFunctionPass &Pass,
- MachineFunction &MF, VirtRegMap &VRM,
- VirtRegAuxInfo &VRAI) {
- return new InlineSpiller(Pass, MF, VRM, VRAI);
+Spiller *
+llvm::createInlineSpiller(const InlineSpiller::RequiredAnalyses &Analyses,
+ MachineFunction &MF, VirtRegMap &VRM,
+ VirtRegAuxInfo &VRAI) {
+ return new InlineSpiller(Analyses, MF, VRM, VRAI);
}
//===-
[llvm-branch-commits] [clang] [llvm] [Coverage] Make additional counters available for BranchRegion. NFC. (PR #120930)
@@ -1627,14 +1627,31 @@ class CodeGenFunction : public CodeGenTypeCache {
}
void markStmtMaybeUsed(const Stmt *S) { PGO.markStmtMaybeUsed(S); }
+ enum CounterForIncrement {
ornata wrote:
is the meaning of "exec counter" and "skip counter" defined anywhere? if not,
it would be good to do that here.
https://github.com/llvm/llvm-project/pull/120930
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [Coverage] Make additional counters available for BranchRegion. NFC. (PR #120930)
@@ -884,6 +884,9 @@ struct CounterCoverageMappingBuilder /// The map of statements to count values. llvm::DenseMap &CounterMap; + CounterExpressionBuilder::SubstMap MapToExpand; ornata wrote: MapToExpand could use a doxygen comment explaining what it is https://github.com/llvm/llvm-project/pull/120930 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [Coverage] Make additional counters available for BranchRegion. NFC. (PR #120930)
@@ -1627,14 +1627,31 @@ class CodeGenFunction : public CodeGenTypeCache {
}
void markStmtMaybeUsed(const Stmt *S) { PGO.markStmtMaybeUsed(S); }
+ enum CounterForIncrement {
ornata wrote:
doxygen comment would be useful here
https://github.com/llvm/llvm-project/pull/120930
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [Coverage][Single] Enable Branch coverage for `BinLAnd` and `BinLOr` (PR #113113)
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113113
>From 16e2bb8b73bcde1c2618bb358a905a9f463c1217 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Sun, 20 Oct 2024 16:24:26 +0900
Subject: [PATCH 1/3] [Coverage][Single] Enable Branch coverage for `BinLAnd`
and `BinLOr`
---
clang/lib/CodeGen/CGExprScalar.cpp | 83 +++-
clang/lib/CodeGen/CGStmt.cpp | 4 --
clang/lib/CodeGen/CodeGenFunction.cpp| 43 ++--
clang/lib/CodeGen/CoverageMappingGen.cpp | 6 --
4 files changed, 104 insertions(+), 32 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprScalar.cpp
b/clang/lib/CodeGen/CGExprScalar.cpp
index 11d4ec8a267605..83962ba96aa484 100644
--- a/clang/lib/CodeGen/CGExprScalar.cpp
+++ b/clang/lib/CodeGen/CGExprScalar.cpp
@@ -4918,6 +4918,9 @@ Value *ScalarExprEmitter::VisitBinAssign(const
BinaryOperator *E) {
}
Value *ScalarExprEmitter::VisitBinLAnd(const BinaryOperator *E) {
+ auto HasLHSSkip = CGF.getIsCounterPair(E);
+ auto HasRHSSkip = CGF.getIsCounterPair(E->getRHS());
+
// Perform vector logical and on comparisons with zero vectors.
if (E->getType()->isVectorType()) {
CGF.incrementProfileCounter(E);
@@ -4964,11 +4967,17 @@ Value *ScalarExprEmitter::VisitBinLAnd(const
BinaryOperator *E) {
CodeGenFunction::isInstrumentedCondition(E->getRHS())) {
CGF.maybeUpdateMCDCCondBitmap(E->getRHS(), RHSCond);
llvm::BasicBlock *FBlock = CGF.createBasicBlock("land.end");
+llvm::BasicBlock *RHSSkip =
+(HasRHSSkip.second ? CGF.createBasicBlock("land.rhsskip") :
FBlock);
llvm::BasicBlock *RHSBlockCnt = CGF.createBasicBlock("land.rhscnt");
-Builder.CreateCondBr(RHSCond, RHSBlockCnt, FBlock);
+Builder.CreateCondBr(RHSCond, RHSBlockCnt, RHSSkip);
CGF.EmitBlock(RHSBlockCnt);
-CGF.incrementProfileCounter(E->getRHS());
+CGF.incrementProfileCounter(false, E->getRHS());
CGF.EmitBranch(FBlock);
+if (HasRHSSkip.second) {
+ CGF.EmitBlock(RHSSkip);
+ CGF.incrementProfileCounter(true, E->getRHS());
+}
CGF.EmitBlock(FBlock);
}
@@ -4997,12 +5006,21 @@ Value *ScalarExprEmitter::VisitBinLAnd(const
BinaryOperator *E) {
llvm::BasicBlock *ContBlock = CGF.createBasicBlock("land.end");
llvm::BasicBlock *RHSBlock = CGF.createBasicBlock("land.rhs");
+ llvm::BasicBlock *LHSFalseBlock =
+ (HasLHSSkip.second ? CGF.createBasicBlock("land.lhsskip") : ContBlock);
+
CodeGenFunction::ConditionalEvaluation eval(CGF);
// Branch on the LHS first. If it is false, go to the failure (cont) block.
- CGF.EmitBranchOnBoolExpr(E->getLHS(), RHSBlock, ContBlock,
+ CGF.EmitBranchOnBoolExpr(E->getLHS(), RHSBlock, LHSFalseBlock,
CGF.getProfileCount(E->getRHS()));
+ if (HasLHSSkip.second) {
+CGF.EmitBlock(LHSFalseBlock);
+CGF.incrementProfileCounter(true, E);
+CGF.EmitBranch(ContBlock);
+ }
+
// Any edges into the ContBlock are now from an (indeterminate number of)
// edges from this first condition. All of these values will be false.
Start
// setting up the PHI node in the Cont Block for this.
@@ -5014,7 +5032,7 @@ Value *ScalarExprEmitter::VisitBinLAnd(const
BinaryOperator *E) {
eval.begin(CGF);
CGF.EmitBlock(RHSBlock);
- CGF.incrementProfileCounter(E);
+ CGF.incrementProfileCounter(false, E);
Value *RHSCond = CGF.EvaluateExprAsBool(E->getRHS());
eval.end(CGF);
@@ -5024,15 +5042,24 @@ Value *ScalarExprEmitter::VisitBinLAnd(const
BinaryOperator *E) {
// If we're generating for profiling or coverage, generate a branch on the
// RHS to a block that increments the RHS true counter needed to track branch
// condition coverage.
+ llvm::BasicBlock *ContIncoming = RHSBlock;
if (InstrumentRegions &&
CodeGenFunction::isInstrumentedCondition(E->getRHS())) {
CGF.maybeUpdateMCDCCondBitmap(E->getRHS(), RHSCond);
llvm::BasicBlock *RHSBlockCnt = CGF.createBasicBlock("land.rhscnt");
-Builder.CreateCondBr(RHSCond, RHSBlockCnt, ContBlock);
+llvm::BasicBlock *RHSBlockSkip =
+(HasRHSSkip.second ? CGF.createBasicBlock("land.rhsskip") : ContBlock);
+Builder.CreateCondBr(RHSCond, RHSBlockCnt, RHSBlockSkip);
CGF.EmitBlock(RHSBlockCnt);
-CGF.incrementProfileCounter(E->getRHS());
+CGF.incrementProfileCounter(false, E->getRHS());
CGF.EmitBranch(ContBlock);
PN->addIncoming(RHSCond, RHSBlockCnt);
+if (HasRHSSkip.second) {
+ CGF.EmitBlock(RHSBlockSkip);
+ CGF.incrementProfileCounter(true, E->getRHS());
+ CGF.EmitBranch(ContBlock);
+ ContIncoming = RHSBlockSkip;
+}
}
// Emit an unconditional branch from this block to ContBlock.
@@ -5042,7 +5069,7 @@ Value *ScalarExprEmitter::VisitBinLAnd(const
BinaryOperator *E) {
CGF.EmitBlock(ContBlock);
}
// Insert an entry into the phi node for the edge with the value of RHSCond.
[llvm-branch-commits] [clang] [llvm] [Coverage][Single] Enable Branch coverage for `BinLAnd` and `BinLOr` (PR #113113)
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113113
>From 16e2bb8b73bcde1c2618bb358a905a9f463c1217 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Sun, 20 Oct 2024 16:24:26 +0900
Subject: [PATCH 1/3] [Coverage][Single] Enable Branch coverage for `BinLAnd`
and `BinLOr`
---
clang/lib/CodeGen/CGExprScalar.cpp | 83 +++-
clang/lib/CodeGen/CGStmt.cpp | 4 --
clang/lib/CodeGen/CodeGenFunction.cpp| 43 ++--
clang/lib/CodeGen/CoverageMappingGen.cpp | 6 --
4 files changed, 104 insertions(+), 32 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprScalar.cpp
b/clang/lib/CodeGen/CGExprScalar.cpp
index 11d4ec8a267605..83962ba96aa484 100644
--- a/clang/lib/CodeGen/CGExprScalar.cpp
+++ b/clang/lib/CodeGen/CGExprScalar.cpp
@@ -4918,6 +4918,9 @@ Value *ScalarExprEmitter::VisitBinAssign(const
BinaryOperator *E) {
}
Value *ScalarExprEmitter::VisitBinLAnd(const BinaryOperator *E) {
+ auto HasLHSSkip = CGF.getIsCounterPair(E);
+ auto HasRHSSkip = CGF.getIsCounterPair(E->getRHS());
+
// Perform vector logical and on comparisons with zero vectors.
if (E->getType()->isVectorType()) {
CGF.incrementProfileCounter(E);
@@ -4964,11 +4967,17 @@ Value *ScalarExprEmitter::VisitBinLAnd(const
BinaryOperator *E) {
CodeGenFunction::isInstrumentedCondition(E->getRHS())) {
CGF.maybeUpdateMCDCCondBitmap(E->getRHS(), RHSCond);
llvm::BasicBlock *FBlock = CGF.createBasicBlock("land.end");
+llvm::BasicBlock *RHSSkip =
+(HasRHSSkip.second ? CGF.createBasicBlock("land.rhsskip") :
FBlock);
llvm::BasicBlock *RHSBlockCnt = CGF.createBasicBlock("land.rhscnt");
-Builder.CreateCondBr(RHSCond, RHSBlockCnt, FBlock);
+Builder.CreateCondBr(RHSCond, RHSBlockCnt, RHSSkip);
CGF.EmitBlock(RHSBlockCnt);
-CGF.incrementProfileCounter(E->getRHS());
+CGF.incrementProfileCounter(false, E->getRHS());
CGF.EmitBranch(FBlock);
+if (HasRHSSkip.second) {
+ CGF.EmitBlock(RHSSkip);
+ CGF.incrementProfileCounter(true, E->getRHS());
+}
CGF.EmitBlock(FBlock);
}
@@ -4997,12 +5006,21 @@ Value *ScalarExprEmitter::VisitBinLAnd(const
BinaryOperator *E) {
llvm::BasicBlock *ContBlock = CGF.createBasicBlock("land.end");
llvm::BasicBlock *RHSBlock = CGF.createBasicBlock("land.rhs");
+ llvm::BasicBlock *LHSFalseBlock =
+ (HasLHSSkip.second ? CGF.createBasicBlock("land.lhsskip") : ContBlock);
+
CodeGenFunction::ConditionalEvaluation eval(CGF);
// Branch on the LHS first. If it is false, go to the failure (cont) block.
- CGF.EmitBranchOnBoolExpr(E->getLHS(), RHSBlock, ContBlock,
+ CGF.EmitBranchOnBoolExpr(E->getLHS(), RHSBlock, LHSFalseBlock,
CGF.getProfileCount(E->getRHS()));
+ if (HasLHSSkip.second) {
+CGF.EmitBlock(LHSFalseBlock);
+CGF.incrementProfileCounter(true, E);
+CGF.EmitBranch(ContBlock);
+ }
+
// Any edges into the ContBlock are now from an (indeterminate number of)
// edges from this first condition. All of these values will be false.
Start
// setting up the PHI node in the Cont Block for this.
@@ -5014,7 +5032,7 @@ Value *ScalarExprEmitter::VisitBinLAnd(const
BinaryOperator *E) {
eval.begin(CGF);
CGF.EmitBlock(RHSBlock);
- CGF.incrementProfileCounter(E);
+ CGF.incrementProfileCounter(false, E);
Value *RHSCond = CGF.EvaluateExprAsBool(E->getRHS());
eval.end(CGF);
@@ -5024,15 +5042,24 @@ Value *ScalarExprEmitter::VisitBinLAnd(const
BinaryOperator *E) {
// If we're generating for profiling or coverage, generate a branch on the
// RHS to a block that increments the RHS true counter needed to track branch
// condition coverage.
+ llvm::BasicBlock *ContIncoming = RHSBlock;
if (InstrumentRegions &&
CodeGenFunction::isInstrumentedCondition(E->getRHS())) {
CGF.maybeUpdateMCDCCondBitmap(E->getRHS(), RHSCond);
llvm::BasicBlock *RHSBlockCnt = CGF.createBasicBlock("land.rhscnt");
-Builder.CreateCondBr(RHSCond, RHSBlockCnt, ContBlock);
+llvm::BasicBlock *RHSBlockSkip =
+(HasRHSSkip.second ? CGF.createBasicBlock("land.rhsskip") : ContBlock);
+Builder.CreateCondBr(RHSCond, RHSBlockCnt, RHSBlockSkip);
CGF.EmitBlock(RHSBlockCnt);
-CGF.incrementProfileCounter(E->getRHS());
+CGF.incrementProfileCounter(false, E->getRHS());
CGF.EmitBranch(ContBlock);
PN->addIncoming(RHSCond, RHSBlockCnt);
+if (HasRHSSkip.second) {
+ CGF.EmitBlock(RHSBlockSkip);
+ CGF.incrementProfileCounter(true, E->getRHS());
+ CGF.EmitBranch(ContBlock);
+ ContIncoming = RHSBlockSkip;
+}
}
// Emit an unconditional branch from this block to ContBlock.
@@ -5042,7 +5069,7 @@ Value *ScalarExprEmitter::VisitBinLAnd(const
BinaryOperator *E) {
CGF.EmitBlock(ContBlock);
}
// Insert an entry into the phi node for the edge with the value of RHSCond.
[llvm-branch-commits] [clang] [llvm] [Coverage][Single] Enable Branch coverage for SwitchStmt (PR #113112)
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113112
>From ec05cc37e1177f06c9a44a1e39dadc9306cc5c68 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Mon, 21 Oct 2024 08:09:31 +0900
Subject: [PATCH 1/4] [Coverage][Single] Enable Branch coverage for SwitchStmt
---
clang/lib/CodeGen/CGStmt.cpp | 12 ++
clang/lib/CodeGen/CoverageMappingGen.cpp | 22 ++-
.../CoverageMapping/single-byte-counters.cpp | 13 ++-
3 files changed, 32 insertions(+), 15 deletions(-)
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index dbc1ce9bf993cd..80fe5cf183de16 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -2259,6 +2259,18 @@ void CodeGenFunction::EmitSwitchStmt(const SwitchStmt
&S) {
ConditionScope.ForceCleanup();
+ // Close the last case (or DefaultBlock).
+ EmitBranch(SwitchExit.getBlock());
+
+ // Insert a False Counter if SwitchStmt doesn't have DefaultStmt.
+ if (getIsCounterPair(S.getCond()).second) {
+auto *ImplicitDefaultBlock = createBasicBlock("sw.false");
+EmitBlock(ImplicitDefaultBlock);
+incrementProfileCounter(true, S.getCond());
+Builder.CreateBr(SwitchInsn->getDefaultDest());
+SwitchInsn->setDefaultDest(ImplicitDefaultBlock);
+ }
+
// Emit continuation.
EmitBlock(SwitchExit.getBlock(), true);
incrementProfileCounter(&S);
diff --git a/clang/lib/CodeGen/CoverageMappingGen.cpp
b/clang/lib/CodeGen/CoverageMappingGen.cpp
index a331d5bc68286b..c5fdf23299e4e9 100644
--- a/clang/lib/CodeGen/CoverageMappingGen.cpp
+++ b/clang/lib/CodeGen/CoverageMappingGen.cpp
@@ -958,6 +958,14 @@ struct CounterCoverageMappingBuilder
return {ExecCnt, SkipCnt};
}
+ Counter getSwitchImplicitDefaultCounter(const Stmt *Cond, Counter
ParentCount,
+ Counter CaseCountSum) {
+return (
+llvm::EnableSingleByteCoverage
+? Counter::getCounter(CounterMap[Cond].second = NextCounterNum++)
+: subtractCounters(ParentCount, CaseCountSum));
+ }
+
bool IsCounterEqual(Counter OutCount, Counter ParentCount) {
if (OutCount == ParentCount)
return true;
@@ -1885,7 +1893,7 @@ struct CounterCoverageMappingBuilder
propagateCounts(Counter::getZero(), Body);
BreakContinue BC = BreakContinueStack.pop_back_val();
-if (!BreakContinueStack.empty() && !llvm::EnableSingleByteCoverage)
+if (!BreakContinueStack.empty())
BreakContinueStack.back().ContinueCount = addCounters(
BreakContinueStack.back().ContinueCount, BC.ContinueCount);
@@ -1900,11 +1908,6 @@ struct CounterCoverageMappingBuilder
MostRecentLocation = getStart(S);
handleFileExit(ExitLoc);
-// When single byte coverage mode is enabled, do not create branch region
by
-// early returning.
-if (llvm::EnableSingleByteCoverage)
- return;
-
// Create a Branch Region around each Case. Subtract the case's
// counter from the Parent counter to track the "False" branch count.
Counter CaseCountSum;
@@ -1920,7 +1923,8 @@ struct CounterCoverageMappingBuilder
// the hidden branch, which will be added later by the CodeGen. This region
// will be associated with the switch statement's condition.
if (!HasDefaultCase) {
- Counter DefaultCount = subtractCounters(ParentCount, CaseCountSum);
+ Counter DefaultCount = getSwitchImplicitDefaultCounter(
+ S->getCond(), ParentCount, CaseCountSum);
createBranchRegion(S->getCond(), Counter::getZero(), DefaultCount);
}
}
@@ -1929,9 +1933,7 @@ struct CounterCoverageMappingBuilder
extendRegion(S);
SourceMappingRegion &Parent = getRegion();
-Counter Count = llvm::EnableSingleByteCoverage
-? getRegionCounter(S)
-: addCounters(Parent.getCounter(),
getRegionCounter(S));
+Counter Count = addCounters(Parent.getCounter(), getRegionCounter(S));
// Reuse the existing region if it starts at our label. This is typical of
// the first case in a switch.
diff --git a/clang/test/CoverageMapping/single-byte-counters.cpp
b/clang/test/CoverageMapping/single-byte-counters.cpp
index d20b695bc2636a..464fa370d86f09 100644
--- a/clang/test/CoverageMapping/single-byte-counters.cpp
+++ b/clang/test/CoverageMapping/single-byte-counters.cpp
@@ -34,19 +34,22 @@ int testIfElseReturn(int x) { // CHECK-NEXT: File 0,
[[@LINE]]:29 -> [[@LINE+9]]
}
// CHECK-NEXT: testSwitch
-int testSwitch(int x) { // CHECK-NEXT: File 0, [[@LINE]]:23 -> [[@LINE+17]]:2
= [[C30:#0]]
+int testSwitch(int x) { // CHECK-NEXT: File 0, [[@LINE]]:23 -> [[@LINE+20]]:2
= [[C30:#0]]
int result;
switch (x) {
-// CHECK-NEXT: Gap,File 0, [[@LINE-1]]:14 ->
[[@LINE+10]]:15 = 0
- case 1: // CHECK-NEXT: File 0, [[@LINE]]:3 -> [[@LINE+2]]:10 =
[[C31:#2]]
+// CHECK-NEXT: Gap,File
[llvm-branch-commits] [clang] [llvm] [Coverage][Single] Enable Branch coverage for CondOp (PR #113110)
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113110
>From 744c5b634de08f9214c82d6fcfde7179bc4edfb0 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Sun, 20 Oct 2024 14:46:07 +0900
Subject: [PATCH 1/5] [Coverage][Single] Enable Branch coverage for CondOp
---
clang/lib/CodeGen/CGExpr.cpp | 6 +--
clang/lib/CodeGen/CGExprAgg.cpp | 14 +--
clang/lib/CodeGen/CGExprComplex.cpp | 15 +---
clang/lib/CodeGen/CGExprScalar.cpp| 37 +++
clang/lib/CodeGen/CodeGenFunction.cpp | 3 +-
clang/lib/CodeGen/CodeGenPGO.cpp | 8
clang/lib/CodeGen/CoverageMappingGen.cpp | 16 ++--
.../CoverageMapping/single-byte-counters.cpp | 11 +++---
8 files changed, 25 insertions(+), 85 deletions(-)
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index cc85f05ad9f70c..67e3a1de17e679 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -5137,8 +5137,7 @@ std::optional
HandleConditionalOperatorLValueSimpleCase(
if (!CGF.ContainsLabel(Dead)) {
// If the true case is live, we need to track its region.
- if (CondExprBool)
-CGF.incrementProfileCounter(E);
+ CGF.incrementProfileCounter(!CondExprBool, E, true);
CGF.markStmtMaybeUsed(Dead);
// If a throw expression we emit it and return an undefined lvalue
// because it can't be used.
@@ -5177,7 +5176,7 @@ ConditionalInfo EmitConditionalBlocks(CodeGenFunction
&CGF,
// Any temporaries created here are conditional.
CGF.EmitBlock(Info.lhsBlock);
- CGF.incrementProfileCounter(E);
+ CGF.incrementProfileCounter(false, E);
eval.begin(CGF);
Info.LHS = BranchGenFunc(CGF, E->getTrueExpr());
eval.end(CGF);
@@ -5188,6 +5187,7 @@ ConditionalInfo EmitConditionalBlocks(CodeGenFunction
&CGF,
// Any temporaries created here are conditional.
CGF.EmitBlock(Info.rhsBlock);
+ CGF.incrementProfileCounter(true, E);
eval.begin(CGF);
Info.RHS = BranchGenFunc(CGF, E->getFalseExpr());
eval.end(CGF);
diff --git a/clang/lib/CodeGen/CGExprAgg.cpp b/clang/lib/CodeGen/CGExprAgg.cpp
index 2ad6587089f101..0c778ef185532f 100644
--- a/clang/lib/CodeGen/CGExprAgg.cpp
+++ b/clang/lib/CodeGen/CGExprAgg.cpp
@@ -36,10 +36,6 @@ using namespace CodeGen;
//Aggregate Expression Emitter
//===--===//
-namespace llvm {
-extern cl::opt EnableSingleByteCoverage;
-} // namespace llvm
-
namespace {
class AggExprEmitter : public StmtVisitor {
CodeGenFunction &CGF;
@@ -1293,10 +1289,7 @@ VisitAbstractConditionalOperator(const
AbstractConditionalOperator *E) {
eval.begin(CGF);
CGF.EmitBlock(LHSBlock);
- if (llvm::EnableSingleByteCoverage)
-CGF.incrementProfileCounter(E->getTrueExpr());
- else
-CGF.incrementProfileCounter(E);
+ CGF.incrementProfileCounter(false, E);
Visit(E->getTrueExpr());
eval.end(CGF);
@@ -1311,8 +1304,7 @@ VisitAbstractConditionalOperator(const
AbstractConditionalOperator *E) {
eval.begin(CGF);
CGF.EmitBlock(RHSBlock);
- if (llvm::EnableSingleByteCoverage)
-CGF.incrementProfileCounter(E->getFalseExpr());
+ CGF.incrementProfileCounter(true, E);
Visit(E->getFalseExpr());
eval.end(CGF);
@@ -1321,8 +1313,6 @@ VisitAbstractConditionalOperator(const
AbstractConditionalOperator *E) {
E->getType());
CGF.EmitBlock(ContBlock);
- if (llvm::EnableSingleByteCoverage)
-CGF.incrementProfileCounter(E);
}
void AggExprEmitter::VisitChooseExpr(const ChooseExpr *CE) {
diff --git a/clang/lib/CodeGen/CGExprComplex.cpp
b/clang/lib/CodeGen/CGExprComplex.cpp
index fef26e7b4ccdbd..bcece9431de764 100644
--- a/clang/lib/CodeGen/CGExprComplex.cpp
+++ b/clang/lib/CodeGen/CGExprComplex.cpp
@@ -28,10 +28,6 @@ using namespace CodeGen;
//Complex Expression Emitter
//===--===//
-namespace llvm {
-extern cl::opt EnableSingleByteCoverage;
-} // namespace llvm
-
typedef CodeGenFunction::ComplexPairTy ComplexPairTy;
/// Return the complex type that we are meant to emit.
@@ -1381,11 +1377,7 @@ VisitAbstractConditionalOperator(const
AbstractConditionalOperator *E) {
eval.begin(CGF);
CGF.EmitBlock(LHSBlock);
- if (llvm::EnableSingleByteCoverage)
-CGF.incrementProfileCounter(E->getTrueExpr());
- else
-CGF.incrementProfileCounter(E);
-
+ CGF.incrementProfileCounter(false, E);
ComplexPairTy LHS = Visit(E->getTrueExpr());
LHSBlock = Builder.GetInsertBlock();
CGF.EmitBranch(ContBlock);
@@ -1393,13 +1385,10 @@ VisitAbstractConditionalOperator(const
AbstractConditionalOperator *E) {
eval.begin(CGF);
CGF.EmitBlock(RHSBlock);
- if (llvm::EnableSingleByteCoverage)
-CGF.incrementProfileCounter(E->getFalseExpr());
+ CGF.incrementProfileCounter(true, E);
Com
[llvm-branch-commits] [llvm] AMDGPU: Reduce 64-bit add width if high bits are known 0 (PR #122049)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/122049
AMDGPU: Reduce 64-bit add width if high bits are known 0
If one of the inputs has all 0 bits, the low part cannot
carry and we can just pass through the original value.
Add case: https://alive2.llvm.org/ce/z/TNc7hf
Sub case: https://alive2.llvm.org/ce/z/AjH2-J
We could do this in the general case with computeKnownBits,
but add is so common this could be potentially expensive for
something which will fire infrequently.
One potential concern is this could break the 64-bit add
we expect to see for addressing mode matching, but these
constants shouldn't appear often in addressing expressions.
One test for large offset expressions changes but isn't worse.
Fixes https://github.com/ROCm/llvm-project/issues/237
XXX - Use computeKnownBits for the general case
Revert "XXX - Use computeKnownBits for the general case"
This reverts commit e3d348374fa67b6daa09d5838d09eed8fe0dc083.
>From 068d33456ce13505ab9f273b9f8be6bebaa4c67b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 8 Jan 2025 11:23:35 +0700
Subject: [PATCH 1/3] AMDGPU: Reduce 64-bit add width if high bits are known 0
If one of the inputs has all 0 bits, the low part cannot
carry and we can just pass through the original value.
Add case: https://alive2.llvm.org/ce/z/TNc7hf
Sub case: https://alive2.llvm.org/ce/z/AjH2-J
We could do this in the general case with computeKnownBits,
but add is so common this could be potentially expensive for
something which will fire infrequently.
One potential concern is this could break the 64-bit add
we expect to see for addressing mode matching, but these
constants shouldn't appear often in addressing expressions.
One test for large offset expressions changes but isn't worse.
Fixes https://github.com/ROCm/llvm-project/issues/237
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 47 ++
llvm/lib/Target/AMDGPU/SIISelLowering.h | 3 +
.../AMDGPU/add64-low-32-bits-known-zero.ll| 56 +++
llvm/test/CodeGen/AMDGPU/global-saddr-load.ll | 54 +++
.../AMDGPU/promote-constOffset-to-imm.ll | 144 +-
.../AMDGPU/sub64-low-32-bits-known-zero.ll| 56 +++
6 files changed, 177 insertions(+), 183 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index b3cfa398d9b5f6..0ac84f4e1f02af 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -13985,6 +13985,43 @@ SDValue SITargetLowering::tryFoldToMad64_32(SDNode *N,
return Accum;
}
+SDValue
+SITargetLowering::foldAddSub64WithZeroLowBitsTo32(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ SDValue RHS = N->getOperand(1);
+ auto *CRHS = dyn_cast(RHS);
+ if (!CRHS)
+return SDValue();
+
+ // TODO: Worth using computeKnownBits? Maybe expensive since it's so
+ // common.
+ uint64_t Val = CRHS->getZExtValue();
+ if (countr_zero(Val) >= 32) {
+SelectionDAG &DAG = DCI.DAG;
+SDLoc SL(N);
+SDValue LHS = N->getOperand(0);
+
+// Avoid carry machinery if we know the low half of the add does not
+// contribute to the final result.
+//
+// add i64:x, K if computeTrailingZeros(K) >= 32
+// => build_pair (add x.hi, K.hi), x.lo
+
+// Breaking the 64-bit add here with this strange constant is unlikely
+// to interfere with addressing mode patterns.
+
+SDValue Hi = getHiHalf64(LHS, DAG);
+SDValue ConstHi32 = DAG.getConstant(Hi_32(Val), SL, MVT::i32);
+SDValue AddHi =
+DAG.getNode(N->getOpcode(), SL, MVT::i32, Hi, ConstHi32,
N->getFlags());
+
+SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
+return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Lo, AddHi);
+ }
+
+ return SDValue();
+}
+
// Collect the ultimate src of each of the mul node's operands, and confirm
// each operand is 8 bytes.
static std::optional>
@@ -14261,6 +14298,11 @@ SDValue SITargetLowering::performAddCombine(SDNode *N,
return V;
}
+ if (VT == MVT::i64) {
+if (SDValue Folded = foldAddSub64WithZeroLowBitsTo32(N, DCI))
+ return Folded;
+ }
+
if ((isMul(LHS) || isMul(RHS)) && Subtarget->hasDot7Insts() &&
(Subtarget->hasDot1Insts() || Subtarget->hasDot8Insts())) {
SDValue TempNode(N, 0);
@@ -14446,6 +14488,11 @@ SDValue SITargetLowering::performSubCombine(SDNode *N,
SelectionDAG &DAG = DCI.DAG;
EVT VT = N->getValueType(0);
+ if (VT == MVT::i64) {
+if (SDValue Folded = foldAddSub64WithZeroLowBitsTo32(N, DCI))
+ return Folded;
+ }
+
if (VT != MVT::i32)
return SDValue();
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h
b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index f4641e7a659907..299c8f5f739235 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -212,6 +212,9 @@ class SITargetLowering final : public AMDGPUTargetLowering {
[llvm-branch-commits] [llvm] AMDGPU: Reduce 64-bit add width if high bits are known 0 (PR #122049)
https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/122049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Reduce 64-bit add width if high bits are known 0 (PR #122049)
https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/122049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Reduce 64-bit add width if high bits are known 0 (PR #122049)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/122049?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#122049** https://app.graphite.dev/github/pr/llvm/llvm-project/122049?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/122049?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#122048** https://app.graphite.dev/github/pr/llvm/llvm-project/122048?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/122049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Reduce 64-bit add width if high bits are known 0 (PR #122049)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
AMDGPU: Reduce 64-bit add width if high bits are known 0
If one of the inputs has all 0 bits, the low part cannot
carry and we can just pass through the original value.
Add case: https://alive2.llvm.org/ce/z/TNc7hf
Sub case: https://alive2.llvm.org/ce/z/AjH2-J
We could do this in the general case with computeKnownBits,
but add is so common this could be potentially expensive for
something which will fire infrequently.
One potential concern is this could break the 64-bit add
we expect to see for addressing mode matching, but these
constants shouldn't appear often in addressing expressions.
One test for large offset expressions changes but isn't worse.
Fixes https://github.com/ROCm/llvm-project/issues/237
---
Patch is 35.21 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/122049.diff
6 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+47)
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.h (+3)
- (modified) llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll (+18-38)
- (modified) llvm/test/CodeGen/AMDGPU/global-saddr-load.ll (+22-32)
- (modified) llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll (+69-75)
- (modified) llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll (+18-38)
``diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index b3cfa398d9b5f6..0ac84f4e1f02af 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -13985,6 +13985,43 @@ SDValue SITargetLowering::tryFoldToMad64_32(SDNode *N,
return Accum;
}
+SDValue
+SITargetLowering::foldAddSub64WithZeroLowBitsTo32(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ SDValue RHS = N->getOperand(1);
+ auto *CRHS = dyn_cast(RHS);
+ if (!CRHS)
+return SDValue();
+
+ // TODO: Worth using computeKnownBits? Maybe expensive since it's so
+ // common.
+ uint64_t Val = CRHS->getZExtValue();
+ if (countr_zero(Val) >= 32) {
+SelectionDAG &DAG = DCI.DAG;
+SDLoc SL(N);
+SDValue LHS = N->getOperand(0);
+
+// Avoid carry machinery if we know the low half of the add does not
+// contribute to the final result.
+//
+// add i64:x, K if computeTrailingZeros(K) >= 32
+// => build_pair (add x.hi, K.hi), x.lo
+
+// Breaking the 64-bit add here with this strange constant is unlikely
+// to interfere with addressing mode patterns.
+
+SDValue Hi = getHiHalf64(LHS, DAG);
+SDValue ConstHi32 = DAG.getConstant(Hi_32(Val), SL, MVT::i32);
+SDValue AddHi =
+DAG.getNode(N->getOpcode(), SL, MVT::i32, Hi, ConstHi32,
N->getFlags());
+
+SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
+return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Lo, AddHi);
+ }
+
+ return SDValue();
+}
+
// Collect the ultimate src of each of the mul node's operands, and confirm
// each operand is 8 bytes.
static std::optional>
@@ -14261,6 +14298,11 @@ SDValue SITargetLowering::performAddCombine(SDNode *N,
return V;
}
+ if (VT == MVT::i64) {
+if (SDValue Folded = foldAddSub64WithZeroLowBitsTo32(N, DCI))
+ return Folded;
+ }
+
if ((isMul(LHS) || isMul(RHS)) && Subtarget->hasDot7Insts() &&
(Subtarget->hasDot1Insts() || Subtarget->hasDot8Insts())) {
SDValue TempNode(N, 0);
@@ -14446,6 +14488,11 @@ SDValue SITargetLowering::performSubCombine(SDNode *N,
SelectionDAG &DAG = DCI.DAG;
EVT VT = N->getValueType(0);
+ if (VT == MVT::i64) {
+if (SDValue Folded = foldAddSub64WithZeroLowBitsTo32(N, DCI))
+ return Folded;
+ }
+
if (VT != MVT::i32)
return SDValue();
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h
b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index f4641e7a659907..299c8f5f739235 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -212,6 +212,9 @@ class SITargetLowering final : public AMDGPUTargetLowering {
unsigned getFusedOpcode(const SelectionDAG &DAG,
const SDNode *N0, const SDNode *N1) const;
SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
+ SDValue foldAddSub64WithZeroLowBitsTo32(SDNode *N,
+ DAGCombinerInfo &DCI) const;
+
SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI)
const;
SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
diff --git a/llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
b/llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
index 981e33f89d956e..52259c4c2e6e12 100644
--- a/llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
+++ b/llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
@@ -10,8 +10,7 @@
define
[llvm-branch-commits] [llvm] AMDGPU: Reduce 64-bit add width if high bits are known 0 (PR #122049)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/122049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Reduce 64-bit add width if low bits are known 0 (PR #122049)
https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/122049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [RISCV] Change linker job in Baremetal toolchain object accomodate GCCInstallation.(2/3) (PR #121830)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121830
>From 48d128350edc71ddca5892552dadf076be766f94 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 09:21:11 -0800
Subject: [PATCH] [RISCV] Change linker job in Baremetal toolchain object to
accomodate valid GCCInstallation.(2/3)
This patch adds the defaults for CXXSstdlib type and other runtime libs.
Additionally, this patch also modifes the linker job and extend it to support
valid GCCInstallation.
This PR preserves the behavior of both toolchain objects in the linker job with
the only new change being that the presence of `--gcc-toolchain` or
`--gcc-install-dir` will imply that GNU linker is the default linker unless
otherwise a differnt linker is passed through `-fuse-ld` flag.
This is the second PR in the series of 3 PRs for merging and extending Baremetal
toolchain object. The division of the PRs is as follows:
- Teach Baremetal toolchain about GCC installation and make sysroot and
assembler
related changes.
- Changes related to linker job and defaults for CXXStdlib and other runtime
libs.
- Finally removing the call to RISCVToolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: I8fdb3490a3888001b1bb999e7ee8df90a187d18d
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 110 +++-
clang/lib/Driver/ToolChains/BareMetal.h | 20 ++--
clang/test/Driver/aarch64-toolchain-extra.c | 6 ++
clang/test/Driver/aarch64-toolchain.c | 73 +
clang/test/Driver/arm-toolchain-extra.c | 7 +-
clang/test/Driver/arm-toolchain.c | 77 +-
clang/test/Driver/baremetal-multilib.yaml | 2 +-
clang/test/Driver/baremetal-sysroot.cpp | 2 +-
clang/test/Driver/baremetal.cpp | 77 +++---
clang/test/Driver/sanitizer-ld.c| 2 +-
10 files changed, 298 insertions(+), 78 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 7b0f2bc2fd3895..38de25e20ea8df 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -172,6 +172,8 @@ BareMetal::BareMetal(const Driver &D, const llvm::Triple
&Triple,
: Generic_ELF(D, Triple, Args) {
GCCInstallation.init(Triple, Args);
SysRoot = computeSysRoot();
+ UseLD =
+ Args.getLastArgValue(options::OPT_fuse_ld_EQ).equals_insensitive("ld");
if (GCCInstallation.isValid()) {
Multilibs = GCCInstallation.getMultilibs();
SelectedMultilibs.assign({GCCInstallation.getMultilib()});
@@ -342,6 +344,32 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::CST_Libstdcxx;
+ return ToolChain::CST_Libcxx;
+}
+
+ToolChain::RuntimeLibType BareMetal::GetDefaultRuntimeLibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain::RLT_Libgcc;
+ return ToolChain::RLT_CompilerRT;
+}
+
+ToolChain::UnwindLibType
+BareMetal::GetUnwindLibType(const llvm::opt::ArgList &Args) const {
+ if (getTriple().isRISCV())
+return ToolChain::UNW_None;
+
+ return ToolChain::GetUnwindLibType(Args);
+}
+
+const char *BareMetal::getDefaultLinker() const {
+ if (isUsingLD())
+return "ld";
+ return "ld.lld";
+}
+
void BareMetal::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
ArgStringList &CC1Args) const {
if (DriverArgs.hasArg(options::OPT_nostdinc))
@@ -535,12 +563,21 @@ void baremetal::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
const llvm::Triple::ArchType Arch = TC.getArch();
const llvm::Triple &Triple = getToolChain().getEffectiveTriple();
- AddLinkerInputs(TC, Inputs, Args, CmdArgs, JA);
+ if (!D.SysRoot.empty())
+CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot));
CmdArgs.push_back("-Bstatic");
- if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+ if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+ CmdArgs.push_back("--no-relax");
+if (TC.isUsingLD()) {
+ CmdArgs.push_back("-m");
+ CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+ : "elf32lriscv");
+}
+CmdArgs.push_back("-X");
+ }
if (Triple.isARM() || Triple.isThumb()) {
bool IsBigEndian = arm::isARMBigEndian(Triple, Args);
@@ -551,19 +588,54 @@ void baremetal::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
CmdArgs.push_back(Arch == llvm::Triple::aarch64_be ? "-EB" : "-EL");
}
- if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles,
- options::OPT_r)) {
-CmdArgs.pu
[llvm-branch-commits] [clang] [RISCV] Integrate RISCV target in baremetal toolchain object and deprecate RISCVToolchain object.(3/3) (PR #121831)
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From 9f9ddaae799bc8a6464df81e215ca2cbefee0719 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
and deprecate RISCVToolchain object.(3/3)
This PR is last in the series of merging RISCVToolchain object into BareMetal
toolchain object. This PR make change to call BareMetal toolchain object for
riscv targets as well and remove RISCVToolChain object.
The division of the PRs is as follows:
- Teach Baremetal toolchain about GCC installation and make sysroot and
assembler
related changes.
- Changes related to linker job and defaults for CXXStdlib and other runtime
libs.
- Finally removing the call to RISCVToolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Change-Id: I2877ac328f55a7638cc185d6034866cbd2ac4203
---
clang/lib/Driver/CMakeLists.txt | 1 -
clang/lib/Driver/Driver.cpp | 7 +-
clang/test/Driver/riscv-args.c | 2 +-
clang/test/Driver/riscv32-toolchain-extra.c | 7 +++---
clang/test/Driver/riscv32-toolchain.c | 26 ++---
clang/test/Driver/riscv64-toolchain-extra.c | 7 +++---
clang/test/Driver/riscv64-toolchain.c | 20
7 files changed, 31 insertions(+), 39 deletions(-)
diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt
index 5bdb6614389cff..eee29af5d181a1 100644
--- a/clang/lib/Driver/CMakeLists.txt
+++ b/clang/lib/Driver/CMakeLists.txt
@@ -74,7 +74,6 @@ add_clang_library(clangDriver
ToolChains/OHOS.cpp
ToolChains/OpenBSD.cpp
ToolChains/PS4CPU.cpp
- ToolChains/RISCVToolchain.cpp
ToolChains/Solaris.cpp
ToolChains/SPIRV.cpp
ToolChains/SPIRVOpenMP.cpp
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 36d6c93c43321f..4dda9a34b08d99 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -41,7 +41,6 @@
#include "ToolChains/PPCFreeBSD.h"
#include "ToolChains/PPCLinux.h"
#include "ToolChains/PS4CPU.h"
-#include "ToolChains/RISCVToolchain.h"
#include "ToolChains/SPIRV.h"
#include "ToolChains/SPIRVOpenMP.h"
#include "ToolChains/SYCL.h"
@@ -6665,11 +6664,7 @@ const ToolChain &Driver::getToolChain(const ArgList
&Args,
break;
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
-if (toolchains::RISCVToolChain::hasGCCToolchain(*this, Args))
- TC =
- std::make_unique(*this, Target,
Args);
-else
- TC = std::make_unique(*this, Target, Args);
+TC = std::make_unique(*this, Target, Args);
break;
case llvm::Triple::ve:
TC = std::make_unique(*this, Target, Args);
diff --git a/clang/test/Driver/riscv-args.c b/clang/test/Driver/riscv-args.c
index cab08e5b0f811e..fc35407baf2cc6 100644
--- a/clang/test/Driver/riscv-args.c
+++ b/clang/test/Driver/riscv-args.c
@@ -3,4 +3,4 @@
// Make sure -T is the last with gcc-toolchain option
// RUN: %clang -### --target=riscv32 --gcc-toolchain= -Xlinker --defsym=FOO=10
-T a.lds -u foo %s 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LD %s
-// CHECK-LD: {{.*}} "--defsym=FOO=10" {{.*}} "-u" "foo" {{.*}} "-T" "a.lds"
+// CHECK-LD: {{.*}} "-T" "a.lds" "-u" "foo" {{.*}} "--defsym=FOO=10"
diff --git a/clang/test/Driver/riscv32-toolchain-extra.c
b/clang/test/Driver/riscv32-toolchain-extra.c
index cbb3c23ebb3421..420f7b52036090 100644
--- a/clang/test/Driver/riscv32-toolchain-extra.c
+++ b/clang/test/Driver/riscv32-toolchain-extra.c
@@ -18,12 +18,12 @@
// RUN: ln -s %S/Inputs/basic_riscv32_nogcc_tree/riscv32-unknown-elf
%t/riscv32-nogcc/riscv32-unknown-elf
// RUN: %t/riscv32-nogcc/bin/clang %s -### -no-canonical-prefixes \
// RUN:--gcc-toolchain=%t/riscv32-nogcc/invalid \
-// RUN:--target=riscv32-unknown-elf --rtlib=platform -fuse-ld= 2>&1 \
+// RUN:--target=riscv32-unknown-elf --rtlib=platform -fuse-ld=ld 2>&1 \
// RUN:| FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32-NOGCC %s
// RUN: %t/riscv32-nogcc/bin/clang %s -### -no-canonical-prefixes \
// RUN:--sysroot=%t/riscv32-nogcc/bin/../riscv32-unknown-elf \
-// RUN:--target=riscv32-unknown-elf --rtlib=platform -fuse-ld= 2>&1 \
+// RUN:--target=riscv32-unknown-elf --rtlib=platform -fuse-ld=ld 2>&1 \
// RUN:| FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32-NOGCC %s
// C-RV32-BAREMETAL-ILP32-NOGCC: "-internal-isystem"
"{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/include"
@@ -31,6 +31,5 @@
// C-RV32-BAREMETAL-ILP32-NOGCC:
"{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/lib/crt0.o"
// C-RV32-BAREMETAL-ILP32-NOGCC:
"{{.*}}/riscv32-nogcc/{{.*}}/riscv32-unknown-unknown-elf/clang_rt.crtbegin.o"
// C-RV32-BAREMETAL-ILP32-NOGCC:
"{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/lib"
-// C-RV32-BAREMETAL-ILP32-NOGCC: "--start-group" "-lc" "
[llvm-branch-commits] [clang] [llvm] [Coverage][Single] Enable Branch coverage for loop statements (PR #113109)
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113109
>From 5d19c77551c6fc585d1b15c4c2a71c3c3f99ef8a Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Fri, 18 Oct 2024 09:33:51 +0900
Subject: [PATCH 1/4] [Coverage][Single] Enable Branch coverage for loop
statements
---
clang/lib/CodeGen/CGStmt.cpp | 82 ---
clang/lib/CodeGen/CodeGenFunction.cpp | 11 +-
clang/lib/CodeGen/CodeGenPGO.cpp | 79 +--
clang/lib/CodeGen/CoverageMappingGen.cpp | 130 +-
.../CoverageMapping/single-byte-counters.cpp | 53 +++
5 files changed, 97 insertions(+), 258 deletions(-)
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index dbc1ce9bf993cd..7d778ce58a1487 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -1039,15 +1039,11 @@ void CodeGenFunction::EmitWhileStmt(const WhileStmt &S,
SourceLocToDebugLoc(R.getEnd()),
checkIfLoopMustProgress(S.getCond(), hasEmptyLoopBody(S)));
- // When single byte coverage mode is enabled, add a counter to loop
condition.
- if (llvm::EnableSingleByteCoverage)
-incrementProfileCounter(S.getCond());
-
// As long as the condition is true, go to the loop body.
llvm::BasicBlock *LoopBody = createBasicBlock("while.body");
if (EmitBoolCondBranch) {
llvm::BasicBlock *ExitBlock = LoopExit.getBlock();
-if (ConditionScope.requiresCleanups())
+if (getIsCounterPair(&S).second || ConditionScope.requiresCleanups())
ExitBlock = createBasicBlock("while.exit");
llvm::MDNode *Weights =
createProfileWeightsForLoop(S.getCond(), getProfileCount(S.getBody()));
@@ -1058,6 +1054,7 @@ void CodeGenFunction::EmitWhileStmt(const WhileStmt &S,
if (ExitBlock != LoopExit.getBlock()) {
EmitBlock(ExitBlock);
+ incrementProfileCounter(true, &S);
EmitBranchThroughCleanup(LoopExit);
}
} else if (const Attr *A = Stmt::getLikelihoodAttr(S.getBody())) {
@@ -1075,11 +1072,7 @@ void CodeGenFunction::EmitWhileStmt(const WhileStmt &S,
{
RunCleanupsScope BodyScope(*this);
EmitBlock(LoopBody);
-// When single byte coverage mode is enabled, add a counter to the body.
-if (llvm::EnableSingleByteCoverage)
- incrementProfileCounter(S.getBody());
-else
- incrementProfileCounter(&S);
+incrementProfileCounter(false, &S);
EmitStmt(S.getBody());
}
@@ -1099,13 +1092,10 @@ void CodeGenFunction::EmitWhileStmt(const WhileStmt &S,
// The LoopHeader typically is just a branch if we skipped emitting
// a branch, try to erase it.
- if (!EmitBoolCondBranch)
+ if (!EmitBoolCondBranch) {
SimplifyForwardingBlocks(LoopHeader.getBlock());
-
- // When single byte coverage mode is enabled, add a counter to continuation
- // block.
- if (llvm::EnableSingleByteCoverage)
-incrementProfileCounter(&S);
+PGO.markStmtAsUsed(true, &S);
+ }
if (CGM.shouldEmitConvergenceTokens())
ConvergenceTokenStack.pop_back();
@@ -1124,10 +1114,7 @@ void CodeGenFunction::EmitDoStmt(const DoStmt &S,
// Emit the body of the loop.
llvm::BasicBlock *LoopBody = createBasicBlock("do.body");
- if (llvm::EnableSingleByteCoverage)
-EmitBlockWithFallThrough(LoopBody, S.getBody());
- else
-EmitBlockWithFallThrough(LoopBody, &S);
+ EmitBlockWithFallThrough(LoopBody, &S);
if (CGM.shouldEmitConvergenceTokens())
ConvergenceTokenStack.push_back(
@@ -1139,9 +1126,6 @@ void CodeGenFunction::EmitDoStmt(const DoStmt &S,
}
EmitBlock(LoopCond.getBlock());
- // When single byte coverage mode is enabled, add a counter to loop
condition.
- if (llvm::EnableSingleByteCoverage)
-incrementProfileCounter(S.getCond());
// C99 6.8.5.2: "The evaluation of the controlling expression takes place
// after each execution of the loop body."
@@ -1164,16 +1148,25 @@ void CodeGenFunction::EmitDoStmt(const DoStmt &S,
SourceLocToDebugLoc(R.getEnd()),
checkIfLoopMustProgress(S.getCond(), hasEmptyLoopBody(S)));
+ auto *LoopFalse =
+ (getIsCounterPair(&S).second ? createBasicBlock("do.loopfalse")
+ : LoopExit.getBlock());
+
// As long as the condition is true, iterate the loop.
if (EmitBoolCondBranch) {
uint64_t BackedgeCount = getProfileCount(S.getBody()) - ParentCount;
Builder.CreateCondBr(
-BoolCondVal, LoopBody, LoopExit.getBlock(),
+BoolCondVal, LoopBody, LoopFalse,
createProfileWeightsForLoop(S.getCond(), BackedgeCount));
}
LoopStack.pop();
+ if (LoopFalse != LoopExit.getBlock()) {
+EmitBlock(LoopFalse);
+incrementProfileCounter(true, &S, true);
+ }
+
// Emit the exit block.
EmitBlock(LoopExit.getBlock());
@@ -1182,11 +1175,6 @@ void CodeGenFunction::EmitDoStmt(const DoStmt &S,
if (!EmitBoolCondBranch)
SimplifyForwardingBlocks(LoopCond.getBlock());
[llvm-branch-commits] [clang] [llvm] [Coverage] Make additional counters available for BranchRegion. NFC. (PR #120930)
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/120930
>From 5e460594c8a2550c38c759b2e6f1c5dc4152f820 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Thu, 17 Oct 2024 22:15:12 +0900
Subject: [PATCH 01/10] [Coverage] Make additional counters available for
BranchRegion. NFC.
`getBranchCounterPair()` allocates an additional Counter to SkipPath
in `SingleByteCoverage`.
`IsCounterEqual()` calculates the comparison with rewinding counter
replacements.
`NumRegionCounters` is updated to take additional counters in account.
`incrementProfileCounter()` has a few additiona arguments.
- `UseSkipPath=true`, to specify setting counters for SkipPath. It
assumes `UseSkipPath=false` is used together.
- `UseBoth` may be specified for marking another path. It introduces
the same effect as issueing `markStmtAsUsed(!SkipPath, S)`.
`llvm-cov` discovers counters in `FalseCount` to allocate
`MaxCounterID` for empty profile data.
---
clang/lib/CodeGen/CodeGenFunction.h | 8 -
clang/lib/CodeGen/CodeGenPGO.cpp | 31 +--
clang/lib/CodeGen/CodeGenPGO.h| 1 +
clang/lib/CodeGen/CoverageMappingGen.cpp | 31 ++-
.../ProfileData/Coverage/CoverageMapping.cpp | 4 +++
5 files changed, 65 insertions(+), 10 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.h
b/clang/lib/CodeGen/CodeGenFunction.h
index 89ac3b342d0a7c..cb1192bf6e11fe 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -1629,11 +1629,17 @@ class CodeGenFunction : public CodeGenTypeCache {
/// Increment the profiler's counter for the given statement by \p StepV.
/// If \p StepV is null, the default increment is 1.
void incrementProfileCounter(const Stmt *S, llvm::Value *StepV = nullptr) {
+incrementProfileCounter(false, S, false, StepV);
+ }
+
+ void incrementProfileCounter(bool UseSkipPath, const Stmt *S,
+ bool UseBoth = false,
+ llvm::Value *StepV = nullptr) {
if (CGM.getCodeGenOpts().hasProfileClangInstr() &&
!CurFn->hasFnAttribute(llvm::Attribute::NoProfile) &&
!CurFn->hasFnAttribute(llvm::Attribute::SkipProfile)) {
auto AL = ApplyDebugLocation::CreateArtificial(*this);
- PGO.emitCounterSetOrIncrement(Builder, S, StepV);
+ PGO.emitCounterSetOrIncrement(Builder, S, UseSkipPath, UseBoth, StepV);
}
PGO.setCurrentStmt(S);
}
diff --git a/clang/lib/CodeGen/CodeGenPGO.cpp b/clang/lib/CodeGen/CodeGenPGO.cpp
index 069469e3de856b..aefd53e12088b4 100644
--- a/clang/lib/CodeGen/CodeGenPGO.cpp
+++ b/clang/lib/CodeGen/CodeGenPGO.cpp
@@ -1138,6 +1138,19 @@ void CodeGenPGO::emitCounterRegionMapping(const Decl *D)
{
if (CoverageMapping.empty())
return;
+ // Scan max(FalseCnt) and update NumRegionCounters.
+ unsigned MaxNumCounters = NumRegionCounters;
+ for (const auto [_, V] : *RegionCounterMap) {
+auto HasCounters = V.getIsCounterPair();
+assert((!HasCounters.first ||
+MaxNumCounters > (V.first & CounterPair::Mask)) &&
+ "TrueCnt should not be reassigned");
+if (HasCounters.second)
+ MaxNumCounters =
+ std::max(MaxNumCounters, (V.second & CounterPair::Mask) + 1);
+ }
+ NumRegionCounters = MaxNumCounters;
+
CGM.getCoverageMapping()->addFunctionMappingRecord(
FuncNameVar, FuncName, FunctionHash, CoverageMapping);
}
@@ -1193,11 +1206,25 @@ std::pair
CodeGenPGO::getIsCounterPair(const Stmt *S) const {
}
void CodeGenPGO::emitCounterSetOrIncrement(CGBuilderTy &Builder, const Stmt *S,
+ bool UseSkipPath, bool UseBoth,
llvm::Value *StepV) {
- if (!RegionCounterMap || !Builder.GetInsertBlock())
+ if (!RegionCounterMap)
return;
- unsigned Counter = (*RegionCounterMap)[S].first;
+ unsigned Counter;
+ auto &TheMap = (*RegionCounterMap)[S];
+ auto IsCounter = TheMap.getIsCounterPair();
+ if (!UseSkipPath) {
+assert(IsCounter.first);
+Counter = (TheMap.first & CounterPair::Mask);
+ } else {
+if (!IsCounter.second)
+ return;
+Counter = (TheMap.second & CounterPair::Mask);
+ }
+
+ if (!Builder.GetInsertBlock())
+return;
// Make sure that pointer to global is passed in with zero addrspace
// This is relevant during GPU profiling
diff --git a/clang/lib/CodeGen/CodeGenPGO.h b/clang/lib/CodeGen/CodeGenPGO.h
index 83f35785e5327d..8b769dd88d7f1e 100644
--- a/clang/lib/CodeGen/CodeGenPGO.h
+++ b/clang/lib/CodeGen/CodeGenPGO.h
@@ -112,6 +112,7 @@ class CodeGenPGO {
public:
std::pair getIsCounterPair(const Stmt *S) const;
void emitCounterSetOrIncrement(CGBuilderTy &Builder, const Stmt *S,
+ bool UseFalsePath, bool UseBoth,
llvm::Value *StepV);
void emitMCDCTestVectorBitmapUpdate(CGBuilderTy &Builder, const Expr *S,
[llvm-branch-commits] [clang] [llvm] [Coverage][Single] Enable Branch coverage for IfStmt (PR #113111)
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113111
>From 3ea6383e2142889550f37389dfaaee81e5ae7d9c Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Sun, 20 Oct 2024 15:15:03 +0900
Subject: [PATCH 1/4] [Coverage][Single] Enable Branch coverage for IfStmt
---
clang/lib/CodeGen/CGStmt.cpp | 31 +++-
clang/lib/CodeGen/CodeGenPGO.cpp | 12 ---
clang/lib/CodeGen/CoverageMappingGen.cpp | 21 +++
.../CoverageMapping/single-byte-counters.cpp | 36 ++-
4 files changed, 38 insertions(+), 62 deletions(-)
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index dbc1ce9bf993cd..c511e5f4f4213a 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -840,8 +840,7 @@ void CodeGenFunction::EmitIfStmt(const IfStmt &S) {
// If the skipped block has no labels in it, just emit the executed block.
// This avoids emitting dead code and simplifies the CFG substantially.
if (S.isConstexpr() || !ContainsLabel(Skipped)) {
- if (CondConstant)
-incrementProfileCounter(&S);
+ incrementProfileCounter(!CondConstant, &S, true);
if (Executed) {
RunCleanupsScope ExecutedScope(*this);
EmitStmt(Executed);
@@ -851,14 +850,14 @@ void CodeGenFunction::EmitIfStmt(const IfStmt &S) {
}
}
+ auto HasSkip = getIsCounterPair(&S);
+
// Otherwise, the condition did not fold, or we couldn't elide it. Just emit
// the conditional branch.
llvm::BasicBlock *ThenBlock = createBasicBlock("if.then");
llvm::BasicBlock *ContBlock = createBasicBlock("if.end");
- llvm::BasicBlock *ElseBlock = ContBlock;
- if (Else)
-ElseBlock = createBasicBlock("if.else");
-
+ llvm::BasicBlock *ElseBlock =
+ (Else || HasSkip.second ? createBasicBlock("if.else") : ContBlock);
// Prefer the PGO based weights over the likelihood attribute.
// When the build isn't optimized the metadata isn't used, so don't generate
// it.
@@ -891,10 +890,7 @@ void CodeGenFunction::EmitIfStmt(const IfStmt &S) {
// Emit the 'then' code.
EmitBlock(ThenBlock);
- if (llvm::EnableSingleByteCoverage)
-incrementProfileCounter(S.getThen());
- else
-incrementProfileCounter(&S);
+ incrementProfileCounter(false, &S);
{
RunCleanupsScope ThenScope(*this);
EmitStmt(S.getThen());
@@ -908,9 +904,9 @@ void CodeGenFunction::EmitIfStmt(const IfStmt &S) {
auto NL = ApplyDebugLocation::CreateEmpty(*this);
EmitBlock(ElseBlock);
}
-// When single byte coverage mode is enabled, add a counter to else block.
-if (llvm::EnableSingleByteCoverage)
- incrementProfileCounter(Else);
+// Add a counter to else block unless it has CounterExpr.
+if (HasSkip.second)
+ incrementProfileCounter(true, &S);
{
RunCleanupsScope ElseScope(*this);
EmitStmt(Else);
@@ -920,15 +916,14 @@ void CodeGenFunction::EmitIfStmt(const IfStmt &S) {
auto NL = ApplyDebugLocation::CreateEmpty(*this);
EmitBranch(ContBlock);
}
+ } else if (HasSkip.second) {
+EmitBlock(ElseBlock);
+incrementProfileCounter(true, &S);
+EmitBranch(ContBlock);
}
// Emit the continuation block for code after the if.
EmitBlock(ContBlock, true);
-
- // When single byte coverage mode is enabled, add a counter to continuation
- // block.
- if (llvm::EnableSingleByteCoverage)
-incrementProfileCounter(&S);
}
bool CodeGenFunction::checkIfLoopMustProgress(const Expr
*ControllingExpression,
diff --git a/clang/lib/CodeGen/CodeGenPGO.cpp b/clang/lib/CodeGen/CodeGenPGO.cpp
index 0f2090da47a374..f6b9b5c82952c4 100644
--- a/clang/lib/CodeGen/CodeGenPGO.cpp
+++ b/clang/lib/CodeGen/CodeGenPGO.cpp
@@ -366,18 +366,6 @@ struct MapRegionCounters : public
RecursiveASTVisitor {
if (Hash.getHashVersion() == PGO_HASH_V1)
return Base::TraverseIfStmt(If);
-// When single byte coverage mode is enabled, add a counter to then and
-// else.
-bool NoSingleByteCoverage = !llvm::EnableSingleByteCoverage;
-for (Stmt *CS : If->children()) {
- if (!CS || NoSingleByteCoverage)
-continue;
- if (CS == If->getThen())
-CounterMap[If->getThen()] = NextCounter++;
- else if (CS == If->getElse())
-CounterMap[If->getElse()] = NextCounter++;
-}
-
// Otherwise, keep track of which branch we're in while traversing.
VisitStmt(If);
diff --git a/clang/lib/CodeGen/CoverageMappingGen.cpp
b/clang/lib/CodeGen/CoverageMappingGen.cpp
index a331d5bc68286b..6c6aecb9994c6b 100644
--- a/clang/lib/CodeGen/CoverageMappingGen.cpp
+++ b/clang/lib/CodeGen/CoverageMappingGen.cpp
@@ -2050,12 +2050,7 @@ struct CounterCoverageMappingBuilder
extendRegion(S->getCond());
Counter ParentCount = getRegion().getCounter();
-auto [ThenCount, ElseCount] =
-(llvm::EnableSingleByteCoverage
- ? std::make_pair(getRegionCounter(S->getThen())
