[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
https://github.com/Xazax-hun approved this pull request. https://github.com/llvm/llvm-project/pull/120436 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From dac7f1e85ec5391d0efe94cbca2161644263660b Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
commit-id:f9d761c5
---
llvm/lib/Target/X86/X86ISelLowering.cpp| 4 ++
llvm/test/CodeGen/X86/atomic-load-store.ll | 47 ++
2 files changed, 51 insertions(+)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 35c0974733aba4..f9d0a49b328247 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2595,6 +2595,10 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
ISD::SCALAR_TO_VECTOR,
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 8cb2e79d66f673..39c54c3df15c7a 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -108,3 +108,50 @@ define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr
%x) {
%ret = load atomic <1 x ptr addrspace(270)>, ptr %x acquire, align 4
ret <1 x ptr addrspace(270)> %ret
}
+
+define <1 x half> @atomic_vec1_half(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_half:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_half:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x half>, ptr %x acquire, align 4
+ ret <1 x half> %ret
+}
+
+define <1 x float> @atomic_vec1_float(ptr %x) {
+; CHECK-LABEL: atomic_vec1_float:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x float>, ptr %x acquire, align 4
+ ret <1 x float> %ret
+}
+
+define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_bfloat:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_bfloat:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
+ ret <1 x bfloat> %ret
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From dac7f1e85ec5391d0efe94cbca2161644263660b Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
commit-id:f9d761c5
---
llvm/lib/Target/X86/X86ISelLowering.cpp| 4 ++
llvm/test/CodeGen/X86/atomic-load-store.ll | 47 ++
2 files changed, 51 insertions(+)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 35c0974733aba4..f9d0a49b328247 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2595,6 +2595,10 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
ISD::SCALAR_TO_VECTOR,
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 8cb2e79d66f673..39c54c3df15c7a 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -108,3 +108,50 @@ define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr
%x) {
%ret = load atomic <1 x ptr addrspace(270)>, ptr %x acquire, align 4
ret <1 x ptr addrspace(270)> %ret
}
+
+define <1 x half> @atomic_vec1_half(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_half:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_half:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x half>, ptr %x acquire, align 4
+ ret <1 x half> %ret
+}
+
+define <1 x float> @atomic_vec1_float(ptr %x) {
+; CHECK-LABEL: atomic_vec1_float:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x float>, ptr %x acquire, align 4
+ ret <1 x float> %ret
+}
+
+define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_bfloat:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_bfloat:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
+ ret <1 x bfloat> %ret
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 05a76cfe898c76a306694d45a2bcbf9f722a15a8 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 238 +
1 file changed, 238 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 39c54c3df15c7a..90eaed8150a559 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -109,6 +109,34 @@ define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr
%x) {
ret <1 x ptr addrspace(270)> %ret
}
+define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_ptr:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_ptr:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x ptr>, ptr %x acquire, align 4
+ ret <1 x ptr> %ret
+}
+
define <1 x half> @atomic_vec1_half(ptr %x) {
; CHECK3-LABEL: atomic_vec1_half:
; CHECK3: ## %bb.0:
@@ -155,3 +183,213 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
%ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
ret <1 x bfloat> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_double:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_i32:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec4_float:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:subq $24, %rsp
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $16, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movaps (%rsp), %xm
[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 5a3a12dc54cb65baf011b805d67f801a35eed9f7 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic <1 x T>` is not valid. This change legalizes
vector types of atomic load via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.
commit-id:5c36cc8c
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 15
llvm/test/CodeGen/X86/atomic-load-store.ll| 84 ++-
3 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 571a710cc92a34..b81c9f87cb27d7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -861,6 +861,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ScalarizeVecRes_ExpOp(SDNode *N);
SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
+ SDValue ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N);
SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
SDValue ScalarizeVecRes_VSELECT(SDNode *N);
SDValue ScalarizeVecRes_SELECT(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 107454a92e356c..c85e4ba2cfa5a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -60,6 +60,9 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N,
unsigned ResNo) {
case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
case ISD::FPOWI: R = ScalarizeVecRes_ExpOp(N); break;
case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
+ case ISD::ATOMIC_LOAD:
+R = ScalarizeVecRes_ATOMIC_LOAD(cast(N));
+break;
case ISD::LOAD: R =
ScalarizeVecRes_LOAD(cast(N));break;
case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
@@ -451,6 +454,18 @@ SDValue
DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
return Op;
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
+ SDValue Result = DAG.getAtomic(
+ ISD::ATOMIC_LOAD, SDLoc(N), N->getMemoryVT().getVectorElementType(),
+ N->getValueType(0).getVectorElementType(), N->getChain(),
N->getBasePtr(),
+ N->getMemOperand());
+
+ // Legalize the chain result - switch anything that used the old chain to
+ // use the new one.
+ ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
+ return Result;
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(N->isUnindexed() && "Indexed vector load?");
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 5bce4401f7bdb0..8cb2e79d66f673 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s --check-prefixes=CHECK,CHECK3
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s --check-prefixes=CHECK,CHECK0
define void @test1(ptr %ptr, i32 %val1) {
; CHECK-LABEL: test1:
@@ -28,3 +28,83 @@ define i32 @test3(ptr %ptr) {
%val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
+
+define <1 x i32> @atomic_vec1_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movl (%rdi), %eax
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x i32>, ptr %x acquire, align 4
+ ret <1 x i32> %ret
+}
+
+define <1 x i8> @atomic_vec1_i8(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i8:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzbl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i8:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movb (%rdi), %al
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i8>, ptr %x acquire, align 4
+ ret <1 x i8> %ret
+}
+
+define <1 x i16> @atomic_vec1_i16(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i16:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i16:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %ax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i16>, ptr %x acquire, align 4
+ ret <1 x i16> %ret
+}
+
+define <1 x i
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 05a76cfe898c76a306694d45a2bcbf9f722a15a8 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 238 +
1 file changed, 238 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 39c54c3df15c7a..90eaed8150a559 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -109,6 +109,34 @@ define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr
%x) {
ret <1 x ptr addrspace(270)> %ret
}
+define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_ptr:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_ptr:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x ptr>, ptr %x acquire, align 4
+ ret <1 x ptr> %ret
+}
+
define <1 x half> @atomic_vec1_half(ptr %x) {
; CHECK3-LABEL: atomic_vec1_half:
; CHECK3: ## %bb.0:
@@ -155,3 +183,213 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
%ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
ret <1 x bfloat> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_double:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_i32:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec4_float:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:subq $24, %rsp
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $16, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movaps (%rsp), %xm
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 05a76cfe898c76a306694d45a2bcbf9f722a15a8 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 238 +
1 file changed, 238 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 39c54c3df15c7a..90eaed8150a559 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -109,6 +109,34 @@ define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr
%x) {
ret <1 x ptr addrspace(270)> %ret
}
+define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_ptr:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_ptr:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x ptr>, ptr %x acquire, align 4
+ ret <1 x ptr> %ret
+}
+
define <1 x half> @atomic_vec1_half(ptr %x) {
; CHECK3-LABEL: atomic_vec1_half:
; CHECK3: ## %bb.0:
@@ -155,3 +183,213 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
%ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
ret <1 x bfloat> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_double:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_i32:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec4_float:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:subq $24, %rsp
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $16, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movaps (%rsp), %xm
[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From dac7f1e85ec5391d0efe94cbca2161644263660b Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
commit-id:f9d761c5
---
llvm/lib/Target/X86/X86ISelLowering.cpp| 4 ++
llvm/test/CodeGen/X86/atomic-load-store.ll | 47 ++
2 files changed, 51 insertions(+)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 35c0974733aba4..f9d0a49b328247 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2595,6 +2595,10 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
ISD::SCALAR_TO_VECTOR,
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 8cb2e79d66f673..39c54c3df15c7a 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -108,3 +108,50 @@ define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr
%x) {
%ret = load atomic <1 x ptr addrspace(270)>, ptr %x acquire, align 4
ret <1 x ptr addrspace(270)> %ret
}
+
+define <1 x half> @atomic_vec1_half(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_half:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_half:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x half>, ptr %x acquire, align 4
+ ret <1 x half> %ret
+}
+
+define <1 x float> @atomic_vec1_float(ptr %x) {
+; CHECK-LABEL: atomic_vec1_float:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x float>, ptr %x acquire, align 4
+ ret <1 x float> %ret
+}
+
+define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_bfloat:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_bfloat:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
+ ret <1 x bfloat> %ret
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 5a3a12dc54cb65baf011b805d67f801a35eed9f7 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic <1 x T>` is not valid. This change legalizes
vector types of atomic load via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.
commit-id:5c36cc8c
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 15
llvm/test/CodeGen/X86/atomic-load-store.ll| 84 ++-
3 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 571a710cc92a34..b81c9f87cb27d7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -861,6 +861,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ScalarizeVecRes_ExpOp(SDNode *N);
SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
+ SDValue ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N);
SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
SDValue ScalarizeVecRes_VSELECT(SDNode *N);
SDValue ScalarizeVecRes_SELECT(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 107454a92e356c..c85e4ba2cfa5a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -60,6 +60,9 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N,
unsigned ResNo) {
case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
case ISD::FPOWI: R = ScalarizeVecRes_ExpOp(N); break;
case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
+ case ISD::ATOMIC_LOAD:
+R = ScalarizeVecRes_ATOMIC_LOAD(cast(N));
+break;
case ISD::LOAD: R =
ScalarizeVecRes_LOAD(cast(N));break;
case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
@@ -451,6 +454,18 @@ SDValue
DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
return Op;
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
+ SDValue Result = DAG.getAtomic(
+ ISD::ATOMIC_LOAD, SDLoc(N), N->getMemoryVT().getVectorElementType(),
+ N->getValueType(0).getVectorElementType(), N->getChain(),
N->getBasePtr(),
+ N->getMemOperand());
+
+ // Legalize the chain result - switch anything that used the old chain to
+ // use the new one.
+ ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
+ return Result;
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(N->isUnindexed() && "Indexed vector load?");
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 5bce4401f7bdb0..8cb2e79d66f673 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s --check-prefixes=CHECK,CHECK3
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s --check-prefixes=CHECK,CHECK0
define void @test1(ptr %ptr, i32 %val1) {
; CHECK-LABEL: test1:
@@ -28,3 +28,83 @@ define i32 @test3(ptr %ptr) {
%val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
+
+define <1 x i32> @atomic_vec1_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movl (%rdi), %eax
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x i32>, ptr %x acquire, align 4
+ ret <1 x i32> %ret
+}
+
+define <1 x i8> @atomic_vec1_i8(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i8:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzbl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i8:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movb (%rdi), %al
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i8>, ptr %x acquire, align 4
+ ret <1 x i8> %ret
+}
+
+define <1 x i16> @atomic_vec1_i16(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i16:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i16:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %ax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i16>, ptr %x acquire, align 4
+ ret <1 x i16> %ret
+}
+
+define <1 x i
[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 5a3a12dc54cb65baf011b805d67f801a35eed9f7 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic <1 x T>` is not valid. This change legalizes
vector types of atomic load via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.
commit-id:5c36cc8c
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 15
llvm/test/CodeGen/X86/atomic-load-store.ll| 84 ++-
3 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 571a710cc92a34..b81c9f87cb27d7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -861,6 +861,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ScalarizeVecRes_ExpOp(SDNode *N);
SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
+ SDValue ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N);
SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
SDValue ScalarizeVecRes_VSELECT(SDNode *N);
SDValue ScalarizeVecRes_SELECT(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 107454a92e356c..c85e4ba2cfa5a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -60,6 +60,9 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N,
unsigned ResNo) {
case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
case ISD::FPOWI: R = ScalarizeVecRes_ExpOp(N); break;
case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
+ case ISD::ATOMIC_LOAD:
+R = ScalarizeVecRes_ATOMIC_LOAD(cast(N));
+break;
case ISD::LOAD: R =
ScalarizeVecRes_LOAD(cast(N));break;
case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
@@ -451,6 +454,18 @@ SDValue
DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
return Op;
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
+ SDValue Result = DAG.getAtomic(
+ ISD::ATOMIC_LOAD, SDLoc(N), N->getMemoryVT().getVectorElementType(),
+ N->getValueType(0).getVectorElementType(), N->getChain(),
N->getBasePtr(),
+ N->getMemOperand());
+
+ // Legalize the chain result - switch anything that used the old chain to
+ // use the new one.
+ ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
+ return Result;
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(N->isUnindexed() && "Indexed vector load?");
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 5bce4401f7bdb0..8cb2e79d66f673 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s --check-prefixes=CHECK,CHECK3
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s --check-prefixes=CHECK,CHECK0
define void @test1(ptr %ptr, i32 %val1) {
; CHECK-LABEL: test1:
@@ -28,3 +28,83 @@ define i32 @test3(ptr %ptr) {
%val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
+
+define <1 x i32> @atomic_vec1_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movl (%rdi), %eax
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x i32>, ptr %x acquire, align 4
+ ret <1 x i32> %ret
+}
+
+define <1 x i8> @atomic_vec1_i8(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i8:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzbl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i8:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movb (%rdi), %al
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i8>, ptr %x acquire, align 4
+ ret <1 x i8> %ret
+}
+
+define <1 x i16> @atomic_vec1_i16(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i16:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i16:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %ax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i16>, ptr %x acquire, align 4
+ ret <1 x i16> %ret
+}
+
+define <1 x i
[llvm-branch-commits] [mlir] [mlir][Properties] Shorten "Property" to "Prop" in most places (PR #120368)
https://github.com/Mogball approved this pull request. Makes sense https://github.com/llvm/llvm-project/pull/120368 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 18c4109 - Revert "[InstCombine] Infer nuw for gep inbounds from base of object (#119225)"
Author: Alexander Kornienko Date: 2024-12-18T18:55:04+01:00 New Revision: 18c410940d8c0c506f759dec6d28dfe40d021a01 URL: https://github.com/llvm/llvm-project/commit/18c410940d8c0c506f759dec6d28dfe40d021a01 DIFF: https://github.com/llvm/llvm-project/commit/18c410940d8c0c506f759dec6d28dfe40d021a01.diff LOG: Revert "[InstCombine] Infer nuw for gep inbounds from base of object (#119225)" This reverts commit e21ab4d16b555c28ded307571d138f594f33e325. Added: Modified: clang/test/CodeGen/attr-counted-by.c clang/test/CodeGen/union-tbaa1.c llvm/lib/Transforms/InstCombine/InstructionCombining.cpp llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll llvm/test/Transforms/InstCombine/cast_phi.ll llvm/test/Transforms/InstCombine/load-cmp.ll llvm/test/Transforms/InstCombine/memcpy-addrspace.ll llvm/test/Transforms/InstCombine/memcpy-from-global.ll llvm/test/Transforms/InstCombine/stpcpy-1.ll llvm/test/Transforms/InstCombine/stpcpy_chk-1.ll llvm/test/Transforms/InstCombine/strlen-1.ll llvm/test/Transforms/InstCombine/strlen-4.ll llvm/test/Transforms/InstCombine/strncat-2.ll llvm/test/Transforms/InstCombine/strnlen-3.ll llvm/test/Transforms/InstCombine/strnlen-4.ll llvm/test/Transforms/InstCombine/strnlen-5.ll llvm/test/Transforms/InstCombine/sub-gep.ll llvm/test/Transforms/InstCombine/wcslen-1.ll llvm/test/Transforms/InstCombine/wcslen-3.ll llvm/test/Transforms/InstCombine/wcslen-5.ll llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll llvm/test/Transforms/LoopVectorize/X86/small-size.ll llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll llvm/test/Transforms/LoopVectorize/non-const-n.ll llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll Removed: diff --git a/clang/test/CodeGen/attr-counted-by.c b/clang/test/CodeGen/attr-counted-by.c index be4c7f07e92150..6b3cad5708835b 100644 --- a/clang/test/CodeGen/attr-counted-by.c +++ b/clang/test/CodeGen/attr-counted-by.c @@ -1043,7 +1043,7 @@ int test12_a, test12_b; // NO-SANITIZE-WITH-ATTR-NEXT:call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR11:[0-9]+]] // NO-SANITIZE-WITH-ATTR-NEXT:call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] // NO-SANITIZE-WITH-ATTR-NEXT:[[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITH-ATTR-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds nuw [6 x i32], ptr [[BAZ]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITH-ATTR-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[IDXPROM]] // NO-SANITIZE-WITH-ATTR-NEXT:[[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] // NO-SANITIZE-WITH-ATTR-NEXT:store i32 [[TMP0]], ptr @test12_b, align 4, !tbaa [[TBAA2]] // NO-SANITIZE-WITH-ATTR-NEXT:[[TMP1:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @test12_foo, i64 4), align 4, !tbaa [[TBAA2]] @@ -1085,7 +1085,7 @@ int test12_a, test12_b; // NO-SANITIZE-WITHOUT-ATTR-NEXT:call void @llvm.lifetime.start.p0(i64 24, ptr nonnull [[BAZ]]) #[[ATTR9:[0-9]+]] // NO-SANITIZE-WITHOUT-ATTR-NEXT:call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) [[BAZ]], ptr noundef nonnull align 4 dereferenceable(24) @test12_bar, i64 24, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]] // NO-SANITIZE-WITHOUT-ATTR-NEXT:[[IDXPROM:%.*]] = sext i32 [[INDEX]] to i64 -// NO-SANITIZE-WITHOUT-ATTR-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds nuw [6 x i32], ptr [[BAZ]], i64 0, i64 [[IDXPROM]] +// NO-SANITIZE-WITHOUT-ATTR-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds [6 x i32], ptr [[BAZ]], i64 0, i64 [[IDXPROM]] // NO-SANITIZE-WITHOUT-ATTR-NEXT:[[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] // NO-SANITIZE-WITHOUT-ATTR-NEXT:store i32 [[TMP0]], ptr @test12_b, align 4, !tbaa [[TBAA2]] // NO-SANITIZE-WITHOUT-ATTR-NEXT:[[TMP1:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @test12_foo, i64 4), align 4, !tbaa [[TBAA2]] diff --git a/clang/test/CodeGen/union-tbaa1.c b/clang/test/CodeGen/union-tbaa1.c index 7d44c9a3fbe6bb..0f7a67cb7eccd1 100644 --- a/clang/test/CodeGen/union-tbaa1.c +++ b/clang/test/CodeGen/union-tbaa1.c @@ -16,17 +16,17 @@ void bar(vect32 p[][2]); // CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARR]], i32 [[TMP0]] // CHECK-NEXT:[[TMP1:%.*]] = load i32, ptr [[ARRAYI
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate loc::ConcreteInt to use APSIntPtr (3/4) (PR #120437)
https://github.com/Xazax-hun approved this pull request. https://github.com/llvm/llvm-project/pull/120437 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
@@ -298,9 +299,12 @@ class SymbolVal : public NonLoc {
/// Value representing integer constant.
class ConcreteInt : public NonLoc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : NonLoc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : NonLoc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
steakhal wrote:
I see now. That was the source of the miscommunication here.
https://github.com/llvm/llvm-project/pull/120436
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][GPU] Add `gpu.assert` op (PR #120431)
https://github.com/matthias-springer edited https://github.com/llvm/llvm-project/pull/120431 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
https://github.com/steakhal ready_for_review https://github.com/llvm/llvm-project/pull/120436 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][GPU] Add `gpu.assert` op (PR #120431)
joker-eph wrote: Can we just use cf.assert ? https://github.com/llvm/llvm-project/pull/120431 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SLP] Check if instructions exist after vectorization (#120434) (PR #120505)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: DianQK (DianQK)
Changes
Fixes #120433.
(cherry picked from commit e7a4d78ad328d02bf515b2fa4af8b2c188a6a636)
---
Full diff: https://github.com/llvm/llvm-project/pull/120505.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (+4-1)
- (added) llvm/test/Transforms/SLPVectorizer/slp-deleted-inst.ll (+51)
``diff
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 746ba51a981fe0..fd08d5d9d7556a 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -18596,8 +18596,11 @@ bool
SLPVectorizerPass::vectorizeCmpInsts(iterator_range CmpInsts,
if (R.isDeleted(I))
continue;
for (Value *Op : I->operands())
- if (auto *RootOp = dyn_cast(Op))
+ if (auto *RootOp = dyn_cast(Op)) {
Changed |= vectorizeRootInstruction(nullptr, RootOp, BB, R, TTI);
+if (R.isDeleted(I))
+ break;
+ }
}
// Try to vectorize operands as vector bundles.
for (CmpInst *I : CmpInsts) {
diff --git a/llvm/test/Transforms/SLPVectorizer/slp-deleted-inst.ll
b/llvm/test/Transforms/SLPVectorizer/slp-deleted-inst.ll
new file mode 100644
index 00..d3995f1bb7f85d
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/slp-deleted-inst.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S -passes=slp-vectorizer < %s | FileCheck %s
+
+define void @foo() {
+; CHECK-LABEL: define void @foo() {
+; CHECK-NEXT: [[BB:.*]]:
+; CHECK-NEXT:br label %[[BB1:.*]]
+; CHECK: [[BB1]]:
+; CHECK-NEXT:[[TMP0:%.*]] = phi <2 x i32> [ [[TMP11:%.*]], %[[BB3:.*]] ],
[ zeroinitializer, %[[BB]] ]
+; CHECK-NEXT:br label %[[BB3]]
+; CHECK: [[BB3]]:
+; CHECK-NEXT:[[TMP1:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i1>
+; CHECK-NEXT:[[TMP2:%.*]] = mul <2 x i1> [[TMP1]], zeroinitializer
+; CHECK-NEXT:[[TMP3:%.*]] = or <2 x i1> zeroinitializer, [[TMP2]]
+; CHECK-NEXT:[[TMP4:%.*]] = and <2 x i1> [[TMP3]], zeroinitializer
+; CHECK-NEXT:[[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i32 0
+; CHECK-NEXT:[[TMP6:%.*]] = zext i1 [[TMP5]] to i32
+; CHECK-NEXT:[[TMP7:%.*]] = extractelement <2 x i1> [[TMP4]], i32 1
+; CHECK-NEXT:[[TMP8:%.*]] = zext i1 [[TMP7]] to i32
+; CHECK-NEXT:[[I22:%.*]] = or i32 [[TMP6]], [[TMP8]]
+; CHECK-NEXT:[[TMP9:%.*]] = insertelement <2 x i32> ,
i32 [[I22]], i32 0
+; CHECK-NEXT:[[TMP10:%.*]] = icmp ult <2 x i32> [[TMP9]], zeroinitializer
+; CHECK-NEXT:[[TMP11]] = select <2 x i1> [[TMP10]], <2 x i32>
zeroinitializer, <2 x i32> zeroinitializer
+; CHECK-NEXT:br label %[[BB1]]
+;
+bb:
+ br label %bb1
+
+bb1: ; preds = %bb3, %bb
+ %i = phi i32 [ %i26, %bb3 ], [ 0, %bb ]
+ %i2 = phi i32 [ %i24, %bb3 ], [ 0, %bb ]
+ br label %bb3
+
+bb3: ; preds = %bb1
+ %i4 = zext i32 %i2 to i64
+ %i5 = mul i64 %i4, 0
+ %i10 = or i64 0, %i5
+ %i11 = trunc i64 %i10 to i32
+ %i12 = and i32 %i11, 0
+ %i13 = zext i32 %i to i64
+ %i14 = mul i64 %i13, 0
+ %i19 = or i64 0, %i14
+ %i20 = trunc i64 %i19 to i32
+ %i21 = and i32 %i20, 0
+ %i22 = or i32 %i12, %i21
+ %i23 = icmp ult i32 %i22, 0
+ %i24 = select i1 %i23, i32 0, i32 0
+ %i25 = icmp ult i32 0, 0
+ %i26 = select i1 %i25, i32 0, i32 0
+ br label %bb1
+}
``
https://github.com/llvm/llvm-project/pull/120505
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SLP] Check if instructions exist after vectorization (#120434) (PR #120505)
https://github.com/alexey-bataev approved this pull request. https://github.com/llvm/llvm-project/pull/120505 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][BoundsChecking] Switch HandlerBuilder to CRTP (PR #120506)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: Vitaly Buka (vitalybuka)
Changes
So far the only implementation is TrapHandlerBuilder.
---
Full diff: https://github.com/llvm/llvm-project/pull/120506.diff
1 Files Affected:
- (modified) llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp (+44-23)
``diff
diff --git a/llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
b/llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
index a985ab07e12eeb..56a9dd40c500f1 100644
--- a/llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
+++ b/llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
@@ -105,11 +105,11 @@ static Value *getBoundsCheckCond(Value *Ptr, Value
*InstVal,
return Or;
}
-class HandlerBuilder {
- BasicBlock *TrapBB = nullptr;
+template class HandlerBuilder {
+ BasicBlock *ReuseTrapBB = nullptr;
public:
- BasicBlock *build(BuilderTy &IRB) {
+ BasicBlock *build(BuilderTy &IRB, BasicBlock *Cont) {
Function *Fn = IRB.GetInsertBlock()->getParent();
auto DebugLoc = IRB.getCurrentDebugLocation();
IRBuilder<>::InsertPointGuard Guard(IRB);
@@ -117,31 +117,45 @@ class HandlerBuilder {
// Create a trapping basic block on demand using a callback. Depending on
// flags, this will either create a single block for the entire function or
// will create a fresh block every time it is called.
-if (TrapBB && SingleTrapBB && !DebugTrapBB)
- return TrapBB;
+if (ReuseTrapBB)
+ return ReuseTrapBB;
-TrapBB = BasicBlock::Create(Fn->getContext(), "trap", Fn);
+BasicBlock *TrapBB = BasicBlock::Create(Fn->getContext(), "trap", Fn);
IRB.SetInsertPoint(TrapBB);
-Intrinsic::ID IntrID = DebugTrapBB ? Intrinsic::ubsantrap :
Intrinsic::trap;
+CallInst *TrapCall = T::CallHandler(IRB);
-CallInst *TrapCall;
-if (DebugTrapBB) {
- TrapCall = IRB.CreateIntrinsic(
- IntrID, {}, ConstantInt::get(IRB.getInt8Ty(), Fn->size()));
+TrapCall->setDoesNotThrow();
+TrapCall->setDebugLoc(DebugLoc);
+if (T::MayReturn) {
+ IRB.CreateBr(Cont);
} else {
- TrapCall = IRB.CreateIntrinsic(IntrID, {}, {});
+ TrapCall->setDoesNotReturn();
+ IRB.CreateUnreachable();
}
-TrapCall->setDoesNotReturn();
-TrapCall->setDoesNotThrow();
-TrapCall->setDebugLoc(DebugLoc);
-IRB.CreateUnreachable();
+if (T::CanReuseTrapBB && SingleTrapBB && !DebugTrapBB)
+ ReuseTrapBB = TrapBB;
return TrapBB;
}
};
+class TrapHandlerBuilder : public HandlerBuilder {
+public:
+ static constexpr bool MayReturn = false;
+ static constexpr bool CanReuseTrapBB = true;
+
+ static CallInst *CallHandler(BuilderTy &IRB) {
+if (!DebugTrapBB)
+ return IRB.CreateIntrinsic(Intrinsic::trap, {}, {});
+return IRB.CreateIntrinsic(
+Intrinsic::ubsantrap, {},
+ConstantInt::get(IRB.getInt8Ty(),
+ IRB.GetInsertBlock()->getParent()->size()));
+ }
+};
+
/// Adds run-time bounds checks to memory accessing instructions.
///
/// \p Or is the condition that should guard the trap.
@@ -164,7 +178,7 @@ static void insertBoundsCheck(Value *Or, BuilderTy &IRB,
HandlerBuilderTy &HB) {
BasicBlock *Cont = OldBB->splitBasicBlock(SplitI);
OldBB->getTerminator()->eraseFromParent();
- BasicBlock *TrapBB = HB.build(IRB);
+ BasicBlock *TrapBB = HB.build(IRB, Cont);
if (C) {
// If we have a constant zero, unconditionally branch.
@@ -180,8 +194,8 @@ static void insertBoundsCheck(Value *Or, BuilderTy &IRB,
HandlerBuilderTy &HB) {
template
bool insertBoundsChecks(
-const ArrayRef> &TrapInfo,
-HandlerBuilderTy &HB) {
+const ArrayRef> &TrapInfo) {
+ HandlerBuilderTy HB;
for (const auto &Entry : TrapInfo) {
Instruction *Inst = Entry.first;
const DataLayout &DL = Inst->getParent()->getDataLayout();
@@ -193,7 +207,8 @@ bool insertBoundsChecks(
}
static bool addBoundsChecking(Function &F, TargetLibraryInfo &TLI,
- ScalarEvolution &SE) {
+ ScalarEvolution &SE,
+ BoundsCheckingPass::ReportingMode Mode) {
if (F.hasFnAttribute(Attribute::NoSanitizeBounds))
return false;
@@ -231,15 +246,21 @@ static bool addBoundsChecking(Function &F,
TargetLibraryInfo &TLI,
TrapInfo.push_back(std::make_pair(&I, Or));
}
- HandlerBuilder HB;
- return insertBoundsChecks(TrapInfo, HB);
+ switch (Mode) {
+ case BoundsCheckingPass::ReportingMode::Trap:
+ case BoundsCheckingPass::ReportingMode::MinRuntimeAbort:
+ case BoundsCheckingPass::ReportingMode::MinRuntime:
+ case BoundsCheckingPass::ReportingMode::FullRuntime:
+ case BoundsCheckingPass::ReportingMode::FullRuntimeAbort:
+return insertBoundsChecks(TrapInfo);
+ }
}
PreservedAnalyses BoundsCheckingPass::run(Function &F, FunctionAnalysisManager
&AM) {
auto &TLI = AM.getResult(F);
auto &SE = AM.getResult(F);
- if (!addBoundsChecking
[llvm-branch-commits] [NFC][BoundsChecking] Switch HandlerBuilder to CRTP (PR #120506)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/120506 So far the only implementation is TrapHandlerBuilder. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][BoundsChecking] Prepare code for CRTP for ReportingMode (PR #119983)
https://github.com/vitalybuka edited https://github.com/llvm/llvm-project/pull/119983 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SLP] Check if instructions exist after vectorization (#120434) (PR #120505)
https://github.com/DianQK milestoned https://github.com/llvm/llvm-project/pull/120505 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
@@ -127,6 +127,34 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
ret <1 x bfloat> %ret
}
+define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_ptr:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_ptr:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x ptr>, ptr %x acquire, align 4
arsenm wrote:
Should test the naturally aligned case, this under-aligned one is a separate
test
https://github.com/llvm/llvm-project/pull/120387
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate loc::ConcreteInt to use APSIntPtr (3/4) (PR #120437)
@@ -514,9 +514,12 @@ class MemRegionVal : public Loc {
class ConcreteInt : public Loc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : Loc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : Loc(ConcreteIntKind, V.get()) {}
steakhal wrote:
I guess this one is resolved now. Is it?
Anything else blocking this PR?
https://github.com/llvm/llvm-project/pull/120437
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
@@ -298,9 +299,12 @@ class SymbolVal : public NonLoc {
/// Value representing integer constant.
class ConcreteInt : public NonLoc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : NonLoc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : NonLoc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
Xazax-hun wrote:
> Currently the infrastructure is set up for holding raw-pointers.
Could you elaborate on what preventing us from changing this?
https://github.com/llvm/llvm-project/pull/120436
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
@@ -298,9 +299,12 @@ class SymbolVal : public NonLoc {
/// Value representing integer constant.
class ConcreteInt : public NonLoc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : NonLoc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : NonLoc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
steakhal wrote:
A union make this void pointer trickery marginally safer at the expense of
declaring all the types we typepun this poor void storage pointer.
Maybe this is something to consider.
https://github.com/llvm/llvm-project/pull/120436
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
@@ -298,9 +299,12 @@ class SymbolVal : public NonLoc {
/// Value representing integer constant.
class ConcreteInt : public NonLoc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : NonLoc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : NonLoc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
steakhal wrote:
Basicall it all boils down to the fact that an sval has a single void pointer
as a storage. I'm currently okay casting a pointer to and from void pointer of
this storage. But I'd be uncomfortable bitcasting an APSIntPtr object into a
void pointer storage, even if it only holds a single pointer inside. This is
why I preferred unboxing the pointer and holding that inside the SVal.
Maybe I overlooked some other techniques. Let me know if you have something in
mind.
https://github.com/llvm/llvm-project/pull/120436
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
https://github.com/steakhal edited https://github.com/llvm/llvm-project/pull/120436 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
@@ -298,9 +299,12 @@ class SymbolVal : public NonLoc {
/// Value representing integer constant.
class ConcreteInt : public NonLoc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : NonLoc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : NonLoc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
Xazax-hun wrote:
Ah, never mind. This does not help us because here we would want to cast the
struct itself.
https://github.com/llvm/llvm-project/pull/120436
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
@@ -298,9 +299,12 @@ class SymbolVal : public NonLoc {
/// Value representing integer constant.
class ConcreteInt : public NonLoc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : NonLoc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : NonLoc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
Xazax-hun wrote:
According to [CppReference](https://en.cppreference.com/w/c/language/struct):
> A pointer to a struct can be cast to a pointer to its first member (or, if
> the member is a bit-field, to its allocation unit). Likewise, a pointer to
> the first member of a struct can be cast to a pointer to the enclosing struct.
https://github.com/llvm/llvm-project/pull/120436
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)
arsenm wrote: > crashes with: > > ``` > WidenVectorResult #0: t3: v2i32,ch = AtomicLoad<(load acquire (s64) from > %ir.x, align 64)> t0, t2 > LLVM ERROR: Do not know how to widen the result of this operator! > ``` At this PR, this is the expectation. A later PR needs to handle the other vector legalization cases https://github.com/llvm/llvm-project/pull/120385 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][GPU] Add `gpu.assert` op (PR #120431)
https://github.com/matthias-springer updated
https://github.com/llvm/llvm-project/pull/120431
>From 4d8342992a22677686ea7a7dd88d032ca2289391 Mon Sep 17 00:00:00 2001
From: Matthias Springer
Date: Wed, 18 Dec 2024 15:42:59 +0100
Subject: [PATCH] [mlir][GPU] Add `gpu.assert` op
---
mlir/include/mlir/Dialect/GPU/IR/GPUOps.td| 11 ++
.../Conversion/GPUCommon/GPUOpsLowering.cpp | 122 +-
.../lib/Conversion/GPUCommon/GPUOpsLowering.h | 21 +++
.../GPUToNVVM/LowerGpuOpsToNVVMOps.cpp| 103 ++-
.../Conversion/GPUToNVVM/gpu-to-nvvm.mlir | 29 +
mlir/test/Dialect/GPU/ops.mlir| 9 ++
mlir/test/Integration/GPU/CUDA/assert.mlir| 38 ++
7 files changed, 270 insertions(+), 63 deletions(-)
create mode 100644 mlir/test/Integration/GPU/CUDA/assert.mlir
diff --git a/mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
b/mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
index 42a017db300af6..793d663c0322a5 100644
--- a/mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
+++ b/mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
@@ -38,6 +38,17 @@ include "mlir/Interfaces/SideEffectInterfaces.td"
class GPU_Op traits = []> :
Op;
+def GPU_AssertOp : GPU_Op<"assert"> {
+ let summary = "Device-side assertion";
+ let description = [{
+The `gpu.assert` op is a device-side assertion. If the given `condition`
+is 0, the kernel execution is aborted, optionally with the given error
+message. This op is useful for debugging and verifying invariants.
+ }];
+ let arguments = (ins I1:$condition, OptionalAttr:$message);
+ let assemblyFormat = "$condition (`,` $message^)? attr-dict";
+}
+
def GPU_Dimension : I32EnumAttr<"Dimension",
"a dimension, either 'x', 'y', or 'z'",
[
diff --git a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
index b3c3fd4956d0bb..544fc57949e24d 100644
--- a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
+++ b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
@@ -19,6 +19,59 @@
using namespace mlir;
+LLVM::LLVMFuncOp mlir::getOrDefineFunction(gpu::GPUModuleOp moduleOp,
+ Location loc, OpBuilder &b,
+ StringRef name,
+ LLVM::LLVMFunctionType type) {
+ LLVM::LLVMFuncOp ret;
+ if (!(ret = moduleOp.template lookupSymbol(name))) {
+OpBuilder::InsertionGuard guard(b);
+b.setInsertionPointToStart(moduleOp.getBody());
+ret = b.create(loc, name, type, LLVM::Linkage::External);
+ }
+ return ret;
+}
+
+static SmallString<16> getUniqueSymbolName(gpu::GPUModuleOp moduleOp,
+ StringRef prefix) {
+ // Get a unique global name.
+ unsigned stringNumber = 0;
+ SmallString<16> stringConstName;
+ do {
+stringConstName.clear();
+(prefix + Twine(stringNumber++)).toStringRef(stringConstName);
+ } while (moduleOp.lookupSymbol(stringConstName));
+ return stringConstName;
+}
+
+LLVM::GlobalOp
+mlir::getOrCreateStringConstant(OpBuilder &b, Location loc,
+gpu::GPUModuleOp moduleOp, Type llvmI8,
+StringRef namePrefix, StringRef str,
+uint64_t alignment, unsigned addrSpace) {
+ llvm::SmallString<20> nullTermStr(str);
+ nullTermStr.push_back('\0'); // Null terminate for C
+ auto globalType =
+ LLVM::LLVMArrayType::get(llvmI8, nullTermStr.size_in_bytes());
+ StringAttr attr = b.getStringAttr(nullTermStr);
+
+ // Try to find existing global.
+ for (auto globalOp : moduleOp.getOps())
+if (globalOp.getGlobalType() == globalType && globalOp.getConstant() &&
+globalOp.getValueAttr() == attr &&
+globalOp.getAlignment().value_or(0) == alignment &&
+globalOp.getAddrSpace() == addrSpace)
+ return globalOp;
+
+ // Not found: create new global.
+ OpBuilder::InsertionGuard guard(b);
+ b.setInsertionPointToStart(moduleOp.getBody());
+ SmallString<16> name = getUniqueSymbolName(moduleOp, namePrefix);
+ return b.create(loc, globalType,
+ /*isConstant=*/true, LLVM::Linkage::Internal,
+ name, attr, alignment, addrSpace);
+}
+
LogicalResult
GPUFuncOpLowering::matchAndRewrite(gpu::GPUFuncOp gpuFuncOp, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const {
@@ -328,61 +381,6 @@ GPUFuncOpLowering::matchAndRewrite(gpu::GPUFuncOp
gpuFuncOp, OpAdaptor adaptor,
return success();
}
-static SmallString<16> getUniqueFormatGlobalName(gpu::GPUModuleOp moduleOp) {
- const char formatStringPrefix[] = "printfFormat_";
- // Get a unique global name.
- unsigned stringNumber = 0;
- SmallString<16> stringConstName;
- do {
-stringConstName.clear();
-(formatStringPrefix + Twine(stringNumber++)).toStringRef(stringConstName);
- } while (moduleOp.lookupSymbol(stringConstName));
-
[llvm-branch-commits] [clang] release/19.x: [clang] hexagon: fix link order for libc/builtins (#117057) (PR #117968)
https://github.com/SidManning approved this pull request. https://github.com/llvm/llvm-project/pull/117968 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate {SymInt, IntSym}Expr to use APSIntPtr (4/4) (PR #120438)
https://github.com/Xazax-hun approved this pull request. https://github.com/llvm/llvm-project/pull/120438 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][GPU] Add NVVM-specific `cf.assert` lowering (PR #120431)
https://github.com/matthias-springer edited https://github.com/llvm/llvm-project/pull/120431 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][GPU] Add NVVM-specific `cf.assert` lowering (PR #120431)
https://github.com/matthias-springer edited https://github.com/llvm/llvm-project/pull/120431 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][GPU] Add `gpu.assert` op (PR #120431)
matthias-springer wrote: > Can we just use cf.assert ? This is a good idea. But I first have to move a few things around because there is an existing pattern in `populateControlFlowToLLVMConversionPatterns`... https://github.com/llvm/llvm-project/pull/120431 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
@@ -298,9 +299,12 @@ class SymbolVal : public NonLoc {
/// Value representing integer constant.
class ConcreteInt : public NonLoc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : NonLoc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : NonLoc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
Xazax-hun wrote:
Is it possible to store `ApsIntPtr` in `NonLoc`?
https://github.com/llvm/llvm-project/pull/120436
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate loc::ConcreteInt to use APSIntPtr (3/4) (PR #120437)
@@ -514,9 +514,12 @@ class MemRegionVal : public Loc {
class ConcreteInt : public Loc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : Loc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : Loc(ConcreteIntKind, V.get()) {}
Xazax-hun wrote:
Is it possible to store `APSIntPtr` in `Loc`?
https://github.com/llvm/llvm-project/pull/120437
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][GPU] Add `gpu.assert` op (PR #120431)
https://github.com/matthias-springer updated
https://github.com/llvm/llvm-project/pull/120431
>From 79ca017333d2f03e99015e6fe821fea5bf2e4537 Mon Sep 17 00:00:00 2001
From: Matthias Springer
Date: Wed, 18 Dec 2024 15:42:59 +0100
Subject: [PATCH] [mlir][GPU] Add `gpu.assert` op
---
.../Conversion/GPUCommon/GPUOpsLowering.cpp | 122 +-
.../lib/Conversion/GPUCommon/GPUOpsLowering.h | 21 +++
.../GPUToNVVM/LowerGpuOpsToNVVMOps.cpp| 99 +-
.../Conversion/GPUToNVVM/gpu-to-nvvm.mlir | 29 +
mlir/test/Integration/GPU/CUDA/assert.mlir| 38 ++
5 files changed, 246 insertions(+), 63 deletions(-)
create mode 100644 mlir/test/Integration/GPU/CUDA/assert.mlir
diff --git a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
index b3c3fd4956d0bb..544fc57949e24d 100644
--- a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
+++ b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
@@ -19,6 +19,59 @@
using namespace mlir;
+LLVM::LLVMFuncOp mlir::getOrDefineFunction(gpu::GPUModuleOp moduleOp,
+ Location loc, OpBuilder &b,
+ StringRef name,
+ LLVM::LLVMFunctionType type) {
+ LLVM::LLVMFuncOp ret;
+ if (!(ret = moduleOp.template lookupSymbol(name))) {
+OpBuilder::InsertionGuard guard(b);
+b.setInsertionPointToStart(moduleOp.getBody());
+ret = b.create(loc, name, type, LLVM::Linkage::External);
+ }
+ return ret;
+}
+
+static SmallString<16> getUniqueSymbolName(gpu::GPUModuleOp moduleOp,
+ StringRef prefix) {
+ // Get a unique global name.
+ unsigned stringNumber = 0;
+ SmallString<16> stringConstName;
+ do {
+stringConstName.clear();
+(prefix + Twine(stringNumber++)).toStringRef(stringConstName);
+ } while (moduleOp.lookupSymbol(stringConstName));
+ return stringConstName;
+}
+
+LLVM::GlobalOp
+mlir::getOrCreateStringConstant(OpBuilder &b, Location loc,
+gpu::GPUModuleOp moduleOp, Type llvmI8,
+StringRef namePrefix, StringRef str,
+uint64_t alignment, unsigned addrSpace) {
+ llvm::SmallString<20> nullTermStr(str);
+ nullTermStr.push_back('\0'); // Null terminate for C
+ auto globalType =
+ LLVM::LLVMArrayType::get(llvmI8, nullTermStr.size_in_bytes());
+ StringAttr attr = b.getStringAttr(nullTermStr);
+
+ // Try to find existing global.
+ for (auto globalOp : moduleOp.getOps())
+if (globalOp.getGlobalType() == globalType && globalOp.getConstant() &&
+globalOp.getValueAttr() == attr &&
+globalOp.getAlignment().value_or(0) == alignment &&
+globalOp.getAddrSpace() == addrSpace)
+ return globalOp;
+
+ // Not found: create new global.
+ OpBuilder::InsertionGuard guard(b);
+ b.setInsertionPointToStart(moduleOp.getBody());
+ SmallString<16> name = getUniqueSymbolName(moduleOp, namePrefix);
+ return b.create(loc, globalType,
+ /*isConstant=*/true, LLVM::Linkage::Internal,
+ name, attr, alignment, addrSpace);
+}
+
LogicalResult
GPUFuncOpLowering::matchAndRewrite(gpu::GPUFuncOp gpuFuncOp, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const {
@@ -328,61 +381,6 @@ GPUFuncOpLowering::matchAndRewrite(gpu::GPUFuncOp
gpuFuncOp, OpAdaptor adaptor,
return success();
}
-static SmallString<16> getUniqueFormatGlobalName(gpu::GPUModuleOp moduleOp) {
- const char formatStringPrefix[] = "printfFormat_";
- // Get a unique global name.
- unsigned stringNumber = 0;
- SmallString<16> stringConstName;
- do {
-stringConstName.clear();
-(formatStringPrefix + Twine(stringNumber++)).toStringRef(stringConstName);
- } while (moduleOp.lookupSymbol(stringConstName));
- return stringConstName;
-}
-
-/// Create an global that contains the given format string. If a global with
-/// the same format string exists already in the module, return that global.
-static LLVM::GlobalOp getOrCreateFormatStringConstant(
-OpBuilder &b, Location loc, gpu::GPUModuleOp moduleOp, Type llvmI8,
-StringRef str, uint64_t alignment = 0, unsigned addrSpace = 0) {
- llvm::SmallString<20> formatString(str);
- formatString.push_back('\0'); // Null terminate for C
- auto globalType =
- LLVM::LLVMArrayType::get(llvmI8, formatString.size_in_bytes());
- StringAttr attr = b.getStringAttr(formatString);
-
- // Try to find existing global.
- for (auto globalOp : moduleOp.getOps())
-if (globalOp.getGlobalType() == globalType && globalOp.getConstant() &&
-globalOp.getValueAttr() == attr &&
-globalOp.getAlignment().value_or(0) == alignment &&
-globalOp.getAddrSpace() == addrSpace)
- return globalOp;
-
- // Not found: create new global.
- OpBuilder::InsertionGuard guar
[llvm-branch-commits] [mlir] [mlir][GPU] Add `gpu.assert` op (PR #120431)
https://github.com/matthias-springer converted_to_draft https://github.com/llvm/llvm-project/pull/120431 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate loc::ConcreteInt to use APSIntPtr (3/4) (PR #120437)
@@ -514,9 +514,12 @@ class MemRegionVal : public Loc {
class ConcreteInt : public Loc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : Loc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : Loc(ConcreteIntKind, V.get()) {}
steakhal wrote:
In short, I don't think. See
https://github.com/llvm/llvm-project/pull/120436#discussion_r1890504894.
https://github.com/llvm/llvm-project/pull/120437
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
@@ -298,9 +299,12 @@ class SymbolVal : public NonLoc {
/// Value representing integer constant.
class ConcreteInt : public NonLoc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : NonLoc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : NonLoc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
steakhal wrote:
Currently the infrastructure is set up for holding raw-pointers.
I don't know of a better way achieving this other than boxing/unboxing like
done so.
I can't hold a pointer to a `APSIntPtr` object, if that's not exactly the
object held by the factory.
In the factory, I can't allocate this, because this is just a view (a
raw-pointer) - so its conceptually different.
The ergonomics would be better on one side if I had `APSIntRef` wrapping a
reference, but then I'd lose copy and assign operations that come really handy
in a lot of places. So these were the factors I considered when designing this
type.
https://github.com/llvm/llvm-project/pull/120436
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][Properties] Shorten "Property" to "Prop" in most places (PR #120368)
https://github.com/zero9178 edited https://github.com/llvm/llvm-project/pull/120368 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][Properties] Shorten "Property" to "Prop" in most places (PR #120368)
@@ -113,13 +113,13 @@ struct AttributeLikeVariable : public VariableElement {
return isa(fe) && classof(cast(fe));
}
- /// Returns true if the variable is a UnitAttr or a UnitProperty.
+ /// Returns true if the variable is a UnitAttr or a UnitProp.
bool isUnit() const {
if (const auto *attr = dyn_cast(this))
return attr->getVar()->attr.getBaseAttr().getAttrDefName() == "UnitAttr";
if (const auto *prop = dyn_cast(this)) {
return prop->getVar()->prop.getBaseProperty().getPropertyDefName() ==
- "UnitProperty";
+ "UnitProp";
zero9178 wrote:
Isn't this going to fail now for `UnitProperty`?
https://github.com/llvm/llvm-project/pull/120368
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][Properties] Shorten "Property" to "Prop" in most places (PR #120368)
@@ -102,8 +102,9 @@ their semantics via a special [TableGen backend][TableGenBackend]: constraints over attributes. A notable subclass hierarchy is `Attr`, which stands for constraints for attributes whose values are of common types. * The `Property` class hierarchy: They are used to specify non-attribute-backed -properties that are inherent to operations. This will be expanded to a -`PropertyConstraint` class or something similar in the future. +properties that are inherent to operations. These properties can have +constraints imposed them using their `predicate` field or the zero9178 wrote: ```suggestion constraints imposed on them using the `predicate` field or the ``` https://github.com/llvm/llvm-project/pull/120368 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][Properties] Shorten "Property" to "Prop" in most places (PR #120368)
https://github.com/zero9178 commented: I am personally in favour of this and besides the past, there probably isn't a better time to do this change than now. I also really like that this only deprecates the old names such that downstream users are notified on their next bump and it can then be removed later. Could we move the documentation changes that are specific to predicates (not renaming) to either the other PR or a new PR/commit? I don't think they should be intermingled here. https://github.com/llvm/llvm-project/pull/120368 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/120387 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/120385 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][GPU] Add `gpu.assert` op (PR #120431)
https://github.com/matthias-springer edited https://github.com/llvm/llvm-project/pull/120431 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
https://github.com/steakhal created
https://github.com/llvm/llvm-project/pull/120436
None
>From bda84413e146d2e39a704a73694fb777249be799 Mon Sep 17 00:00:00 2001
From: Balazs Benics
Date: Wed, 18 Dec 2024 15:55:27 +0100
Subject: [PATCH] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr
(2/4)
---
.../Core/PathSensitive/MemRegion.h| 2 +-
.../StaticAnalyzer/Core/PathSensitive/SVals.h | 8 +++--
.../Checkers/ArrayBoundCheckerV2.cpp | 14 -
.../Checkers/BasicObjCFoundationChecks.cpp| 2 +-
.../Checkers/BitwiseShiftChecker.cpp | 8 ++---
.../Checkers/BuiltinFunctionChecker.cpp | 8 +++--
.../Checkers/CheckPlacementNew.cpp| 2 +-
.../lib/StaticAnalyzer/Checkers/Iterator.cpp | 14 -
.../Checkers/IteratorModeling.cpp | 4 +--
.../Checkers/MmapWriteExecChecker.cpp | 2 +-
.../StaticAnalyzer/Checkers/StreamChecker.cpp | 2 +-
.../Core/BugReporterVisitors.cpp | 2 +-
clang/lib/StaticAnalyzer/Core/MemRegion.cpp | 8 ++---
.../lib/StaticAnalyzer/Core/ProgramState.cpp | 6 ++--
clang/lib/StaticAnalyzer/Core/SValBuilder.cpp | 2 +-
clang/lib/StaticAnalyzer/Core/SVals.cpp | 10 +++
.../Core/SimpleConstraintManager.cpp | 2 +-
.../StaticAnalyzer/Core/SimpleSValBuilder.cpp | 30 ++-
18 files changed, 65 insertions(+), 61 deletions(-)
diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
index 0d9566285f5d4e..f88bf70d72398c 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
@@ -1206,7 +1206,7 @@ class ElementRegion : public TypedValueRegion {
: TypedValueRegion(sReg, ElementRegionKind), ElementType(elementType),
Index(Idx) {
assert((!isa(Idx) ||
-Idx.castAs().getValue().isSigned()) &&
+Idx.castAs().getValue()->isSigned()) &&
"The index must be signed");
assert(!elementType.isNull() && !elementType->isVoidType() &&
"Invalid region type!");
diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
index a054a819a15a85..57d7514280f10f 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
@@ -17,6 +17,7 @@
#include "clang/AST/Expr.h"
#include "clang/AST/Type.h"
#include "clang/Basic/LLVM.h"
+#include "clang/StaticAnalyzer/Core/PathSensitive/APSIntPtr.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/SymExpr.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/FoldingSet.h"
@@ -298,9 +299,12 @@ class SymbolVal : public NonLoc {
/// Value representing integer constant.
class ConcreteInt : public NonLoc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : NonLoc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : NonLoc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
+ }
static bool classof(SVal V) { return V.getKind() == ConcreteIntKind; }
};
diff --git a/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
b/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
index 3f837564cf47c4..6422933c8828a9 100644
--- a/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
+++ b/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
@@ -22,6 +22,7 @@
#include "clang/StaticAnalyzer/Core/PathSensitive/CheckerContext.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/DynamicExtent.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h"
+#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/Support/FormatVariadic.h"
#include "llvm/Support/raw_ostream.h"
@@ -241,26 +242,25 @@ computeOffset(ProgramStateRef State, SValBuilder &SVB,
SVal Location) {
static std::pair
getSimplifiedOffsets(NonLoc offset, nonloc::ConcreteInt extent,
SValBuilder &svalBuilder) {
+ const llvm::APSInt &extentVal = extent.getValue();
std::optional SymVal = offset.getAs();
if (SymVal && SymVal->isExpression()) {
if (const SymIntExpr *SIE = dyn_cast(SymVal->getSymbol())) {
- llvm::APSInt constant =
- APSIntType(extent.getValue()).convert(SIE->getRHS());
+ llvm::APSInt constant = APSIntType(extentVal).convert(SIE->getRHS());
switch (SIE->getOpcode()) {
case BO_Mul:
// The constant should never be 0 here, becasue multiplication by zero
// is simplified by the engine.
-if ((extent.getValue() % constant) != 0)
+if ((extentVal % constant) != 0)
return std::pair(offset, exte
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
steakhal wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/120436?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#120438** https://app.graphite.dev/github/pr/llvm/llvm-project/120438?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#120437** https://app.graphite.dev/github/pr/llvm/llvm-project/120437?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#120436** https://app.graphite.dev/github/pr/llvm/llvm-project/120436?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/120436?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#120435** https://app.graphite.dev/github/pr/llvm/llvm-project/120435?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/120436 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate {SymInt, IntSym}Expr to use APSIntPtr (4/4) (PR #120438)
https://github.com/steakhal created
https://github.com/llvm/llvm-project/pull/120438
None
>From ffda1054d5a3e8f4ce42c3bedfc29cc8a0c69df1 Mon Sep 17 00:00:00 2001
From: Balazs Benics
Date: Wed, 18 Dec 2024 15:59:23 +0100
Subject: [PATCH] [analyzer][NFC] Migrate {SymInt,IntSym}Expr to use APSIntPtr
(4/4)
---
.../Core/PathSensitive/SMTConstraintManager.h| 4 ++--
.../Core/PathSensitive/SValBuilder.h | 7 +++
.../Core/PathSensitive/SymbolManager.h | 16 +++-
.../Checkers/ExprInspectionChecker.cpp | 4 ++--
clang/lib/StaticAnalyzer/Core/SValBuilder.cpp| 8 ++--
.../StaticAnalyzer/Core/SimpleSValBuilder.cpp| 2 +-
clang/lib/StaticAnalyzer/Core/SymbolManager.cpp | 8 +++-
7 files changed, 20 insertions(+), 29 deletions(-)
diff --git
a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
index 72038b92f8edfe..7cfb24e5e649db 100644
---
a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
+++
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
@@ -175,9 +175,9 @@ class SMTConstraintManager : public
clang::ento::SimpleConstraintManager {
const llvm::APSInt *LHS, *RHS;
if (const SymIntExpr *SIE = dyn_cast(BSE)) {
LHS = getSymVal(State, SIE->getLHS());
-RHS = &SIE->getRHS();
+RHS = SIE->getRHS().get();
} else if (const IntSymExpr *ISE = dyn_cast(BSE)) {
-LHS = &ISE->getLHS();
+LHS = ISE->getLHS().get();
RHS = getSymVal(State, ISE->getRHS());
} else if (const SymSymExpr *SSM = dyn_cast(BSE)) {
// Early termination to avoid expensive call
diff --git
a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
index ec2b2b24569480..54430d426a82a8 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
@@ -329,11 +329,10 @@ class SValBuilder {
}
nonloc::SymbolVal makeNonLoc(const SymExpr *lhs, BinaryOperator::Opcode op,
- const llvm::APSInt &rhs, QualType type);
+ APSIntPtr rhs, QualType type);
- nonloc::SymbolVal makeNonLoc(const llvm::APSInt &rhs,
- BinaryOperator::Opcode op, const SymExpr *lhs,
- QualType type);
+ nonloc::SymbolVal makeNonLoc(APSIntPtr rhs, BinaryOperator::Opcode op,
+ const SymExpr *lhs, QualType type);
nonloc::SymbolVal makeNonLoc(const SymExpr *lhs, BinaryOperator::Opcode op,
const SymExpr *rhs, QualType type);
diff --git
a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
index 3b64d38ee2b233..73732d532f630f 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
@@ -18,6 +18,7 @@
#include "clang/AST/Type.h"
#include "clang/Analysis/AnalysisDeclContext.h"
#include "clang/Basic/LLVM.h"
+#include "clang/StaticAnalyzer/Core/PathSensitive/APSIntPtr.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/StoreRef.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/SymExpr.h"
@@ -410,9 +411,7 @@ class BinarySymExpr : public SymExpr {
return 1;
}
- static const llvm::APSInt *getPointer(const llvm::APSInt &Value) {
-return &Value;
- }
+ static const llvm::APSInt *getPointer(APSIntPtr Value) { return Value.get();
}
static const SymExpr *getPointer(const SymExpr *Value) { return Value; }
static void dumpToStreamImpl(raw_ostream &os, const SymExpr *Value);
@@ -468,11 +467,11 @@ class BinarySymExprImpl : public BinarySymExpr {
};
/// Represents a symbolic expression like 'x' + 3.
-using SymIntExpr = BinarySymExprImpl;
/// Represents a symbolic expression like 3 - 'x'.
-using IntSymExpr = BinarySymExprImpl;
/// Represents a symbolic expression like 'x' + 'y'.
@@ -537,15 +536,14 @@ class SymbolManager {
QualType From, QualType To);
const SymIntExpr *getSymIntExpr(const SymExpr *lhs, BinaryOperator::Opcode
op,
- const llvm::APSInt& rhs, QualType t);
+ APSIntPtr rhs, QualType t);
const SymIntExpr *getSymIntExpr(const SymExpr &lhs, BinaryOperator::Opcode
op,
- const llvm::APSInt& rhs, QualType t) {
+ APSIntPtr rhs, QualType t) {
return getSymIntExpr(&lhs, op, rhs, t);
}
- const IntSymExpr *getIntSymExpr(const llvm::APSInt& lhs,
-
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate loc::ConcreteInt to use APSIntPtr (3/4) (PR #120437)
https://github.com/steakhal created
https://github.com/llvm/llvm-project/pull/120437
None
>From 81c7a2837ca2da2436613f4411e3b3cd37289051 Mon Sep 17 00:00:00 2001
From: Balazs Benics
Date: Wed, 18 Dec 2024 15:57:26 +0100
Subject: [PATCH] [analyzer][NFC] Migrate loc::ConcreteInt to use APSIntPtr
(3/4)
---
.../clang/StaticAnalyzer/Core/PathSensitive/SVals.h| 7 +--
clang/lib/StaticAnalyzer/Core/SValBuilder.cpp | 2 +-
clang/lib/StaticAnalyzer/Core/SVals.cpp| 6 +++---
clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp| 2 +-
4 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
index 57d7514280f10f..aeb57b28077c61 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
@@ -514,9 +514,12 @@ class MemRegionVal : public Loc {
class ConcreteInt : public Loc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : Loc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : Loc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
+ }
static bool classof(SVal V) { return V.getKind() == ConcreteIntKind; }
};
diff --git a/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
b/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
index 5741fff0cc12f7..6fbdc956313d57 100644
--- a/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
+++ b/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
@@ -671,7 +671,7 @@ class EvalCastVisitor : public SValVisitor {
SVal VisitConcreteInt(loc::ConcreteInt V) {
// Pointer to bool.
if (CastTy->isBooleanType())
- return VB.makeTruthVal(V.getValue().getBoolValue(), CastTy);
+ return VB.makeTruthVal(V.getValue()->getBoolValue(), CastTy);
// Pointer to integer.
if (CastTy->isIntegralOrEnumerationType()) {
diff --git a/clang/lib/StaticAnalyzer/Core/SVals.cpp
b/clang/lib/StaticAnalyzer/Core/SVals.cpp
index ec88f52a2b3c58..3ab01a04dcec4c 100644
--- a/clang/lib/StaticAnalyzer/Core/SVals.cpp
+++ b/clang/lib/StaticAnalyzer/Core/SVals.cpp
@@ -113,7 +113,7 @@ const llvm::APSInt *SVal::getAsInteger() const {
if (auto CI = getAs())
return CI->getValue().get();
if (auto CI = getAs())
-return &CI->getValue();
+return CI->getValue().get();
return nullptr;
}
@@ -249,7 +249,7 @@ bool SVal::isConstant() const {
bool SVal::isConstant(int I) const {
if (std::optional LV = getAs())
-return LV->getValue() == I;
+return *LV->getValue().get() == I;
if (std::optional NV = getAs())
return *NV->getValue().get() == I;
return false;
@@ -380,7 +380,7 @@ void NonLoc::dumpToStream(raw_ostream &os) const {
void Loc::dumpToStream(raw_ostream &os) const {
switch (getKind()) {
case loc::ConcreteIntKind:
-os << castAs().getValue().getZExtValue() << " (Loc)";
+os << castAs().getValue()->getZExtValue() << " (Loc)";
break;
case loc::GotoLabelKind:
os << "&&" << castAs().getLabel()->getName();
diff --git a/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp
b/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp
index d2e6870ad17079..136b1729c94691 100644
--- a/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp
+++ b/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp
@@ -1210,7 +1210,7 @@ const llvm::APSInt
*SimpleSValBuilder::getConstValue(ProgramStateRef state,
const llvm::APSInt *SimpleSValBuilder::getConcreteValue(SVal V) {
if (std::optional X = V.getAs())
-return &X->getValue();
+return X->getValue().get();
if (std::optional X = V.getAs())
return X->getValue().get();
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate {SymInt, IntSym}Expr to use APSIntPtr (4/4) (PR #120438)
steakhal wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/120438?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#120438** https://app.graphite.dev/github/pr/llvm/llvm-project/120438?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/120438?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#120437** https://app.graphite.dev/github/pr/llvm/llvm-project/120437?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#120436** https://app.graphite.dev/github/pr/llvm/llvm-project/120436?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#120435** https://app.graphite.dev/github/pr/llvm/llvm-project/120435?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/120438 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate loc::ConcreteInt to use APSIntPtr (3/4) (PR #120437)
steakhal wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/120437?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#120438** https://app.graphite.dev/github/pr/llvm/llvm-project/120438?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#120437** https://app.graphite.dev/github/pr/llvm/llvm-project/120437?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/120437?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#120436** https://app.graphite.dev/github/pr/llvm/llvm-project/120436?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#120435** https://app.graphite.dev/github/pr/llvm/llvm-project/120435?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/120437 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate nonloc::ConcreteInt to use APSIntPtr (2/4) (PR #120436)
llvmbot wrote:
@llvm/pr-subscribers-clang-static-analyzer-1
Author: Balazs Benics (steakhal)
Changes
---
Patch is 22.29 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/120436.diff
18 Files Affected:
- (modified) clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
(+1-1)
- (modified) clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
(+6-2)
- (modified) clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp (+7-7)
- (modified) clang/lib/StaticAnalyzer/Checkers/BasicObjCFoundationChecks.cpp
(+1-1)
- (modified) clang/lib/StaticAnalyzer/Checkers/BitwiseShiftChecker.cpp (+4-4)
- (modified) clang/lib/StaticAnalyzer/Checkers/BuiltinFunctionChecker.cpp
(+5-3)
- (modified) clang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp (+1-1)
- (modified) clang/lib/StaticAnalyzer/Checkers/Iterator.cpp (+7-7)
- (modified) clang/lib/StaticAnalyzer/Checkers/IteratorModeling.cpp (+2-2)
- (modified) clang/lib/StaticAnalyzer/Checkers/MmapWriteExecChecker.cpp (+1-1)
- (modified) clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp (+1-1)
- (modified) clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp (+1-1)
- (modified) clang/lib/StaticAnalyzer/Core/MemRegion.cpp (+3-5)
- (modified) clang/lib/StaticAnalyzer/Core/ProgramState.cpp (+2-4)
- (modified) clang/lib/StaticAnalyzer/Core/SValBuilder.cpp (+1-1)
- (modified) clang/lib/StaticAnalyzer/Core/SVals.cpp (+5-5)
- (modified) clang/lib/StaticAnalyzer/Core/SimpleConstraintManager.cpp (+1-1)
- (modified) clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp (+16-14)
``diff
diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
index 0d9566285f5d4e..f88bf70d72398c 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
@@ -1206,7 +1206,7 @@ class ElementRegion : public TypedValueRegion {
: TypedValueRegion(sReg, ElementRegionKind), ElementType(elementType),
Index(Idx) {
assert((!isa(Idx) ||
-Idx.castAs().getValue().isSigned()) &&
+Idx.castAs().getValue()->isSigned()) &&
"The index must be signed");
assert(!elementType.isNull() && !elementType->isVoidType() &&
"Invalid region type!");
diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
index a054a819a15a85..57d7514280f10f 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
@@ -17,6 +17,7 @@
#include "clang/AST/Expr.h"
#include "clang/AST/Type.h"
#include "clang/Basic/LLVM.h"
+#include "clang/StaticAnalyzer/Core/PathSensitive/APSIntPtr.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/SymExpr.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/FoldingSet.h"
@@ -298,9 +299,12 @@ class SymbolVal : public NonLoc {
/// Value representing integer constant.
class ConcreteInt : public NonLoc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : NonLoc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : NonLoc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
+ }
static bool classof(SVal V) { return V.getKind() == ConcreteIntKind; }
};
diff --git a/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
b/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
index 3f837564cf47c4..6422933c8828a9 100644
--- a/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
+++ b/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
@@ -22,6 +22,7 @@
#include "clang/StaticAnalyzer/Core/PathSensitive/CheckerContext.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/DynamicExtent.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h"
+#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/Support/FormatVariadic.h"
#include "llvm/Support/raw_ostream.h"
@@ -241,26 +242,25 @@ computeOffset(ProgramStateRef State, SValBuilder &SVB,
SVal Location) {
static std::pair
getSimplifiedOffsets(NonLoc offset, nonloc::ConcreteInt extent,
SValBuilder &svalBuilder) {
+ const llvm::APSInt &extentVal = extent.getValue();
std::optional SymVal = offset.getAs();
if (SymVal && SymVal->isExpression()) {
if (const SymIntExpr *SIE = dyn_cast(SymVal->getSymbol())) {
- llvm::APSInt constant =
- APSIntType(extent.getValue()).convert(SIE->getRHS());
+ llvm::APSInt constant = APSIntType(extentVal).convert(SIE->getRHS());
switch (SIE->getOpcode()) {
case BO_Mul:
// The constant
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate loc::ConcreteInt to use APSIntPtr (3/4) (PR #120437)
https://github.com/steakhal ready_for_review https://github.com/llvm/llvm-project/pull/120437 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate {SymInt, IntSym}Expr to use APSIntPtr (4/4) (PR #120438)
https://github.com/steakhal ready_for_review https://github.com/llvm/llvm-project/pull/120438 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate loc::ConcreteInt to use APSIntPtr (3/4) (PR #120437)
llvmbot wrote:
@llvm/pr-subscribers-clang-static-analyzer-1
Author: Balazs Benics (steakhal)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/120437.diff
4 Files Affected:
- (modified) clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
(+5-2)
- (modified) clang/lib/StaticAnalyzer/Core/SValBuilder.cpp (+1-1)
- (modified) clang/lib/StaticAnalyzer/Core/SVals.cpp (+3-3)
- (modified) clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp (+1-1)
``diff
diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
index 57d7514280f10f..aeb57b28077c61 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SVals.h
@@ -514,9 +514,12 @@ class MemRegionVal : public Loc {
class ConcreteInt : public Loc {
public:
- explicit ConcreteInt(const llvm::APSInt &V) : Loc(ConcreteIntKind, &V) {}
+ explicit ConcreteInt(APSIntPtr V) : Loc(ConcreteIntKind, V.get()) {}
- const llvm::APSInt &getValue() const { return *castDataAs(); }
+ APSIntPtr getValue() const {
+// This is safe because in the ctor we take a safe APSIntPtr.
+return APSIntPtr::unsafeConstructor(castDataAs());
+ }
static bool classof(SVal V) { return V.getKind() == ConcreteIntKind; }
};
diff --git a/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
b/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
index 5741fff0cc12f7..6fbdc956313d57 100644
--- a/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
+++ b/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
@@ -671,7 +671,7 @@ class EvalCastVisitor : public SValVisitor {
SVal VisitConcreteInt(loc::ConcreteInt V) {
// Pointer to bool.
if (CastTy->isBooleanType())
- return VB.makeTruthVal(V.getValue().getBoolValue(), CastTy);
+ return VB.makeTruthVal(V.getValue()->getBoolValue(), CastTy);
// Pointer to integer.
if (CastTy->isIntegralOrEnumerationType()) {
diff --git a/clang/lib/StaticAnalyzer/Core/SVals.cpp
b/clang/lib/StaticAnalyzer/Core/SVals.cpp
index ec88f52a2b3c58..3ab01a04dcec4c 100644
--- a/clang/lib/StaticAnalyzer/Core/SVals.cpp
+++ b/clang/lib/StaticAnalyzer/Core/SVals.cpp
@@ -113,7 +113,7 @@ const llvm::APSInt *SVal::getAsInteger() const {
if (auto CI = getAs())
return CI->getValue().get();
if (auto CI = getAs())
-return &CI->getValue();
+return CI->getValue().get();
return nullptr;
}
@@ -249,7 +249,7 @@ bool SVal::isConstant() const {
bool SVal::isConstant(int I) const {
if (std::optional LV = getAs())
-return LV->getValue() == I;
+return *LV->getValue().get() == I;
if (std::optional NV = getAs())
return *NV->getValue().get() == I;
return false;
@@ -380,7 +380,7 @@ void NonLoc::dumpToStream(raw_ostream &os) const {
void Loc::dumpToStream(raw_ostream &os) const {
switch (getKind()) {
case loc::ConcreteIntKind:
-os << castAs().getValue().getZExtValue() << " (Loc)";
+os << castAs().getValue()->getZExtValue() << " (Loc)";
break;
case loc::GotoLabelKind:
os << "&&" << castAs().getLabel()->getName();
diff --git a/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp
b/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp
index d2e6870ad17079..136b1729c94691 100644
--- a/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp
+++ b/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp
@@ -1210,7 +1210,7 @@ const llvm::APSInt
*SimpleSValBuilder::getConstValue(ProgramStateRef state,
const llvm::APSInt *SimpleSValBuilder::getConcreteValue(SVal V) {
if (std::optional X = V.getAs())
-return &X->getValue();
+return X->getValue().get();
if (std::optional X = V.getAs())
return X->getValue().get();
``
https://github.com/llvm/llvm-project/pull/120437
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [analyzer][NFC] Migrate {SymInt, IntSym}Expr to use APSIntPtr (4/4) (PR #120438)
llvmbot wrote:
@llvm/pr-subscribers-clang-static-analyzer-1
Author: Balazs Benics (steakhal)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/120438.diff
7 Files Affected:
- (modified)
clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
(+2-2)
- (modified)
clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h (+3-4)
- (modified)
clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h (+7-9)
- (modified) clang/lib/StaticAnalyzer/Checkers/ExprInspectionChecker.cpp (+2-2)
- (modified) clang/lib/StaticAnalyzer/Core/SValBuilder.cpp (+2-6)
- (modified) clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp (+1-1)
- (modified) clang/lib/StaticAnalyzer/Core/SymbolManager.cpp (+3-5)
``diff
diff --git
a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
index 72038b92f8edfe..7cfb24e5e649db 100644
---
a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
+++
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
@@ -175,9 +175,9 @@ class SMTConstraintManager : public
clang::ento::SimpleConstraintManager {
const llvm::APSInt *LHS, *RHS;
if (const SymIntExpr *SIE = dyn_cast(BSE)) {
LHS = getSymVal(State, SIE->getLHS());
-RHS = &SIE->getRHS();
+RHS = SIE->getRHS().get();
} else if (const IntSymExpr *ISE = dyn_cast(BSE)) {
-LHS = &ISE->getLHS();
+LHS = ISE->getLHS().get();
RHS = getSymVal(State, ISE->getRHS());
} else if (const SymSymExpr *SSM = dyn_cast(BSE)) {
// Early termination to avoid expensive call
diff --git
a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
index ec2b2b24569480..54430d426a82a8 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
@@ -329,11 +329,10 @@ class SValBuilder {
}
nonloc::SymbolVal makeNonLoc(const SymExpr *lhs, BinaryOperator::Opcode op,
- const llvm::APSInt &rhs, QualType type);
+ APSIntPtr rhs, QualType type);
- nonloc::SymbolVal makeNonLoc(const llvm::APSInt &rhs,
- BinaryOperator::Opcode op, const SymExpr *lhs,
- QualType type);
+ nonloc::SymbolVal makeNonLoc(APSIntPtr rhs, BinaryOperator::Opcode op,
+ const SymExpr *lhs, QualType type);
nonloc::SymbolVal makeNonLoc(const SymExpr *lhs, BinaryOperator::Opcode op,
const SymExpr *rhs, QualType type);
diff --git
a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
index 3b64d38ee2b233..73732d532f630f 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
@@ -18,6 +18,7 @@
#include "clang/AST/Type.h"
#include "clang/Analysis/AnalysisDeclContext.h"
#include "clang/Basic/LLVM.h"
+#include "clang/StaticAnalyzer/Core/PathSensitive/APSIntPtr.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/StoreRef.h"
#include "clang/StaticAnalyzer/Core/PathSensitive/SymExpr.h"
@@ -410,9 +411,7 @@ class BinarySymExpr : public SymExpr {
return 1;
}
- static const llvm::APSInt *getPointer(const llvm::APSInt &Value) {
-return &Value;
- }
+ static const llvm::APSInt *getPointer(APSIntPtr Value) { return Value.get();
}
static const SymExpr *getPointer(const SymExpr *Value) { return Value; }
static void dumpToStreamImpl(raw_ostream &os, const SymExpr *Value);
@@ -468,11 +467,11 @@ class BinarySymExprImpl : public BinarySymExpr {
};
/// Represents a symbolic expression like 'x' + 3.
-using SymIntExpr = BinarySymExprImpl;
/// Represents a symbolic expression like 3 - 'x'.
-using IntSymExpr = BinarySymExprImpl;
/// Represents a symbolic expression like 'x' + 'y'.
@@ -537,15 +536,14 @@ class SymbolManager {
QualType From, QualType To);
const SymIntExpr *getSymIntExpr(const SymExpr *lhs, BinaryOperator::Opcode
op,
- const llvm::APSInt& rhs, QualType t);
+ APSIntPtr rhs, QualType t);
const SymIntExpr *getSymIntExpr(const SymExpr &lhs, BinaryOperator::Opcode
op,
- const llvm::APSInt& rhs, QualType t) {
+ APSIntPtr rhs, QualType t) {
return getSymIntExpr(&lhs, op, rhs, t);
}
- const IntSymExpr *getIntSymExpr(const llvm::APSInt& lhs,
-
[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From e294f9f7a5d5c624c5a356808f738bcc722d2068 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic <1 x T>` is not valid. This change legalizes vector types of
atomic load via scalarization in SelectionDAG so that it can, for example,
translate from `v1i32` to `i32`.
commit-id:5c36cc8c
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
.../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 15 +++
llvm/test/CodeGen/X86/atomic-load-store.ll| 9 +
3 files changed, 25 insertions(+)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 571a710cc92a34..b81c9f87cb27d7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -861,6 +861,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ScalarizeVecRes_ExpOp(SDNode *N);
SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
+ SDValue ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N);
SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
SDValue ScalarizeVecRes_VSELECT(SDNode *N);
SDValue ScalarizeVecRes_SELECT(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 107454a92e356c..c85e4ba2cfa5a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -60,6 +60,9 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N,
unsigned ResNo) {
case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
case ISD::FPOWI: R = ScalarizeVecRes_ExpOp(N); break;
case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
+ case ISD::ATOMIC_LOAD:
+R = ScalarizeVecRes_ATOMIC_LOAD(cast(N));
+break;
case ISD::LOAD: R =
ScalarizeVecRes_LOAD(cast(N));break;
case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
@@ -451,6 +454,18 @@ SDValue
DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
return Op;
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
+ SDValue Result = DAG.getAtomic(
+ ISD::ATOMIC_LOAD, SDLoc(N), N->getMemoryVT().getVectorElementType(),
+ N->getValueType(0).getVectorElementType(), N->getChain(),
N->getBasePtr(),
+ N->getMemOperand());
+
+ // Legalize the chain result - switch anything that used the old chain to
+ // use the new one.
+ ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
+ return Result;
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(N->isUnindexed() && "Indexed vector load?");
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 5bce4401f7bdb0..9cac8167542d8b 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -28,3 +28,12 @@ define i32 @test3(ptr %ptr) {
%val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
+
+define <1 x i32> @atomic_vec1_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movl (%rdi), %eax
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x i32>, ptr %x acquire, align 4
+ ret <1 x i32> %ret
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 3773e662b5a89f432705103279af9680ce9cf299 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 223 +
1 file changed, 223 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 2bde0d2ffd06ad..435e58bef6642d 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -110,3 +110,226 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
ret <1 x bfloat> %ret
}
+define <1 x i64> @atomic_vec1_i64(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i64:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:movq %rdi, %rsi
+; CHECK-NEXT:movq %rsp, %rdx
+; CHECK-NEXT:movl $8, %edi
+; CHECK-NEXT:movl $2, %ecx
+; CHECK-NEXT:callq ___atomic_load
+; CHECK-NEXT:movq (%rsp), %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:.cfi_def_cfa_offset 16
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) {
+; CHECK-LABEL: atomic_vec1_double:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:movq %rdi, %rsi
+; CHECK-NEXT:movq %rsp, %rdx
+; CHECK-NEXT:movl $8, %edi
+; CHECK-NEXT:movl $2, %ecx
+; CHECK-NEXT:callq ___atomic_load
+; CHECK-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:popq %rax
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:.cfi_def_cfa_offset 16
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec2_i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:movq %rdi, %rsi
+; CHECK-NEXT:movq %rsp, %rdx
+; CHECK-NEXT:movl $8, %edi
+; CHECK-NEXT:movl $2, %ecx
+; CHECK-NEXT:callq ___atomic_load
+; CHECK-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:popq %rax
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:.cfi_def_cfa_offset 16
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) {
+; CHECK-LABEL: atomic_vec4_float:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:subq $24, %rsp
+; CHECK-NEXT:.cfi_def_cfa_offset 32
+; CHECK-NEXT:movq %rdi, %rsi
+; CHECK-NEXT:movq %rsp, %rdx
+; CHECK-NEXT:movl $16, %edi
+; CHECK-NEXT:movl $2, %ecx
+; CHECK-NEXT:callq ___atomic_load
+; CHECK-NEXT:movaps (%rsp), %xmm0
+; CHECK-NEXT:addq $24, %rsp
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec4_float:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:subq $24, %rsp
+; CHECK0-NEXT:.cfi_def_cfa_offset 32
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $16, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movaps (%rsp), %xmm0
+; CHECK0-NEXT:addq $24, %rsp
+; CHECK0-NEXT:retq
+ %ret = load atomic <4 x float>, ptr %x acquire, align 4
+ ret <4 x float> %ret
+}
+
+define <8 x double> @atomic_vec8_double(ptr %x) {
+; CHECK-LABEL: atomic_vec8_double:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:subq $72, %rsp
+; CHECK-NEXT:.cfi_def_cfa_offset 80
+; CHECK-NEXT:movq %rdi, %rsi
+; CHECK-NEXT:movq %rsp, %rdx
+; CHECK-NEXT:movl $64, %edi
+; CHECK-NEXT:movl $2, %ecx
+; CHECK-NEXT:callq ___atomic_load
+; CHECK-NEXT:
[llvm-branch-commits] [llvm] [SelectionDAG][X86] Add floating point promotion. (PR #120386)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 141279f61705e146e742360603fc9a044f37fca6 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [SelectionDAG][X86] Add floating point promotion.
When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
commit-id:f9d761c5
---
llvm/lib/Target/X86/X86ISelLowering.cpp| 4 ++
llvm/test/CodeGen/X86/atomic-load-store.ll | 75 +-
2 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 2571873dba8483..8006d32d077a65 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2595,6 +2595,10 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
ISD::SCALAR_TO_VECTOR,
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 9cac8167542d8b..2bde0d2ffd06ad 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -1,12 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s --check-prefix=CHECK0
define void @test1(ptr %ptr, i32 %val1) {
; CHECK-LABEL: test1:
; CHECK: ## %bb.0:
; CHECK-NEXT:xchgl %esi, (%rdi)
; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: test1:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:xchgl %esi, (%rdi)
+; CHECK0-NEXT:retq
store atomic i32 %val1, ptr %ptr seq_cst, align 4
ret void
}
@@ -16,6 +21,11 @@ define void @test2(ptr %ptr, i32 %val1) {
; CHECK: ## %bb.0:
; CHECK-NEXT:movl %esi, (%rdi)
; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: test2:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movl %esi, (%rdi)
+; CHECK0-NEXT:retq
store atomic i32 %val1, ptr %ptr release, align 4
ret void
}
@@ -25,6 +35,11 @@ define i32 @test3(ptr %ptr) {
; CHECK: ## %bb.0:
; CHECK-NEXT:movl (%rdi), %eax
; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: test3:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movl (%rdi), %eax
+; CHECK0-NEXT:retq
%val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
@@ -34,6 +49,64 @@ define <1 x i32> @atomic_vec1_i32(ptr %x) {
; CHECK: ## %bb.0:
; CHECK-NEXT:movl (%rdi), %eax
; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movl (%rdi), %eax
+; CHECK0-NEXT:retq
%ret = load atomic <1 x i32>, ptr %x acquire, align 4
ret <1 x i32> %ret
}
+
+define <1 x half> @atomic_vec1_half(ptr %x) {
+; CHECK-LABEL: atomic_vec1_half:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movzwl (%rdi), %eax
+; CHECK-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_half:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x half>, ptr %x acquire, align 4
+ ret <1 x half> %ret
+}
+
+define <1 x float> @atomic_vec1_float(ptr %x) {
+; CHECK-LABEL: atomic_vec1_float:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_float:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x float>, ptr %x acquire, align 4
+ ret <1 x float> %ret
+}
+
+define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
+; CHECK-LABEL: atomic_vec1_bfloat:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movzwl (%rdi), %eax
+; CHECK-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_bfloat:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
+ ret <1 x bfloat> %re
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 3773e662b5a89f432705103279af9680ce9cf299 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 223 +
1 file changed, 223 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 2bde0d2ffd06ad..435e58bef6642d 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -110,3 +110,226 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
ret <1 x bfloat> %ret
}
+define <1 x i64> @atomic_vec1_i64(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i64:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:movq %rdi, %rsi
+; CHECK-NEXT:movq %rsp, %rdx
+; CHECK-NEXT:movl $8, %edi
+; CHECK-NEXT:movl $2, %ecx
+; CHECK-NEXT:callq ___atomic_load
+; CHECK-NEXT:movq (%rsp), %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:.cfi_def_cfa_offset 16
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) {
+; CHECK-LABEL: atomic_vec1_double:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:movq %rdi, %rsi
+; CHECK-NEXT:movq %rsp, %rdx
+; CHECK-NEXT:movl $8, %edi
+; CHECK-NEXT:movl $2, %ecx
+; CHECK-NEXT:callq ___atomic_load
+; CHECK-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:popq %rax
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:.cfi_def_cfa_offset 16
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec2_i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:movq %rdi, %rsi
+; CHECK-NEXT:movq %rsp, %rdx
+; CHECK-NEXT:movl $8, %edi
+; CHECK-NEXT:movl $2, %ecx
+; CHECK-NEXT:callq ___atomic_load
+; CHECK-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:popq %rax
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:.cfi_def_cfa_offset 16
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) {
+; CHECK-LABEL: atomic_vec4_float:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:subq $24, %rsp
+; CHECK-NEXT:.cfi_def_cfa_offset 32
+; CHECK-NEXT:movq %rdi, %rsi
+; CHECK-NEXT:movq %rsp, %rdx
+; CHECK-NEXT:movl $16, %edi
+; CHECK-NEXT:movl $2, %ecx
+; CHECK-NEXT:callq ___atomic_load
+; CHECK-NEXT:movaps (%rsp), %xmm0
+; CHECK-NEXT:addq $24, %rsp
+; CHECK-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec4_float:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:subq $24, %rsp
+; CHECK0-NEXT:.cfi_def_cfa_offset 32
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $16, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movaps (%rsp), %xmm0
+; CHECK0-NEXT:addq $24, %rsp
+; CHECK0-NEXT:retq
+ %ret = load atomic <4 x float>, ptr %x acquire, align 4
+ ret <4 x float> %ret
+}
+
+define <8 x double> @atomic_vec8_double(ptr %x) {
+; CHECK-LABEL: atomic_vec8_double:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:subq $72, %rsp
+; CHECK-NEXT:.cfi_def_cfa_offset 80
+; CHECK-NEXT:movq %rdi, %rsi
+; CHECK-NEXT:movq %rsp, %rdx
+; CHECK-NEXT:movl $64, %edi
+; CHECK-NEXT:movl $2, %ecx
+; CHECK-NEXT:callq ___atomic_load
+; CHECK-NEXT:
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)
https://github.com/optimisan converted_to_draft https://github.com/llvm/llvm-project/pull/119540 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 813fffe3965e96b9dce5ca5d1640d8bfd041e5d7 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 238 +
1 file changed, 238 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 39c54c3df15c7a..90eaed8150a559 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -109,6 +109,34 @@ define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr
%x) {
ret <1 x ptr addrspace(270)> %ret
}
+define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_ptr:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_ptr:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x ptr>, ptr %x acquire, align 4
+ ret <1 x ptr> %ret
+}
+
define <1 x half> @atomic_vec1_half(ptr %x) {
; CHECK3-LABEL: atomic_vec1_half:
; CHECK3: ## %bb.0:
@@ -155,3 +183,213 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
%ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
ret <1 x bfloat> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_double:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_i32:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec4_float:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:subq $24, %rsp
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $16, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movaps (%rsp), %xm
[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 70bb5b9e2b2bea40974d2db1a4c3b65e542a5516 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
commit-id:f9d761c5
---
llvm/lib/Target/X86/X86ISelLowering.cpp| 4 ++
llvm/test/CodeGen/X86/atomic-load-store.ll | 47 ++
2 files changed, 51 insertions(+)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index ad5e2e7ea83bbb..4c21cbc375090c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2595,6 +2595,10 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
ISD::SCALAR_TO_VECTOR,
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 8cb2e79d66f673..39c54c3df15c7a 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -108,3 +108,50 @@ define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr
%x) {
%ret = load atomic <1 x ptr addrspace(270)>, ptr %x acquire, align 4
ret <1 x ptr addrspace(270)> %ret
}
+
+define <1 x half> @atomic_vec1_half(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_half:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_half:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x half>, ptr %x acquire, align 4
+ ret <1 x half> %ret
+}
+
+define <1 x float> @atomic_vec1_float(ptr %x) {
+; CHECK-LABEL: atomic_vec1_float:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x float>, ptr %x acquire, align 4
+ ret <1 x float> %ret
+}
+
+define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_bfloat:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_bfloat:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
+ ret <1 x bfloat> %ret
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 726354562d08de91f5a12b93764d5eaceb007052 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic <1 x T>` is not valid. This change legalizes vector types of
atomic load via scalarization in SelectionDAG so that it can, for example,
translate from `v1i32` to `i32`.
commit-id:5c36cc8c
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 15
llvm/test/CodeGen/X86/atomic-load-store.ll| 84 ++-
3 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 571a710cc92a34..b81c9f87cb27d7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -861,6 +861,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ScalarizeVecRes_ExpOp(SDNode *N);
SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
+ SDValue ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N);
SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
SDValue ScalarizeVecRes_VSELECT(SDNode *N);
SDValue ScalarizeVecRes_SELECT(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 107454a92e356c..c85e4ba2cfa5a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -60,6 +60,9 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N,
unsigned ResNo) {
case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
case ISD::FPOWI: R = ScalarizeVecRes_ExpOp(N); break;
case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
+ case ISD::ATOMIC_LOAD:
+R = ScalarizeVecRes_ATOMIC_LOAD(cast(N));
+break;
case ISD::LOAD: R =
ScalarizeVecRes_LOAD(cast(N));break;
case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
@@ -451,6 +454,18 @@ SDValue
DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
return Op;
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
+ SDValue Result = DAG.getAtomic(
+ ISD::ATOMIC_LOAD, SDLoc(N), N->getMemoryVT().getVectorElementType(),
+ N->getValueType(0).getVectorElementType(), N->getChain(),
N->getBasePtr(),
+ N->getMemOperand());
+
+ // Legalize the chain result - switch anything that used the old chain to
+ // use the new one.
+ ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
+ return Result;
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(N->isUnindexed() && "Indexed vector load?");
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 5bce4401f7bdb0..8cb2e79d66f673 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s --check-prefixes=CHECK,CHECK3
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s --check-prefixes=CHECK,CHECK0
define void @test1(ptr %ptr, i32 %val1) {
; CHECK-LABEL: test1:
@@ -28,3 +28,83 @@ define i32 @test3(ptr %ptr) {
%val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
+
+define <1 x i32> @atomic_vec1_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movl (%rdi), %eax
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x i32>, ptr %x acquire, align 4
+ ret <1 x i32> %ret
+}
+
+define <1 x i8> @atomic_vec1_i8(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i8:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzbl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i8:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movb (%rdi), %al
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i8>, ptr %x acquire, align 4
+ ret <1 x i8> %ret
+}
+
+define <1 x i16> @atomic_vec1_i16(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i16:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i16:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %ax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i16>, ptr %x acquire, align 4
+ ret <1 x i16> %ret
+}
+
+define <1 x
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 813fffe3965e96b9dce5ca5d1640d8bfd041e5d7 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 238 +
1 file changed, 238 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 39c54c3df15c7a..90eaed8150a559 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -109,6 +109,34 @@ define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr
%x) {
ret <1 x ptr addrspace(270)> %ret
}
+define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_ptr:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_ptr:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x ptr>, ptr %x acquire, align 4
+ ret <1 x ptr> %ret
+}
+
define <1 x half> @atomic_vec1_half(ptr %x) {
; CHECK3-LABEL: atomic_vec1_half:
; CHECK3: ## %bb.0:
@@ -155,3 +183,213 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
%ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
ret <1 x bfloat> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_double:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_i32:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec4_float:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:subq $24, %rsp
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $16, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movaps (%rsp), %xm
[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 726354562d08de91f5a12b93764d5eaceb007052 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic <1 x T>` is not valid. This change legalizes vector types of
atomic load via scalarization in SelectionDAG so that it can, for example,
translate from `v1i32` to `i32`.
commit-id:5c36cc8c
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 15
llvm/test/CodeGen/X86/atomic-load-store.ll| 84 ++-
3 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 571a710cc92a34..b81c9f87cb27d7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -861,6 +861,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ScalarizeVecRes_ExpOp(SDNode *N);
SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
+ SDValue ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N);
SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
SDValue ScalarizeVecRes_VSELECT(SDNode *N);
SDValue ScalarizeVecRes_SELECT(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 107454a92e356c..c85e4ba2cfa5a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -60,6 +60,9 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N,
unsigned ResNo) {
case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
case ISD::FPOWI: R = ScalarizeVecRes_ExpOp(N); break;
case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
+ case ISD::ATOMIC_LOAD:
+R = ScalarizeVecRes_ATOMIC_LOAD(cast(N));
+break;
case ISD::LOAD: R =
ScalarizeVecRes_LOAD(cast(N));break;
case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
@@ -451,6 +454,18 @@ SDValue
DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
return Op;
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
+ SDValue Result = DAG.getAtomic(
+ ISD::ATOMIC_LOAD, SDLoc(N), N->getMemoryVT().getVectorElementType(),
+ N->getValueType(0).getVectorElementType(), N->getChain(),
N->getBasePtr(),
+ N->getMemOperand());
+
+ // Legalize the chain result - switch anything that used the old chain to
+ // use the new one.
+ ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
+ return Result;
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(N->isUnindexed() && "Indexed vector load?");
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 5bce4401f7bdb0..8cb2e79d66f673 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s --check-prefixes=CHECK,CHECK3
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s --check-prefixes=CHECK,CHECK0
define void @test1(ptr %ptr, i32 %val1) {
; CHECK-LABEL: test1:
@@ -28,3 +28,83 @@ define i32 @test3(ptr %ptr) {
%val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
+
+define <1 x i32> @atomic_vec1_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movl (%rdi), %eax
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x i32>, ptr %x acquire, align 4
+ ret <1 x i32> %ret
+}
+
+define <1 x i8> @atomic_vec1_i8(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i8:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzbl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i8:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movb (%rdi), %al
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i8>, ptr %x acquire, align 4
+ ret <1 x i8> %ret
+}
+
+define <1 x i16> @atomic_vec1_i16(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i16:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i16:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %ax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i16>, ptr %x acquire, align 4
+ ret <1 x i16> %ret
+}
+
+define <1 x
[llvm-branch-commits] [clang] release/19.x: [clang-format] Fix idempotent format of hash in macro body (#118513) (PR #119503)
https://github.com/HazardyKnusperkeks approved this pull request. https://github.com/llvm/llvm-project/pull/119503 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 00f4bf5 - Revert "LLVMContext: Cleanup registration of known bundle IDs (#120359)"
Author: Jan Patrick Lehr
Date: 2024-12-18T10:58:55+01:00
New Revision: 00f4bf5a582298ec942d86bf69571dfe66354598
URL:
https://github.com/llvm/llvm-project/commit/00f4bf5a582298ec942d86bf69571dfe66354598
DIFF:
https://github.com/llvm/llvm-project/commit/00f4bf5a582298ec942d86bf69571dfe66354598.diff
LOG: Revert "LLVMContext: Cleanup registration of known bundle IDs (#120359)"
This reverts commit 3666de9c8e3bfd3a3b604e0e434341ec49cb3a6d.
Added:
Modified:
llvm/lib/IR/LLVMContext.cpp
Removed:
diff --git a/llvm/lib/IR/LLVMContext.cpp b/llvm/lib/IR/LLVMContext.cpp
index 9acc15f11316a2..eb51a751bfa088 100644
--- a/llvm/lib/IR/LLVMContext.cpp
+++ b/llvm/lib/IR/LLVMContext.cpp
@@ -31,35 +31,6 @@
using namespace llvm;
-static constexpr StringRef knownBundleName(unsigned BundleTagID) {
- switch (BundleTagID) {
- case LLVMContext::OB_deopt:
-return "deopt";
- case LLVMContext::OB_funclet:
-return "funclet";
- case LLVMContext::OB_gc_transition:
-return "gc-transition";
- case LLVMContext::OB_cfguardtarget:
-return "cfguardtarget";
- case LLVMContext::OB_preallocated:
-return "preallocated";
- case LLVMContext::OB_gc_live:
-return "gc-live";
- case LLVMContext::OB_clang_arc_attachedcall:
-return "clang.arc.attachedcall";
- case LLVMContext::OB_ptrauth:
-return "ptrauth";
- case LLVMContext::OB_kcfi:
-return "kcfi";
- case LLVMContext::OB_convergencectrl:
-return "convergencectrl";
- default:
-llvm_unreachable("unknown bundle id");
- }
-
- llvm_unreachable("covered switch");
-}
-
LLVMContext::LLVMContext() : pImpl(new LLVMContextImpl(*this)) {
// Create the fixed metadata kinds. This is done in the same order as the
// MD_* enum values so that they correspond.
@@ -75,12 +46,56 @@ LLVMContext::LLVMContext() : pImpl(new
LLVMContextImpl(*this)) {
(void)ID;
}
- for (unsigned BundleTagID = LLVMContext::OB_deopt;
- BundleTagID <= LLVMContext::OB_convergencectrl; ++BundleTagID) {
-[[maybe_unused]] const auto *Entry =
-pImpl->getOrInsertBundleTag(knownBundleName(BundleTagID));
-assert(Entry->second == BundleTagID && "operand bundle id drifted!");
- }
+ auto *DeoptEntry = pImpl->getOrInsertBundleTag("deopt");
+ assert(DeoptEntry->second == LLVMContext::OB_deopt &&
+ "deopt operand bundle id drifted!");
+ (void)DeoptEntry;
+
+ auto *FuncletEntry = pImpl->getOrInsertBundleTag("funclet");
+ assert(FuncletEntry->second == LLVMContext::OB_funclet &&
+ "funclet operand bundle id drifted!");
+ (void)FuncletEntry;
+
+ auto *GCTransitionEntry = pImpl->getOrInsertBundleTag("gc-transition");
+ assert(GCTransitionEntry->second == LLVMContext::OB_gc_transition &&
+ "gc-transition operand bundle id drifted!");
+ (void)GCTransitionEntry;
+
+ auto *CFGuardTargetEntry = pImpl->getOrInsertBundleTag("cfguardtarget");
+ assert(CFGuardTargetEntry->second == LLVMContext::OB_cfguardtarget &&
+ "cfguardtarget operand bundle id drifted!");
+ (void)CFGuardTargetEntry;
+
+ auto *PreallocatedEntry = pImpl->getOrInsertBundleTag("preallocated");
+ assert(PreallocatedEntry->second == LLVMContext::OB_preallocated &&
+ "preallocated operand bundle id drifted!");
+ (void)PreallocatedEntry;
+
+ auto *GCLiveEntry = pImpl->getOrInsertBundleTag("gc-live");
+ assert(GCLiveEntry->second == LLVMContext::OB_gc_live &&
+ "gc-transition operand bundle id drifted!");
+ (void)GCLiveEntry;
+
+ auto *ClangAttachedCall =
+ pImpl->getOrInsertBundleTag("clang.arc.attachedcall");
+ assert(ClangAttachedCall->second == LLVMContext::OB_clang_arc_attachedcall &&
+ "clang.arc.attachedcall operand bundle id drifted!");
+ (void)ClangAttachedCall;
+
+ auto *PtrauthEntry = pImpl->getOrInsertBundleTag("ptrauth");
+ assert(PtrauthEntry->second == LLVMContext::OB_ptrauth &&
+ "ptrauth operand bundle id drifted!");
+ (void)PtrauthEntry;
+
+ auto *KCFIEntry = pImpl->getOrInsertBundleTag("kcfi");
+ assert(KCFIEntry->second == LLVMContext::OB_kcfi &&
+ "kcfi operand bundle id drifted!");
+ (void)KCFIEntry;
+
+ auto *ConvergenceCtrlEntry = pImpl->getOrInsertBundleTag("convergencectrl");
+ assert(ConvergenceCtrlEntry->second == LLVMContext::OB_convergencectrl &&
+ "convergencectrl operand bundle id drifted!");
+ (void)ConvergenceCtrlEntry;
SyncScope::ID SingleThreadSSID =
pImpl->getOrInsertSyncScopeID("singlethread");
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
@@ -110,3 +110,226 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
ret <1 x bfloat> %ret
}
+define <1 x i64> @atomic_vec1_i64(ptr %x) {
RKSimon wrote:
add nounwind to get rid of cfi noise
https://github.com/llvm/llvm-project/pull/120387
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [ubsan] Runtime and driver support for local-bounds (PR #120515)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/120515 Implements ``-f[no-]sanitize-trap=local-bounds``, and ``-f[no-]sanitize-recover=local-bounds``. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [ubsan] Runtime and driver support for local-bounds (PR #120515)
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
Implements ``-f[no-]sanitize-trap=local-bounds``,
and ``-f[no-]sanitize-recover=local-bounds``.
---
Full diff: https://github.com/llvm/llvm-project/pull/120515.diff
11 Files Affected:
- (modified) clang/docs/ReleaseNotes.rst (+2)
- (modified) clang/lib/CodeGen/BackendUtil.cpp (+14-3)
- (modified) clang/lib/Driver/SanitizerArgs.cpp (+5-4)
- (modified) clang/test/CodeGen/bounds-checking.c (+1-1)
- (modified) compiler-rt/lib/ubsan/ubsan_checks.inc (+1)
- (modified) compiler-rt/lib/ubsan/ubsan_handlers.cpp (+22)
- (modified) compiler-rt/lib/ubsan/ubsan_handlers.h (+3)
- (modified) compiler-rt/lib/ubsan/ubsan_interface.inc (+2)
- (modified) compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp (+1)
- (modified) compiler-rt/test/ubsan/TestCases/Misc/local_bounds.cpp (+8-3)
- (modified) compiler-rt/test/ubsan_minimal/TestCases/local_bounds.cpp (+3-2)
``diff
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 29794f27d30057..5bbc6f67674b52 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1199,6 +1199,8 @@ Sanitizers
``-fsanitize=type`` flag. This sanitizer detects violations of C/C++
type-based
aliasing rules.
+- Implemented ``-f[no-]sanitize-trap=local-bounds``, and
``-f[no-]sanitize-recover=local-bounds``.
+
Python Binding Changes
--
- Fixed an issue that led to crashes when calling
``Type.get_exception_specification_kind``.
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index b1003f2ce5032e..e6c9d77d29f6f1 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -1028,9 +1028,20 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
// of the pipeline.
if (LangOpts.Sanitize.has(SanitizerKind::LocalBounds))
PB.registerScalarOptimizerLateEPCallback(
- [](FunctionPassManager &FPM, OptimizationLevel Level) {
-FPM.addPass(
-BoundsCheckingPass(BoundsCheckingPass::ReportingMode::Trap));
+ [this](FunctionPassManager &FPM, OptimizationLevel Level) {
+BoundsCheckingPass::ReportingMode Mode;
+if (CodeGenOpts.SanitizeTrap.has(SanitizerKind::LocalBounds)) {
+ Mode = BoundsCheckingPass::ReportingMode::Trap;
+} else if (CodeGenOpts.SanitizeMinimalRuntime) {
+ Mode =
CodeGenOpts.SanitizeRecover.has(SanitizerKind::LocalBounds)
+ ? BoundsCheckingPass::ReportingMode::MinRuntime
+ : BoundsCheckingPass::ReportingMode::MinRuntimeAbort;
+} else {
+ Mode =
CodeGenOpts.SanitizeRecover.has(SanitizerKind::LocalBounds)
+ ? BoundsCheckingPass::ReportingMode::FullRuntime
+ : BoundsCheckingPass::ReportingMode::FullRuntimeAbort;
+}
+FPM.addPass(BoundsCheckingPass(Mode));
});
// Don't add sanitizers if we are here from ThinLTO PostLink. That already
diff --git a/clang/lib/Driver/SanitizerArgs.cpp
b/clang/lib/Driver/SanitizerArgs.cpp
index 0edfe641416129..0e777c1647f526 100644
--- a/clang/lib/Driver/SanitizerArgs.cpp
+++ b/clang/lib/Driver/SanitizerArgs.cpp
@@ -27,9 +27,9 @@ using namespace llvm::opt;
static const SanitizerMask NeedsUbsanRt =
SanitizerKind::Undefined | SanitizerKind::Integer |
-SanitizerKind::ImplicitConversion | SanitizerKind::Nullability |
-SanitizerKind::CFI | SanitizerKind::FloatDivideByZero |
-SanitizerKind::ObjCCast;
+SanitizerKind::LocalBounds | SanitizerKind::ImplicitConversion |
+SanitizerKind::Nullability | SanitizerKind::CFI |
+SanitizerKind::FloatDivideByZero | SanitizerKind::ObjCCast;
static const SanitizerMask NeedsUbsanCxxRt =
SanitizerKind::Vptr | SanitizerKind::CFI;
static const SanitizerMask NotAllowedWithTrap = SanitizerKind::Vptr;
@@ -68,7 +68,8 @@ static const SanitizerMask TrappingSupported =
SanitizerKind::ImplicitConversion | SanitizerKind::Nullability |
SanitizerKind::LocalBounds | SanitizerKind::CFI |
SanitizerKind::FloatDivideByZero | SanitizerKind::ObjCCast;
-static const SanitizerMask TrappingDefault = SanitizerKind::CFI;
+static const SanitizerMask TrappingDefault =
+SanitizerKind::CFI | SanitizerKind::LocalBounds;
static const SanitizerMask CFIClasses =
SanitizerKind::CFIVCall | SanitizerKind::CFINVCall |
SanitizerKind::CFIMFCall | SanitizerKind::CFIDerivedCast |
diff --git a/clang/test/CodeGen/bounds-checking.c
b/clang/test/CodeGen/bounds-checking.c
index f6c4880e70a150..4d862c693652bb 100644
--- a/clang/test/CodeGen/bounds-checking.c
+++ b/clang/test/CodeGen/bounds-checking.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fsanitize=local-bounds -emit-llvm -triple
x86_64-apple-darwin10 %s -o - | FileCheck %s
+// RUN: %clang_cc1 -fsanitize=local-bounds -fsanitize-
[llvm-branch-commits] [ubsan] Runtime and driver support for local-bounds (PR #120515)
llvmbot wrote:
@llvm/pr-subscribers-clang-driver
Author: Vitaly Buka (vitalybuka)
Changes
Implements ``-f[no-]sanitize-trap=local-bounds``,
and ``-f[no-]sanitize-recover=local-bounds``.
---
Full diff: https://github.com/llvm/llvm-project/pull/120515.diff
11 Files Affected:
- (modified) clang/docs/ReleaseNotes.rst (+2)
- (modified) clang/lib/CodeGen/BackendUtil.cpp (+14-3)
- (modified) clang/lib/Driver/SanitizerArgs.cpp (+5-4)
- (modified) clang/test/CodeGen/bounds-checking.c (+1-1)
- (modified) compiler-rt/lib/ubsan/ubsan_checks.inc (+1)
- (modified) compiler-rt/lib/ubsan/ubsan_handlers.cpp (+22)
- (modified) compiler-rt/lib/ubsan/ubsan_handlers.h (+3)
- (modified) compiler-rt/lib/ubsan/ubsan_interface.inc (+2)
- (modified) compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp (+1)
- (modified) compiler-rt/test/ubsan/TestCases/Misc/local_bounds.cpp (+8-3)
- (modified) compiler-rt/test/ubsan_minimal/TestCases/local_bounds.cpp (+3-2)
``diff
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 29794f27d30057..5bbc6f67674b52 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1199,6 +1199,8 @@ Sanitizers
``-fsanitize=type`` flag. This sanitizer detects violations of C/C++
type-based
aliasing rules.
+- Implemented ``-f[no-]sanitize-trap=local-bounds``, and
``-f[no-]sanitize-recover=local-bounds``.
+
Python Binding Changes
--
- Fixed an issue that led to crashes when calling
``Type.get_exception_specification_kind``.
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index b1003f2ce5032e..e6c9d77d29f6f1 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -1028,9 +1028,20 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
// of the pipeline.
if (LangOpts.Sanitize.has(SanitizerKind::LocalBounds))
PB.registerScalarOptimizerLateEPCallback(
- [](FunctionPassManager &FPM, OptimizationLevel Level) {
-FPM.addPass(
-BoundsCheckingPass(BoundsCheckingPass::ReportingMode::Trap));
+ [this](FunctionPassManager &FPM, OptimizationLevel Level) {
+BoundsCheckingPass::ReportingMode Mode;
+if (CodeGenOpts.SanitizeTrap.has(SanitizerKind::LocalBounds)) {
+ Mode = BoundsCheckingPass::ReportingMode::Trap;
+} else if (CodeGenOpts.SanitizeMinimalRuntime) {
+ Mode =
CodeGenOpts.SanitizeRecover.has(SanitizerKind::LocalBounds)
+ ? BoundsCheckingPass::ReportingMode::MinRuntime
+ : BoundsCheckingPass::ReportingMode::MinRuntimeAbort;
+} else {
+ Mode =
CodeGenOpts.SanitizeRecover.has(SanitizerKind::LocalBounds)
+ ? BoundsCheckingPass::ReportingMode::FullRuntime
+ : BoundsCheckingPass::ReportingMode::FullRuntimeAbort;
+}
+FPM.addPass(BoundsCheckingPass(Mode));
});
// Don't add sanitizers if we are here from ThinLTO PostLink. That already
diff --git a/clang/lib/Driver/SanitizerArgs.cpp
b/clang/lib/Driver/SanitizerArgs.cpp
index 0edfe641416129..0e777c1647f526 100644
--- a/clang/lib/Driver/SanitizerArgs.cpp
+++ b/clang/lib/Driver/SanitizerArgs.cpp
@@ -27,9 +27,9 @@ using namespace llvm::opt;
static const SanitizerMask NeedsUbsanRt =
SanitizerKind::Undefined | SanitizerKind::Integer |
-SanitizerKind::ImplicitConversion | SanitizerKind::Nullability |
-SanitizerKind::CFI | SanitizerKind::FloatDivideByZero |
-SanitizerKind::ObjCCast;
+SanitizerKind::LocalBounds | SanitizerKind::ImplicitConversion |
+SanitizerKind::Nullability | SanitizerKind::CFI |
+SanitizerKind::FloatDivideByZero | SanitizerKind::ObjCCast;
static const SanitizerMask NeedsUbsanCxxRt =
SanitizerKind::Vptr | SanitizerKind::CFI;
static const SanitizerMask NotAllowedWithTrap = SanitizerKind::Vptr;
@@ -68,7 +68,8 @@ static const SanitizerMask TrappingSupported =
SanitizerKind::ImplicitConversion | SanitizerKind::Nullability |
SanitizerKind::LocalBounds | SanitizerKind::CFI |
SanitizerKind::FloatDivideByZero | SanitizerKind::ObjCCast;
-static const SanitizerMask TrappingDefault = SanitizerKind::CFI;
+static const SanitizerMask TrappingDefault =
+SanitizerKind::CFI | SanitizerKind::LocalBounds;
static const SanitizerMask CFIClasses =
SanitizerKind::CFIVCall | SanitizerKind::CFINVCall |
SanitizerKind::CFIMFCall | SanitizerKind::CFIDerivedCast |
diff --git a/clang/test/CodeGen/bounds-checking.c
b/clang/test/CodeGen/bounds-checking.c
index f6c4880e70a150..4d862c693652bb 100644
--- a/clang/test/CodeGen/bounds-checking.c
+++ b/clang/test/CodeGen/bounds-checking.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fsanitize=local-bounds -emit-llvm -triple
x86_64-apple-darwin10 %s -o - | FileCheck %s
+// RUN: %clang_cc1 -fsanitize=local-bounds -fsanitize-trap=loca
[llvm-branch-commits] [ubsan] Runtime and driver support for local-bounds (PR #120515)
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: Vitaly Buka (vitalybuka)
Changes
Implements ``-f[no-]sanitize-trap=local-bounds``,
and ``-f[no-]sanitize-recover=local-bounds``.
---
Full diff: https://github.com/llvm/llvm-project/pull/120515.diff
11 Files Affected:
- (modified) clang/docs/ReleaseNotes.rst (+2)
- (modified) clang/lib/CodeGen/BackendUtil.cpp (+14-3)
- (modified) clang/lib/Driver/SanitizerArgs.cpp (+5-4)
- (modified) clang/test/CodeGen/bounds-checking.c (+1-1)
- (modified) compiler-rt/lib/ubsan/ubsan_checks.inc (+1)
- (modified) compiler-rt/lib/ubsan/ubsan_handlers.cpp (+22)
- (modified) compiler-rt/lib/ubsan/ubsan_handlers.h (+3)
- (modified) compiler-rt/lib/ubsan/ubsan_interface.inc (+2)
- (modified) compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp (+1)
- (modified) compiler-rt/test/ubsan/TestCases/Misc/local_bounds.cpp (+8-3)
- (modified) compiler-rt/test/ubsan_minimal/TestCases/local_bounds.cpp (+3-2)
``diff
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 29794f27d30057..5bbc6f67674b52 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1199,6 +1199,8 @@ Sanitizers
``-fsanitize=type`` flag. This sanitizer detects violations of C/C++
type-based
aliasing rules.
+- Implemented ``-f[no-]sanitize-trap=local-bounds``, and
``-f[no-]sanitize-recover=local-bounds``.
+
Python Binding Changes
--
- Fixed an issue that led to crashes when calling
``Type.get_exception_specification_kind``.
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index b1003f2ce5032e..e6c9d77d29f6f1 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -1028,9 +1028,20 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
// of the pipeline.
if (LangOpts.Sanitize.has(SanitizerKind::LocalBounds))
PB.registerScalarOptimizerLateEPCallback(
- [](FunctionPassManager &FPM, OptimizationLevel Level) {
-FPM.addPass(
-BoundsCheckingPass(BoundsCheckingPass::ReportingMode::Trap));
+ [this](FunctionPassManager &FPM, OptimizationLevel Level) {
+BoundsCheckingPass::ReportingMode Mode;
+if (CodeGenOpts.SanitizeTrap.has(SanitizerKind::LocalBounds)) {
+ Mode = BoundsCheckingPass::ReportingMode::Trap;
+} else if (CodeGenOpts.SanitizeMinimalRuntime) {
+ Mode =
CodeGenOpts.SanitizeRecover.has(SanitizerKind::LocalBounds)
+ ? BoundsCheckingPass::ReportingMode::MinRuntime
+ : BoundsCheckingPass::ReportingMode::MinRuntimeAbort;
+} else {
+ Mode =
CodeGenOpts.SanitizeRecover.has(SanitizerKind::LocalBounds)
+ ? BoundsCheckingPass::ReportingMode::FullRuntime
+ : BoundsCheckingPass::ReportingMode::FullRuntimeAbort;
+}
+FPM.addPass(BoundsCheckingPass(Mode));
});
// Don't add sanitizers if we are here from ThinLTO PostLink. That already
diff --git a/clang/lib/Driver/SanitizerArgs.cpp
b/clang/lib/Driver/SanitizerArgs.cpp
index 0edfe641416129..0e777c1647f526 100644
--- a/clang/lib/Driver/SanitizerArgs.cpp
+++ b/clang/lib/Driver/SanitizerArgs.cpp
@@ -27,9 +27,9 @@ using namespace llvm::opt;
static const SanitizerMask NeedsUbsanRt =
SanitizerKind::Undefined | SanitizerKind::Integer |
-SanitizerKind::ImplicitConversion | SanitizerKind::Nullability |
-SanitizerKind::CFI | SanitizerKind::FloatDivideByZero |
-SanitizerKind::ObjCCast;
+SanitizerKind::LocalBounds | SanitizerKind::ImplicitConversion |
+SanitizerKind::Nullability | SanitizerKind::CFI |
+SanitizerKind::FloatDivideByZero | SanitizerKind::ObjCCast;
static const SanitizerMask NeedsUbsanCxxRt =
SanitizerKind::Vptr | SanitizerKind::CFI;
static const SanitizerMask NotAllowedWithTrap = SanitizerKind::Vptr;
@@ -68,7 +68,8 @@ static const SanitizerMask TrappingSupported =
SanitizerKind::ImplicitConversion | SanitizerKind::Nullability |
SanitizerKind::LocalBounds | SanitizerKind::CFI |
SanitizerKind::FloatDivideByZero | SanitizerKind::ObjCCast;
-static const SanitizerMask TrappingDefault = SanitizerKind::CFI;
+static const SanitizerMask TrappingDefault =
+SanitizerKind::CFI | SanitizerKind::LocalBounds;
static const SanitizerMask CFIClasses =
SanitizerKind::CFIVCall | SanitizerKind::CFINVCall |
SanitizerKind::CFIMFCall | SanitizerKind::CFIDerivedCast |
diff --git a/clang/test/CodeGen/bounds-checking.c
b/clang/test/CodeGen/bounds-checking.c
index f6c4880e70a150..4d862c693652bb 100644
--- a/clang/test/CodeGen/bounds-checking.c
+++ b/clang/test/CodeGen/bounds-checking.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fsanitize=local-bounds -emit-llvm -triple
x86_64-apple-darwin10 %s -o - | FileCheck %s
+// RUN: %clang_cc1 -fsanitize=local-bounds -fsanitize-trap=loc
[llvm-branch-commits] [clang] [llvm] [Coverage] Make additional counters available for BranchRegion. NFC. (PR #112730)
@@ -1193,11 +1206,26 @@ std::pair
CodeGenPGO::getIsCounterPair(const Stmt *S) const {
}
void CodeGenPGO::emitCounterSetOrIncrement(CGBuilderTy &Builder, const Stmt *S,
+ bool UseSkipPath, bool UseBoth,
llvm::Value *StepV) {
- if (!RegionCounterMap || !Builder.GetInsertBlock())
+ if (!RegionCounterMap)
return;
- unsigned Counter = (*RegionCounterMap)[S].first;
+ unsigned Counter;
+ auto &TheMap = (*RegionCounterMap)[S];
ornata wrote:
static_cast?
https://github.com/llvm/llvm-project/pull/112730
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [Coverage] Make additional counters available for BranchRegion. NFC. (PR #112730)
@@ -1193,11 +1206,26 @@ std::pair
CodeGenPGO::getIsCounterPair(const Stmt *S) const {
}
void CodeGenPGO::emitCounterSetOrIncrement(CGBuilderTy &Builder, const Stmt *S,
+ bool UseSkipPath, bool UseBoth,
llvm::Value *StepV) {
- if (!RegionCounterMap || !Builder.GetInsertBlock())
+ if (!RegionCounterMap)
return;
- unsigned Counter = (*RegionCounterMap)[S].first;
+ unsigned Counter;
+ auto &TheMap = (*RegionCounterMap)[S];
+ auto IsCounter = TheMap.getIsCounterPair();
+ if (!UseSkipPath) {
+if (!IsCounter.first)
+ return;
+Counter = (TheMap.first & CounterPair::Mask);
ornata wrote:
This patch introduces a lot of code like
```
(X & CounterPair::Mask)
```
Would it make sense to create a small helper function to do this?
https://github.com/llvm/llvm-project/pull/112730
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/119194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)
wangpc-pp wrote: closed as it has been splitted into several small patches. https://github.com/llvm/llvm-project/pull/119194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [Coverage] Make additional counters available for BranchRegion. NFC. (PR #112730)
@@ -1193,11 +1206,26 @@ std::pair
CodeGenPGO::getIsCounterPair(const Stmt *S) const {
}
void CodeGenPGO::emitCounterSetOrIncrement(CGBuilderTy &Builder, const Stmt *S,
+ bool UseSkipPath, bool UseBoth,
llvm::Value *StepV) {
- if (!RegionCounterMap || !Builder.GetInsertBlock())
+ if (!RegionCounterMap)
return;
- unsigned Counter = (*RegionCounterMap)[S].first;
+ unsigned Counter;
+ auto &TheMap = (*RegionCounterMap)[S];
+ auto IsCounter = TheMap.getIsCounterPair();
+ if (!UseSkipPath) {
+if (!IsCounter.first)
+ return;
+Counter = (TheMap.first & CounterPair::Mask);
+ } else {
+if (!IsCounter.second)
+ return;
+Counter = (TheMap.second & CounterPair::Mask);
+ }
+
+ if (!Builder.GetInsertBlock())
ornata wrote:
When can this happen? Comment?
https://github.com/llvm/llvm-project/pull/112730
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [Coverage] Make additional counters available for BranchRegion. NFC. (PR #112730)
@@ -112,6 +112,7 @@ class CodeGenPGO {
public:
std::pair getIsCounterPair(const Stmt *S) const;
ornata wrote:
I think this function could use some documentation, or a better name.
This can happen in a later commit.
https://github.com/llvm/llvm-project/pull/112730
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
@@ -155,3 +183,214 @@ define <1 x float> @atomic_vec1_float(ptr %x) {
%ret = load atomic <1 x float>, ptr %x acquire, align 4
ret <1 x float> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
arsenm wrote:
Same, another under aligned case
https://github.com/llvm/llvm-project/pull/120387
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [Coverage] Make additional counters available for BranchRegion. NFC. (PR #112730)
@@ -887,6 +887,9 @@ struct CounterCoverageMappingBuilder /// The map of statements to count values. llvm::DenseMap &CounterMap; + CounterExpressionBuilder::ReplaceMap MapToExpand; + unsigned NextCounterNum; ornata wrote: Explicitly initialize to 0? https://github.com/llvm/llvm-project/pull/112730 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
@@ -155,3 +183,214 @@ define <1 x float> @atomic_vec1_float(ptr %x) {
%ret = load atomic <1 x float>, ptr %x acquire, align 4
ret <1 x float> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_double:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
arsenm wrote:
these are all under aligned
https://github.com/llvm/llvm-project/pull/120387
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][BoundsChecking] Switch HandlerBuilder to CRTP (PR #120506)
https://github.com/vitalybuka converted_to_draft https://github.com/llvm/llvm-project/pull/120506 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC][BoundsChecking] Prepare code for CRTP for ReportingMode (PR #119983)
https://github.com/vitalybuka converted_to_draft https://github.com/llvm/llvm-project/pull/119983 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 4d3fcb3a0279d9aac8e43acd7060e89115324ba2 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic <1 x T>` is not valid. This change legalizes
vector types of atomic load via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.
commit-id:5c36cc8c
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 15 +++
llvm/test/CodeGen/X86/atomic-load-store.ll| 103 +-
3 files changed, 117 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 571a710cc92a34..b81c9f87cb27d7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -861,6 +861,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ScalarizeVecRes_ExpOp(SDNode *N);
SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
+ SDValue ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N);
SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
SDValue ScalarizeVecRes_VSELECT(SDNode *N);
SDValue ScalarizeVecRes_SELECT(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 107454a92e356c..c85e4ba2cfa5a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -60,6 +60,9 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N,
unsigned ResNo) {
case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
case ISD::FPOWI: R = ScalarizeVecRes_ExpOp(N); break;
case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
+ case ISD::ATOMIC_LOAD:
+R = ScalarizeVecRes_ATOMIC_LOAD(cast(N));
+break;
case ISD::LOAD: R =
ScalarizeVecRes_LOAD(cast(N));break;
case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
@@ -451,6 +454,18 @@ SDValue
DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
return Op;
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
+ SDValue Result = DAG.getAtomic(
+ ISD::ATOMIC_LOAD, SDLoc(N), N->getMemoryVT().getVectorElementType(),
+ N->getValueType(0).getVectorElementType(), N->getChain(),
N->getBasePtr(),
+ N->getMemOperand());
+
+ // Legalize the chain result - switch anything that used the old chain to
+ // use the new one.
+ ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
+ return Result;
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(N->isUnindexed() && "Indexed vector load?");
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 5bce4401f7bdb0..20919a7e4fe0da 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s --check-prefixes=CHECK,CHECK3
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s --check-prefixes=CHECK,CHECK0
define void @test1(ptr %ptr, i32 %val1) {
; CHECK-LABEL: test1:
@@ -28,3 +28,102 @@ define i32 @test3(ptr %ptr) {
%val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
+
+define <1 x i32> @atomic_vec1_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movl (%rdi), %eax
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x i32>, ptr %x acquire, align 4
+ ret <1 x i32> %ret
+}
+
+define <1 x i8> @atomic_vec1_i8(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i8:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzbl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i8:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movb (%rdi), %al
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i8>, ptr %x acquire, align 4
+ ret <1 x i8> %ret
+}
+
+define <1 x i16> @atomic_vec1_i16(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i16:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i16:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %ax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i16>, ptr %x acquire, align 4
+ ret <1 x i16> %ret
+}
+
+define <1
[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 255a0118423f386364b2cee01ca18fa244c1c439 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
commit-id:f9d761c5
---
llvm/lib/Target/X86/X86ISelLowering.cpp| 4 +++
llvm/test/CodeGen/X86/atomic-load-store.ll | 29 +-
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 35c0974733aba4..f9d0a49b328247 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2595,6 +2595,10 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
ISD::SCALAR_TO_VECTOR,
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 20919a7e4fe0da..b063a044543196 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -115,7 +115,6 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
; CHECK3-NEXT:movzwl (%rdi), %eax
; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
; CHECK3-NEXT:retq
-;
; CHECK0-LABEL: atomic_vec1_bfloat:
; CHECK0: ## %bb.0:
; CHECK0-NEXT:movw (%rdi), %cx
@@ -127,3 +126,31 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
%ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
ret <1 x bfloat> %ret
}
+
+define <1 x half> @atomic_vec1_half(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_half:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_half:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x half>, ptr %x acquire, align 4
+ ret <1 x half> %ret
+}
+
+define <1 x float> @atomic_vec1_float(ptr %x) {
+; CHECK-LABEL: atomic_vec1_float:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x float>, ptr %x acquire, align 4
+ ret <1 x float> %ret
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 5e8da0562f2206a6b6b4cf52d1a450cabe17d275 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 239 +
1 file changed, 239 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index b063a044543196..a9462ca4166a88 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -127,6 +127,34 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
ret <1 x bfloat> %ret
}
+define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_ptr:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_ptr:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x ptr>, ptr %x acquire, align 4
+ ret <1 x ptr> %ret
+}
+
define <1 x half> @atomic_vec1_half(ptr %x) {
; CHECK3-LABEL: atomic_vec1_half:
; CHECK3: ## %bb.0:
@@ -154,3 +182,214 @@ define <1 x float> @atomic_vec1_float(ptr %x) {
%ret = load atomic <1 x float>, ptr %x acquire, align 4
ret <1 x float> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_double:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_i32:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec4_float:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:subq $24, %rsp
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $16, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movaps (%rsp), %xmm0
+; CHECK3-NEXT:addq $2
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 5e8da0562f2206a6b6b4cf52d1a450cabe17d275 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 239 +
1 file changed, 239 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index b063a044543196..a9462ca4166a88 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -127,6 +127,34 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
ret <1 x bfloat> %ret
}
+define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_ptr:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_ptr:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x ptr>, ptr %x acquire, align 4
+ ret <1 x ptr> %ret
+}
+
define <1 x half> @atomic_vec1_half(ptr %x) {
; CHECK3-LABEL: atomic_vec1_half:
; CHECK3: ## %bb.0:
@@ -154,3 +182,214 @@ define <1 x float> @atomic_vec1_float(ptr %x) {
%ret = load atomic <1 x float>, ptr %x acquire, align 4
ret <1 x float> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_double:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_i32:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec4_float:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:subq $24, %rsp
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $16, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movaps (%rsp), %xmm0
+; CHECK3-NEXT:addq $2
[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 255a0118423f386364b2cee01ca18fa244c1c439 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
commit-id:f9d761c5
---
llvm/lib/Target/X86/X86ISelLowering.cpp| 4 +++
llvm/test/CodeGen/X86/atomic-load-store.ll | 29 +-
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 35c0974733aba4..f9d0a49b328247 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2595,6 +2595,10 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
ISD::SCALAR_TO_VECTOR,
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 20919a7e4fe0da..b063a044543196 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -115,7 +115,6 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
; CHECK3-NEXT:movzwl (%rdi), %eax
; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
; CHECK3-NEXT:retq
-;
; CHECK0-LABEL: atomic_vec1_bfloat:
; CHECK0: ## %bb.0:
; CHECK0-NEXT:movw (%rdi), %cx
@@ -127,3 +126,31 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
%ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
ret <1 x bfloat> %ret
}
+
+define <1 x half> @atomic_vec1_half(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_half:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_half:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x half>, ptr %x acquire, align 4
+ ret <1 x half> %ret
+}
+
+define <1 x float> @atomic_vec1_float(ptr %x) {
+; CHECK-LABEL: atomic_vec1_float:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x float>, ptr %x acquire, align 4
+ ret <1 x float> %ret
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 4d3fcb3a0279d9aac8e43acd7060e89115324ba2 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic <1 x T>` is not valid. This change legalizes
vector types of atomic load via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.
commit-id:5c36cc8c
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 15 +++
llvm/test/CodeGen/X86/atomic-load-store.ll| 103 +-
3 files changed, 117 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 571a710cc92a34..b81c9f87cb27d7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -861,6 +861,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ScalarizeVecRes_ExpOp(SDNode *N);
SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
+ SDValue ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N);
SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
SDValue ScalarizeVecRes_VSELECT(SDNode *N);
SDValue ScalarizeVecRes_SELECT(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 107454a92e356c..c85e4ba2cfa5a7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -60,6 +60,9 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N,
unsigned ResNo) {
case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
case ISD::FPOWI: R = ScalarizeVecRes_ExpOp(N); break;
case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
+ case ISD::ATOMIC_LOAD:
+R = ScalarizeVecRes_ATOMIC_LOAD(cast(N));
+break;
case ISD::LOAD: R =
ScalarizeVecRes_LOAD(cast(N));break;
case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
@@ -451,6 +454,18 @@ SDValue
DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
return Op;
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
+ SDValue Result = DAG.getAtomic(
+ ISD::ATOMIC_LOAD, SDLoc(N), N->getMemoryVT().getVectorElementType(),
+ N->getValueType(0).getVectorElementType(), N->getChain(),
N->getBasePtr(),
+ N->getMemOperand());
+
+ // Legalize the chain result - switch anything that used the old chain to
+ // use the new one.
+ ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
+ return Result;
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(N->isUnindexed() && "Indexed vector load?");
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 5bce4401f7bdb0..20919a7e4fe0da 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs |
FileCheck %s --check-prefixes=CHECK,CHECK3
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 |
FileCheck %s --check-prefixes=CHECK,CHECK0
define void @test1(ptr %ptr, i32 %val1) {
; CHECK-LABEL: test1:
@@ -28,3 +28,102 @@ define i32 @test3(ptr %ptr) {
%val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
+
+define <1 x i32> @atomic_vec1_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movl (%rdi), %eax
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x i32>, ptr %x acquire, align 4
+ ret <1 x i32> %ret
+}
+
+define <1 x i8> @atomic_vec1_i8(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i8:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzbl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i8:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movb (%rdi), %al
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i8>, ptr %x acquire, align 4
+ ret <1 x i8> %ret
+}
+
+define <1 x i16> @atomic_vec1_i16(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_i16:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i16:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %ax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i16>, ptr %x acquire, align 4
+ ret <1 x i16> %ret
+}
+
+define <1
[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From e3dd93936b625a505f42a064d692fa5d99023c2f Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
commit-id:f9d761c5
---
llvm/lib/Target/X86/X86ISelLowering.cpp| 4
llvm/test/CodeGen/X86/atomic-load-store.ll | 28 ++
2 files changed, 32 insertions(+)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 35c0974733aba4..f9d0a49b328247 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2595,6 +2595,10 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
ISD::SCALAR_TO_VECTOR,
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 20919a7e4fe0da..01f4fd07b51a14 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -127,3 +127,31 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
%ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
ret <1 x bfloat> %ret
}
+
+define <1 x half> @atomic_vec1_half(ptr %x) {
+; CHECK3-LABEL: atomic_vec1_half:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_half:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:movw (%rdi), %cx
+; CHECK0-NEXT:## implicit-def: $eax
+; CHECK0-NEXT:movw %cx, %ax
+; CHECK0-NEXT:## implicit-def: $xmm0
+; CHECK0-NEXT:pinsrw $0, %eax, %xmm0
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x half>, ptr %x acquire, align 4
+ ret <1 x half> %ret
+}
+
+define <1 x float> @atomic_vec1_float(ptr %x) {
+; CHECK-LABEL: atomic_vec1_float:
+; CHECK: ## %bb.0:
+; CHECK-NEXT:movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:retq
+ %ret = load atomic <1 x float>, ptr %x acquire, align 4
+ ret <1 x float> %ret
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From e71ac0570acb438d795531890966eee49b098996 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 239 +
1 file changed, 239 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 01f4fd07b51a14..56a8e44473e497 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -128,6 +128,34 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
ret <1 x bfloat> %ret
}
+define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_ptr:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_ptr:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x ptr>, ptr %x acquire, align 4
+ ret <1 x ptr> %ret
+}
+
define <1 x half> @atomic_vec1_half(ptr %x) {
; CHECK3-LABEL: atomic_vec1_half:
; CHECK3: ## %bb.0:
@@ -155,3 +183,214 @@ define <1 x float> @atomic_vec1_float(ptr %x) {
%ret = load atomic <1 x float>, ptr %x acquire, align 4
ret <1 x float> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_double:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_i32:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec4_float:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:subq $24, %rsp
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $16, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movaps (%rsp), %xmm0
+; CHECK3-NEXT:addq $2
[llvm-branch-commits] [llvm] [X86] Add atomic vector tests for >1 sizes. (PR #120387)
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From e71ac0570acb438d795531890966eee49b098996 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for >1 sizes.
Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.
commit-id:a06a5cc6
---
llvm/test/CodeGen/X86/atomic-load-store.ll | 239 +
1 file changed, 239 insertions(+)
diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll
b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 01f4fd07b51a14..56a8e44473e497 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -128,6 +128,34 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
ret <1 x bfloat> %ret
}
+define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_ptr:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_ptr:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x ptr>, ptr %x acquire, align 4
+ ret <1 x ptr> %ret
+}
+
define <1 x half> @atomic_vec1_half(ptr %x) {
; CHECK3-LABEL: atomic_vec1_half:
; CHECK3: ## %bb.0:
@@ -155,3 +183,214 @@ define <1 x float> @atomic_vec1_float(ptr %x) {
%ret = load atomic <1 x float>, ptr %x acquire, align 4
ret <1 x float> %ret
}
+
+define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_i64:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movq (%rsp), %rax
+; CHECK3-NEXT:popq %rcx
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq (%rsp), %rax
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+ ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec1_double:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <1 x double>, ptr %x acquire, align 4
+ ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec2_i32:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:pushq %rax
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $8, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK3-NEXT:popq %rax
+; CHECK3-NEXT:retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0: ## %bb.0:
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:movq %rdi, %rsi
+; CHECK0-NEXT:movl $8, %edi
+; CHECK0-NEXT:movq %rsp, %rdx
+; CHECK0-NEXT:movl $2, %ecx
+; CHECK0-NEXT:callq ___atomic_load
+; CHECK0-NEXT:movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:retq
+ %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+ ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) nounwind {
+; CHECK3-LABEL: atomic_vec4_float:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:subq $24, %rsp
+; CHECK3-NEXT:movq %rdi, %rsi
+; CHECK3-NEXT:movq %rsp, %rdx
+; CHECK3-NEXT:movl $16, %edi
+; CHECK3-NEXT:movl $2, %ecx
+; CHECK3-NEXT:callq ___atomic_load
+; CHECK3-NEXT:movaps (%rsp), %xmm0
+; CHECK3-NEXT:addq $2
[llvm-branch-commits] [llvm] [DirectX] TypedUAVLoadAdditionalFormats shader flag (PR #120280)
https://github.com/bogner closed https://github.com/llvm/llvm-project/pull/120280 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
