[llvm-branch-commits] [llvm] e7a9fd4 - [LV] Add test case for PR54427.
Author: Florian Hahn
Date: 2022-04-25T13:18:14+01:00
New Revision: e7a9fd4f57d6c51c2c97a545da6552c698eea347
URL:
https://github.com/llvm/llvm-project/commit/e7a9fd4f57d6c51c2c97a545da6552c698eea347
DIFF:
https://github.com/llvm/llvm-project/commit/e7a9fd4f57d6c51c2c97a545da6552c698eea347.diff
LOG: [LV] Add test case for PR54427.
Reduced test for #54427.
Added:
llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll
Modified:
Removed:
diff --git a/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll
b/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll
new file mode 100644
index 0..a4e595e98fb7b
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll
@@ -0,0 +1,46 @@
+; RUN: opt -passes=loop-vectorize -force-vector-interleave=2
-force-vector-width=1 -S %s | FileCheck %s
+
+target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+
+; Test for PR54427.
+define void @test_nonconst_start_and_step(i32* %dst, i32 %start, i32 %step,
i64 %N) {
+; CHECK-LABEL: @test_nonconst_start_and_step(
+; CHECK: [[NEG_STEP:%.+]] = sub i32 0, %step
+; CHECK: vector.body:
+; CHECK-NEXT:[[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [
[[INDEX_NEXT:%.*]], %vector.body ]
+; CHECK-NEXT:[[INDUCTION3:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT:[[INDUCTION4:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT:[[TMP2:%.*]] = trunc i64 [[INDEX]] to i32
+; CHECK-NEXT:[[TMP3:%.*]] = mul i32 [[TMP2]], [[NEG_STEP]]
+; CHECK-NEXT:[[OFFSET_IDX:%.*]] = add i32 %start, [[TMP3]]
+; CHECK-NEXT:[[TMP4:%.*]] = mul i32 0, [[NEG_STEP]]
+; CHECK-NEXT:[[INDUCTION:%.*]] = sub i32 [[OFFSET_IDX]], [[TMP4]]
+; CHECK-NEXT:[[TMP5:%.*]] = mul i32 1, [[NEG_STEP]]
+; CHECK-NEXT:[[INDUCTION2:%.*]] = sub i32 [[OFFSET_IDX]], [[TMP5]]
+; CHECK-NEXT:[[TMP6:%.*]] = sub nsw i32 [[INDUCTION]], %step
+; CHECK-NEXT:[[TMP7:%.*]] = sub nsw i32 [[INDUCTION2]], %step
+; CHECK-NEXT:[[TMP8:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]],
i64 [[INDUCTION3]]
+; CHECK-NEXT:[[TMP9:%.*]] = getelementptr inbounds i32, i32* [[DST]], i64
[[INDUCTION4]]
+; CHECK-NEXT:store i32 [[TMP6]], i32* [[TMP8]], align 2
+; CHECK-NEXT:store i32 [[TMP7]], i32* [[TMP9]], align 2
+; CHECK-NEXT:[[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT:[[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]]
+; CHECK-NEXT:br i1 [[TMP10]], label %middle.block, label %vector.body
+;
+entry:
+ br label %loop
+
+loop:
+ %primary.iv = phi i64 [ 0, %entry ], [ %primary.iv.next, %loop ]
+ %iv.down = phi i32 [ %start, %entry ], [ %iv.down.next, %loop ]
+ %iv.down.next = sub nsw i32 %iv.down, %step
+ %gep.dst = getelementptr inbounds i32, i32* %dst, i64 %primary.iv
+ store i32 %iv.down.next, i32* %gep.dst, align 2
+ %primary.iv.next = add nuw nsw i64 %primary.iv, 1
+ %exitcond = icmp eq i64 %primary.iv.next, %N
+ br i1 %exitcond, label %exit, label %loop
+
+exit:
+ ret void
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 0d2efbb - [LV] Always use add to add scalar iv and (startidx + step) for ints.
Author: Florian Hahn
Date: 2022-04-25T13:18:22+01:00
New Revision: 0d2efbb8b82c13ea6e4aef727c5360eea6679605
URL:
https://github.com/llvm/llvm-project/commit/0d2efbb8b82c13ea6e4aef727c5360eea6679605
DIFF:
https://github.com/llvm/llvm-project/commit/0d2efbb8b82c13ea6e4aef727c5360eea6679605.diff
LOG: [LV] Always use add to add scalar iv and (startidx + step) for ints.
In the integer case, step will be negative and InductionOpCode will be
Sub for inductions counting down.
By using the InductionOpCode for integers, we would incorrectly subtract
a negative value, when it should be added instead.
This fixes #54427 on the 14.x branch.
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index e1cc7946073ea..93eaed6551302 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -2544,19 +2544,19 @@ void InnerLoopVectorizer::widenIntOrFpInduction(
Type *ScalarTy = IntegerType::get(ScalarIV->getContext(),
Step->getType()->getScalarSizeInBits());
-Instruction::BinaryOps IncOp = ID.getInductionOpcode();
-if (IncOp == Instruction::BinaryOpsEnd)
- IncOp = Instruction::Add;
for (unsigned Part = 0; Part < UF; ++Part) {
Value *StartIdx = ConstantInt::get(ScalarTy, Part);
- Instruction::BinaryOps MulOp = Instruction::Mul;
+ Value *EntryPart;
if (Step->getType()->isFloatingPointTy()) {
StartIdx = Builder.CreateUIToFP(StartIdx, Step->getType());
-MulOp = Instruction::FMul;
+Value *MulOp = Builder.CreateFMul(StartIdx, Step);
+EntryPart = Builder.CreateBinOp(ID.getInductionOpcode(), ScalarIV,
+MulOp, "induction");
+ } else {
+EntryPart = Builder.CreateAdd(
+ScalarIV, Builder.CreateMul(StartIdx, Step), "induction");
+EntryPart->dump();
}
-
- Value *Mul = Builder.CreateBinOp(MulOp, StartIdx, Step);
- Value *EntryPart = Builder.CreateBinOp(IncOp, ScalarIV, Mul,
"induction");
State.set(Def, EntryPart, Part);
if (Trunc) {
assert(!Step->getType()->isFloatingPointTy() &&
diff --git a/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll
b/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll
index a4e595e98fb7b..5266b3f9eaecd 100644
--- a/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll
+++ b/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll
@@ -15,9 +15,9 @@ define void @test_nonconst_start_and_step(i32* %dst, i32
%start, i32 %step, i64
; CHECK-NEXT:[[TMP3:%.*]] = mul i32 [[TMP2]], [[NEG_STEP]]
; CHECK-NEXT:[[OFFSET_IDX:%.*]] = add i32 %start, [[TMP3]]
; CHECK-NEXT:[[TMP4:%.*]] = mul i32 0, [[NEG_STEP]]
-; CHECK-NEXT:[[INDUCTION:%.*]] = sub i32 [[OFFSET_IDX]], [[TMP4]]
+; CHECK-NEXT:[[INDUCTION:%.*]] = add i32 [[OFFSET_IDX]], [[TMP4]]
; CHECK-NEXT:[[TMP5:%.*]] = mul i32 1, [[NEG_STEP]]
-; CHECK-NEXT:[[INDUCTION2:%.*]] = sub i32 [[OFFSET_IDX]], [[TMP5]]
+; CHECK-NEXT:[[INDUCTION2:%.*]] = add i32 [[OFFSET_IDX]], [[TMP5]]
; CHECK-NEXT:[[TMP6:%.*]] = sub nsw i32 [[INDUCTION]], %step
; CHECK-NEXT:[[TMP7:%.*]] = sub nsw i32 [[INDUCTION2]], %step
; CHECK-NEXT:[[TMP8:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]],
i64 [[INDUCTION3]]
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ebf29ba - [LV] Remove stray debug dump added in 0d2efbb8b82c.
Author: Florian Hahn
Date: 2022-04-25T14:48:12+01:00
New Revision: ebf29ba9f0a3a1076c613aef59e65d65435daaee
URL:
https://github.com/llvm/llvm-project/commit/ebf29ba9f0a3a1076c613aef59e65d65435daaee
DIFF:
https://github.com/llvm/llvm-project/commit/ebf29ba9f0a3a1076c613aef59e65d65435daaee.diff
LOG: [LV] Remove stray debug dump added in 0d2efbb8b82c.
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 93eaed6551302..46ff0994e04e7 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -2555,7 +2555,6 @@ void InnerLoopVectorizer::widenIntOrFpInduction(
} else {
EntryPart = Builder.CreateAdd(
ScalarIV, Builder.CreateMul(StartIdx, Step), "induction");
-EntryPart->dump();
}
State.set(Def, EntryPart, Part);
if (Trunc) {
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] 324127d - [libcxx] Add some missing xlocale wrapper functions for OpenBSD
Author: Brad Smith
Date: 2022-04-25T15:14:49-07:00
New Revision: 324127d8da95554086c02d609c5b05d3405f73a0
URL:
https://github.com/llvm/llvm-project/commit/324127d8da95554086c02d609c5b05d3405f73a0
DIFF:
https://github.com/llvm/llvm-project/commit/324127d8da95554086c02d609c5b05d3405f73a0.diff
LOG: [libcxx] Add some missing xlocale wrapper functions for OpenBSD
Reviewed By: Mordante
Differential Revision: https://reviews.llvm.org/D122861
(cherry picked from commit a0d40a579a6f27a1b1cdb7d68b2145e332c02c4e)
Added:
Modified:
libcxx/include/__support/openbsd/xlocale.h
Removed:
diff --git a/libcxx/include/__support/openbsd/xlocale.h
b/libcxx/include/__support/openbsd/xlocale.h
index 49d66fde1e8ed..f3917f333fb37 100644
--- a/libcxx/include/__support/openbsd/xlocale.h
+++ b/libcxx/include/__support/openbsd/xlocale.h
@@ -16,4 +16,24 @@
#include
#include
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+inline _LIBCPP_HIDE_FROM_ABI long
+strtol_l(const char *nptr, char **endptr, int base, locale_t) {
+ return ::strtol(nptr, endptr, base);
+}
+
+inline _LIBCPP_HIDE_FROM_ABI unsigned long
+strtoul_l(const char *nptr, char **endptr, int base, locale_t) {
+ return ::strtoul(nptr, endptr, base);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
#endif
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 50c6ba7 - [RISCV] Only try LUI+SH*ADD+ADDI for int materialization if LUI+ADDI+SH*ADD failed.
Author: Craig Topper
Date: 2022-04-25T15:30:48-07:00
New Revision: 50c6ba751fa2c3ae8854ba09229bda62b3617c55
URL:
https://github.com/llvm/llvm-project/commit/50c6ba751fa2c3ae8854ba09229bda62b3617c55
DIFF:
https://github.com/llvm/llvm-project/commit/50c6ba751fa2c3ae8854ba09229bda62b3617c55.diff
LOG: [RISCV] Only try LUI+SH*ADD+ADDI for int materialization if
LUI+ADDI+SH*ADD failed.
There's an assert in LUI+SH*ADD+ADDI materialization that makes sure the
lower 12 bits aren't zero since that case should have been handled as
LUI+ADDI+SH*ADD. But nothing prevented the LUI+SH*ADD+ADDI checks from
running after the earlier code handled it.
The sequence would be the same length or longer so it wouldn't replace
the earlier sequence, but the assert happened before that was checked.
The vector holding the sequence also wasn't reset before the second
check so that guaranteed the sequence would never be found to be
shorter.
This patch fixes this by only trying the second expansion when the
earlier fails.
Fixes PR54812.
Reviewed By: benshi001
Differential Revision: https://reviews.llvm.org/D123406
(cherry picked from commit 70046438d02ba1ec6bc2e2fc496b610cc1068b0f)
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
llvm/test/CodeGen/RISCV/imm.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index e935179e5f9b0..4adcd25600f20 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -302,32 +302,34 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset
&ActiveFeatures) {
TmpSeq.push_back(RISCVMatInt::Inst(Opc, 0));
if (TmpSeq.size() < Res.size())
Res = TmpSeq;
-}
-// Try to use LUI+SH*ADD+ADDI.
-int64_t Hi52 = ((uint64_t)Val + 0x800ull) & ~0xfffull;
-int64_t Lo12 = SignExtend64<12>(Val);
-Div = 0;
-if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) {
- Div = 3;
- Opc = RISCV::SH1ADD;
-} else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) {
- Div = 5;
- Opc = RISCV::SH2ADD;
-} else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) {
- Div = 9;
- Opc = RISCV::SH3ADD;
-}
-// Build the new instruction sequence.
-if (Div > 0) {
- // For Val that has zero Lo12 (implies Val equals to Hi52) should has
- // already been processed to LUI+SH*ADD by previous optimization.
- assert(Lo12 != 0 &&
- "unexpected instruction sequence for immediate materialisation");
- generateInstSeqImpl(Hi52 / Div, ActiveFeatures, TmpSeq);
- TmpSeq.push_back(RISCVMatInt::Inst(Opc, 0));
- TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12));
- if (TmpSeq.size() < Res.size())
-Res = TmpSeq;
+} else {
+ // Try to use LUI+SH*ADD+ADDI.
+ int64_t Hi52 = ((uint64_t)Val + 0x800ull) & ~0xfffull;
+ int64_t Lo12 = SignExtend64<12>(Val);
+ Div = 0;
+ if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) {
+Div = 3;
+Opc = RISCV::SH1ADD;
+ } else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) {
+Div = 5;
+Opc = RISCV::SH2ADD;
+ } else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) {
+Div = 9;
+Opc = RISCV::SH3ADD;
+ }
+ // Build the new instruction sequence.
+ if (Div > 0) {
+// For Val that has zero Lo12 (implies Val equals to Hi52) should has
+// already been processed to LUI+SH*ADD by previous optimization.
+assert(Lo12 != 0 &&
+ "unexpected instruction sequence for immediate
materialisation");
+assert(TmpSeq.empty() && "Expected empty TmpSeq");
+generateInstSeqImpl(Hi52 / Div, ActiveFeatures, TmpSeq);
+TmpSeq.push_back(RISCVMatInt::Inst(Opc, 0));
+TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12));
+if (TmpSeq.size() < Res.size())
+ Res = TmpSeq;
+ }
}
}
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index 5de49d8a7f2cb..9fa688b6f75d5 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -2401,3 +2401,39 @@ define i64 @li_rori_3() {
; RV64IZBS-NEXT:ret
ret i64 -2281701377
}
+
+; This used to assert when compiled with Zba.
+define i64 @PR54812() {
+; RV32I-LABEL: PR54812:
+; RV32I: # %bb.0:
+; RV32I-NEXT:lui a0, 521599
+; RV32I-NEXT:li a1, -1
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: PR54812:
+; RV64I: # %bb.0:
+; RV64I-NEXT:lui a0, 1048447
+; RV64I-NEXT:addiw a0, a0, 1407
+; RV64I-NEXT:slli a0, a0, 12
+; RV64I-NEXT:ret
+;
+; RV64IZBA-LABEL: PR54812:
+; RV64IZBA: # %bb.0:
+; RV64IZBA-NEXT:lui a0, 872917
+; RV64IZBA-NEXT:sh1add a0, a0, a0
+; RV64IZBA-NEXT:ret
+;
+; RV64IZBB-LABEL: PR54812:
+; RV64IZBB: # %bb.0:
+; RV64IZBB-NEXT
[llvm-branch-commits] [lld] dc30b0d - [ELF] --emit-relocs: fix missing STT_SECTION when the first input section is synthetic
Author: Fangrui Song
Date: 2022-04-25T15:18:15-07:00
New Revision: dc30b0d3320da810f402a3fd1f79720cfa8eb98d
URL:
https://github.com/llvm/llvm-project/commit/dc30b0d3320da810f402a3fd1f79720cfa8eb98d
DIFF:
https://github.com/llvm/llvm-project/commit/dc30b0d3320da810f402a3fd1f79720cfa8eb98d.diff
LOG: [ELF] --emit-relocs: fix missing STT_SECTION when the first input section
is synthetic
addSectionSymbols suppresses the STT_SECTION symbol if the first input section
is non-SHF_MERGE synthetic. This is incorrect when the first input section is
synthetic
while a non-synthetic input section exists:
* `.bss : { *(COMMON) *(.bss) }`
(abc388ed3cf0ef7e617ebe243d3b0b32d29e69a5 regressed the case because
COMMON symbols precede .bss in the absence of a linker script)
* Place a synthetic section in another section: `.data : { *(.got) *(.data) }`
For `%t/a1` in the new test emit-relocs-synthetic.s, ld.lld produces incorrect
relocations with symbol index 0.
```
<_start>:
0: 8b 05 33 00 00 00 movl51(%rip), %eax # 0x39
0002: R_X86_64_PC32*ABS*+0xd
6: 8b 05 1c 00 00 00 movl28(%rip), %eax # 0x28
0008: R_X86_64_PC32common-0x4
c: 8b 05 06 00 00 00 movl6(%rip), %eax # 0x18
000e: R_X86_64_GOTPCRELX *ABS*+0x4
```
Fix the issue by checking every input section.
Reviewed By: ikudrin
Differential Revision: https://reviews.llvm.org/D122463
(cherry picked from commit 7370a489b1005e424b23bd0009af2365aef4db53)
Added:
lld/test/ELF/emit-relocs-synthetic.s
Modified:
lld/ELF/Writer.cpp
Removed:
diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp
index 9383ac46c8e72..5794f048c9909 100644
--- a/lld/ELF/Writer.cpp
+++ b/lld/ELF/Writer.cpp
@@ -722,23 +722,30 @@ template void
Writer::addSectionSymbols() {
auto *sec = dyn_cast(cmd);
if (!sec)
continue;
-auto i = llvm::find_if(sec->commands, [](SectionCommand *cmd) {
- if (auto *isd = dyn_cast(cmd))
-return !isd->sections.empty();
- return false;
-});
-if (i == sec->commands.end())
- continue;
-InputSectionBase *isec = cast(*i)->sections[0];
-
-// Relocations are not using REL[A] section symbols.
-if (isec->type == SHT_REL || isec->type == SHT_RELA)
- continue;
-
-// Unlike other synthetic sections, mergeable output sections contain data
-// copied from input sections, and there may be a relocation pointing to
its
-// contents if -r or --emit-reloc is given.
-if (isa(isec) && !(isec->flags & SHF_MERGE))
+OutputSection &osec = *sec;
+InputSectionBase *isec = nullptr;
+// Iterate over all input sections and add a STT_SECTION symbol if any
input
+// section may be a relocation target.
+for (SectionCommand *cmd : osec.commands) {
+ auto *isd = dyn_cast(cmd);
+ if (!isd)
+continue;
+ for (InputSectionBase *s : isd->sections) {
+// Relocations are not using REL[A] section symbols.
+if (s->type == SHT_REL || s->type == SHT_RELA)
+ continue;
+
+// Unlike other synthetic sections, mergeable output sections contain
+// data copied from input sections, and there may be a relocation
+// pointing to its contents if -r or --emit-reloc is given.
+if (isa(s) && !(s->flags & SHF_MERGE))
+ continue;
+
+isec = s;
+break;
+ }
+}
+if (!isec)
continue;
// Set the symbol to be relative to the output section so that its st_value
diff --git a/lld/test/ELF/emit-relocs-synthetic.s
b/lld/test/ELF/emit-relocs-synthetic.s
new file mode 100644
index 0..737f96e5e191c
--- /dev/null
+++ b/lld/test/ELF/emit-relocs-synthetic.s
@@ -0,0 +1,54 @@
+# REQUIRES: x86
+## Regression test: add STT_SECTION even if synthetic sections are interleaved
+## with regular input sections.
+
+# RUN: rm -rf %t && split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/a.s -o %t/a.o
+# RUN: ld.lld --emit-relocs --no-relax -T %t/1.t %t/a.o -o %t/a1
+# RUN: llvm-objdump -dr %t/a1 | FileCheck %s --check-prefixes=CHECK,CHECK1
+# RUN: ld.lld --emit-relocs --no-relax -T %t/2.t %t/a.o -o %t/a2
+# RUN: llvm-objdump -dr %t/a2 | FileCheck %s --check-prefixes=CHECK,CHECK2
+
+# CHECK: <_start>:
+## %t/a1: bss is at offset 17. bss-4 = .bss + 0xd
+## %t/a2: bss is at offset 16. bss-4 = .bss + 0xc
+# CHECK-NEXT:movl [[#]](%rip), %eax
+# CHECK1-NEXT: R_X86_64_PC32.bss+0xd
+# CHECK2-NEXT: R_X86_64_PC32.bss+0xc
+# CHECK-NEXT:movl [[#]](%rip), %eax
+# CHECK-NEXT: R_X86_64_PC32common-0x4
+# CHECK-NEXT:movl [[#]](%rip), %eax
+## %t/a1: input .data is at offset 8. 8-4 = 0x4
+## %t/a2: input .data is at offset 0. 0-4 = -0x4
+# C
[llvm-branch-commits] [llvm] 21ce6cf - [RISCV] Add tests showing incorrect BUILD_VECTOR lowering
Author: Fraser Cormack
Date: 2022-04-25T20:27:35-07:00
New Revision: 21ce6cfd1d9357b54173d43e3d18960f487f6663
URL:
https://github.com/llvm/llvm-project/commit/21ce6cfd1d9357b54173d43e3d18960f487f6663
DIFF:
https://github.com/llvm/llvm-project/commit/21ce6cfd1d9357b54173d43e3d18960f487f6663.diff
LOG: [RISCV] Add tests showing incorrect BUILD_VECTOR lowering
These tests both use vector constants misidentified as VID sequences.
Because the initial run of elements has a zero step, the elements are
skipped until such a step can be identified. The bug is that the skipped
elements are never validated, even though the computed step is
incompatible across the entire sequence.
A fix will follow in a subseqeuent patch.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D123785
(cherry picked from commit 00537946aa29928894ba140687de1b6f9494e44d)
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
Removed:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index 80c4ad8662b14..6fb669feb462a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -704,3 +704,24 @@ define <8 x i16> @splat_idx_v8i16(<8 x i16> %v, i64 %idx) {
%splat = shufflevector <8 x i16> %ins, <8 x i16> poison, <8 x i32>
zeroinitializer
ret <8 x i16> %splat
}
+
+; FIXME: This is not a vid sequence!
+define <4 x i8> @buildvec_not_vid_v4i8_1() {
+; CHECK-LABEL: buildvec_not_vid_v4i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT:vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT:vid.v v8
+; CHECK-NEXT:ret
+ ret <4 x i8>
+}
+
+; FIXME: This is not a vid sequence!
+define <4 x i8> @buildvec_not_vid_v4i8_2() {
+; CHECK-LABEL: buildvec_not_vid_v4i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT:vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT:vid.v v8
+; CHECK-NEXT:vrsub.vi v8, v8, 3
+; CHECK-NEXT:ret
+ ret <4 x i8>
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 58d5fbe - [llvm-mt] Add support /notify_update
Author: Alex Brachet
Date: 2022-04-25T19:07:04-07:00
New Revision: 58d5fbe2c20bbd2499675c2d7a35dc157c767fec
URL:
https://github.com/llvm/llvm-project/commit/58d5fbe2c20bbd2499675c2d7a35dc157c767fec
DIFF:
https://github.com/llvm/llvm-project/commit/58d5fbe2c20bbd2499675c2d7a35dc157c767fec.diff
LOG: [llvm-mt] Add support /notify_update
`/notify_update` is an undocumented feature used by CMake. From their usage, it
looks like this feature just changes `mt`'s exit code if the output file was
changed. See
https://gitlab.kitware.com/cmake/cmake/-/blob/master/Source/cmcmd.cxx#L2300
this is also consistent with some testing I have done of the mt.exeshipped with
Visual Studio. See also the comment at
https://gitlab.kitware.com/cmake/cmake/-/blob/master/Source/cmcmd.cxx#L2440.
There might be a more performant way to implement this by first checking
calling `llvm::sys::fs::file_size()` and if it is the same as the new output's
size use `llvm::WritableMemoryBuffer` and fallback to `llvm::FileOutputBuffer`
otherwise, but these don't inherit from a common ancestor so any
implementation doing this would be really ugly.
Fixes https://github.com/llvm/llvm-project/issues/54329
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D121438
(cherry picked from commit e970d2823cf2a666cb597bf06ff8e0d0b880d361)
Added:
llvm/test/tools/llvm-mt/notify_update.test
Modified:
llvm/tools/llvm-mt/Opts.td
llvm/tools/llvm-mt/llvm-mt.cpp
Removed:
diff --git a/llvm/test/tools/llvm-mt/notify_update.test
b/llvm/test/tools/llvm-mt/notify_update.test
new file mode 100644
index 0..f3461b3ec8fc5
--- /dev/null
+++ b/llvm/test/tools/llvm-mt/notify_update.test
@@ -0,0 +1,16 @@
+REQUIRES: libxml2
+UNSUPPORTED: system-windows
+
+Exits normally without /notify_update
+RUN: llvm-mt /manifest %p/Inputs/test_manifest.manifest /out:%t.manifest
+RUN: rm -f %t.manifest
+
+We can't check exit code so all we can do is see if not considered it as a
failure
+
+File didn't exist previously so it's an update
+RUN: not llvm-mt /manifest %p/Inputs/test_manifest.manifest /out:%t.manifest
/notify_update
+RUN: llvm-mt /manifest %p/Inputs/test_manifest.manifest /out:%t.manifest
/notify_update
+
+New manifest, so it's an update
+RUN: not llvm-mt /manifest %p/Inputs/additional.manifest /out:%t.manifest
/notify_update
+RUN: llvm-mt /manifest %p/Inputs/additional.manifest /out:%t.manifest
/notify_update
diff --git a/llvm/tools/llvm-mt/Opts.td b/llvm/tools/llvm-mt/Opts.td
index da5b2c992ee35..c4f7375c6d8fa 100644
--- a/llvm/tools/llvm-mt/Opts.td
+++ b/llvm/tools/llvm-mt/Opts.td
@@ -23,7 +23,7 @@ def validate_file_hashes : Joined<["/", "-"],
"validate_file_hashes:">, HelpText
def canonicalize : Flag<["/", "-"], "canonicalize:">, HelpText<"Not
supported">, Group;
def check_for_duplicates : Flag<["/", "-"], "check_for_duplicates:">,
HelpText<"Not supported">, Group;
def make_cdfs : Flag<["/", "-"], "makecdfs:">, HelpText<"Not supported">,
Group;
-def notify_update : Flag<["/", "-"], "notify_update">, HelpText<"Not
supported">, Group;
+def notify_update : Flag<["/", "-"], "notify_update">, HelpText<"Exit with a
special exit code if the output file has changed">;
def verbose : Flag<["/", "-"], "verbose">, HelpText<"Not supported">,
Group;
def help : Flag<["/", "-"], "?">;
def help_long : Flag<["/", "-"], "help">, Alias;
diff --git a/llvm/tools/llvm-mt/llvm-mt.cpp b/llvm/tools/llvm-mt/llvm-mt.cpp
index 60735a95efa97..74885ec28f1c3 100644
--- a/llvm/tools/llvm-mt/llvm-mt.cpp
+++ b/llvm/tools/llvm-mt/llvm-mt.cpp
@@ -141,6 +141,29 @@ int main(int Argc, const char **Argv) {
std::unique_ptr OutputBuffer = Merger.getMergedManifest();
if (!OutputBuffer)
reportError("empty manifest not written");
+
+ int ExitCode = 0;
+ if (InputArgs.hasArg(OPT_notify_update)) {
+ErrorOr> OutBuffOrErr =
+MemoryBuffer::getFile(OutputFile);
+// Assume if we couldn't open the output file then it doesn't exist meaning
+// there was a change.
+bool Same = false;
+if (OutBuffOrErr) {
+ const std::unique_ptr &FileBuffer = *OutBuffOrErr;
+ Same = std::equal(OutputBuffer->getBufferStart(),
+OutputBuffer->getBufferEnd(),
+FileBuffer->getBufferStart());
+}
+if (!Same) {
+#if LLVM_ON_UNIX
+ ExitCode = 0xbb;
+#elif defined(_WIN32)
+ ExitCode = 0x41020001;
+#endif
+}
+ }
+
Expected> FileOrErr =
FileOutputBuffer::create(OutputFile, OutputBuffer->getBufferSize());
if (!FileOrErr)
@@ -149,5 +172,5 @@ int main(int Argc, const char **Argv) {
std::copy(OutputBuffer->getBufferStart(), OutputBuffer->getBufferEnd(),
FileBuffer->getBufferStart());
error(FileBuffer->commit());
- return 0;
+ return ExitCode;
}
___
llvm-branch-commits mailing list
ll
[llvm-branch-commits] [llvm] 9efcce9 - [RISCV] Fix lowering of BUILD_VECTORs as VID sequences
Author: Fraser Cormack
Date: 2022-04-25T20:27:35-07:00
New Revision: 9efcce92b55bc87627b52dd1139fb9031e400b52
URL:
https://github.com/llvm/llvm-project/commit/9efcce92b55bc87627b52dd1139fb9031e400b52
DIFF:
https://github.com/llvm/llvm-project/commit/9efcce92b55bc87627b52dd1139fb9031e400b52.diff
LOG: [RISCV] Fix lowering of BUILD_VECTORs as VID sequences
This patch fixes a bug when lowering BUILD_VECTOR via VID sequences.
After adding support for fractional steps in D106533, elements with zero
steps may be skipped if no step has yet been computed. This allowed
certain sequences to slip through the cracks, being identified as VID
sequences when in fact they are not.
The fix for this is to perform a second loop over the BUILD_VECTOR to
validate the entire sequence once the step has been computed. This isn't
the most efficient, but on balance the code is more readable and
maintainable than doing back-validation during the first loop.
Fixes the tests introduced in D123785.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D123786
(cherry picked from commit c5cac48549ed254cd5ad5eef770ebfb22ccd9f64)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e7672a7652cdd..73a29a1d9dcc3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1908,37 +1908,27 @@ static Optional
isSimpleVIDSequence(SDValue Op) {
// A zero-value value
diff erence means that we're somewhere in the middle
// of a fractional step, e.g. <0,0,0*,0,1,1,1,1>. Wait until we notice a
// step change before evaluating the sequence.
- if (ValDiff != 0) {
-int64_t Remainder = ValDiff % IdxDiff;
-// Normalize the step if it's greater than 1.
-if (Remainder != ValDiff) {
- // The
diff erence must cleanly divide the element span.
- if (Remainder != 0)
-return None;
- ValDiff /= IdxDiff;
- IdxDiff = 1;
-}
-
-if (!SeqStepNum)
- SeqStepNum = ValDiff;
-else if (ValDiff != SeqStepNum)
- return None;
+ if (ValDiff == 0)
+continue;
-if (!SeqStepDenom)
- SeqStepDenom = IdxDiff;
-else if (IdxDiff != *SeqStepDenom)
+ int64_t Remainder = ValDiff % IdxDiff;
+ // Normalize the step if it's greater than 1.
+ if (Remainder != ValDiff) {
+// The
diff erence must cleanly divide the element span.
+if (Remainder != 0)
return None;
+ValDiff /= IdxDiff;
+IdxDiff = 1;
}
-}
-// Record and/or check any addend.
-if (SeqStepNum && SeqStepDenom) {
- uint64_t ExpectedVal =
- (int64_t)(Idx * (uint64_t)*SeqStepNum) / *SeqStepDenom;
- int64_t Addend = SignExtend64(Val - ExpectedVal, EltSizeInBits);
- if (!SeqAddend)
-SeqAddend = Addend;
- else if (SeqAddend != Addend)
+ if (!SeqStepNum)
+SeqStepNum = ValDiff;
+ else if (ValDiff != SeqStepNum)
+return None;
+
+ if (!SeqStepDenom)
+SeqStepDenom = IdxDiff;
+ else if (IdxDiff != *SeqStepDenom)
return None;
}
@@ -1946,11 +1936,29 @@ static Optional
isSimpleVIDSequence(SDValue Op) {
if (!PrevElt || PrevElt->first != Val)
PrevElt = std::make_pair(Val, Idx);
}
- // We need to have logged both a step and an addend for this to count as
- // a legal index sequence.
- if (!SeqStepNum || !SeqStepDenom || !SeqAddend)
+
+ // We need to have logged a step for this to count as a legal index sequence.
+ if (!SeqStepNum || !SeqStepDenom)
return None;
+ // Loop back through the sequence and validate elements we might have skipped
+ // while waiting for a valid step. While doing this, log any sequence addend.
+ for (unsigned Idx = 0; Idx < NumElts; Idx++) {
+if (Op.getOperand(Idx).isUndef())
+ continue;
+uint64_t Val = Op.getConstantOperandVal(Idx) &
+ maskTrailingOnes(EltSizeInBits);
+uint64_t ExpectedVal =
+(int64_t)(Idx * (uint64_t)*SeqStepNum) / *SeqStepDenom;
+int64_t Addend = SignExtend64(Val - ExpectedVal, EltSizeInBits);
+if (!SeqAddend)
+ SeqAddend = Addend;
+else if (Addend != SeqAddend)
+ return None;
+ }
+
+ assert(SeqAddend && "Must have an addend if we have a step");
+
return VIDSequence{*SeqStepNum, *SeqStepDenom, *SeqAddend};
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index 6fb669feb462a..085f5bc1d8493 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors
[llvm-branch-commits] [llvm] e19be41 - [RISCV] Add another test showing incorrect BUILD_VECTOR lowering
Author: Fraser Cormack
Date: 2022-04-25T20:27:35-07:00
New Revision: e19be4195b8700ee48a84a50e65b1d4612b22cca
URL:
https://github.com/llvm/llvm-project/commit/e19be4195b8700ee48a84a50e65b1d4612b22cca
DIFF:
https://github.com/llvm/llvm-project/commit/e19be4195b8700ee48a84a50e65b1d4612b22cca.diff
LOG: [RISCV] Add another test showing incorrect BUILD_VECTOR lowering
This test shows a (contrived) BUILD_VECTOR which is correctly identified
as a sequence of ((vid * -3) / 8) + 5. However, the issue is that using
shift-right for the divide is invalid as the step values are negative.
This patch just adds the test: the fix is added in D123796.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D123989
(cherry picked from commit 627e21048a2c040d3e353cc4f0eb8f207b6ea61c)
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
Removed:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index 085f5bc1d8493..3e10b0f3a49c5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -726,3 +726,18 @@ define <4 x i8> @buildvec_not_vid_v4i8_2() {
; CHECK-NEXT:ret
ret <4 x i8>
}
+
+; FIXME: This is not a valid way to emit this vid sequence: shift-right for
+; division only works for non-negative numbers!
+define <16 x i8> @buildvec_not_vid_v16i8() {
+; CHECK-LABEL: buildvec_not_vid_v16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT:vsetivli zero, 16, e8, m1, ta, mu
+; CHECK-NEXT:vid.v v8
+; CHECK-NEXT:li a0, -3
+; CHECK-NEXT:vmul.vx v8, v8, a0
+; CHECK-NEXT:vsrl.vi v8, v8, 3
+; CHECK-NEXT:vadd.vi v8, v8, 5
+; CHECK-NEXT:ret
+ ret <16 x i8>
+}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 1f4c7b2 - [RISCV] Don't emit fractional VIDs with negative steps
Author: Fraser Cormack
Date: 2022-04-25T20:27:35-07:00
New Revision: 1f4c7b2a9120357c2ee91bc407bf443734df54ec
URL:
https://github.com/llvm/llvm-project/commit/1f4c7b2a9120357c2ee91bc407bf443734df54ec
DIFF:
https://github.com/llvm/llvm-project/commit/1f4c7b2a9120357c2ee91bc407bf443734df54ec.diff
LOG: [RISCV] Don't emit fractional VIDs with negative steps
We can't shift-right negative numbers to divide them, so avoid emitting
such sequences. Use negative numerators as a proxy for this situation, since
the indices are always non-negative.
An alternative strategy could be to add a compiler flag to emit division
instructions, which would at least allow us to test the VID sequence
matching itself.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D123796
(cherry picked from commit 3e678cb77264907fbc2899c291ce23af308073ff)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 73a29a1d9dcc3..274b86593e0fd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2117,7 +2117,8 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG
&DAG,
// a single addi instruction.
if (((StepOpcode == ISD::MUL && isInt<12>(SplatStepVal)) ||
(StepOpcode == ISD::SHL && isUInt<5>(SplatStepVal))) &&
-isPowerOf2_32(StepDenominator) && isInt<5>(Addend)) {
+isPowerOf2_32(StepDenominator) &&
+(SplatStepVal >= 0 || StepDenominator == 1) && isInt<5>(Addend)) {
SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, ContainerVT, Mask, VL);
// Convert right out of the scalable type so we can use standard ISD
// nodes for the rest of the computation. If we used scalable types with
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index 3e10b0f3a49c5..b623d838de3eb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -727,17 +727,17 @@ define <4 x i8> @buildvec_not_vid_v4i8_2() {
ret <4 x i8>
}
-; FIXME: This is not a valid way to emit this vid sequence: shift-right for
-; division only works for non-negative numbers!
+; We match this as a VID sequence (-3 / 8) + 5 but choose not to introduce
+; division to compute it.
define <16 x i8> @buildvec_not_vid_v16i8() {
; CHECK-LABEL: buildvec_not_vid_v16i8:
; CHECK: # %bb.0:
+; CHECK-NEXT:li a0, 3
; CHECK-NEXT:vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT:vid.v v8
-; CHECK-NEXT:li a0, -3
-; CHECK-NEXT:vmul.vx v8, v8, a0
-; CHECK-NEXT:vsrl.vi v8, v8, 3
-; CHECK-NEXT:vadd.vi v8, v8, 5
+; CHECK-NEXT:vmv.s.x v9, a0
+; CHECK-NEXT:vmv.v.i v8, 0
+; CHECK-NEXT:vsetivli zero, 7, e8, m1, tu, mu
+; CHECK-NEXT:vslideup.vi v8, v9, 6
; CHECK-NEXT:ret
ret <16 x i8>
}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 0e27d08 - [RISCV] Fix crash for section alignment with .option norvc
Author: Luís Marques
Date: 2022-04-25T20:44:44-07:00
New Revision: 0e27d08cdeb338766a477fba071b3df7a06ea6e2
URL:
https://github.com/llvm/llvm-project/commit/0e27d08cdeb338766a477fba071b3df7a06ea6e2
DIFF:
https://github.com/llvm/llvm-project/commit/0e27d08cdeb338766a477fba071b3df7a06ea6e2.diff
LOG: [RISCV] Fix crash for section alignment with .option norvc
The existing code wasn't getting the subtarget info from the fragment,
so the current status of RVC would be ignored. This would cause a crash
for the new test case when the target then reported it couldn't write
the requested number of code alignment bytes.
Differential Revision: https://reviews.llvm.org/D122236
(cherry picked from commit d09d297c5d28bd0af4dd8bf3ca66d8dbbd196d9d)
Added:
llvm/test/MC/RISCV/align-option-relax.s
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/test/MC/RISCV/align.s
Removed:
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 514789b3f6459..4b940093482f5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -583,10 +583,11 @@ void RISCVAsmBackend::applyFixup(const MCAssembler &Asm,
const MCFixup &Fixup,
bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
const MCAlignFragment &AF, unsigned &Size) {
// Calculate Nops Size only when linker relaxation enabled.
- if (!STI.getFeatureBits()[RISCV::FeatureRelax])
+ const MCSubtargetInfo *STI = AF.getSubtargetInfo();
+ if (!STI->getFeatureBits()[RISCV::FeatureRelax])
return false;
- bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
+ bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC];
unsigned MinNopLen = HasStdExtC ? 2 : 4;
if (AF.getAlignment() <= MinNopLen) {
@@ -606,7 +607,8 @@ bool
RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
const MCAsmLayout &Layout,
MCAlignFragment &AF) {
// Insert the fixup only when linker relaxation enabled.
- if (!STI.getFeatureBits()[RISCV::FeatureRelax])
+ const MCSubtargetInfo *STI = AF.getSubtargetInfo();
+ if (!STI->getFeatureBits()[RISCV::FeatureRelax])
return false;
// Calculate total Nops we need to insert. If there are none to insert
diff --git a/llvm/test/MC/RISCV/align-option-relax.s
b/llvm/test/MC/RISCV/align-option-relax.s
new file mode 100644
index 0..890e1e72d7706
--- /dev/null
+++ b/llvm/test/MC/RISCV/align-option-relax.s
@@ -0,0 +1,8 @@
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \
+# RUN: | llvm-readobj -r - | FileCheck %s
+
+# Check that .option relax overrides -mno-relax and enables R_RISCV_ALIGN
+# relocations.
+# CHECK: R_RISCV_ALIGN
+ .option relax
+ .align 4
diff --git a/llvm/test/MC/RISCV/align.s b/llvm/test/MC/RISCV/align.s
index 804effb6600b2..75ea8eb77bbd4 100644
--- a/llvm/test/MC/RISCV/align.s
+++ b/llvm/test/MC/RISCV/align.s
@@ -112,3 +112,11 @@ data1:
# C-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN
data2:
.word 9
+# Check that the initial alignment is properly handled when using .option to
+# disable the C extension. This used to crash.
+# C-EXT-RELAX-INST: <.text2>:
+# C-EXT-RELAX-INST-NEXT: add a0, a0, a1
+ .section .text2, "x"
+ .option norvc
+ .balign 4
+ add a0, a0, a1
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] a368017 - [asan] Always skip first object from dl_iterate_phdr
Author: Michael Forney
Date: 2022-04-25T20:43:30-07:00
New Revision: a36801750327d05d5f8a19aec33819ae3f8f5e35
URL:
https://github.com/llvm/llvm-project/commit/a36801750327d05d5f8a19aec33819ae3f8f5e35
DIFF:
https://github.com/llvm/llvm-project/commit/a36801750327d05d5f8a19aec33819ae3f8f5e35.diff
LOG: [asan] Always skip first object from dl_iterate_phdr
All platforms return the main executable as the first dl_phdr_info.
FreeBSD, NetBSD, Solaris, and Linux-musl place the executable name
in the dlpi_name field of this entry. It appears that only Linux-glibc
uses the empty string.
To make this work generically on all platforms, unconditionally
skip the first object (like is currently done for FreeBSD and NetBSD).
This fixes first DSO detection on Linux-musl. It also would likely
fix detection on Solaris/Illumos if it were to gain PIE support
(since dlpi_addr would not be NULL).
Additionally, only skip the Linux VDSO on linux.
Finally, use the empty string as the "seen first dl_phdr_info"
marker rather than (char *)-1. If there was no other object, we
would try to dereference it for a string comparison.
Reviewed By: MaskRay, vitalybuka
Differential Revision: https://reviews.llvm.org/D119515
(cherry picked from commit 795b07f5498c7e5783237418f34d7ea69e801f87)
Added:
Modified:
compiler-rt/lib/asan/asan_linux.cpp
Removed:
diff --git a/compiler-rt/lib/asan/asan_linux.cpp
b/compiler-rt/lib/asan/asan_linux.cpp
index 1d92c530bd110..defd81bc19e22 100644
--- a/compiler-rt/lib/asan/asan_linux.cpp
+++ b/compiler-rt/lib/asan/asan_linux.cpp
@@ -131,30 +131,24 @@ static int FindFirstDSOCallback(struct dl_phdr_info
*info, size_t size,
VReport(2, "info->dlpi_name = %s\tinfo->dlpi_addr = %p\n", info->dlpi_name,
(void *)info->dlpi_addr);
- // Continue until the first dynamic library is found
- if (!info->dlpi_name || info->dlpi_name[0] == 0)
-return 0;
-
- // Ignore vDSO
- if (internal_strncmp(info->dlpi_name, "linux-", sizeof("linux-") - 1) == 0)
-return 0;
+ const char **name = (const char **)data;
-#if SANITIZER_FREEBSD || SANITIZER_NETBSD
// Ignore first entry (the main program)
- char **p = (char **)data;
- if (!(*p)) {
-*p = (char *)-1;
+ if (!*name) {
+*name = "";
return 0;
}
-#endif
-#if SANITIZER_SOLARIS
- // Ignore executable on Solaris
- if (info->dlpi_addr == 0)
+#if SANITIZER_LINUX
+ // Ignore vDSO. glibc versions earlier than 2.15 (and some patched
+ // by distributors) return an empty name for the vDSO entry, so
+ // detect this as well.
+ if (!info->dlpi_name[0] ||
+ internal_strncmp(info->dlpi_name, "linux-", sizeof("linux-") - 1) == 0)
return 0;
-#endif
+#endif
- *(const char **)data = info->dlpi_name;
+ *name = info->dlpi_name;
return 1;
}
@@ -175,7 +169,7 @@ void AsanCheckDynamicRTPrereqs() {
// Ensure that dynamic RT is the first DSO in the list
const char *first_dso_name = nullptr;
dl_iterate_phdr(FindFirstDSOCallback, &first_dso_name);
- if (first_dso_name && !IsDynamicRTName(first_dso_name)) {
+ if (first_dso_name && first_dso_name[0] && !IsDynamicRTName(first_dso_name))
{
Report("ASan runtime does not come first in initial library list; "
"you should either link runtime to your application or "
"manually preload it with LD_PRELOAD.\n");
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
