[llvm-branch-commits] [llvm] 5086fa0 - [PowerPC] Pre-commit reduced test case for PR45297. NFC.
Author: Kai Luo
Date: 2020-04-22T14:54:22-07:00
New Revision: 5086fa033344b5b16db92c9aa75be1e061921842
URL:
https://github.com/llvm/llvm-project/commit/5086fa033344b5b16db92c9aa75be1e061921842
DIFF:
https://github.com/llvm/llvm-project/commit/5086fa033344b5b16db92c9aa75be1e061921842.diff
LOG: [PowerPC] Pre-commit reduced test case for PR45297. NFC.
(cherry picked from commit 70f9f4dd9d19ed2cec0d9adf60fede9401898b85)
Added:
llvm/test/CodeGen/PowerPC/pr45297.ll
Modified:
Removed:
diff --git a/llvm/test/CodeGen/PowerPC/pr45297.ll
b/llvm/test/CodeGen/PowerPC/pr45297.ll
new file mode 100644
index ..71c19744fb70
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr45297.ll
@@ -0,0 +1,10 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mattr=+altivec -mattr=-power8-vector -mattr=-vsx < %s | FileCheck %s
+; XFAIL: *
+
+define dso_local void @test(float %0) local_unnamed_addr {
+entry:
+ %1 = fptosi float %0 to i32
+ store i32 %1, i32* undef, align 4
+ ret void
+}
___
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[llvm-branch-commits] [llvm] 66cfbf1 - [PowerPC] Fix test for PR45297 to adapt build without asserts. NFC.
Author: Kai Luo
Date: 2020-04-22T14:54:22-07:00
New Revision: 66cfbf17a18513de5551d6cdda563a2864d13400
URL:
https://github.com/llvm/llvm-project/commit/66cfbf17a18513de5551d6cdda563a2864d13400
DIFF:
https://github.com/llvm/llvm-project/commit/66cfbf17a18513de5551d6cdda563a2864d13400.diff
LOG: [PowerPC] Fix test for PR45297 to adapt build without asserts. NFC.
(cherry picked from commit 26b46b67d806a5299a93b1b3bca1548cb47487ff)
Added:
Modified:
llvm/test/CodeGen/PowerPC/pr45297.ll
Removed:
diff --git a/llvm/test/CodeGen/PowerPC/pr45297.ll
b/llvm/test/CodeGen/PowerPC/pr45297.ll
index 97d05efe0498..5bd5df543950 100644
--- a/llvm/test/CodeGen/PowerPC/pr45297.ll
+++ b/llvm/test/CodeGen/PowerPC/pr45297.ll
@@ -1,7 +1,7 @@
; RUN: not --crash llc -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \
; RUN: -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s
-; CHECK: LLVM ERROR: Cannot select: t{{[0-9]+}}: ch =
PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)>
+; CHECK: LLVM ERROR: Cannot select: {{.*}}: ch =
PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)>
@Global = dso_local global i32 55, align 4
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[llvm-branch-commits] [llvm] b11ecd1 - [PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled
Author: Kai Luo
Date: 2020-04-22T14:54:22-07:00
New Revision: b11ecd196540d87cb7db190d405056984740d2ce
URL:
https://github.com/llvm/llvm-project/commit/b11ecd196540d87cb7db190d405056984740d2ce
DIFF:
https://github.com/llvm/llvm-project/commit/b11ecd196540d87cb7db190d405056984740d2ce.diff
LOG: [PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled
Summary:
In https://bugs.llvm.org/show_bug.cgi?id=45297, it fails selecting
instructions for `PPCISD::ST_VSR_SCAL_INT`. The reason it generate the
`PPCISD::ST_VSR_SCAL_INT` with `-power8-vector` in IR is PPC's
combiner checks `hasP8Altivec` rather than `hasP8Vector`. This patch
should resolve PR45297.
Differential Revision: https://reviews.llvm.org/D76773
(cherry picked from commit 8eb40e41f6ec99985a292e342ec303a0bd6f5f41)
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/pr45297.ll
Removed:
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 764563c17c24..352a05529bc9 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13591,7 +13591,7 @@ SDValue PPCTargetLowering::combineStoreFPToInt(SDNode
*N,
(Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
(Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
- if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Altivec() ||
+ if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() ||
cast(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt)
return SDValue();
diff --git a/llvm/test/CodeGen/PowerPC/pr45297.ll
b/llvm/test/CodeGen/PowerPC/pr45297.ll
index 5bd5df543950..39583d5a04cc 100644
--- a/llvm/test/CodeGen/PowerPC/pr45297.ll
+++ b/llvm/test/CodeGen/PowerPC/pr45297.ll
@@ -1,11 +1,20 @@
-; RUN: not --crash llc -verify-machineinstrs \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \
; RUN: -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s
-; CHECK: LLVM ERROR: Cannot select: {{.*}}: ch =
PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)>
@Global = dso_local global i32 55, align 4
define dso_local void @test(float %0) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:fctiwz f0, f1
+; CHECK-NEXT:addi r3, r1, -4
+; CHECK-NEXT:addis r4, r2, Global@toc@ha
+; CHECK-NEXT:stfiwx f0, 0, r3
+; CHECK-NEXT:lwz r3, -4(r1)
+; CHECK-NEXT:stw r3, Global@toc@l(r4)
+; CHECK-NEXT:blr
entry:
%1 = fptosi float %0 to i32
store i32 %1, i32* @Global, align 4
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[llvm-branch-commits] [llvm] 40633cc - [PowerPC] Enhance test for PR45297. NFC.
Author: Kai Luo
Date: 2020-04-22T14:54:22-07:00
New Revision: 40633cc752a4ffecac22c6134761464bdbc8e10a
URL:
https://github.com/llvm/llvm-project/commit/40633cc752a4ffecac22c6134761464bdbc8e10a
DIFF:
https://github.com/llvm/llvm-project/commit/40633cc752a4ffecac22c6134761464bdbc8e10a.diff
LOG: [PowerPC] Enhance test for PR45297. NFC.
(cherry picked from commit 351b19231554d4dba29c42c798176f1ff3286a32)
Added:
Modified:
llvm/test/CodeGen/PowerPC/pr45297.ll
Removed:
diff --git a/llvm/test/CodeGen/PowerPC/pr45297.ll
b/llvm/test/CodeGen/PowerPC/pr45297.ll
index 71c19744fb70..97d05efe0498 100644
--- a/llvm/test/CodeGen/PowerPC/pr45297.ll
+++ b/llvm/test/CodeGen/PowerPC/pr45297.ll
@@ -1,10 +1,13 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mattr=+altivec -mattr=-power8-vector -mattr=-vsx < %s | FileCheck %s
-; XFAIL: *
+; RUN: not --crash llc -verify-machineinstrs \
+; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \
+; RUN: -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s
+; CHECK: LLVM ERROR: Cannot select: t{{[0-9]+}}: ch =
PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)>
+
+@Global = dso_local global i32 55, align 4
define dso_local void @test(float %0) local_unnamed_addr {
entry:
%1 = fptosi float %0 to i32
- store i32 %1, i32* undef, align 4
+ store i32 %1, i32* @Global, align 4
ret void
}
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