[llvm-branch-commits] [llvm-branch] r341520 - ReleaseNotes: support for new-pm passes in the opt tool
Author: hans Date: Thu Sep 6 01:03:05 2018 New Revision: 341520 URL: http://llvm.org/viewvc/llvm-project?rev=341520&view=rev Log: ReleaseNotes: support for new-pm passes in the opt tool Modified: llvm/branches/release_70/docs/ReleaseNotes.rst Modified: llvm/branches/release_70/docs/ReleaseNotes.rst URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/docs/ReleaseNotes.rst?rev=341520&r1=341519&r2=341520&view=diff == --- llvm/branches/release_70/docs/ReleaseNotes.rst (original) +++ llvm/branches/release_70/docs/ReleaseNotes.rst Thu Sep 6 01:03:05 2018 @@ -131,6 +131,9 @@ Non-comprehensive list of changes in thi * CodeView debug info can now be emitted MinGW configurations, if requested. +* The :program:`opt` tool now supports the :option:`-load-pass-plugin` for + loading pass plugins for the new PassManager. + * Note.. .. NOTE ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [cfe-branch] r341521 - ReleaseNotes: libc++ _LIBCPP_HIDE_FROM_ABI_PER_TU
Author: hans Date: Thu Sep 6 01:09:39 2018 New Revision: 341521 URL: http://llvm.org/viewvc/llvm-project?rev=341521&view=rev Log: ReleaseNotes: libc++ _LIBCPP_HIDE_FROM_ABI_PER_TU Modified: cfe/branches/release_70/docs/ReleaseNotes.rst Modified: cfe/branches/release_70/docs/ReleaseNotes.rst URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_70/docs/ReleaseNotes.rst?rev=341521&r1=341520&r2=341521&view=diff == --- cfe/branches/release_70/docs/ReleaseNotes.rst (original) +++ cfe/branches/release_70/docs/ReleaseNotes.rst Thu Sep 6 01:09:39 2018 @@ -390,8 +390,15 @@ The following methods have been added: - ... -Significant Known Problems -== +libc++ Changes +== +Users that wish to link together translation units built with different +versions of libc++'s headers into the same final linked image should define the +`_LIBCPP_HIDE_FROM_ABI_PER_TU` macro to `1` when building those translation +units. In a future release, not defining `_LIBCPP_HIDE_FROM_ABI_PER_TU` to `1` +and linking translation units built with different versions of libc++'s headers +together may lead to ODR violations and ABI issues. + Additional Information == ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm-branch] r341522 - ReleaseNotes: ARM SVE asm/disasm support
Author: hans Date: Thu Sep 6 01:11:04 2018 New Revision: 341522 URL: http://llvm.org/viewvc/llvm-project?rev=341522&view=rev Log: ReleaseNotes: ARM SVE asm/disasm support Modified: llvm/branches/release_70/docs/ReleaseNotes.rst Modified: llvm/branches/release_70/docs/ReleaseNotes.rst URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/docs/ReleaseNotes.rst?rev=341522&r1=341521&r2=341522&view=diff == --- llvm/branches/release_70/docs/ReleaseNotes.rst (original) +++ llvm/branches/release_70/docs/ReleaseNotes.rst Thu Sep 6 01:11:04 2018 @@ -167,6 +167,9 @@ Changes to the AArch64 Target * Support for TLS on Windows has been added. +* Assembler and disassembler support for the ARM Scalable Vector Extension has + been added. + Changes to the ARM Target - ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm-branch] r341523 - Merging r341416:
Author: hans
Date: Thu Sep 6 01:16:34 2018
New Revision: 341523
URL: http://llvm.org/viewvc/llvm-project?rev=341523&view=rev
Log:
Merging r341416:
r341416 | annat | 2018-09-05 00:12:23 +0200 (Wed, 05 Sep 2018) | 11 lines
[LV] First order recurrence phis should not be treated as uniform
This is fix for PR38786.
First order recurrence phis were incorrectly treated as uniform,
which caused them to be vectorized as uniform instructions.
Patch by Ayal Zaks and Orivej Desh!
Reviewed by: Anna
Differential Revision: https://reviews.llvm.org/D51639
Modified:
llvm/branches/release_70/ (props changed)
llvm/branches/release_70/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/branches/release_70/test/Transforms/LoopVectorize/X86/uniform-phi.ll
Propchange: llvm/branches/release_70/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Sep 6 01:16:34 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338841,338902,338915,338968,339073,339091,339166,339179,339184,339190,339225,339316,339319,339411,339492,339515,339533,339535-339536,339600,339636,339674,339769,339822,339883,339895-339896,339945,340158,340303,340416-340417,340455,340641,340691,340751,340820,340839,340900,340959,341094,341244
+/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338841,338902,338915,338968,339073,339091,339166,339179,339184,339190,339225,339316,339319,339411,339492,339515,339533,339535-339536,339600,339636,339674,339769,339822,339883,339895-339896,339945,340158,340303,340416-340417,340455,340641,340691,340751,340820,340839,340900,340959,341094,341244,341416
Modified: llvm/branches/release_70/lib/Transforms/Vectorize/LoopVectorize.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Transforms/Vectorize/LoopVectorize.cpp?rev=341523&r1=341522&r2=341523&view=diff
==
--- llvm/branches/release_70/lib/Transforms/Vectorize/LoopVectorize.cpp
(original)
+++ llvm/branches/release_70/lib/Transforms/Vectorize/LoopVectorize.cpp Thu Sep
6 01:16:34 2018
@@ -4510,6 +4510,13 @@ void LoopVectorizationCostModel::collect
for (auto OV : I->operand_values()) {
if (isOutOfScope(OV))
continue;
+ // First order recurrence Phi's should typically be considered
+ // non-uniform.
+ auto *OP = dyn_cast(OV);
+ if (OP && Legal->isFirstOrderRecurrence(OP))
+continue;
+ // If all the users of the operand are uniform, then add the
+ // operand into the uniform worklist.
auto *OI = cast(OV);
if (llvm::all_of(OI->users(), [&](User *U) -> bool {
auto *J = cast(U);
Modified:
llvm/branches/release_70/test/Transforms/LoopVectorize/X86/uniform-phi.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/test/Transforms/LoopVectorize/X86/uniform-phi.ll?rev=341523&r1=341522&r2=341523&view=diff
==
--- llvm/branches/release_70/test/Transforms/LoopVectorize/X86/uniform-phi.ll
(original)
+++ llvm/branches/release_70/test/Transforms/LoopVectorize/X86/uniform-phi.ll
Thu Sep 6 01:16:34 2018
@@ -75,3 +75,25 @@ for.end:
ret i64 %retval
}
+; CHECK-LABEL: PR38786
+; Check that first order recurrence phis (%phi32 and %phi64) are not uniform.
+; CHECK-NOT: LV: Found uniform instruction: %phi
+define void @PR38786(double* %y, double* %x, i64 %n) {
+entry:
+ br label %for.body
+
+for.body:
+ %phi32 = phi i32 [ 0, %entry ], [ %i32next, %for.body ]
+ %phi64 = phi i64 [ 0, %entry ], [ %i64next, %for.body ]
+ %i32next = add i32 %phi32, 1
+ %i64next = zext i32 %i32next to i64
+ %xip = getelementptr inbounds double, double* %x, i64 %i64next
+ %yip = getelementptr inbounds double, double* %y, i64 %phi64
+ %xi = load double, double* %xip, align 8
+ store double %xi, double* %yip, align 8
+ %cmp = icmp slt i64 %i64next, %n
+ br i1 %cmp, label %for.body, label %for.end
+
+for.end:
+ ret void
+}
___
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[llvm-branch-commits] [compiler-rt-branch] r341524 - Merging r341442:
Author: hans Date: Thu Sep 6 01:19:33 2018 New Revision: 341524 URL: http://llvm.org/viewvc/llvm-project?rev=341524&view=rev Log: Merging r341442: r341442 | bcain | 2018-09-05 04:15:54 +0200 (Wed, 05 Sep 2018) | 8 lines Add glibc_prereq to platform limits mmsghdr sendmmsg requires glibc >= 2.14. Fixes PR38589. Review: https://reviews.llvm.org/D51538 Modified: compiler-rt/branches/release_70/ (props changed) compiler-rt/branches/release_70/lib/sanitizer_common/sanitizer_platform_limits_posix.cc Propchange: compiler-rt/branches/release_70/ -- --- svn:mergeinfo (original) +++ svn:mergeinfo Thu Sep 6 01:19:33 2018 @@ -1 +1 @@ -/compiler-rt/trunk:338577,338606,339303,340758,340769 +/compiler-rt/trunk:338577,338606,339303,340758,340769,341442 Modified: compiler-rt/branches/release_70/lib/sanitizer_common/sanitizer_platform_limits_posix.cc URL: http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_70/lib/sanitizer_common/sanitizer_platform_limits_posix.cc?rev=341524&r1=341523&r2=341524&view=diff == --- compiler-rt/branches/release_70/lib/sanitizer_common/sanitizer_platform_limits_posix.cc (original) +++ compiler-rt/branches/release_70/lib/sanitizer_common/sanitizer_platform_limits_posix.cc Thu Sep 6 01:19:33 2018 @@ -1037,7 +1037,11 @@ CHECK_SIZE_AND_OFFSET(cmsghdr, cmsg_len) CHECK_SIZE_AND_OFFSET(cmsghdr, cmsg_level); CHECK_SIZE_AND_OFFSET(cmsghdr, cmsg_type); -#if SANITIZER_LINUX && (!defined(__ANDROID__) || __ANDROID_API__ >= 21) +#ifndef __GLIBC_PREREQ +#define __GLIBC_PREREQ(x, y) 0 +#endif + +#if SANITIZER_LINUX && (__ANDROID_API__ >= 21 || __GLIBC_PREREQ (2, 14)) CHECK_TYPE_SIZE(mmsghdr); CHECK_SIZE_AND_OFFSET(mmsghdr, msg_hdr); CHECK_SIZE_AND_OFFSET(mmsghdr, msg_len); @@ -1078,9 +1082,6 @@ COMPILER_CHECK(sizeof(__sanitizer_sigact // Can't write checks for sa_handler and sa_sigaction due to them being // preprocessor macros. CHECK_STRUCT_SIZE_AND_OFFSET(sigaction, sa_mask); -#ifndef __GLIBC_PREREQ -#define __GLIBC_PREREQ(x, y) 0 -#endif #if !defined(__s390x__) || __GLIBC_PREREQ (2, 20) // On s390x glibc 2.19 and earlier sa_flags was unsigned long, and sa_resv // didn't exist. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] r341529 - Merging r340609:
Author: hans
Date: Thu Sep 6 01:54:44 2018
New Revision: 341529
URL: http://llvm.org/viewvc/llvm-project?rev=341529&view=rev
Log:
Merging r340609:
r340609 | ldionne | 2018-08-24 16:10:28 +0200 (Fri, 24 Aug 2018) | 13 lines
[libc++] Fix handling of negated character classes in regex
Summary:
This commit fixes a regression introduced in r316095, where we don't match
inverted character classes when there's no negated characrers in the []'s.
rdar://problem/43060054
Reviewers: mclow.lists, timshen, EricWF
Subscribers: christof, dexonsmith, cfe-commits
Differential Revision: https://reviews.llvm.org/D50534
Added:
libcxx/branches/release_70/test/std/re/re.alg/re.alg.match/inverted_character_classes.pass.cpp
- copied unchanged from r340609,
libcxx/trunk/test/std/re/re.alg/re.alg.match/inverted_character_classes.pass.cpp
Modified:
libcxx/branches/release_70/ (props changed)
libcxx/branches/release_70/include/regex
libcxx/branches/release_70/test/std/re/re.alg/re.alg.search/invert_neg_word_search.pass.cpp
Propchange: libcxx/branches/release_70/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Sep 6 01:54:44 2018
@@ -1,2 +1,2 @@
/libcxx/branches/apple:136569-137939
-/libcxx/trunk:339431,339675,339697,339702,339741-339743,339794,339804,339816,339874,340406,340544,340823
+/libcxx/trunk:339431,339675,339697,339702,339741-339743,339794,339804,339816,339874,340406,340544,340609,340823
Modified: libcxx/branches/release_70/include/regex
URL:
http://llvm.org/viewvc/llvm-project/libcxx/branches/release_70/include/regex?rev=341529&r1=341528&r2=341529&view=diff
==
--- libcxx/branches/release_70/include/regex (original)
+++ libcxx/branches/release_70/include/regex Thu Sep 6 01:54:44 2018
@@ -2414,20 +2414,17 @@ __bracket_expression<_CharT, _Traits>::_
goto __exit;
}
}
-// set of "__found" chars =
+// When there's at least one of __neg_chars_ and __neg_mask_, the set
+// of "__found" chars is
// union(complement(union(__neg_chars_, __neg_mask_)),
// other cases...)
//
-// __neg_chars_ and __neg_mask_'d better be handled together, as there
-// are no short circuit opportunities.
-//
-// In addition, when __neg_mask_/__neg_chars_ is empty, they should be
-// treated as all ones/all chars.
+// It doesn't make sense to check this when there are no __neg_chars_
+// and no __neg_mask_.
+if (!(__neg_mask_ == 0 && __neg_chars_.empty()))
{
- const bool __in_neg_mask = (__neg_mask_ == 0) ||
- __traits_.isctype(__ch, __neg_mask_);
+const bool __in_neg_mask = __traits_.isctype(__ch, __neg_mask_);
const bool __in_neg_chars =
- __neg_chars_.empty() ||
std::find(__neg_chars_.begin(), __neg_chars_.end(), __ch) !=
__neg_chars_.end();
if (!(__in_neg_mask || __in_neg_chars))
Modified:
libcxx/branches/release_70/test/std/re/re.alg/re.alg.search/invert_neg_word_search.pass.cpp
URL:
http://llvm.org/viewvc/llvm-project/libcxx/branches/release_70/test/std/re/re.alg/re.alg.search/invert_neg_word_search.pass.cpp?rev=341529&r1=341528&r2=341529&view=diff
==
---
libcxx/branches/release_70/test/std/re/re.alg/re.alg.search/invert_neg_word_search.pass.cpp
(original)
+++
libcxx/branches/release_70/test/std/re/re.alg/re.alg.search/invert_neg_word_search.pass.cpp
Thu Sep 6 01:54:44 2018
@@ -18,7 +18,7 @@
#include
#include
-#include "test_macros.h"
+
// PR34310
int main()
___
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[llvm-branch-commits] [llvm-branch] r341530 - Merging r341512:
Author: hans
Date: Thu Sep 6 01:58:13 2018
New Revision: 341530
URL: http://llvm.org/viewvc/llvm-project?rev=341530&view=rev
Log:
Merging r341512:
r341512 | ctopper | 2018-09-06 04:03:14 +0200 (Thu, 06 Sep 2018) | 7 lines
[X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives.
This basically reverts a change made in r336217, but improves the text of the
error message for not allowing IP-relative addressing in 32-bit mode.
Fixes PR38826.
Patch by Iain Sandoe.
Added:
llvm/branches/release_70/test/MC/X86/pr38826.s
- copied unchanged from r341512, llvm/trunk/test/MC/X86/pr38826.s
Modified:
llvm/branches/release_70/ (props changed)
llvm/branches/release_70/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/branches/release_70/test/CodeGen/X86/eip-addressing-i386.ll
llvm/branches/release_70/test/MC/X86/x86_errors.s
Propchange: llvm/branches/release_70/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Sep 6 01:58:13 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338841,338902,338915,338968,339073,339091,339166,339179,339184,339190,339225,339316,339319,339411,339492,339515,339533,339535-339536,339600,339636,339674,339769,339822,339883,339895-339896,339945,340158,340303,340416-340417,340455,340641,340691,340751,340820,340839,340900,340959,341094,341244,341416
+/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338841,338902,338915,338968,339073,339091,339166,339179,339184,339190,339225,339316,339319,339411,339492,339515,339533,339535-339536,339600,339636,339674,339769,339822,339883,339895-339896,339945,340158,340303,340416-340417,340455,340641,340691,340751,340820,340839,340900,340959,341094,341244,341416,341512
Modified: llvm/branches/release_70/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=341530&r1=341529&r2=341530&view=diff
==
--- llvm/branches/release_70/lib/Target/X86/AsmParser/X86AsmParser.cpp
(original)
+++ llvm/branches/release_70/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Sep
6 01:58:13 2018
@@ -1054,7 +1054,7 @@ static bool CheckBaseRegAndIndexRegAndSc
// RIP/EIP-relative addressing is only supported in 64-bit mode.
if (!Is64BitMode && BaseReg != 0 &&
(BaseReg == X86::RIP || BaseReg == X86::EIP)) {
-ErrMsg = "RIP-relative addressing requires 64-bit mode";
+ErrMsg = "IP-relative addressing requires 64-bit mode";
return true;
}
@@ -1099,7 +1099,7 @@ bool X86AsmParser::ParseRegister(unsigne
// checked.
// FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
// REX prefix.
-if (RegNo == X86::RIZ || RegNo == X86::RIP || RegNo == X86::EIP ||
+if (RegNo == X86::RIZ || RegNo == X86::RIP ||
X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
X86II::isX86_64NonExtLowByteReg(RegNo) ||
X86II::isX86_64ExtendedReg(RegNo))
Modified: llvm/branches/release_70/test/CodeGen/X86/eip-addressing-i386.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/test/CodeGen/X86/eip-addressing-i386.ll?rev=341530&r1=341529&r2=341530&view=diff
==
--- llvm/branches/release_70/test/CodeGen/X86/eip-addressing-i386.ll (original)
+++ llvm/branches/release_70/test/CodeGen/X86/eip-addressing-i386.ll Thu Sep 6
01:58:13 2018
@@ -1,8 +1,8 @@
; RUN: not llc -mtriple i386-apple-- -o /dev/null < %s 2>&1| FileCheck %s
-; CHECK: :1:13: error: register %eip is only available in 64-bit
mode
+; CHECK: :1:13: error: IP-relative addressing requires 64-bit mode
; CHECK-NEXT: jmpl *_foo(%eip)
-; Make sure that we emit an error if we encounter RIP-relative instructions in
+; Make sure that we emit an error if we encounter IP-relative instructions in
; 32-bit mode.
define i32 @foo() { ret i32 0 }
Modified: llvm/branches/release_70/test/MC/X86/x86_errors.s
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/test/MC/X86/x86_errors.s?rev=341530&r1=341529&r2=341530&view=diff
==
--- llvm/branches/release_70/test/MC/X86/x86_errors.s (original)
+++ llvm/branches/release_70/test/MC/X86/x86_errors.s Thu Sep 6 01:58:13 2018
@@ -103,11 +103,11 @@ lea (%si,%bx), %ax
// 64: error: invalid 16-bit base register
lea (%di,%bx), %ax
-// 32: error: register %ei
